1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * QEMU Xtensa CPU 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 5fcf5ef2aSThomas Huth * Copyright (c) 2012 SUSE LINUX Products GmbH 6fcf5ef2aSThomas Huth * All rights reserved. 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * Redistribution and use in source and binary forms, with or without 9fcf5ef2aSThomas Huth * modification, are permitted provided that the following conditions are met: 10fcf5ef2aSThomas Huth * * Redistributions of source code must retain the above copyright 11fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer. 12fcf5ef2aSThomas Huth * * Redistributions in binary form must reproduce the above copyright 13fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer in the 14fcf5ef2aSThomas Huth * documentation and/or other materials provided with the distribution. 15fcf5ef2aSThomas Huth * * Neither the name of the Open Source and Linux Lab nor the 16fcf5ef2aSThomas Huth * names of its contributors may be used to endorse or promote products 17fcf5ef2aSThomas Huth * derived from this software without specific prior written permission. 18fcf5ef2aSThomas Huth * 19fcf5ef2aSThomas Huth * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20fcf5ef2aSThomas Huth * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21fcf5ef2aSThomas Huth * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22fcf5ef2aSThomas Huth * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23fcf5ef2aSThomas Huth * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24fcf5ef2aSThomas Huth * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25fcf5ef2aSThomas Huth * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26fcf5ef2aSThomas Huth * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27fcf5ef2aSThomas Huth * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28fcf5ef2aSThomas Huth * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29fcf5ef2aSThomas Huth */ 30fcf5ef2aSThomas Huth 31fcf5ef2aSThomas Huth #include "qemu/osdep.h" 32fcf5ef2aSThomas Huth #include "qapi/error.h" 33fcf5ef2aSThomas Huth #include "cpu.h" 340b8fa32fSMarkus Armbruster #include "qemu/module.h" 35fcf5ef2aSThomas Huth #include "migration/vmstate.h" 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth 38fcf5ef2aSThomas Huth static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) 39fcf5ef2aSThomas Huth { 40fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(cs); 41fcf5ef2aSThomas Huth 42fcf5ef2aSThomas Huth cpu->env.pc = value; 43fcf5ef2aSThomas Huth } 44fcf5ef2aSThomas Huth 45fcf5ef2aSThomas Huth static bool xtensa_cpu_has_work(CPUState *cs) 46fcf5ef2aSThomas Huth { 47ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 48fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(cs); 49fcf5ef2aSThomas Huth 50bd527a83SMax Filippov return !cpu->env.runstall && cpu->env.pending_irq_level; 51ba7651fbSMax Filippov #else 52ba7651fbSMax Filippov return true; 53ba7651fbSMax Filippov #endif 54fcf5ef2aSThomas Huth } 55fcf5ef2aSThomas Huth 56*130ea832SMax Filippov #ifdef CONFIG_USER_ONLY 57*130ea832SMax Filippov static bool abi_call0; 58*130ea832SMax Filippov 59*130ea832SMax Filippov void xtensa_set_abi_call0(void) 60*130ea832SMax Filippov { 61*130ea832SMax Filippov abi_call0 = true; 62*130ea832SMax Filippov } 63*130ea832SMax Filippov 64*130ea832SMax Filippov bool xtensa_abi_call0(void) 65*130ea832SMax Filippov { 66*130ea832SMax Filippov return abi_call0; 67*130ea832SMax Filippov } 68*130ea832SMax Filippov #endif 69*130ea832SMax Filippov 70fcf5ef2aSThomas Huth /* CPUClass::reset() */ 71fcf5ef2aSThomas Huth static void xtensa_cpu_reset(CPUState *s) 72fcf5ef2aSThomas Huth { 73fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(s); 74fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); 75fcf5ef2aSThomas Huth CPUXtensaState *env = &cpu->env; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth xcc->parent_reset(s); 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth env->exception_taken = 0; 8017ab14acSMax Filippov env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; 81fcf5ef2aSThomas Huth env->sregs[LITBASE] &= ~1; 82ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 83fcf5ef2aSThomas Huth env->sregs[PS] = xtensa_option_enabled(env->config, 84fcf5ef2aSThomas Huth XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; 85ba7651fbSMax Filippov env->pending_irq_level = 0; 86ba7651fbSMax Filippov #else 87*130ea832SMax Filippov env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); 88*130ea832SMax Filippov if (xtensa_option_enabled(env->config, 89*130ea832SMax Filippov XTENSA_OPTION_WINDOWED_REGISTER) && 90*130ea832SMax Filippov !xtensa_abi_call0()) { 91*130ea832SMax Filippov env->sregs[PS] |= PS_WOE; 92*130ea832SMax Filippov } 93ba7651fbSMax Filippov #endif 94fcf5ef2aSThomas Huth env->sregs[VECBASE] = env->config->vecbase; 95fcf5ef2aSThomas Huth env->sregs[IBREAKENABLE] = 0; 969e03ade4SMax Filippov env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; 97fcf5ef2aSThomas Huth env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, 98fcf5ef2aSThomas Huth XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; 99fcf5ef2aSThomas Huth env->sregs[CONFIGID0] = env->config->configid[0]; 100fcf5ef2aSThomas Huth env->sregs[CONFIGID1] = env->config->configid[1]; 101b345e140SMax Filippov env->exclusive_addr = -1; 102fcf5ef2aSThomas Huth 103ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 104fcf5ef2aSThomas Huth reset_mmu(env); 105bd527a83SMax Filippov s->halted = env->runstall; 106ba7651fbSMax Filippov #endif 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) 110fcf5ef2aSThomas Huth { 111fcf5ef2aSThomas Huth ObjectClass *oc; 112fcf5ef2aSThomas Huth char *typename; 113fcf5ef2aSThomas Huth 114a5247d76SIgor Mammedov typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); 115fcf5ef2aSThomas Huth oc = object_class_by_name(typename); 116fcf5ef2aSThomas Huth g_free(typename); 117fcf5ef2aSThomas Huth if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || 118fcf5ef2aSThomas Huth object_class_is_abstract(oc)) { 119fcf5ef2aSThomas Huth return NULL; 120fcf5ef2aSThomas Huth } 121fcf5ef2aSThomas Huth return oc; 122fcf5ef2aSThomas Huth } 123fcf5ef2aSThomas Huth 1245a6539e6SMax Filippov static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) 1255a6539e6SMax Filippov { 1265a6539e6SMax Filippov XtensaCPU *cpu = XTENSA_CPU(cs); 1275a6539e6SMax Filippov 1285a6539e6SMax Filippov info->private_data = cpu->env.config->isa; 1295a6539e6SMax Filippov info->print_insn = print_insn_xtensa; 1305a6539e6SMax Filippov } 1315a6539e6SMax Filippov 132fcf5ef2aSThomas Huth static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) 133fcf5ef2aSThomas Huth { 134fcf5ef2aSThomas Huth CPUState *cs = CPU(dev); 135fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); 136fcf5ef2aSThomas Huth Error *local_err = NULL; 137fcf5ef2aSThomas Huth 138ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 139ba7651fbSMax Filippov xtensa_irq_init(&XTENSA_CPU(dev)->env); 140ba7651fbSMax Filippov #endif 1418e36271bSIgor Mammedov 142fcf5ef2aSThomas Huth cpu_exec_realizefn(cs, &local_err); 143fcf5ef2aSThomas Huth if (local_err != NULL) { 144fcf5ef2aSThomas Huth error_propagate(errp, local_err); 145fcf5ef2aSThomas Huth return; 146fcf5ef2aSThomas Huth } 147fcf5ef2aSThomas Huth 148fcf5ef2aSThomas Huth cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; 149fcf5ef2aSThomas Huth 150fcf5ef2aSThomas Huth qemu_init_vcpu(cs); 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth xcc->parent_realize(dev, errp); 153fcf5ef2aSThomas Huth } 154fcf5ef2aSThomas Huth 155fcf5ef2aSThomas Huth static void xtensa_cpu_initfn(Object *obj) 156fcf5ef2aSThomas Huth { 157fcf5ef2aSThomas Huth XtensaCPU *cpu = XTENSA_CPU(obj); 158fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); 159fcf5ef2aSThomas Huth CPUXtensaState *env = &cpu->env; 160fcf5ef2aSThomas Huth 1617506ed90SRichard Henderson cpu_set_cpustate_pointers(cpu); 162fcf5ef2aSThomas Huth env->config = xcc->config; 163fcf5ef2aSThomas Huth 164ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY 1653a3c9dc4SMax Filippov env->address_space_er = g_malloc(sizeof(*env->address_space_er)); 1663a3c9dc4SMax Filippov env->system_er = g_malloc(sizeof(*env->system_er)); 16709d98b69SThomas Huth memory_region_init_io(env->system_er, obj, NULL, env, "er", 1683a3c9dc4SMax Filippov UINT64_C(0x100000000)); 1693a3c9dc4SMax Filippov address_space_init(env->address_space_er, env->system_er, "ER"); 170ba7651fbSMax Filippov #endif 171fcf5ef2aSThomas Huth } 172fcf5ef2aSThomas Huth 173fcf5ef2aSThomas Huth static const VMStateDescription vmstate_xtensa_cpu = { 174fcf5ef2aSThomas Huth .name = "cpu", 175fcf5ef2aSThomas Huth .unmigratable = 1, 176fcf5ef2aSThomas Huth }; 177fcf5ef2aSThomas Huth 178fcf5ef2aSThomas Huth static void xtensa_cpu_class_init(ObjectClass *oc, void *data) 179fcf5ef2aSThomas Huth { 180fcf5ef2aSThomas Huth DeviceClass *dc = DEVICE_CLASS(oc); 181fcf5ef2aSThomas Huth CPUClass *cc = CPU_CLASS(oc); 182fcf5ef2aSThomas Huth XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); 183fcf5ef2aSThomas Huth 184bf853881SPhilippe Mathieu-Daudé device_class_set_parent_realize(dc, xtensa_cpu_realizefn, 185bf853881SPhilippe Mathieu-Daudé &xcc->parent_realize); 186fcf5ef2aSThomas Huth 187fcf5ef2aSThomas Huth xcc->parent_reset = cc->reset; 188fcf5ef2aSThomas Huth cc->reset = xtensa_cpu_reset; 189fcf5ef2aSThomas Huth 190fcf5ef2aSThomas Huth cc->class_by_name = xtensa_cpu_class_by_name; 191fcf5ef2aSThomas Huth cc->has_work = xtensa_cpu_has_work; 192fcf5ef2aSThomas Huth cc->do_interrupt = xtensa_cpu_do_interrupt; 193fcf5ef2aSThomas Huth cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt; 194fcf5ef2aSThomas Huth cc->dump_state = xtensa_cpu_dump_state; 195fcf5ef2aSThomas Huth cc->set_pc = xtensa_cpu_set_pc; 196fcf5ef2aSThomas Huth cc->gdb_read_register = xtensa_cpu_gdb_read_register; 197fcf5ef2aSThomas Huth cc->gdb_write_register = xtensa_cpu_gdb_write_register; 198fcf5ef2aSThomas Huth cc->gdb_stop_before_watchpoint = true; 199b008c456SRichard Henderson cc->tlb_fill = xtensa_cpu_tlb_fill; 200b008c456SRichard Henderson #ifndef CONFIG_USER_ONLY 201fcf5ef2aSThomas Huth cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; 202fcf5ef2aSThomas Huth cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; 20376b7dd64SMax Filippov cc->do_transaction_failed = xtensa_cpu_do_transaction_failed; 204fcf5ef2aSThomas Huth #endif 205fcf5ef2aSThomas Huth cc->debug_excp_handler = xtensa_breakpoint_handler; 2065a6539e6SMax Filippov cc->disas_set_info = xtensa_cpu_disas_set_info; 20755c3ceefSRichard Henderson cc->tcg_initialize = xtensa_translate_init; 208fcf5ef2aSThomas Huth dc->vmsd = &vmstate_xtensa_cpu; 209fcf5ef2aSThomas Huth } 210fcf5ef2aSThomas Huth 211fcf5ef2aSThomas Huth static const TypeInfo xtensa_cpu_type_info = { 212fcf5ef2aSThomas Huth .name = TYPE_XTENSA_CPU, 213fcf5ef2aSThomas Huth .parent = TYPE_CPU, 214fcf5ef2aSThomas Huth .instance_size = sizeof(XtensaCPU), 215fcf5ef2aSThomas Huth .instance_init = xtensa_cpu_initfn, 216fcf5ef2aSThomas Huth .abstract = true, 217fcf5ef2aSThomas Huth .class_size = sizeof(XtensaCPUClass), 218fcf5ef2aSThomas Huth .class_init = xtensa_cpu_class_init, 219fcf5ef2aSThomas Huth }; 220fcf5ef2aSThomas Huth 221fcf5ef2aSThomas Huth static void xtensa_cpu_register_types(void) 222fcf5ef2aSThomas Huth { 223fcf5ef2aSThomas Huth type_register_static(&xtensa_cpu_type_info); 224fcf5ef2aSThomas Huth } 225fcf5ef2aSThomas Huth 226fcf5ef2aSThomas Huth type_init(xtensa_cpu_register_types) 227