1/* Xtensa configuration-specific ISA information.
2
3   Copyright (c) 2003-2010 Tensilica Inc.
4
5   Permission is hereby granted, free of charge, to any person obtaining
6   a copy of this software and associated documentation files (the
7   "Software"), to deal in the Software without restriction, including
8   without limitation the rights to use, copy, modify, merge, publish,
9   distribute, sublicense, and/or sell copies of the Software, and to
10   permit persons to whom the Software is furnished to do so, subject to
11   the following conditions:
12
13   The above copyright notice and this permission notice shall be included
14   in all copies or substantial portions of the Software.
15
16   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
23
24#include "xtensa-isa.h"
25#include "xtensa-isa-internal.h"
26
27
28/* Sysregs.  */
29
30static xtensa_sysreg_internal sysregs[] = {
31  { "MMID", 89, 0 },
32  { "DDR", 104, 0 },
33  { "176", 176, 0 },
34  { "208", 208, 0 },
35  { "INTERRUPT", 226, 0 },
36  { "INTCLEAR", 227, 0 },
37  { "CCOUNT", 234, 0 },
38  { "PRID", 235, 0 },
39  { "ICOUNT", 236, 0 },
40  { "CCOMPARE0", 240, 0 },
41  { "VECBASE", 231, 0 },
42  { "EPC1", 177, 0 },
43  { "EPC2", 178, 0 },
44  { "EPC3", 179, 0 },
45  { "EXCSAVE1", 209, 0 },
46  { "EXCSAVE2", 210, 0 },
47  { "EXCSAVE3", 211, 0 },
48  { "EPS2", 194, 0 },
49  { "EPS3", 195, 0 },
50  { "EXCCAUSE", 232, 0 },
51  { "DEPC", 192, 0 },
52  { "EXCVADDR", 238, 0 },
53  { "SAR", 3, 0 },
54  { "LITBASE", 5, 0 },
55  { "PS", 230, 0 },
56  { "INTENABLE", 228, 0 },
57  { "DBREAKA0", 144, 0 },
58  { "DBREAKC0", 160, 0 },
59  { "IBREAKA0", 128, 0 },
60  { "IBREAKENABLE", 96, 0 },
61  { "ICOUNTLEVEL", 237, 0 },
62  { "DEBUGCAUSE", 233, 0 }
63};
64
65#define NUM_SYSREGS 32
66#define MAX_SPECIAL_REG 240
67#define MAX_USER_REG 0
68
69
70/* Processor states.  */
71
72static xtensa_state_internal states[] = {
73  { "PC", 32, 0 },
74  { "ICOUNT", 32, 0 },
75  { "DDR", 32, 0 },
76  { "INTERRUPT", 15, 0 },
77  { "CCOUNT", 32, 0 },
78  { "XTSYNC", 1, 0 },
79  { "VECBASE", 25, 0 },
80  { "EPC1", 32, 0 },
81  { "EPC2", 32, 0 },
82  { "EPC3", 32, 0 },
83  { "EXCSAVE1", 32, 0 },
84  { "EXCSAVE2", 32, 0 },
85  { "EXCSAVE3", 32, 0 },
86  { "EPS2", 6, 0 },
87  { "EPS3", 6, 0 },
88  { "EXCCAUSE", 6, 0 },
89  { "PSINTLEVEL", 4, 0 },
90  { "PSUM", 1, 0 },
91  { "PSEXCM", 1, 0 },
92  { "DEPC", 32, 0 },
93  { "EXCVADDR", 32, 0 },
94  { "SAR", 6, 0 },
95  { "LITBADDR", 20, 0 },
96  { "LITBEN", 1, 0 },
97  { "InOCDMode", 1, 0 },
98  { "INTENABLE", 15, 0 },
99  { "DBREAKA0", 32, 0 },
100  { "DBREAKC0", 8, 0 },
101  { "IBREAKA0", 32, 0 },
102  { "IBREAKENABLE", 1, 0 },
103  { "ICOUNTLEVEL", 4, 0 },
104  { "DEBUGCAUSE", 6, 0 },
105  { "DBNUM", 4, 0 },
106  { "CCOMPARE0", 32, 0 }
107};
108
109#define NUM_STATES 34
110
111enum xtensa_state_id {
112  STATE_PC,
113  STATE_ICOUNT,
114  STATE_DDR,
115  STATE_INTERRUPT,
116  STATE_CCOUNT,
117  STATE_XTSYNC,
118  STATE_VECBASE,
119  STATE_EPC1,
120  STATE_EPC2,
121  STATE_EPC3,
122  STATE_EXCSAVE1,
123  STATE_EXCSAVE2,
124  STATE_EXCSAVE3,
125  STATE_EPS2,
126  STATE_EPS3,
127  STATE_EXCCAUSE,
128  STATE_PSINTLEVEL,
129  STATE_PSUM,
130  STATE_PSEXCM,
131  STATE_DEPC,
132  STATE_EXCVADDR,
133  STATE_SAR,
134  STATE_LITBADDR,
135  STATE_LITBEN,
136  STATE_InOCDMode,
137  STATE_INTENABLE,
138  STATE_DBREAKA0,
139  STATE_DBREAKC0,
140  STATE_IBREAKA0,
141  STATE_IBREAKENABLE,
142  STATE_ICOUNTLEVEL,
143  STATE_DEBUGCAUSE,
144  STATE_DBNUM,
145  STATE_CCOMPARE0
146};
147
148
149/* Field definitions.  */
150
151static unsigned
152Field_t_Slot_inst_get (const xtensa_insnbuf insn)
153{
154  unsigned tie_t = 0;
155  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
156  return tie_t;
157}
158
159static void
160Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
161{
162  uint32 tie_t;
163  tie_t = (val << 28) >> 28;
164  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
165}
166
167static unsigned
168Field_s_Slot_inst_get (const xtensa_insnbuf insn)
169{
170  unsigned tie_t = 0;
171  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
172  return tie_t;
173}
174
175static void
176Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
177{
178  uint32 tie_t;
179  tie_t = (val << 28) >> 28;
180  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
181}
182
183static unsigned
184Field_r_Slot_inst_get (const xtensa_insnbuf insn)
185{
186  unsigned tie_t = 0;
187  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
188  return tie_t;
189}
190
191static void
192Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
193{
194  uint32 tie_t;
195  tie_t = (val << 28) >> 28;
196  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
197}
198
199static unsigned
200Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
201{
202  unsigned tie_t = 0;
203  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
204  return tie_t;
205}
206
207static void
208Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
209{
210  uint32 tie_t;
211  tie_t = (val << 28) >> 28;
212  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
213}
214
215static unsigned
216Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
217{
218  unsigned tie_t = 0;
219  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
220  return tie_t;
221}
222
223static void
224Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
225{
226  uint32 tie_t;
227  tie_t = (val << 28) >> 28;
228  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
229}
230
231static unsigned
232Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
233{
234  unsigned tie_t = 0;
235  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
236  return tie_t;
237}
238
239static void
240Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
241{
242  uint32 tie_t;
243  tie_t = (val << 28) >> 28;
244  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
245}
246
247static unsigned
248Field_m_Slot_inst_get (const xtensa_insnbuf insn)
249{
250  unsigned tie_t = 0;
251  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
252  return tie_t;
253}
254
255static void
256Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
257{
258  uint32 tie_t;
259  tie_t = (val << 30) >> 30;
260  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
261}
262
263static unsigned
264Field_n_Slot_inst_get (const xtensa_insnbuf insn)
265{
266  unsigned tie_t = 0;
267  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
268  return tie_t;
269}
270
271static void
272Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
273{
274  uint32 tie_t;
275  tie_t = (val << 30) >> 30;
276  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
277}
278
279static unsigned
280Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
281{
282  unsigned tie_t = 0;
283  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
284  return tie_t;
285}
286
287static void
288Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
289{
290  uint32 tie_t;
291  tie_t = (val << 29) >> 29;
292  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
293}
294
295static unsigned
296Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
297{
298  unsigned tie_t = 0;
299  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
300  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
301  return tie_t;
302}
303
304static void
305Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
306{
307  uint32 tie_t;
308  tie_t = (val << 28) >> 28;
309  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
310  tie_t = (val << 24) >> 28;
311  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
312}
313
314static unsigned
315Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
316{
317  unsigned tie_t = 0;
318  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
319  return tie_t;
320}
321
322static void
323Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
324{
325  uint32 tie_t;
326  tie_t = (val << 28) >> 28;
327  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
328}
329
330static unsigned
331Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
332{
333  unsigned tie_t = 0;
334  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
335  return tie_t;
336}
337
338static void
339Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
340{
341  uint32 tie_t;
342  tie_t = (val << 31) >> 31;
343  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
344}
345
346static unsigned
347Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
348{
349  unsigned tie_t = 0;
350  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
351  return tie_t;
352}
353
354static void
355Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
356{
357  uint32 tie_t;
358  tie_t = (val << 31) >> 31;
359  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
360}
361
362static unsigned
363Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
364{
365  unsigned tie_t = 0;
366  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
367  return tie_t;
368}
369
370static void
371Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
372{
373  uint32 tie_t;
374  tie_t = (val << 28) >> 28;
375  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
376}
377
378static unsigned
379Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
380{
381  unsigned tie_t = 0;
382  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
383  return tie_t;
384}
385
386static void
387Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
388{
389  uint32 tie_t;
390  tie_t = (val << 28) >> 28;
391  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
392}
393
394static unsigned
395Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
396{
397  unsigned tie_t = 0;
398  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
399  return tie_t;
400}
401
402static void
403Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
404{
405  uint32 tie_t;
406  tie_t = (val << 28) >> 28;
407  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
408}
409
410static unsigned
411Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
412{
413  unsigned tie_t = 0;
414  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
415  return tie_t;
416}
417
418static void
419Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
420{
421  uint32 tie_t;
422  tie_t = (val << 28) >> 28;
423  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
424}
425
426static unsigned
427Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
428{
429  unsigned tie_t = 0;
430  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
431  return tie_t;
432}
433
434static void
435Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
436{
437  uint32 tie_t;
438  tie_t = (val << 28) >> 28;
439  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
440}
441
442static unsigned
443Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
444{
445  unsigned tie_t = 0;
446  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
447  return tie_t;
448}
449
450static void
451Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
452{
453  uint32 tie_t;
454  tie_t = (val << 31) >> 31;
455  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
456}
457
458static unsigned
459Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
460{
461  unsigned tie_t = 0;
462  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
463  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
464  return tie_t;
465}
466
467static void
468Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
469{
470  uint32 tie_t;
471  tie_t = (val << 28) >> 28;
472  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
473  tie_t = (val << 27) >> 31;
474  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
475}
476
477static unsigned
478Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
479{
480  unsigned tie_t = 0;
481  tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
482  return tie_t;
483}
484
485static void
486Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
487{
488  uint32 tie_t;
489  tie_t = (val << 20) >> 20;
490  insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
491}
492
493static unsigned
494Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
495{
496  unsigned tie_t = 0;
497  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
498  return tie_t;
499}
500
501static void
502Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
503{
504  uint32 tie_t;
505  tie_t = (val << 24) >> 24;
506  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
507}
508
509static unsigned
510Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
511{
512  unsigned tie_t = 0;
513  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
514  return tie_t;
515}
516
517static void
518Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
519{
520  uint32 tie_t;
521  tie_t = (val << 28) >> 28;
522  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
523}
524
525static unsigned
526Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
527{
528  unsigned tie_t = 0;
529  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
530  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
531  return tie_t;
532}
533
534static void
535Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
536{
537  uint32 tie_t;
538  tie_t = (val << 24) >> 24;
539  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
540  tie_t = (val << 20) >> 28;
541  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
542}
543
544static unsigned
545Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
546{
547  unsigned tie_t = 0;
548  tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
549  return tie_t;
550}
551
552static void
553Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
554{
555  uint32 tie_t;
556  tie_t = (val << 16) >> 16;
557  insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
558}
559
560static unsigned
561Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
562{
563  unsigned tie_t = 0;
564  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
565  return tie_t;
566}
567
568static void
569Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
570{
571  uint32 tie_t;
572  tie_t = (val << 14) >> 14;
573  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
574}
575
576static unsigned
577Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
578{
579  unsigned tie_t = 0;
580  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
581  return tie_t;
582}
583
584static void
585Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
586{
587  uint32 tie_t;
588  tie_t = (val << 28) >> 28;
589  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
590}
591
592static unsigned
593Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
594{
595  unsigned tie_t = 0;
596  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
597  return tie_t;
598}
599
600static void
601Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
602{
603  uint32 tie_t;
604  tie_t = (val << 31) >> 31;
605  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
606}
607
608static unsigned
609Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
610{
611  unsigned tie_t = 0;
612  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
613  return tie_t;
614}
615
616static void
617Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
618{
619  uint32 tie_t;
620  tie_t = (val << 31) >> 31;
621  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
622}
623
624static unsigned
625Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
626{
627  unsigned tie_t = 0;
628  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
629  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
630  return tie_t;
631}
632
633static void
634Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
635{
636  uint32 tie_t;
637  tie_t = (val << 28) >> 28;
638  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
639  tie_t = (val << 27) >> 31;
640  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
641}
642
643static unsigned
644Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
645{
646  unsigned tie_t = 0;
647  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
648  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
649  return tie_t;
650}
651
652static void
653Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
654{
655  uint32 tie_t;
656  tie_t = (val << 28) >> 28;
657  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
658  tie_t = (val << 27) >> 31;
659  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
660}
661
662static unsigned
663Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
664{
665  unsigned tie_t = 0;
666  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
667  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
668  return tie_t;
669}
670
671static void
672Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
673{
674  uint32 tie_t;
675  tie_t = (val << 28) >> 28;
676  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
677  tie_t = (val << 27) >> 31;
678  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
679}
680
681static unsigned
682Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
683{
684  unsigned tie_t = 0;
685  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
686  return tie_t;
687}
688
689static void
690Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
691{
692  uint32 tie_t;
693  tie_t = (val << 31) >> 31;
694  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
695}
696
697static unsigned
698Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
699{
700  unsigned tie_t = 0;
701  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
702  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
703  return tie_t;
704}
705
706static void
707Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
708{
709  uint32 tie_t;
710  tie_t = (val << 28) >> 28;
711  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
712  tie_t = (val << 27) >> 31;
713  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
714}
715
716static unsigned
717Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
718{
719  unsigned tie_t = 0;
720  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
721  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
722  return tie_t;
723}
724
725static void
726Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
727{
728  uint32 tie_t;
729  tie_t = (val << 28) >> 28;
730  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
731  tie_t = (val << 24) >> 28;
732  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
733}
734
735static unsigned
736Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
737{
738  unsigned tie_t = 0;
739  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
740  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
741  return tie_t;
742}
743
744static void
745Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
746{
747  uint32 tie_t;
748  tie_t = (val << 28) >> 28;
749  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
750  tie_t = (val << 24) >> 28;
751  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
752}
753
754static unsigned
755Field_st_Slot_inst_get (const xtensa_insnbuf insn)
756{
757  unsigned tie_t = 0;
758  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
759  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
760  return tie_t;
761}
762
763static void
764Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
765{
766  uint32 tie_t;
767  tie_t = (val << 28) >> 28;
768  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
769  tie_t = (val << 24) >> 28;
770  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
771}
772
773static unsigned
774Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
775{
776  unsigned tie_t = 0;
777  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
778  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
779  return tie_t;
780}
781
782static void
783Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
784{
785  uint32 tie_t;
786  tie_t = (val << 28) >> 28;
787  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
788  tie_t = (val << 24) >> 28;
789  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
790}
791
792static unsigned
793Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
794{
795  unsigned tie_t = 0;
796  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
797  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
798  return tie_t;
799}
800
801static void
802Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
803{
804  uint32 tie_t;
805  tie_t = (val << 28) >> 28;
806  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
807  tie_t = (val << 24) >> 28;
808  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
809}
810
811static unsigned
812Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
813{
814  unsigned tie_t = 0;
815  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
816  return tie_t;
817}
818
819static void
820Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
821{
822  uint32 tie_t;
823  tie_t = (val << 28) >> 28;
824  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
825}
826
827static unsigned
828Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
829{
830  unsigned tie_t = 0;
831  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
832  return tie_t;
833}
834
835static void
836Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
837{
838  uint32 tie_t;
839  tie_t = (val << 28) >> 28;
840  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
841}
842
843static unsigned
844Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
845{
846  unsigned tie_t = 0;
847  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
848  return tie_t;
849}
850
851static void
852Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
853{
854  uint32 tie_t;
855  tie_t = (val << 28) >> 28;
856  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
857}
858
859static unsigned
860Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
861{
862  unsigned tie_t = 0;
863  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
864  return tie_t;
865}
866
867static void
868Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
869{
870  uint32 tie_t;
871  tie_t = (val << 31) >> 31;
872  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
873}
874
875static unsigned
876Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
877{
878  unsigned tie_t = 0;
879  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
880  return tie_t;
881}
882
883static void
884Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
885{
886  uint32 tie_t;
887  tie_t = (val << 28) >> 28;
888  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
889}
890
891static unsigned
892Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
893{
894  unsigned tie_t = 0;
895  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
896  return tie_t;
897}
898
899static void
900Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
901{
902  uint32 tie_t;
903  tie_t = (val << 28) >> 28;
904  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
905}
906
907static unsigned
908Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
909{
910  unsigned tie_t = 0;
911  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
912  return tie_t;
913}
914
915static void
916Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
917{
918  uint32 tie_t;
919  tie_t = (val << 30) >> 30;
920  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
921}
922
923static unsigned
924Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
925{
926  unsigned tie_t = 0;
927  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
928  return tie_t;
929}
930
931static void
932Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
933{
934  uint32 tie_t;
935  tie_t = (val << 30) >> 30;
936  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
937}
938
939static unsigned
940Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
941{
942  unsigned tie_t = 0;
943  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
944  return tie_t;
945}
946
947static void
948Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
949{
950  uint32 tie_t;
951  tie_t = (val << 28) >> 28;
952  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
953}
954
955static unsigned
956Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
957{
958  unsigned tie_t = 0;
959  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
960  return tie_t;
961}
962
963static void
964Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
965{
966  uint32 tie_t;
967  tie_t = (val << 28) >> 28;
968  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
969}
970
971static unsigned
972Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
973{
974  unsigned tie_t = 0;
975  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
976  return tie_t;
977}
978
979static void
980Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
981{
982  uint32 tie_t;
983  tie_t = (val << 29) >> 29;
984  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
985}
986
987static unsigned
988Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
989{
990  unsigned tie_t = 0;
991  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
992  return tie_t;
993}
994
995static void
996Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
997{
998  uint32 tie_t;
999  tie_t = (val << 29) >> 29;
1000  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1001}
1002
1003static unsigned
1004Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1005{
1006  unsigned tie_t = 0;
1007  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1008  return tie_t;
1009}
1010
1011static void
1012Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1013{
1014  uint32 tie_t;
1015  tie_t = (val << 31) >> 31;
1016  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1017}
1018
1019static unsigned
1020Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1021{
1022  unsigned tie_t = 0;
1023  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1024  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1025  return tie_t;
1026}
1027
1028static void
1029Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1030{
1031  uint32 tie_t;
1032  tie_t = (val << 28) >> 28;
1033  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1034  tie_t = (val << 26) >> 30;
1035  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1036}
1037
1038static unsigned
1039Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1040{
1041  unsigned tie_t = 0;
1042  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1043  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1044  return tie_t;
1045}
1046
1047static void
1048Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1049{
1050  uint32 tie_t;
1051  tie_t = (val << 28) >> 28;
1052  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1053  tie_t = (val << 26) >> 30;
1054  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1055}
1056
1057static unsigned
1058Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1059{
1060  unsigned tie_t = 0;
1061  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1062  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1063  return tie_t;
1064}
1065
1066static void
1067Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1068{
1069  uint32 tie_t;
1070  tie_t = (val << 28) >> 28;
1071  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1072  tie_t = (val << 25) >> 29;
1073  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1074}
1075
1076static unsigned
1077Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1078{
1079  unsigned tie_t = 0;
1080  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1081  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1082  return tie_t;
1083}
1084
1085static void
1086Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1087{
1088  uint32 tie_t;
1089  tie_t = (val << 28) >> 28;
1090  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1091  tie_t = (val << 25) >> 29;
1092  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1093}
1094
1095static unsigned
1096Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1097{
1098  unsigned tie_t = 0;
1099  tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1100  return tie_t;
1101}
1102
1103static void
1104Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1105{
1106  uint32 tie_t;
1107  tie_t = (val << 17) >> 17;
1108  insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1109}
1110
1111static unsigned
1112Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1113{
1114  unsigned tie_t = 0;
1115  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1116  return tie_t;
1117}
1118
1119static void
1120Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1121{
1122  uint32 tie_t;
1123  tie_t = (val << 14) >> 14;
1124  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1125}
1126
1127static void
1128Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1129		    uint32 val ATTRIBUTE_UNUSED)
1130{
1131  /* Do nothing.  */
1132}
1133
1134static unsigned
1135Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1136{
1137  return 0;
1138}
1139
1140enum xtensa_field_id {
1141  FIELD_t,
1142  FIELD_bbi4,
1143  FIELD_bbi,
1144  FIELD_imm12,
1145  FIELD_imm8,
1146  FIELD_s,
1147  FIELD_imm12b,
1148  FIELD_imm16,
1149  FIELD_m,
1150  FIELD_n,
1151  FIELD_offset,
1152  FIELD_op0,
1153  FIELD_op1,
1154  FIELD_op2,
1155  FIELD_r,
1156  FIELD_sa4,
1157  FIELD_sae4,
1158  FIELD_sae,
1159  FIELD_sal,
1160  FIELD_sargt,
1161  FIELD_sas4,
1162  FIELD_sas,
1163  FIELD_sr,
1164  FIELD_st,
1165  FIELD_thi3,
1166  FIELD_imm4,
1167  FIELD_i,
1168  FIELD_imm6lo,
1169  FIELD_imm6hi,
1170  FIELD_imm7lo,
1171  FIELD_imm7hi,
1172  FIELD_z,
1173  FIELD_imm6,
1174  FIELD_imm7,
1175  FIELD_xt_wbr15_imm,
1176  FIELD_xt_wbr18_imm,
1177  FIELD__ar0
1178};
1179
1180
1181/* Functional units.  */
1182
1183static xtensa_funcUnit_internal funcUnits[] = {
1184
1185};
1186
1187
1188/* Register files.  */
1189
1190enum xtensa_regfile_id {
1191  REGFILE_AR
1192};
1193
1194static xtensa_regfile_internal regfiles[] = {
1195  { "AR", "a", REGFILE_AR, 32, 16 }
1196};
1197
1198
1199/* Interfaces.  */
1200
1201static xtensa_interface_internal interfaces[] = {
1202
1203};
1204
1205
1206/* Constant tables.  */
1207
1208/* constant table ai4c */
1209static const unsigned CONST_TBL_ai4c_0[] = {
1210  0xffffffff,
1211  0x1,
1212  0x2,
1213  0x3,
1214  0x4,
1215  0x5,
1216  0x6,
1217  0x7,
1218  0x8,
1219  0x9,
1220  0xa,
1221  0xb,
1222  0xc,
1223  0xd,
1224  0xe,
1225  0xf,
1226  0
1227};
1228
1229/* constant table b4c */
1230static const unsigned CONST_TBL_b4c_0[] = {
1231  0xffffffff,
1232  0x1,
1233  0x2,
1234  0x3,
1235  0x4,
1236  0x5,
1237  0x6,
1238  0x7,
1239  0x8,
1240  0xa,
1241  0xc,
1242  0x10,
1243  0x20,
1244  0x40,
1245  0x80,
1246  0x100,
1247  0
1248};
1249
1250/* constant table b4cu */
1251static const unsigned CONST_TBL_b4cu_0[] = {
1252  0x8000,
1253  0x10000,
1254  0x2,
1255  0x3,
1256  0x4,
1257  0x5,
1258  0x6,
1259  0x7,
1260  0x8,
1261  0xa,
1262  0xc,
1263  0x10,
1264  0x20,
1265  0x40,
1266  0x80,
1267  0x100,
1268  0
1269};
1270
1271
1272/* Instruction operands.  */
1273
1274static int
1275Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1276{
1277  return 0;
1278}
1279
1280static int
1281Operand_art_encode (uint32 *valp)
1282{
1283  int error;
1284  error = (*valp & ~0xf) != 0;
1285  return error;
1286}
1287
1288static int
1289Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1290{
1291  return 0;
1292}
1293
1294static int
1295Operand_ars_encode (uint32 *valp)
1296{
1297  int error;
1298  error = (*valp & ~0xf) != 0;
1299  return error;
1300}
1301
1302static int
1303Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1304{
1305  return 0;
1306}
1307
1308static int
1309Operand_arr_encode (uint32 *valp)
1310{
1311  int error;
1312  error = (*valp & ~0xf) != 0;
1313  return error;
1314}
1315
1316static int
1317Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1318{
1319  return 0;
1320}
1321
1322static int
1323Operand_ar0_encode (uint32 *valp)
1324{
1325  int error;
1326  error = (*valp & ~0xf) != 0;
1327  return error;
1328}
1329
1330static int
1331Operand_soffsetx4_decode (uint32 *valp)
1332{
1333  unsigned soffsetx4_0, offset_0;
1334  offset_0 = *valp & 0x3ffff;
1335  soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1336  *valp = soffsetx4_0;
1337  return 0;
1338}
1339
1340static int
1341Operand_soffsetx4_encode (uint32 *valp)
1342{
1343  unsigned offset_0, soffsetx4_0;
1344  soffsetx4_0 = *valp;
1345  offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1346  *valp = offset_0;
1347  return 0;
1348}
1349
1350static int
1351Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1352{
1353  *valp -= (pc & ~0x3);
1354  return 0;
1355}
1356
1357static int
1358Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1359{
1360  *valp += (pc & ~0x3);
1361  return 0;
1362}
1363
1364static int
1365Operand_lsi4x4_decode (uint32 *valp)
1366{
1367  unsigned lsi4x4_0, r_0;
1368  r_0 = *valp & 0xf;
1369  lsi4x4_0 = r_0 << 2;
1370  *valp = lsi4x4_0;
1371  return 0;
1372}
1373
1374static int
1375Operand_lsi4x4_encode (uint32 *valp)
1376{
1377  unsigned r_0, lsi4x4_0;
1378  lsi4x4_0 = *valp;
1379  r_0 = ((lsi4x4_0 >> 2) & 0xf);
1380  *valp = r_0;
1381  return 0;
1382}
1383
1384static int
1385Operand_simm7_decode (uint32 *valp)
1386{
1387  unsigned simm7_0, imm7_0;
1388  imm7_0 = *valp & 0x7f;
1389  simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1390  *valp = simm7_0;
1391  return 0;
1392}
1393
1394static int
1395Operand_simm7_encode (uint32 *valp)
1396{
1397  unsigned imm7_0, simm7_0;
1398  simm7_0 = *valp;
1399  imm7_0 = (simm7_0 & 0x7f);
1400  *valp = imm7_0;
1401  return 0;
1402}
1403
1404static int
1405Operand_uimm6_decode (uint32 *valp)
1406{
1407  unsigned uimm6_0, imm6_0;
1408  imm6_0 = *valp & 0x3f;
1409  uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
1410  *valp = uimm6_0;
1411  return 0;
1412}
1413
1414static int
1415Operand_uimm6_encode (uint32 *valp)
1416{
1417  unsigned imm6_0, uimm6_0;
1418  uimm6_0 = *valp;
1419  imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1420  *valp = imm6_0;
1421  return 0;
1422}
1423
1424static int
1425Operand_uimm6_ator (uint32 *valp, uint32 pc)
1426{
1427  *valp -= pc;
1428  return 0;
1429}
1430
1431static int
1432Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
1433{
1434  *valp += pc;
1435  return 0;
1436}
1437
1438static int
1439Operand_ai4const_decode (uint32 *valp)
1440{
1441  unsigned ai4const_0, t_0;
1442  t_0 = *valp & 0xf;
1443  ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
1444  *valp = ai4const_0;
1445  return 0;
1446}
1447
1448static int
1449Operand_ai4const_encode (uint32 *valp)
1450{
1451  unsigned t_0, ai4const_0;
1452  ai4const_0 = *valp;
1453  switch (ai4const_0)
1454    {
1455    case 0xffffffff: t_0 = 0; break;
1456    case 0x1: t_0 = 0x1; break;
1457    case 0x2: t_0 = 0x2; break;
1458    case 0x3: t_0 = 0x3; break;
1459    case 0x4: t_0 = 0x4; break;
1460    case 0x5: t_0 = 0x5; break;
1461    case 0x6: t_0 = 0x6; break;
1462    case 0x7: t_0 = 0x7; break;
1463    case 0x8: t_0 = 0x8; break;
1464    case 0x9: t_0 = 0x9; break;
1465    case 0xa: t_0 = 0xa; break;
1466    case 0xb: t_0 = 0xb; break;
1467    case 0xc: t_0 = 0xc; break;
1468    case 0xd: t_0 = 0xd; break;
1469    case 0xe: t_0 = 0xe; break;
1470    default: t_0 = 0xf; break;
1471    }
1472  *valp = t_0;
1473  return 0;
1474}
1475
1476static int
1477Operand_b4const_decode (uint32 *valp)
1478{
1479  unsigned b4const_0, r_0;
1480  r_0 = *valp & 0xf;
1481  b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
1482  *valp = b4const_0;
1483  return 0;
1484}
1485
1486static int
1487Operand_b4const_encode (uint32 *valp)
1488{
1489  unsigned r_0, b4const_0;
1490  b4const_0 = *valp;
1491  switch (b4const_0)
1492    {
1493    case 0xffffffff: r_0 = 0; break;
1494    case 0x1: r_0 = 0x1; break;
1495    case 0x2: r_0 = 0x2; break;
1496    case 0x3: r_0 = 0x3; break;
1497    case 0x4: r_0 = 0x4; break;
1498    case 0x5: r_0 = 0x5; break;
1499    case 0x6: r_0 = 0x6; break;
1500    case 0x7: r_0 = 0x7; break;
1501    case 0x8: r_0 = 0x8; break;
1502    case 0xa: r_0 = 0x9; break;
1503    case 0xc: r_0 = 0xa; break;
1504    case 0x10: r_0 = 0xb; break;
1505    case 0x20: r_0 = 0xc; break;
1506    case 0x40: r_0 = 0xd; break;
1507    case 0x80: r_0 = 0xe; break;
1508    default: r_0 = 0xf; break;
1509    }
1510  *valp = r_0;
1511  return 0;
1512}
1513
1514static int
1515Operand_b4constu_decode (uint32 *valp)
1516{
1517  unsigned b4constu_0, r_0;
1518  r_0 = *valp & 0xf;
1519  b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
1520  *valp = b4constu_0;
1521  return 0;
1522}
1523
1524static int
1525Operand_b4constu_encode (uint32 *valp)
1526{
1527  unsigned r_0, b4constu_0;
1528  b4constu_0 = *valp;
1529  switch (b4constu_0)
1530    {
1531    case 0x8000: r_0 = 0; break;
1532    case 0x10000: r_0 = 0x1; break;
1533    case 0x2: r_0 = 0x2; break;
1534    case 0x3: r_0 = 0x3; break;
1535    case 0x4: r_0 = 0x4; break;
1536    case 0x5: r_0 = 0x5; break;
1537    case 0x6: r_0 = 0x6; break;
1538    case 0x7: r_0 = 0x7; break;
1539    case 0x8: r_0 = 0x8; break;
1540    case 0xa: r_0 = 0x9; break;
1541    case 0xc: r_0 = 0xa; break;
1542    case 0x10: r_0 = 0xb; break;
1543    case 0x20: r_0 = 0xc; break;
1544    case 0x40: r_0 = 0xd; break;
1545    case 0x80: r_0 = 0xe; break;
1546    default: r_0 = 0xf; break;
1547    }
1548  *valp = r_0;
1549  return 0;
1550}
1551
1552static int
1553Operand_uimm8_decode (uint32 *valp)
1554{
1555  unsigned uimm8_0, imm8_0;
1556  imm8_0 = *valp & 0xff;
1557  uimm8_0 = imm8_0;
1558  *valp = uimm8_0;
1559  return 0;
1560}
1561
1562static int
1563Operand_uimm8_encode (uint32 *valp)
1564{
1565  unsigned imm8_0, uimm8_0;
1566  uimm8_0 = *valp;
1567  imm8_0 = (uimm8_0 & 0xff);
1568  *valp = imm8_0;
1569  return 0;
1570}
1571
1572static int
1573Operand_uimm8x2_decode (uint32 *valp)
1574{
1575  unsigned uimm8x2_0, imm8_0;
1576  imm8_0 = *valp & 0xff;
1577  uimm8x2_0 = imm8_0 << 1;
1578  *valp = uimm8x2_0;
1579  return 0;
1580}
1581
1582static int
1583Operand_uimm8x2_encode (uint32 *valp)
1584{
1585  unsigned imm8_0, uimm8x2_0;
1586  uimm8x2_0 = *valp;
1587  imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
1588  *valp = imm8_0;
1589  return 0;
1590}
1591
1592static int
1593Operand_uimm8x4_decode (uint32 *valp)
1594{
1595  unsigned uimm8x4_0, imm8_0;
1596  imm8_0 = *valp & 0xff;
1597  uimm8x4_0 = imm8_0 << 2;
1598  *valp = uimm8x4_0;
1599  return 0;
1600}
1601
1602static int
1603Operand_uimm8x4_encode (uint32 *valp)
1604{
1605  unsigned imm8_0, uimm8x4_0;
1606  uimm8x4_0 = *valp;
1607  imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
1608  *valp = imm8_0;
1609  return 0;
1610}
1611
1612static int
1613Operand_uimm4x16_decode (uint32 *valp)
1614{
1615  unsigned uimm4x16_0, op2_0;
1616  op2_0 = *valp & 0xf;
1617  uimm4x16_0 = op2_0 << 4;
1618  *valp = uimm4x16_0;
1619  return 0;
1620}
1621
1622static int
1623Operand_uimm4x16_encode (uint32 *valp)
1624{
1625  unsigned op2_0, uimm4x16_0;
1626  uimm4x16_0 = *valp;
1627  op2_0 = ((uimm4x16_0 >> 4) & 0xf);
1628  *valp = op2_0;
1629  return 0;
1630}
1631
1632static int
1633Operand_simm8_decode (uint32 *valp)
1634{
1635  unsigned simm8_0, imm8_0;
1636  imm8_0 = *valp & 0xff;
1637  simm8_0 = ((int) imm8_0 << 24) >> 24;
1638  *valp = simm8_0;
1639  return 0;
1640}
1641
1642static int
1643Operand_simm8_encode (uint32 *valp)
1644{
1645  unsigned imm8_0, simm8_0;
1646  simm8_0 = *valp;
1647  imm8_0 = (simm8_0 & 0xff);
1648  *valp = imm8_0;
1649  return 0;
1650}
1651
1652static int
1653Operand_simm8x256_decode (uint32 *valp)
1654{
1655  unsigned simm8x256_0, imm8_0;
1656  imm8_0 = *valp & 0xff;
1657  simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
1658  *valp = simm8x256_0;
1659  return 0;
1660}
1661
1662static int
1663Operand_simm8x256_encode (uint32 *valp)
1664{
1665  unsigned imm8_0, simm8x256_0;
1666  simm8x256_0 = *valp;
1667  imm8_0 = ((simm8x256_0 >> 8) & 0xff);
1668  *valp = imm8_0;
1669  return 0;
1670}
1671
1672static int
1673Operand_simm12b_decode (uint32 *valp)
1674{
1675  unsigned simm12b_0, imm12b_0;
1676  imm12b_0 = *valp & 0xfff;
1677  simm12b_0 = ((int) imm12b_0 << 20) >> 20;
1678  *valp = simm12b_0;
1679  return 0;
1680}
1681
1682static int
1683Operand_simm12b_encode (uint32 *valp)
1684{
1685  unsigned imm12b_0, simm12b_0;
1686  simm12b_0 = *valp;
1687  imm12b_0 = (simm12b_0 & 0xfff);
1688  *valp = imm12b_0;
1689  return 0;
1690}
1691
1692static int
1693Operand_msalp32_decode (uint32 *valp)
1694{
1695  unsigned msalp32_0, sal_0;
1696  sal_0 = *valp & 0x1f;
1697  msalp32_0 = 0x20 - sal_0;
1698  *valp = msalp32_0;
1699  return 0;
1700}
1701
1702static int
1703Operand_msalp32_encode (uint32 *valp)
1704{
1705  unsigned sal_0, msalp32_0;
1706  msalp32_0 = *valp;
1707  sal_0 = (0x20 - msalp32_0) & 0x1f;
1708  *valp = sal_0;
1709  return 0;
1710}
1711
1712static int
1713Operand_op2p1_decode (uint32 *valp)
1714{
1715  unsigned op2p1_0, op2_0;
1716  op2_0 = *valp & 0xf;
1717  op2p1_0 = op2_0 + 0x1;
1718  *valp = op2p1_0;
1719  return 0;
1720}
1721
1722static int
1723Operand_op2p1_encode (uint32 *valp)
1724{
1725  unsigned op2_0, op2p1_0;
1726  op2p1_0 = *valp;
1727  op2_0 = (op2p1_0 - 0x1) & 0xf;
1728  *valp = op2_0;
1729  return 0;
1730}
1731
1732static int
1733Operand_label8_decode (uint32 *valp)
1734{
1735  unsigned label8_0, imm8_0;
1736  imm8_0 = *valp & 0xff;
1737  label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
1738  *valp = label8_0;
1739  return 0;
1740}
1741
1742static int
1743Operand_label8_encode (uint32 *valp)
1744{
1745  unsigned imm8_0, label8_0;
1746  label8_0 = *valp;
1747  imm8_0 = (label8_0 - 0x4) & 0xff;
1748  *valp = imm8_0;
1749  return 0;
1750}
1751
1752static int
1753Operand_label8_ator (uint32 *valp, uint32 pc)
1754{
1755  *valp -= pc;
1756  return 0;
1757}
1758
1759static int
1760Operand_label8_rtoa (uint32 *valp, uint32 pc)
1761{
1762  *valp += pc;
1763  return 0;
1764}
1765
1766static int
1767Operand_label12_decode (uint32 *valp)
1768{
1769  unsigned label12_0, imm12_0;
1770  imm12_0 = *valp & 0xfff;
1771  label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
1772  *valp = label12_0;
1773  return 0;
1774}
1775
1776static int
1777Operand_label12_encode (uint32 *valp)
1778{
1779  unsigned imm12_0, label12_0;
1780  label12_0 = *valp;
1781  imm12_0 = (label12_0 - 0x4) & 0xfff;
1782  *valp = imm12_0;
1783  return 0;
1784}
1785
1786static int
1787Operand_label12_ator (uint32 *valp, uint32 pc)
1788{
1789  *valp -= pc;
1790  return 0;
1791}
1792
1793static int
1794Operand_label12_rtoa (uint32 *valp, uint32 pc)
1795{
1796  *valp += pc;
1797  return 0;
1798}
1799
1800static int
1801Operand_soffset_decode (uint32 *valp)
1802{
1803  unsigned soffset_0, offset_0;
1804  offset_0 = *valp & 0x3ffff;
1805  soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
1806  *valp = soffset_0;
1807  return 0;
1808}
1809
1810static int
1811Operand_soffset_encode (uint32 *valp)
1812{
1813  unsigned offset_0, soffset_0;
1814  soffset_0 = *valp;
1815  offset_0 = (soffset_0 - 0x4) & 0x3ffff;
1816  *valp = offset_0;
1817  return 0;
1818}
1819
1820static int
1821Operand_soffset_ator (uint32 *valp, uint32 pc)
1822{
1823  *valp -= pc;
1824  return 0;
1825}
1826
1827static int
1828Operand_soffset_rtoa (uint32 *valp, uint32 pc)
1829{
1830  *valp += pc;
1831  return 0;
1832}
1833
1834static int
1835Operand_uimm16x4_decode (uint32 *valp)
1836{
1837  unsigned uimm16x4_0, imm16_0;
1838  imm16_0 = *valp & 0xffff;
1839  uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
1840  *valp = uimm16x4_0;
1841  return 0;
1842}
1843
1844static int
1845Operand_uimm16x4_encode (uint32 *valp)
1846{
1847  unsigned imm16_0, uimm16x4_0;
1848  uimm16x4_0 = *valp;
1849  imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
1850  *valp = imm16_0;
1851  return 0;
1852}
1853
1854static int
1855Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
1856{
1857  *valp -= ((pc + 3) & ~0x3);
1858  return 0;
1859}
1860
1861static int
1862Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
1863{
1864  *valp += ((pc + 3) & ~0x3);
1865  return 0;
1866}
1867
1868static int
1869Operand_immt_decode (uint32 *valp)
1870{
1871  unsigned immt_0, t_0;
1872  t_0 = *valp & 0xf;
1873  immt_0 = t_0;
1874  *valp = immt_0;
1875  return 0;
1876}
1877
1878static int
1879Operand_immt_encode (uint32 *valp)
1880{
1881  unsigned t_0, immt_0;
1882  immt_0 = *valp;
1883  t_0 = immt_0 & 0xf;
1884  *valp = t_0;
1885  return 0;
1886}
1887
1888static int
1889Operand_imms_decode (uint32 *valp)
1890{
1891  unsigned imms_0, s_0;
1892  s_0 = *valp & 0xf;
1893  imms_0 = s_0;
1894  *valp = imms_0;
1895  return 0;
1896}
1897
1898static int
1899Operand_imms_encode (uint32 *valp)
1900{
1901  unsigned s_0, imms_0;
1902  imms_0 = *valp;
1903  s_0 = imms_0 & 0xf;
1904  *valp = s_0;
1905  return 0;
1906}
1907
1908static int
1909Operand_xt_wbr15_label_decode (uint32 *valp)
1910{
1911  unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
1912  xt_wbr15_imm_0 = *valp & 0x7fff;
1913  xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
1914  *valp = xt_wbr15_label_0;
1915  return 0;
1916}
1917
1918static int
1919Operand_xt_wbr15_label_encode (uint32 *valp)
1920{
1921  unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
1922  xt_wbr15_label_0 = *valp;
1923  xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
1924  *valp = xt_wbr15_imm_0;
1925  return 0;
1926}
1927
1928static int
1929Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
1930{
1931  *valp -= pc;
1932  return 0;
1933}
1934
1935static int
1936Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
1937{
1938  *valp += pc;
1939  return 0;
1940}
1941
1942static int
1943Operand_xt_wbr18_label_decode (uint32 *valp)
1944{
1945  unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
1946  xt_wbr18_imm_0 = *valp & 0x3ffff;
1947  xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
1948  *valp = xt_wbr18_label_0;
1949  return 0;
1950}
1951
1952static int
1953Operand_xt_wbr18_label_encode (uint32 *valp)
1954{
1955  unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
1956  xt_wbr18_label_0 = *valp;
1957  xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
1958  *valp = xt_wbr18_imm_0;
1959  return 0;
1960}
1961
1962static int
1963Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
1964{
1965  *valp -= pc;
1966  return 0;
1967}
1968
1969static int
1970Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
1971{
1972  *valp += pc;
1973  return 0;
1974}
1975
1976static xtensa_operand_internal operands[] = {
1977  { "art", FIELD_t, REGFILE_AR, 1,
1978    XTENSA_OPERAND_IS_REGISTER,
1979    Operand_art_encode, Operand_art_decode,
1980    0, 0 },
1981  { "ars", FIELD_s, REGFILE_AR, 1,
1982    XTENSA_OPERAND_IS_REGISTER,
1983    Operand_ars_encode, Operand_ars_decode,
1984    0, 0 },
1985  { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
1986    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
1987    Operand_ars_encode, Operand_ars_decode,
1988    0, 0 },
1989  { "arr", FIELD_r, REGFILE_AR, 1,
1990    XTENSA_OPERAND_IS_REGISTER,
1991    Operand_arr_encode, Operand_arr_decode,
1992    0, 0 },
1993  { "ar0", FIELD__ar0, REGFILE_AR, 1,
1994    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
1995    Operand_ar0_encode, Operand_ar0_decode,
1996    0, 0 },
1997  { "soffsetx4", FIELD_offset, -1, 0,
1998    XTENSA_OPERAND_IS_PCRELATIVE,
1999    Operand_soffsetx4_encode, Operand_soffsetx4_decode,
2000    Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2001  { "lsi4x4", FIELD_r, -1, 0,
2002    0,
2003    Operand_lsi4x4_encode, Operand_lsi4x4_decode,
2004    0, 0 },
2005  { "simm7", FIELD_imm7, -1, 0,
2006    0,
2007    Operand_simm7_encode, Operand_simm7_decode,
2008    0, 0 },
2009  { "uimm6", FIELD_imm6, -1, 0,
2010    XTENSA_OPERAND_IS_PCRELATIVE,
2011    Operand_uimm6_encode, Operand_uimm6_decode,
2012    Operand_uimm6_ator, Operand_uimm6_rtoa },
2013  { "ai4const", FIELD_t, -1, 0,
2014    0,
2015    Operand_ai4const_encode, Operand_ai4const_decode,
2016    0, 0 },
2017  { "b4const", FIELD_r, -1, 0,
2018    0,
2019    Operand_b4const_encode, Operand_b4const_decode,
2020    0, 0 },
2021  { "b4constu", FIELD_r, -1, 0,
2022    0,
2023    Operand_b4constu_encode, Operand_b4constu_decode,
2024    0, 0 },
2025  { "uimm8", FIELD_imm8, -1, 0,
2026    0,
2027    Operand_uimm8_encode, Operand_uimm8_decode,
2028    0, 0 },
2029  { "uimm8x2", FIELD_imm8, -1, 0,
2030    0,
2031    Operand_uimm8x2_encode, Operand_uimm8x2_decode,
2032    0, 0 },
2033  { "uimm8x4", FIELD_imm8, -1, 0,
2034    0,
2035    Operand_uimm8x4_encode, Operand_uimm8x4_decode,
2036    0, 0 },
2037  { "uimm4x16", FIELD_op2, -1, 0,
2038    0,
2039    Operand_uimm4x16_encode, Operand_uimm4x16_decode,
2040    0, 0 },
2041  { "simm8", FIELD_imm8, -1, 0,
2042    0,
2043    Operand_simm8_encode, Operand_simm8_decode,
2044    0, 0 },
2045  { "simm8x256", FIELD_imm8, -1, 0,
2046    0,
2047    Operand_simm8x256_encode, Operand_simm8x256_decode,
2048    0, 0 },
2049  { "simm12b", FIELD_imm12b, -1, 0,
2050    0,
2051    Operand_simm12b_encode, Operand_simm12b_decode,
2052    0, 0 },
2053  { "msalp32", FIELD_sal, -1, 0,
2054    0,
2055    Operand_msalp32_encode, Operand_msalp32_decode,
2056    0, 0 },
2057  { "op2p1", FIELD_op2, -1, 0,
2058    0,
2059    Operand_op2p1_encode, Operand_op2p1_decode,
2060    0, 0 },
2061  { "label8", FIELD_imm8, -1, 0,
2062    XTENSA_OPERAND_IS_PCRELATIVE,
2063    Operand_label8_encode, Operand_label8_decode,
2064    Operand_label8_ator, Operand_label8_rtoa },
2065  { "label12", FIELD_imm12, -1, 0,
2066    XTENSA_OPERAND_IS_PCRELATIVE,
2067    Operand_label12_encode, Operand_label12_decode,
2068    Operand_label12_ator, Operand_label12_rtoa },
2069  { "soffset", FIELD_offset, -1, 0,
2070    XTENSA_OPERAND_IS_PCRELATIVE,
2071    Operand_soffset_encode, Operand_soffset_decode,
2072    Operand_soffset_ator, Operand_soffset_rtoa },
2073  { "uimm16x4", FIELD_imm16, -1, 0,
2074    XTENSA_OPERAND_IS_PCRELATIVE,
2075    Operand_uimm16x4_encode, Operand_uimm16x4_decode,
2076    Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2077  { "immt", FIELD_t, -1, 0,
2078    0,
2079    Operand_immt_encode, Operand_immt_decode,
2080    0, 0 },
2081  { "imms", FIELD_s, -1, 0,
2082    0,
2083    Operand_imms_encode, Operand_imms_decode,
2084    0, 0 },
2085  { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
2086    XTENSA_OPERAND_IS_PCRELATIVE,
2087    Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
2088    Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
2089  { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
2090    XTENSA_OPERAND_IS_PCRELATIVE,
2091    Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
2092    Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
2093  { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2094  { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2095  { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
2096  { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2097  { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2098  { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
2099  { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2100  { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2101  { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2102  { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2103  { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2104  { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2105  { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2106  { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2107  { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2108  { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
2109  { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
2110  { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
2111  { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
2112  { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
2113  { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
2114  { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
2115  { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
2116  { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
2117  { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
2118  { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
2119  { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
2120  { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
2121  { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
2122  { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
2123  { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
2124  { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
2125  { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
2126  { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
2127  { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
2128  { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }
2129};
2130
2131enum xtensa_operand_id {
2132  OPERAND_art,
2133  OPERAND_ars,
2134  OPERAND__ars_invisible,
2135  OPERAND_arr,
2136  OPERAND_ar0,
2137  OPERAND_soffsetx4,
2138  OPERAND_lsi4x4,
2139  OPERAND_simm7,
2140  OPERAND_uimm6,
2141  OPERAND_ai4const,
2142  OPERAND_b4const,
2143  OPERAND_b4constu,
2144  OPERAND_uimm8,
2145  OPERAND_uimm8x2,
2146  OPERAND_uimm8x4,
2147  OPERAND_uimm4x16,
2148  OPERAND_simm8,
2149  OPERAND_simm8x256,
2150  OPERAND_simm12b,
2151  OPERAND_msalp32,
2152  OPERAND_op2p1,
2153  OPERAND_label8,
2154  OPERAND_label12,
2155  OPERAND_soffset,
2156  OPERAND_uimm16x4,
2157  OPERAND_immt,
2158  OPERAND_imms,
2159  OPERAND_xt_wbr15_label,
2160  OPERAND_xt_wbr18_label,
2161  OPERAND_t,
2162  OPERAND_bbi4,
2163  OPERAND_bbi,
2164  OPERAND_imm12,
2165  OPERAND_imm8,
2166  OPERAND_s,
2167  OPERAND_imm12b,
2168  OPERAND_imm16,
2169  OPERAND_m,
2170  OPERAND_n,
2171  OPERAND_offset,
2172  OPERAND_op0,
2173  OPERAND_op1,
2174  OPERAND_op2,
2175  OPERAND_r,
2176  OPERAND_sa4,
2177  OPERAND_sae4,
2178  OPERAND_sae,
2179  OPERAND_sal,
2180  OPERAND_sargt,
2181  OPERAND_sas4,
2182  OPERAND_sas,
2183  OPERAND_sr,
2184  OPERAND_st,
2185  OPERAND_thi3,
2186  OPERAND_imm4,
2187  OPERAND_i,
2188  OPERAND_imm6lo,
2189  OPERAND_imm6hi,
2190  OPERAND_imm7lo,
2191  OPERAND_imm7hi,
2192  OPERAND_z,
2193  OPERAND_imm6,
2194  OPERAND_imm7,
2195  OPERAND_xt_wbr15_imm,
2196  OPERAND_xt_wbr18_imm
2197};
2198
2199
2200/* Iclass table.  */
2201
2202static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
2203  { { STATE_PSEXCM }, 'o' },
2204  { { STATE_EPC1 }, 'i' }
2205};
2206
2207static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
2208  { { STATE_DEPC }, 'i' }
2209};
2210
2211static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
2212  { { OPERAND_arr }, 'o' },
2213  { { OPERAND_ars }, 'i' },
2214  { { OPERAND_art }, 'i' }
2215};
2216
2217static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
2218  { { OPERAND_arr }, 'o' },
2219  { { OPERAND_ars }, 'i' },
2220  { { OPERAND_ai4const }, 'i' }
2221};
2222
2223static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
2224  { { OPERAND_ars }, 'i' },
2225  { { OPERAND_uimm6 }, 'i' }
2226};
2227
2228static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
2229  { { OPERAND_art }, 'o' },
2230  { { OPERAND_ars }, 'i' },
2231  { { OPERAND_lsi4x4 }, 'i' }
2232};
2233
2234static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
2235  { { OPERAND_art }, 'o' },
2236  { { OPERAND_ars }, 'i' }
2237};
2238
2239static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
2240  { { OPERAND_ars }, 'o' },
2241  { { OPERAND_simm7 }, 'i' }
2242};
2243
2244static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
2245  { { OPERAND__ars_invisible }, 'i' }
2246};
2247
2248static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
2249  { { OPERAND_art }, 'i' },
2250  { { OPERAND_ars }, 'i' },
2251  { { OPERAND_lsi4x4 }, 'i' }
2252};
2253
2254static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
2255  { { OPERAND_art }, 'o' },
2256  { { OPERAND_ars }, 'i' },
2257  { { OPERAND_simm8 }, 'i' }
2258};
2259
2260static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
2261  { { OPERAND_art }, 'o' },
2262  { { OPERAND_ars }, 'i' },
2263  { { OPERAND_simm8x256 }, 'i' }
2264};
2265
2266static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
2267  { { OPERAND_arr }, 'o' },
2268  { { OPERAND_ars }, 'i' },
2269  { { OPERAND_art }, 'i' }
2270};
2271
2272static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
2273  { { OPERAND_arr }, 'o' },
2274  { { OPERAND_ars }, 'i' },
2275  { { OPERAND_art }, 'i' }
2276};
2277
2278static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
2279  { { OPERAND_ars }, 'i' },
2280  { { OPERAND_b4const }, 'i' },
2281  { { OPERAND_label8 }, 'i' }
2282};
2283
2284static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
2285  { { OPERAND_ars }, 'i' },
2286  { { OPERAND_bbi }, 'i' },
2287  { { OPERAND_label8 }, 'i' }
2288};
2289
2290static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
2291  { { OPERAND_ars }, 'i' },
2292  { { OPERAND_b4constu }, 'i' },
2293  { { OPERAND_label8 }, 'i' }
2294};
2295
2296static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
2297  { { OPERAND_ars }, 'i' },
2298  { { OPERAND_art }, 'i' },
2299  { { OPERAND_label8 }, 'i' }
2300};
2301
2302static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
2303  { { OPERAND_ars }, 'i' },
2304  { { OPERAND_label12 }, 'i' }
2305};
2306
2307static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
2308  { { OPERAND_soffsetx4 }, 'i' },
2309  { { OPERAND_ar0 }, 'o' }
2310};
2311
2312static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
2313  { { OPERAND_ars }, 'i' },
2314  { { OPERAND_ar0 }, 'o' }
2315};
2316
2317static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
2318  { { OPERAND_arr }, 'o' },
2319  { { OPERAND_art }, 'i' },
2320  { { OPERAND_sae }, 'i' },
2321  { { OPERAND_op2p1 }, 'i' }
2322};
2323
2324static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
2325  { { OPERAND_soffset }, 'i' }
2326};
2327
2328static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
2329  { { OPERAND_ars }, 'i' }
2330};
2331
2332static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
2333  { { OPERAND_art }, 'o' },
2334  { { OPERAND_ars }, 'i' },
2335  { { OPERAND_uimm8x2 }, 'i' }
2336};
2337
2338static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
2339  { { OPERAND_art }, 'o' },
2340  { { OPERAND_ars }, 'i' },
2341  { { OPERAND_uimm8x2 }, 'i' }
2342};
2343
2344static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
2345  { { OPERAND_art }, 'o' },
2346  { { OPERAND_ars }, 'i' },
2347  { { OPERAND_uimm8x4 }, 'i' }
2348};
2349
2350static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
2351  { { OPERAND_art }, 'o' },
2352  { { OPERAND_uimm16x4 }, 'i' }
2353};
2354
2355static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
2356  { { STATE_LITBADDR }, 'i' },
2357  { { STATE_LITBEN }, 'i' }
2358};
2359
2360static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
2361  { { OPERAND_art }, 'o' },
2362  { { OPERAND_ars }, 'i' },
2363  { { OPERAND_uimm8 }, 'i' }
2364};
2365
2366static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
2367  { { OPERAND_art }, 'o' },
2368  { { OPERAND_simm12b }, 'i' }
2369};
2370
2371static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
2372  { { OPERAND_arr }, 'm' },
2373  { { OPERAND_ars }, 'i' },
2374  { { OPERAND_art }, 'i' }
2375};
2376
2377static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
2378  { { OPERAND_arr }, 'o' },
2379  { { OPERAND_art }, 'i' }
2380};
2381
2382static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
2383  { { OPERAND__ars_invisible }, 'i' }
2384};
2385
2386static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
2387  { { OPERAND_art }, 'i' },
2388  { { OPERAND_ars }, 'i' },
2389  { { OPERAND_uimm8x2 }, 'i' }
2390};
2391
2392static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
2393  { { OPERAND_art }, 'i' },
2394  { { OPERAND_ars }, 'i' },
2395  { { OPERAND_uimm8x4 }, 'i' }
2396};
2397
2398static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
2399  { { OPERAND_art }, 'i' },
2400  { { OPERAND_ars }, 'i' },
2401  { { OPERAND_uimm8 }, 'i' }
2402};
2403
2404static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
2405  { { OPERAND_ars }, 'i' }
2406};
2407
2408static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
2409  { { STATE_SAR }, 'o' }
2410};
2411
2412static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
2413  { { OPERAND_sas }, 'i' }
2414};
2415
2416static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
2417  { { STATE_SAR }, 'o' }
2418};
2419
2420static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
2421  { { OPERAND_arr }, 'o' },
2422  { { OPERAND_ars }, 'i' }
2423};
2424
2425static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
2426  { { STATE_SAR }, 'i' }
2427};
2428
2429static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
2430  { { OPERAND_arr }, 'o' },
2431  { { OPERAND_ars }, 'i' },
2432  { { OPERAND_art }, 'i' }
2433};
2434
2435static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
2436  { { STATE_SAR }, 'i' }
2437};
2438
2439static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
2440  { { OPERAND_arr }, 'o' },
2441  { { OPERAND_art }, 'i' }
2442};
2443
2444static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
2445  { { STATE_SAR }, 'i' }
2446};
2447
2448static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
2449  { { OPERAND_arr }, 'o' },
2450  { { OPERAND_ars }, 'i' },
2451  { { OPERAND_msalp32 }, 'i' }
2452};
2453
2454static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
2455  { { OPERAND_arr }, 'o' },
2456  { { OPERAND_art }, 'i' },
2457  { { OPERAND_sargt }, 'i' }
2458};
2459
2460static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
2461  { { OPERAND_arr }, 'o' },
2462  { { OPERAND_art }, 'i' },
2463  { { OPERAND_s }, 'i' }
2464};
2465
2466static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
2467  { { STATE_XTSYNC }, 'i' }
2468};
2469
2470static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
2471  { { OPERAND_art }, 'o' },
2472  { { OPERAND_s }, 'i' }
2473};
2474
2475static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
2476  { { STATE_PSUM }, 'i' },
2477  { { STATE_PSEXCM }, 'i' },
2478  { { STATE_PSINTLEVEL }, 'm' }
2479};
2480
2481static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
2482  { { OPERAND_art }, 'o' }
2483};
2484
2485static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
2486  { { STATE_SAR }, 'i' }
2487};
2488
2489static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
2490  { { OPERAND_art }, 'i' }
2491};
2492
2493static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
2494  { { STATE_SAR }, 'o' },
2495  { { STATE_XTSYNC }, 'o' }
2496};
2497
2498static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
2499  { { OPERAND_art }, 'm' }
2500};
2501
2502static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
2503  { { STATE_SAR }, 'm' }
2504};
2505
2506static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
2507  { { OPERAND_art }, 'o' }
2508};
2509
2510static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
2511  { { STATE_LITBADDR }, 'i' },
2512  { { STATE_LITBEN }, 'i' }
2513};
2514
2515static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
2516  { { OPERAND_art }, 'i' }
2517};
2518
2519static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
2520  { { STATE_LITBADDR }, 'o' },
2521  { { STATE_LITBEN }, 'o' }
2522};
2523
2524static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
2525  { { OPERAND_art }, 'm' }
2526};
2527
2528static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
2529  { { STATE_LITBADDR }, 'm' },
2530  { { STATE_LITBEN }, 'm' }
2531};
2532
2533static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
2534  { { OPERAND_art }, 'o' }
2535};
2536
2537static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
2538  { { OPERAND_art }, 'i' }
2539};
2540
2541static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
2542  { { OPERAND_art }, 'o' }
2543};
2544
2545static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
2546  { { OPERAND_art }, 'o' }
2547};
2548
2549static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
2550  { { STATE_PSUM }, 'i' },
2551  { { STATE_PSEXCM }, 'i' },
2552  { { STATE_PSINTLEVEL }, 'i' }
2553};
2554
2555static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
2556  { { OPERAND_art }, 'i' }
2557};
2558
2559static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
2560  { { STATE_PSUM }, 'o' },
2561  { { STATE_PSEXCM }, 'o' },
2562  { { STATE_PSINTLEVEL }, 'o' }
2563};
2564
2565static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
2566  { { OPERAND_art }, 'm' }
2567};
2568
2569static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
2570  { { STATE_PSUM }, 'm' },
2571  { { STATE_PSEXCM }, 'm' },
2572  { { STATE_PSINTLEVEL }, 'm' }
2573};
2574
2575static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
2576  { { OPERAND_art }, 'o' }
2577};
2578
2579static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
2580  { { STATE_EPC1 }, 'i' }
2581};
2582
2583static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
2584  { { OPERAND_art }, 'i' }
2585};
2586
2587static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
2588  { { STATE_EPC1 }, 'o' }
2589};
2590
2591static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
2592  { { OPERAND_art }, 'm' }
2593};
2594
2595static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
2596  { { STATE_EPC1 }, 'm' }
2597};
2598
2599static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
2600  { { OPERAND_art }, 'o' }
2601};
2602
2603static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
2604  { { STATE_EXCSAVE1 }, 'i' }
2605};
2606
2607static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
2608  { { OPERAND_art }, 'i' }
2609};
2610
2611static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
2612  { { STATE_EXCSAVE1 }, 'o' }
2613};
2614
2615static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
2616  { { OPERAND_art }, 'm' }
2617};
2618
2619static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
2620  { { STATE_EXCSAVE1 }, 'm' }
2621};
2622
2623static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
2624  { { OPERAND_art }, 'o' }
2625};
2626
2627static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
2628  { { STATE_EPC2 }, 'i' }
2629};
2630
2631static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
2632  { { OPERAND_art }, 'i' }
2633};
2634
2635static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
2636  { { STATE_EPC2 }, 'o' }
2637};
2638
2639static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
2640  { { OPERAND_art }, 'm' }
2641};
2642
2643static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
2644  { { STATE_EPC2 }, 'm' }
2645};
2646
2647static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
2648  { { OPERAND_art }, 'o' }
2649};
2650
2651static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
2652  { { STATE_EXCSAVE2 }, 'i' }
2653};
2654
2655static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
2656  { { OPERAND_art }, 'i' }
2657};
2658
2659static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
2660  { { STATE_EXCSAVE2 }, 'o' }
2661};
2662
2663static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
2664  { { OPERAND_art }, 'm' }
2665};
2666
2667static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
2668  { { STATE_EXCSAVE2 }, 'm' }
2669};
2670
2671static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
2672  { { OPERAND_art }, 'o' }
2673};
2674
2675static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
2676  { { STATE_EPC3 }, 'i' }
2677};
2678
2679static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
2680  { { OPERAND_art }, 'i' }
2681};
2682
2683static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
2684  { { STATE_EPC3 }, 'o' }
2685};
2686
2687static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
2688  { { OPERAND_art }, 'm' }
2689};
2690
2691static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
2692  { { STATE_EPC3 }, 'm' }
2693};
2694
2695static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
2696  { { OPERAND_art }, 'o' }
2697};
2698
2699static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
2700  { { STATE_EXCSAVE3 }, 'i' }
2701};
2702
2703static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
2704  { { OPERAND_art }, 'i' }
2705};
2706
2707static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
2708  { { STATE_EXCSAVE3 }, 'o' }
2709};
2710
2711static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
2712  { { OPERAND_art }, 'm' }
2713};
2714
2715static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
2716  { { STATE_EXCSAVE3 }, 'm' }
2717};
2718
2719static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
2720  { { OPERAND_art }, 'o' }
2721};
2722
2723static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
2724  { { STATE_EPS2 }, 'i' }
2725};
2726
2727static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
2728  { { OPERAND_art }, 'i' }
2729};
2730
2731static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
2732  { { STATE_EPS2 }, 'o' }
2733};
2734
2735static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
2736  { { OPERAND_art }, 'm' }
2737};
2738
2739static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
2740  { { STATE_EPS2 }, 'm' }
2741};
2742
2743static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
2744  { { OPERAND_art }, 'o' }
2745};
2746
2747static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
2748  { { STATE_EPS3 }, 'i' }
2749};
2750
2751static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
2752  { { OPERAND_art }, 'i' }
2753};
2754
2755static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
2756  { { STATE_EPS3 }, 'o' }
2757};
2758
2759static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
2760  { { OPERAND_art }, 'm' }
2761};
2762
2763static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
2764  { { STATE_EPS3 }, 'm' }
2765};
2766
2767static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
2768  { { OPERAND_art }, 'o' }
2769};
2770
2771static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
2772  { { STATE_EXCVADDR }, 'i' }
2773};
2774
2775static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
2776  { { OPERAND_art }, 'i' }
2777};
2778
2779static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
2780  { { STATE_EXCVADDR }, 'o' }
2781};
2782
2783static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
2784  { { OPERAND_art }, 'm' }
2785};
2786
2787static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
2788  { { STATE_EXCVADDR }, 'm' }
2789};
2790
2791static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
2792  { { OPERAND_art }, 'o' }
2793};
2794
2795static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
2796  { { STATE_DEPC }, 'i' }
2797};
2798
2799static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
2800  { { OPERAND_art }, 'i' }
2801};
2802
2803static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
2804  { { STATE_DEPC }, 'o' }
2805};
2806
2807static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
2808  { { OPERAND_art }, 'm' }
2809};
2810
2811static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
2812  { { STATE_DEPC }, 'm' }
2813};
2814
2815static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
2816  { { OPERAND_art }, 'o' }
2817};
2818
2819static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
2820  { { STATE_EXCCAUSE }, 'i' },
2821  { { STATE_XTSYNC }, 'i' }
2822};
2823
2824static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
2825  { { OPERAND_art }, 'i' }
2826};
2827
2828static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
2829  { { STATE_EXCCAUSE }, 'o' }
2830};
2831
2832static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
2833  { { OPERAND_art }, 'm' }
2834};
2835
2836static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
2837  { { STATE_EXCCAUSE }, 'm' }
2838};
2839
2840static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
2841  { { OPERAND_art }, 'o' }
2842};
2843
2844static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
2845  { { OPERAND_art }, 'o' }
2846};
2847
2848static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
2849  { { STATE_VECBASE }, 'i' }
2850};
2851
2852static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
2853  { { OPERAND_art }, 'i' }
2854};
2855
2856static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
2857  { { STATE_VECBASE }, 'o' }
2858};
2859
2860static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
2861  { { OPERAND_art }, 'm' }
2862};
2863
2864static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
2865  { { STATE_VECBASE }, 'm' }
2866};
2867
2868static xtensa_arg_internal Iclass_xt_mul16_args[] = {
2869  { { OPERAND_arr }, 'o' },
2870  { { OPERAND_ars }, 'i' },
2871  { { OPERAND_art }, 'i' }
2872};
2873
2874static xtensa_arg_internal Iclass_xt_mul32_args[] = {
2875  { { OPERAND_arr }, 'o' },
2876  { { OPERAND_ars }, 'i' },
2877  { { OPERAND_art }, 'i' }
2878};
2879
2880static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
2881  { { OPERAND_s }, 'i' }
2882};
2883
2884static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
2885  { { STATE_PSUM }, 'o' },
2886  { { STATE_PSEXCM }, 'o' },
2887  { { STATE_PSINTLEVEL }, 'o' },
2888  { { STATE_EPC1 }, 'i' },
2889  { { STATE_EPC2 }, 'i' },
2890  { { STATE_EPC3 }, 'i' },
2891  { { STATE_EPS2 }, 'i' },
2892  { { STATE_EPS3 }, 'i' },
2893  { { STATE_InOCDMode }, 'm' }
2894};
2895
2896static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
2897  { { OPERAND_s }, 'i' }
2898};
2899
2900static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
2901  { { STATE_PSINTLEVEL }, 'o' }
2902};
2903
2904static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
2905  { { OPERAND_art }, 'o' }
2906};
2907
2908static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
2909  { { STATE_INTERRUPT }, 'i' }
2910};
2911
2912static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
2913  { { OPERAND_art }, 'i' }
2914};
2915
2916static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
2917  { { STATE_XTSYNC }, 'o' },
2918  { { STATE_INTERRUPT }, 'm' }
2919};
2920
2921static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
2922  { { OPERAND_art }, 'i' }
2923};
2924
2925static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
2926  { { STATE_XTSYNC }, 'o' },
2927  { { STATE_INTERRUPT }, 'm' }
2928};
2929
2930static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
2931  { { OPERAND_art }, 'o' }
2932};
2933
2934static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
2935  { { STATE_INTENABLE }, 'i' }
2936};
2937
2938static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
2939  { { OPERAND_art }, 'i' }
2940};
2941
2942static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
2943  { { STATE_INTENABLE }, 'o' }
2944};
2945
2946static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
2947  { { OPERAND_art }, 'm' }
2948};
2949
2950static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
2951  { { STATE_INTENABLE }, 'm' }
2952};
2953
2954static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
2955  { { OPERAND_imms }, 'i' },
2956  { { OPERAND_immt }, 'i' }
2957};
2958
2959static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
2960  { { STATE_PSEXCM }, 'i' },
2961  { { STATE_PSINTLEVEL }, 'i' }
2962};
2963
2964static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
2965  { { OPERAND_imms }, 'i' }
2966};
2967
2968static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
2969  { { STATE_PSEXCM }, 'i' },
2970  { { STATE_PSINTLEVEL }, 'i' }
2971};
2972
2973static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
2974  { { OPERAND_art }, 'o' }
2975};
2976
2977static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
2978  { { STATE_DBREAKA0 }, 'i' }
2979};
2980
2981static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
2982  { { OPERAND_art }, 'i' }
2983};
2984
2985static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
2986  { { STATE_DBREAKA0 }, 'o' },
2987  { { STATE_XTSYNC }, 'o' }
2988};
2989
2990static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
2991  { { OPERAND_art }, 'm' }
2992};
2993
2994static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
2995  { { STATE_DBREAKA0 }, 'm' },
2996  { { STATE_XTSYNC }, 'o' }
2997};
2998
2999static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
3000  { { OPERAND_art }, 'o' }
3001};
3002
3003static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
3004  { { STATE_DBREAKC0 }, 'i' }
3005};
3006
3007static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
3008  { { OPERAND_art }, 'i' }
3009};
3010
3011static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
3012  { { STATE_DBREAKC0 }, 'o' },
3013  { { STATE_XTSYNC }, 'o' }
3014};
3015
3016static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
3017  { { OPERAND_art }, 'm' }
3018};
3019
3020static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
3021  { { STATE_DBREAKC0 }, 'm' },
3022  { { STATE_XTSYNC }, 'o' }
3023};
3024
3025static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
3026  { { OPERAND_art }, 'o' }
3027};
3028
3029static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
3030  { { STATE_IBREAKA0 }, 'i' }
3031};
3032
3033static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
3034  { { OPERAND_art }, 'i' }
3035};
3036
3037static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
3038  { { STATE_IBREAKA0 }, 'o' }
3039};
3040
3041static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
3042  { { OPERAND_art }, 'm' }
3043};
3044
3045static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
3046  { { STATE_IBREAKA0 }, 'm' }
3047};
3048
3049static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
3050  { { OPERAND_art }, 'o' }
3051};
3052
3053static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
3054  { { STATE_IBREAKENABLE }, 'i' }
3055};
3056
3057static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
3058  { { OPERAND_art }, 'i' }
3059};
3060
3061static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
3062  { { STATE_IBREAKENABLE }, 'o' }
3063};
3064
3065static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
3066  { { OPERAND_art }, 'm' }
3067};
3068
3069static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
3070  { { STATE_IBREAKENABLE }, 'm' }
3071};
3072
3073static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
3074  { { OPERAND_art }, 'o' }
3075};
3076
3077static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
3078  { { STATE_DEBUGCAUSE }, 'i' },
3079  { { STATE_DBNUM }, 'i' }
3080};
3081
3082static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
3083  { { OPERAND_art }, 'i' }
3084};
3085
3086static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
3087  { { STATE_DEBUGCAUSE }, 'o' },
3088  { { STATE_DBNUM }, 'o' }
3089};
3090
3091static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
3092  { { OPERAND_art }, 'm' }
3093};
3094
3095static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
3096  { { STATE_DEBUGCAUSE }, 'm' },
3097  { { STATE_DBNUM }, 'm' }
3098};
3099
3100static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
3101  { { OPERAND_art }, 'o' }
3102};
3103
3104static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
3105  { { STATE_ICOUNT }, 'i' }
3106};
3107
3108static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
3109  { { OPERAND_art }, 'i' }
3110};
3111
3112static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
3113  { { STATE_XTSYNC }, 'o' },
3114  { { STATE_ICOUNT }, 'o' }
3115};
3116
3117static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
3118  { { OPERAND_art }, 'm' }
3119};
3120
3121static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
3122  { { STATE_XTSYNC }, 'o' },
3123  { { STATE_ICOUNT }, 'm' }
3124};
3125
3126static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
3127  { { OPERAND_art }, 'o' }
3128};
3129
3130static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
3131  { { STATE_ICOUNTLEVEL }, 'i' }
3132};
3133
3134static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
3135  { { OPERAND_art }, 'i' }
3136};
3137
3138static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
3139  { { STATE_ICOUNTLEVEL }, 'o' }
3140};
3141
3142static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
3143  { { OPERAND_art }, 'm' }
3144};
3145
3146static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
3147  { { STATE_ICOUNTLEVEL }, 'm' }
3148};
3149
3150static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
3151  { { OPERAND_art }, 'o' }
3152};
3153
3154static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
3155  { { STATE_DDR }, 'i' }
3156};
3157
3158static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
3159  { { OPERAND_art }, 'i' }
3160};
3161
3162static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
3163  { { STATE_XTSYNC }, 'o' },
3164  { { STATE_DDR }, 'o' }
3165};
3166
3167static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
3168  { { OPERAND_art }, 'm' }
3169};
3170
3171static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
3172  { { STATE_XTSYNC }, 'o' },
3173  { { STATE_DDR }, 'm' }
3174};
3175
3176static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
3177  { { OPERAND_imms }, 'i' }
3178};
3179
3180static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
3181  { { STATE_InOCDMode }, 'm' },
3182  { { STATE_EPC2 }, 'i' },
3183  { { STATE_PSUM }, 'o' },
3184  { { STATE_PSEXCM }, 'o' },
3185  { { STATE_PSINTLEVEL }, 'o' },
3186  { { STATE_EPS2 }, 'i' }
3187};
3188
3189static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
3190  { { STATE_InOCDMode }, 'm' }
3191};
3192
3193static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
3194  { { OPERAND_art }, 'i' }
3195};
3196
3197static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
3198  { { STATE_XTSYNC }, 'o' }
3199};
3200
3201static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
3202  { { OPERAND_art }, 'o' }
3203};
3204
3205static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
3206  { { STATE_CCOUNT }, 'i' }
3207};
3208
3209static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
3210  { { OPERAND_art }, 'i' }
3211};
3212
3213static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
3214  { { STATE_XTSYNC }, 'o' },
3215  { { STATE_CCOUNT }, 'o' }
3216};
3217
3218static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
3219  { { OPERAND_art }, 'm' }
3220};
3221
3222static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
3223  { { STATE_XTSYNC }, 'o' },
3224  { { STATE_CCOUNT }, 'm' }
3225};
3226
3227static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
3228  { { OPERAND_art }, 'o' }
3229};
3230
3231static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
3232  { { STATE_CCOMPARE0 }, 'i' }
3233};
3234
3235static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
3236  { { OPERAND_art }, 'i' }
3237};
3238
3239static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
3240  { { STATE_CCOMPARE0 }, 'o' },
3241  { { STATE_INTERRUPT }, 'm' }
3242};
3243
3244static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
3245  { { OPERAND_art }, 'm' }
3246};
3247
3248static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
3249  { { STATE_CCOMPARE0 }, 'm' },
3250  { { STATE_INTERRUPT }, 'm' }
3251};
3252
3253static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
3254  { { OPERAND_ars }, 'i' }
3255};
3256
3257static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
3258  { { STATE_XTSYNC }, 'o' }
3259};
3260
3261static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
3262  { { OPERAND_art }, 'o' },
3263  { { OPERAND_ars }, 'i' }
3264};
3265
3266static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
3267  { { OPERAND_art }, 'i' },
3268  { { OPERAND_ars }, 'i' }
3269};
3270
3271static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
3272  { { STATE_XTSYNC }, 'o' }
3273};
3274
3275static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
3276  { { OPERAND_ars }, 'i' }
3277};
3278
3279static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
3280  { { OPERAND_art }, 'o' },
3281  { { OPERAND_ars }, 'i' }
3282};
3283
3284static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
3285  { { OPERAND_art }, 'i' },
3286  { { OPERAND_ars }, 'i' }
3287};
3288
3289static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
3290  { { OPERAND_art }, 'o' },
3291  { { OPERAND_ars }, 'i' }
3292};
3293
3294static xtensa_iclass_internal iclasses[] = {
3295  { 0, 0 /* xt_iclass_excw */,
3296    0, 0, 0, 0 },
3297  { 0, 0 /* xt_iclass_rfe */,
3298    2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
3299  { 0, 0 /* xt_iclass_rfde */,
3300    1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
3301  { 0, 0 /* xt_iclass_syscall */,
3302    0, 0, 0, 0 },
3303  { 0, 0 /* xt_iclass_simcall */,
3304    0, 0, 0, 0 },
3305  { 3, Iclass_xt_iclass_add_n_args,
3306    0, 0, 0, 0 },
3307  { 3, Iclass_xt_iclass_addi_n_args,
3308    0, 0, 0, 0 },
3309  { 2, Iclass_xt_iclass_bz6_args,
3310    0, 0, 0, 0 },
3311  { 0, 0 /* xt_iclass_ill_n */,
3312    0, 0, 0, 0 },
3313  { 3, Iclass_xt_iclass_loadi4_args,
3314    0, 0, 0, 0 },
3315  { 2, Iclass_xt_iclass_mov_n_args,
3316    0, 0, 0, 0 },
3317  { 2, Iclass_xt_iclass_movi_n_args,
3318    0, 0, 0, 0 },
3319  { 0, 0 /* xt_iclass_nopn */,
3320    0, 0, 0, 0 },
3321  { 1, Iclass_xt_iclass_retn_args,
3322    0, 0, 0, 0 },
3323  { 3, Iclass_xt_iclass_storei4_args,
3324    0, 0, 0, 0 },
3325  { 3, Iclass_xt_iclass_addi_args,
3326    0, 0, 0, 0 },
3327  { 3, Iclass_xt_iclass_addmi_args,
3328    0, 0, 0, 0 },
3329  { 3, Iclass_xt_iclass_addsub_args,
3330    0, 0, 0, 0 },
3331  { 3, Iclass_xt_iclass_bit_args,
3332    0, 0, 0, 0 },
3333  { 3, Iclass_xt_iclass_bsi8_args,
3334    0, 0, 0, 0 },
3335  { 3, Iclass_xt_iclass_bsi8b_args,
3336    0, 0, 0, 0 },
3337  { 3, Iclass_xt_iclass_bsi8u_args,
3338    0, 0, 0, 0 },
3339  { 3, Iclass_xt_iclass_bst8_args,
3340    0, 0, 0, 0 },
3341  { 2, Iclass_xt_iclass_bsz12_args,
3342    0, 0, 0, 0 },
3343  { 2, Iclass_xt_iclass_call0_args,
3344    0, 0, 0, 0 },
3345  { 2, Iclass_xt_iclass_callx0_args,
3346    0, 0, 0, 0 },
3347  { 4, Iclass_xt_iclass_exti_args,
3348    0, 0, 0, 0 },
3349  { 0, 0 /* xt_iclass_ill */,
3350    0, 0, 0, 0 },
3351  { 1, Iclass_xt_iclass_jump_args,
3352    0, 0, 0, 0 },
3353  { 1, Iclass_xt_iclass_jumpx_args,
3354    0, 0, 0, 0 },
3355  { 3, Iclass_xt_iclass_l16ui_args,
3356    0, 0, 0, 0 },
3357  { 3, Iclass_xt_iclass_l16si_args,
3358    0, 0, 0, 0 },
3359  { 3, Iclass_xt_iclass_l32i_args,
3360    0, 0, 0, 0 },
3361  { 2, Iclass_xt_iclass_l32r_args,
3362    2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
3363  { 3, Iclass_xt_iclass_l8i_args,
3364    0, 0, 0, 0 },
3365  { 2, Iclass_xt_iclass_movi_args,
3366    0, 0, 0, 0 },
3367  { 3, Iclass_xt_iclass_movz_args,
3368    0, 0, 0, 0 },
3369  { 2, Iclass_xt_iclass_neg_args,
3370    0, 0, 0, 0 },
3371  { 0, 0 /* xt_iclass_nop */,
3372    0, 0, 0, 0 },
3373  { 1, Iclass_xt_iclass_return_args,
3374    0, 0, 0, 0 },
3375  { 3, Iclass_xt_iclass_s16i_args,
3376    0, 0, 0, 0 },
3377  { 3, Iclass_xt_iclass_s32i_args,
3378    0, 0, 0, 0 },
3379  { 3, Iclass_xt_iclass_s8i_args,
3380    0, 0, 0, 0 },
3381  { 1, Iclass_xt_iclass_sar_args,
3382    1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
3383  { 1, Iclass_xt_iclass_sari_args,
3384    1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
3385  { 2, Iclass_xt_iclass_shifts_args,
3386    1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
3387  { 3, Iclass_xt_iclass_shiftst_args,
3388    1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
3389  { 2, Iclass_xt_iclass_shiftt_args,
3390    1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
3391  { 3, Iclass_xt_iclass_slli_args,
3392    0, 0, 0, 0 },
3393  { 3, Iclass_xt_iclass_srai_args,
3394    0, 0, 0, 0 },
3395  { 3, Iclass_xt_iclass_srli_args,
3396    0, 0, 0, 0 },
3397  { 0, 0 /* xt_iclass_memw */,
3398    0, 0, 0, 0 },
3399  { 0, 0 /* xt_iclass_extw */,
3400    0, 0, 0, 0 },
3401  { 0, 0 /* xt_iclass_isync */,
3402    0, 0, 0, 0 },
3403  { 0, 0 /* xt_iclass_sync */,
3404    1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
3405  { 2, Iclass_xt_iclass_rsil_args,
3406    3, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
3407  { 1, Iclass_xt_iclass_rsr_sar_args,
3408    1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
3409  { 1, Iclass_xt_iclass_wsr_sar_args,
3410    2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
3411  { 1, Iclass_xt_iclass_xsr_sar_args,
3412    1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
3413  { 1, Iclass_xt_iclass_rsr_litbase_args,
3414    2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
3415  { 1, Iclass_xt_iclass_wsr_litbase_args,
3416    2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
3417  { 1, Iclass_xt_iclass_xsr_litbase_args,
3418    2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
3419  { 1, Iclass_xt_iclass_rsr_176_args,
3420    0, 0, 0, 0 },
3421  { 1, Iclass_xt_iclass_wsr_176_args,
3422    0, 0, 0, 0 },
3423  { 1, Iclass_xt_iclass_rsr_208_args,
3424    0, 0, 0, 0 },
3425  { 1, Iclass_xt_iclass_rsr_ps_args,
3426    3, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
3427  { 1, Iclass_xt_iclass_wsr_ps_args,
3428    3, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
3429  { 1, Iclass_xt_iclass_xsr_ps_args,
3430    3, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
3431  { 1, Iclass_xt_iclass_rsr_epc1_args,
3432    1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
3433  { 1, Iclass_xt_iclass_wsr_epc1_args,
3434    1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
3435  { 1, Iclass_xt_iclass_xsr_epc1_args,
3436    1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
3437  { 1, Iclass_xt_iclass_rsr_excsave1_args,
3438    1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
3439  { 1, Iclass_xt_iclass_wsr_excsave1_args,
3440    1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
3441  { 1, Iclass_xt_iclass_xsr_excsave1_args,
3442    1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
3443  { 1, Iclass_xt_iclass_rsr_epc2_args,
3444    1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
3445  { 1, Iclass_xt_iclass_wsr_epc2_args,
3446    1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
3447  { 1, Iclass_xt_iclass_xsr_epc2_args,
3448    1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
3449  { 1, Iclass_xt_iclass_rsr_excsave2_args,
3450    1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
3451  { 1, Iclass_xt_iclass_wsr_excsave2_args,
3452    1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
3453  { 1, Iclass_xt_iclass_xsr_excsave2_args,
3454    1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
3455  { 1, Iclass_xt_iclass_rsr_epc3_args,
3456    1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
3457  { 1, Iclass_xt_iclass_wsr_epc3_args,
3458    1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
3459  { 1, Iclass_xt_iclass_xsr_epc3_args,
3460    1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
3461  { 1, Iclass_xt_iclass_rsr_excsave3_args,
3462    1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
3463  { 1, Iclass_xt_iclass_wsr_excsave3_args,
3464    1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
3465  { 1, Iclass_xt_iclass_xsr_excsave3_args,
3466    1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
3467  { 1, Iclass_xt_iclass_rsr_eps2_args,
3468    1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
3469  { 1, Iclass_xt_iclass_wsr_eps2_args,
3470    1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
3471  { 1, Iclass_xt_iclass_xsr_eps2_args,
3472    1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
3473  { 1, Iclass_xt_iclass_rsr_eps3_args,
3474    1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
3475  { 1, Iclass_xt_iclass_wsr_eps3_args,
3476    1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
3477  { 1, Iclass_xt_iclass_xsr_eps3_args,
3478    1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
3479  { 1, Iclass_xt_iclass_rsr_excvaddr_args,
3480    1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
3481  { 1, Iclass_xt_iclass_wsr_excvaddr_args,
3482    1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
3483  { 1, Iclass_xt_iclass_xsr_excvaddr_args,
3484    1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
3485  { 1, Iclass_xt_iclass_rsr_depc_args,
3486    1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
3487  { 1, Iclass_xt_iclass_wsr_depc_args,
3488    1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
3489  { 1, Iclass_xt_iclass_xsr_depc_args,
3490    1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
3491  { 1, Iclass_xt_iclass_rsr_exccause_args,
3492    2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
3493  { 1, Iclass_xt_iclass_wsr_exccause_args,
3494    1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
3495  { 1, Iclass_xt_iclass_xsr_exccause_args,
3496    1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
3497  { 1, Iclass_xt_iclass_rsr_prid_args,
3498    0, 0, 0, 0 },
3499  { 1, Iclass_xt_iclass_rsr_vecbase_args,
3500    1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
3501  { 1, Iclass_xt_iclass_wsr_vecbase_args,
3502    1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
3503  { 1, Iclass_xt_iclass_xsr_vecbase_args,
3504    1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
3505  { 3, Iclass_xt_mul16_args,
3506    0, 0, 0, 0 },
3507  { 3, Iclass_xt_mul32_args,
3508    0, 0, 0, 0 },
3509  { 1, Iclass_xt_iclass_rfi_args,
3510    9, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
3511  { 1, Iclass_xt_iclass_wait_args,
3512    1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
3513  { 1, Iclass_xt_iclass_rsr_interrupt_args,
3514    1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
3515  { 1, Iclass_xt_iclass_wsr_intset_args,
3516    2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
3517  { 1, Iclass_xt_iclass_wsr_intclear_args,
3518    2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
3519  { 1, Iclass_xt_iclass_rsr_intenable_args,
3520    1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
3521  { 1, Iclass_xt_iclass_wsr_intenable_args,
3522    1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
3523  { 1, Iclass_xt_iclass_xsr_intenable_args,
3524    1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
3525  { 2, Iclass_xt_iclass_break_args,
3526    2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
3527  { 1, Iclass_xt_iclass_break_n_args,
3528    2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
3529  { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
3530    1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
3531  { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
3532    2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
3533  { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
3534    2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
3535  { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
3536    1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
3537  { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
3538    2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
3539  { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
3540    2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
3541  { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
3542    1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
3543  { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
3544    1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
3545  { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
3546    1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
3547  { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
3548    1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
3549  { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
3550    1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
3551  { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
3552    1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
3553  { 1, Iclass_xt_iclass_rsr_debugcause_args,
3554    2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
3555  { 1, Iclass_xt_iclass_wsr_debugcause_args,
3556    2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
3557  { 1, Iclass_xt_iclass_xsr_debugcause_args,
3558    2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
3559  { 1, Iclass_xt_iclass_rsr_icount_args,
3560    1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
3561  { 1, Iclass_xt_iclass_wsr_icount_args,
3562    2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
3563  { 1, Iclass_xt_iclass_xsr_icount_args,
3564    2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
3565  { 1, Iclass_xt_iclass_rsr_icountlevel_args,
3566    1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
3567  { 1, Iclass_xt_iclass_wsr_icountlevel_args,
3568    1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
3569  { 1, Iclass_xt_iclass_xsr_icountlevel_args,
3570    1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
3571  { 1, Iclass_xt_iclass_rsr_ddr_args,
3572    1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
3573  { 1, Iclass_xt_iclass_wsr_ddr_args,
3574    2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
3575  { 1, Iclass_xt_iclass_xsr_ddr_args,
3576    2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
3577  { 1, Iclass_xt_iclass_rfdo_args,
3578    6, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
3579  { 0, 0 /* xt_iclass_rfdd */,
3580    1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
3581  { 1, Iclass_xt_iclass_wsr_mmid_args,
3582    1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
3583  { 1, Iclass_xt_iclass_rsr_ccount_args,
3584    1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
3585  { 1, Iclass_xt_iclass_wsr_ccount_args,
3586    2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
3587  { 1, Iclass_xt_iclass_xsr_ccount_args,
3588    2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
3589  { 1, Iclass_xt_iclass_rsr_ccompare0_args,
3590    1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
3591  { 1, Iclass_xt_iclass_wsr_ccompare0_args,
3592    2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
3593  { 1, Iclass_xt_iclass_xsr_ccompare0_args,
3594    2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
3595  { 1, Iclass_xt_iclass_idtlb_args,
3596    1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
3597  { 2, Iclass_xt_iclass_rdtlb_args,
3598    0, 0, 0, 0 },
3599  { 2, Iclass_xt_iclass_wdtlb_args,
3600    1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
3601  { 1, Iclass_xt_iclass_iitlb_args,
3602    0, 0, 0, 0 },
3603  { 2, Iclass_xt_iclass_ritlb_args,
3604    0, 0, 0, 0 },
3605  { 2, Iclass_xt_iclass_witlb_args,
3606    0, 0, 0, 0 },
3607  { 2, Iclass_xt_iclass_nsa_args,
3608    0, 0, 0, 0 },
3609  { 0, 0 /* xt_iclass_rer */,
3610    0, 0, 0, 0 },
3611  { 0, 0 /* xt_iclass_wer */,
3612    0, 0, 0, 0 }
3613};
3614
3615enum xtensa_iclass_id {
3616  ICLASS_xt_iclass_excw,
3617  ICLASS_xt_iclass_rfe,
3618  ICLASS_xt_iclass_rfde,
3619  ICLASS_xt_iclass_syscall,
3620  ICLASS_xt_iclass_simcall,
3621  ICLASS_xt_iclass_add_n,
3622  ICLASS_xt_iclass_addi_n,
3623  ICLASS_xt_iclass_bz6,
3624  ICLASS_xt_iclass_ill_n,
3625  ICLASS_xt_iclass_loadi4,
3626  ICLASS_xt_iclass_mov_n,
3627  ICLASS_xt_iclass_movi_n,
3628  ICLASS_xt_iclass_nopn,
3629  ICLASS_xt_iclass_retn,
3630  ICLASS_xt_iclass_storei4,
3631  ICLASS_xt_iclass_addi,
3632  ICLASS_xt_iclass_addmi,
3633  ICLASS_xt_iclass_addsub,
3634  ICLASS_xt_iclass_bit,
3635  ICLASS_xt_iclass_bsi8,
3636  ICLASS_xt_iclass_bsi8b,
3637  ICLASS_xt_iclass_bsi8u,
3638  ICLASS_xt_iclass_bst8,
3639  ICLASS_xt_iclass_bsz12,
3640  ICLASS_xt_iclass_call0,
3641  ICLASS_xt_iclass_callx0,
3642  ICLASS_xt_iclass_exti,
3643  ICLASS_xt_iclass_ill,
3644  ICLASS_xt_iclass_jump,
3645  ICLASS_xt_iclass_jumpx,
3646  ICLASS_xt_iclass_l16ui,
3647  ICLASS_xt_iclass_l16si,
3648  ICLASS_xt_iclass_l32i,
3649  ICLASS_xt_iclass_l32r,
3650  ICLASS_xt_iclass_l8i,
3651  ICLASS_xt_iclass_movi,
3652  ICLASS_xt_iclass_movz,
3653  ICLASS_xt_iclass_neg,
3654  ICLASS_xt_iclass_nop,
3655  ICLASS_xt_iclass_return,
3656  ICLASS_xt_iclass_s16i,
3657  ICLASS_xt_iclass_s32i,
3658  ICLASS_xt_iclass_s8i,
3659  ICLASS_xt_iclass_sar,
3660  ICLASS_xt_iclass_sari,
3661  ICLASS_xt_iclass_shifts,
3662  ICLASS_xt_iclass_shiftst,
3663  ICLASS_xt_iclass_shiftt,
3664  ICLASS_xt_iclass_slli,
3665  ICLASS_xt_iclass_srai,
3666  ICLASS_xt_iclass_srli,
3667  ICLASS_xt_iclass_memw,
3668  ICLASS_xt_iclass_extw,
3669  ICLASS_xt_iclass_isync,
3670  ICLASS_xt_iclass_sync,
3671  ICLASS_xt_iclass_rsil,
3672  ICLASS_xt_iclass_rsr_sar,
3673  ICLASS_xt_iclass_wsr_sar,
3674  ICLASS_xt_iclass_xsr_sar,
3675  ICLASS_xt_iclass_rsr_litbase,
3676  ICLASS_xt_iclass_wsr_litbase,
3677  ICLASS_xt_iclass_xsr_litbase,
3678  ICLASS_xt_iclass_rsr_176,
3679  ICLASS_xt_iclass_wsr_176,
3680  ICLASS_xt_iclass_rsr_208,
3681  ICLASS_xt_iclass_rsr_ps,
3682  ICLASS_xt_iclass_wsr_ps,
3683  ICLASS_xt_iclass_xsr_ps,
3684  ICLASS_xt_iclass_rsr_epc1,
3685  ICLASS_xt_iclass_wsr_epc1,
3686  ICLASS_xt_iclass_xsr_epc1,
3687  ICLASS_xt_iclass_rsr_excsave1,
3688  ICLASS_xt_iclass_wsr_excsave1,
3689  ICLASS_xt_iclass_xsr_excsave1,
3690  ICLASS_xt_iclass_rsr_epc2,
3691  ICLASS_xt_iclass_wsr_epc2,
3692  ICLASS_xt_iclass_xsr_epc2,
3693  ICLASS_xt_iclass_rsr_excsave2,
3694  ICLASS_xt_iclass_wsr_excsave2,
3695  ICLASS_xt_iclass_xsr_excsave2,
3696  ICLASS_xt_iclass_rsr_epc3,
3697  ICLASS_xt_iclass_wsr_epc3,
3698  ICLASS_xt_iclass_xsr_epc3,
3699  ICLASS_xt_iclass_rsr_excsave3,
3700  ICLASS_xt_iclass_wsr_excsave3,
3701  ICLASS_xt_iclass_xsr_excsave3,
3702  ICLASS_xt_iclass_rsr_eps2,
3703  ICLASS_xt_iclass_wsr_eps2,
3704  ICLASS_xt_iclass_xsr_eps2,
3705  ICLASS_xt_iclass_rsr_eps3,
3706  ICLASS_xt_iclass_wsr_eps3,
3707  ICLASS_xt_iclass_xsr_eps3,
3708  ICLASS_xt_iclass_rsr_excvaddr,
3709  ICLASS_xt_iclass_wsr_excvaddr,
3710  ICLASS_xt_iclass_xsr_excvaddr,
3711  ICLASS_xt_iclass_rsr_depc,
3712  ICLASS_xt_iclass_wsr_depc,
3713  ICLASS_xt_iclass_xsr_depc,
3714  ICLASS_xt_iclass_rsr_exccause,
3715  ICLASS_xt_iclass_wsr_exccause,
3716  ICLASS_xt_iclass_xsr_exccause,
3717  ICLASS_xt_iclass_rsr_prid,
3718  ICLASS_xt_iclass_rsr_vecbase,
3719  ICLASS_xt_iclass_wsr_vecbase,
3720  ICLASS_xt_iclass_xsr_vecbase,
3721  ICLASS_xt_mul16,
3722  ICLASS_xt_mul32,
3723  ICLASS_xt_iclass_rfi,
3724  ICLASS_xt_iclass_wait,
3725  ICLASS_xt_iclass_rsr_interrupt,
3726  ICLASS_xt_iclass_wsr_intset,
3727  ICLASS_xt_iclass_wsr_intclear,
3728  ICLASS_xt_iclass_rsr_intenable,
3729  ICLASS_xt_iclass_wsr_intenable,
3730  ICLASS_xt_iclass_xsr_intenable,
3731  ICLASS_xt_iclass_break,
3732  ICLASS_xt_iclass_break_n,
3733  ICLASS_xt_iclass_rsr_dbreaka0,
3734  ICLASS_xt_iclass_wsr_dbreaka0,
3735  ICLASS_xt_iclass_xsr_dbreaka0,
3736  ICLASS_xt_iclass_rsr_dbreakc0,
3737  ICLASS_xt_iclass_wsr_dbreakc0,
3738  ICLASS_xt_iclass_xsr_dbreakc0,
3739  ICLASS_xt_iclass_rsr_ibreaka0,
3740  ICLASS_xt_iclass_wsr_ibreaka0,
3741  ICLASS_xt_iclass_xsr_ibreaka0,
3742  ICLASS_xt_iclass_rsr_ibreakenable,
3743  ICLASS_xt_iclass_wsr_ibreakenable,
3744  ICLASS_xt_iclass_xsr_ibreakenable,
3745  ICLASS_xt_iclass_rsr_debugcause,
3746  ICLASS_xt_iclass_wsr_debugcause,
3747  ICLASS_xt_iclass_xsr_debugcause,
3748  ICLASS_xt_iclass_rsr_icount,
3749  ICLASS_xt_iclass_wsr_icount,
3750  ICLASS_xt_iclass_xsr_icount,
3751  ICLASS_xt_iclass_rsr_icountlevel,
3752  ICLASS_xt_iclass_wsr_icountlevel,
3753  ICLASS_xt_iclass_xsr_icountlevel,
3754  ICLASS_xt_iclass_rsr_ddr,
3755  ICLASS_xt_iclass_wsr_ddr,
3756  ICLASS_xt_iclass_xsr_ddr,
3757  ICLASS_xt_iclass_rfdo,
3758  ICLASS_xt_iclass_rfdd,
3759  ICLASS_xt_iclass_wsr_mmid,
3760  ICLASS_xt_iclass_rsr_ccount,
3761  ICLASS_xt_iclass_wsr_ccount,
3762  ICLASS_xt_iclass_xsr_ccount,
3763  ICLASS_xt_iclass_rsr_ccompare0,
3764  ICLASS_xt_iclass_wsr_ccompare0,
3765  ICLASS_xt_iclass_xsr_ccompare0,
3766  ICLASS_xt_iclass_idtlb,
3767  ICLASS_xt_iclass_rdtlb,
3768  ICLASS_xt_iclass_wdtlb,
3769  ICLASS_xt_iclass_iitlb,
3770  ICLASS_xt_iclass_ritlb,
3771  ICLASS_xt_iclass_witlb,
3772  ICLASS_xt_iclass_nsa,
3773  ICLASS_xt_iclass_rer,
3774  ICLASS_xt_iclass_wer
3775};
3776
3777
3778/*  Opcode encodings.  */
3779
3780static void
3781Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
3782{
3783  slotbuf[0] = 0x2080;
3784}
3785
3786static void
3787Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
3788{
3789  slotbuf[0] = 0x3000;
3790}
3791
3792static void
3793Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
3794{
3795  slotbuf[0] = 0x3200;
3796}
3797
3798static void
3799Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
3800{
3801  slotbuf[0] = 0x5000;
3802}
3803
3804static void
3805Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
3806{
3807  slotbuf[0] = 0x5100;
3808}
3809
3810static void
3811Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
3812{
3813  slotbuf[0] = 0xa;
3814}
3815
3816static void
3817Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
3818{
3819  slotbuf[0] = 0xb;
3820}
3821
3822static void
3823Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
3824{
3825  slotbuf[0] = 0x8c;
3826}
3827
3828static void
3829Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
3830{
3831  slotbuf[0] = 0xcc;
3832}
3833
3834static void
3835Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
3836{
3837  slotbuf[0] = 0xf06d;
3838}
3839
3840static void
3841Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
3842{
3843  slotbuf[0] = 0x8;
3844}
3845
3846static void
3847Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
3848{
3849  slotbuf[0] = 0xd;
3850}
3851
3852static void
3853Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
3854{
3855  slotbuf[0] = 0xc;
3856}
3857
3858static void
3859Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
3860{
3861  slotbuf[0] = 0xf03d;
3862}
3863
3864static void
3865Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
3866{
3867  slotbuf[0] = 0xf00d;
3868}
3869
3870static void
3871Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
3872{
3873  slotbuf[0] = 0x9;
3874}
3875
3876static void
3877Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
3878{
3879  slotbuf[0] = 0xc002;
3880}
3881
3882static void
3883Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
3884{
3885  slotbuf[0] = 0xd002;
3886}
3887
3888static void
3889Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
3890{
3891  slotbuf[0] = 0x800000;
3892}
3893
3894static void
3895Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
3896{
3897  slotbuf[0] = 0xc00000;
3898}
3899
3900static void
3901Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
3902{
3903  slotbuf[0] = 0x900000;
3904}
3905
3906static void
3907Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
3908{
3909  slotbuf[0] = 0xa00000;
3910}
3911
3912static void
3913Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
3914{
3915  slotbuf[0] = 0xb00000;
3916}
3917
3918static void
3919Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
3920{
3921  slotbuf[0] = 0xd00000;
3922}
3923
3924static void
3925Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
3926{
3927  slotbuf[0] = 0xe00000;
3928}
3929
3930static void
3931Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
3932{
3933  slotbuf[0] = 0xf00000;
3934}
3935
3936static void
3937Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
3938{
3939  slotbuf[0] = 0x100000;
3940}
3941
3942static void
3943Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
3944{
3945  slotbuf[0] = 0x200000;
3946}
3947
3948static void
3949Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
3950{
3951  slotbuf[0] = 0x300000;
3952}
3953
3954static void
3955Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
3956{
3957  slotbuf[0] = 0x26;
3958}
3959
3960static void
3961Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
3962{
3963  slotbuf[0] = 0x66;
3964}
3965
3966static void
3967Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
3968{
3969  slotbuf[0] = 0xe6;
3970}
3971
3972static void
3973Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
3974{
3975  slotbuf[0] = 0xa6;
3976}
3977
3978static void
3979Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
3980{
3981  slotbuf[0] = 0x6007;
3982}
3983
3984static void
3985Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
3986{
3987  slotbuf[0] = 0xe007;
3988}
3989
3990static void
3991Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
3992{
3993  slotbuf[0] = 0xf6;
3994}
3995
3996static void
3997Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
3998{
3999  slotbuf[0] = 0xb6;
4000}
4001
4002static void
4003Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
4004{
4005  slotbuf[0] = 0x1007;
4006}
4007
4008static void
4009Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
4010{
4011  slotbuf[0] = 0x9007;
4012}
4013
4014static void
4015Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
4016{
4017  slotbuf[0] = 0xa007;
4018}
4019
4020static void
4021Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
4022{
4023  slotbuf[0] = 0x2007;
4024}
4025
4026static void
4027Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
4028{
4029  slotbuf[0] = 0xb007;
4030}
4031
4032static void
4033Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
4034{
4035  slotbuf[0] = 0x3007;
4036}
4037
4038static void
4039Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
4040{
4041  slotbuf[0] = 0x8007;
4042}
4043
4044static void
4045Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
4046{
4047  slotbuf[0] = 0x7;
4048}
4049
4050static void
4051Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
4052{
4053  slotbuf[0] = 0x4007;
4054}
4055
4056static void
4057Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
4058{
4059  slotbuf[0] = 0xc007;
4060}
4061
4062static void
4063Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
4064{
4065  slotbuf[0] = 0x5007;
4066}
4067
4068static void
4069Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
4070{
4071  slotbuf[0] = 0xd007;
4072}
4073
4074static void
4075Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
4076{
4077  slotbuf[0] = 0x16;
4078}
4079
4080static void
4081Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
4082{
4083  slotbuf[0] = 0x56;
4084}
4085
4086static void
4087Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
4088{
4089  slotbuf[0] = 0xd6;
4090}
4091
4092static void
4093Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
4094{
4095  slotbuf[0] = 0x96;
4096}
4097
4098static void
4099Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4100{
4101  slotbuf[0] = 0x5;
4102}
4103
4104static void
4105Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4106{
4107  slotbuf[0] = 0xc0;
4108}
4109
4110static void
4111Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
4112{
4113  slotbuf[0] = 0x40000;
4114}
4115
4116static void
4117Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
4118{
4119  slotbuf[0] = 0;
4120}
4121
4122static void
4123Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
4124{
4125  slotbuf[0] = 0x6;
4126}
4127
4128static void
4129Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
4130{
4131  slotbuf[0] = 0xa0;
4132}
4133
4134static void
4135Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
4136{
4137  slotbuf[0] = 0x1002;
4138}
4139
4140static void
4141Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
4142{
4143  slotbuf[0] = 0x9002;
4144}
4145
4146static void
4147Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
4148{
4149  slotbuf[0] = 0x2002;
4150}
4151
4152static void
4153Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
4154{
4155  slotbuf[0] = 0x1;
4156}
4157
4158static void
4159Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
4160{
4161  slotbuf[0] = 0x2;
4162}
4163
4164static void
4165Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
4166{
4167  slotbuf[0] = 0xa002;
4168}
4169
4170static void
4171Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
4172{
4173  slotbuf[0] = 0x830000;
4174}
4175
4176static void
4177Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
4178{
4179  slotbuf[0] = 0x930000;
4180}
4181
4182static void
4183Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
4184{
4185  slotbuf[0] = 0xa30000;
4186}
4187
4188static void
4189Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
4190{
4191  slotbuf[0] = 0xb30000;
4192}
4193
4194static void
4195Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
4196{
4197  slotbuf[0] = 0x600000;
4198}
4199
4200static void
4201Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
4202{
4203  slotbuf[0] = 0x600100;
4204}
4205
4206static void
4207Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
4208{
4209  slotbuf[0] = 0x20f0;
4210}
4211
4212static void
4213Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
4214{
4215  slotbuf[0] = 0x80;
4216}
4217
4218static void
4219Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
4220{
4221  slotbuf[0] = 0x5002;
4222}
4223
4224static void
4225Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
4226{
4227  slotbuf[0] = 0x6002;
4228}
4229
4230static void
4231Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
4232{
4233  slotbuf[0] = 0x4002;
4234}
4235
4236static void
4237Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
4238{
4239  slotbuf[0] = 0x400000;
4240}
4241
4242static void
4243Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
4244{
4245  slotbuf[0] = 0x401000;
4246}
4247
4248static void
4249Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
4250{
4251  slotbuf[0] = 0x402000;
4252}
4253
4254static void
4255Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
4256{
4257  slotbuf[0] = 0x403000;
4258}
4259
4260static void
4261Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
4262{
4263  slotbuf[0] = 0x404000;
4264}
4265
4266static void
4267Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
4268{
4269  slotbuf[0] = 0xa10000;
4270}
4271
4272static void
4273Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
4274{
4275  slotbuf[0] = 0x810000;
4276}
4277
4278static void
4279Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
4280{
4281  slotbuf[0] = 0x910000;
4282}
4283
4284static void
4285Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
4286{
4287  slotbuf[0] = 0xb10000;
4288}
4289
4290static void
4291Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
4292{
4293  slotbuf[0] = 0x10000;
4294}
4295
4296static void
4297Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
4298{
4299  slotbuf[0] = 0x210000;
4300}
4301
4302static void
4303Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
4304{
4305  slotbuf[0] = 0x410000;
4306}
4307
4308static void
4309Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
4310{
4311  slotbuf[0] = 0x20c0;
4312}
4313
4314static void
4315Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
4316{
4317  slotbuf[0] = 0x20d0;
4318}
4319
4320static void
4321Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
4322{
4323  slotbuf[0] = 0x2000;
4324}
4325
4326static void
4327Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
4328{
4329  slotbuf[0] = 0x2010;
4330}
4331
4332static void
4333Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
4334{
4335  slotbuf[0] = 0x2020;
4336}
4337
4338static void
4339Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
4340{
4341  slotbuf[0] = 0x2030;
4342}
4343
4344static void
4345Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
4346{
4347  slotbuf[0] = 0x6000;
4348}
4349
4350static void
4351Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
4352{
4353  slotbuf[0] = 0x30300;
4354}
4355
4356static void
4357Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
4358{
4359  slotbuf[0] = 0x130300;
4360}
4361
4362static void
4363Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
4364{
4365  slotbuf[0] = 0x610300;
4366}
4367
4368static void
4369Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4370{
4371  slotbuf[0] = 0x30500;
4372}
4373
4374static void
4375Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4376{
4377  slotbuf[0] = 0x130500;
4378}
4379
4380static void
4381Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4382{
4383  slotbuf[0] = 0x610500;
4384}
4385
4386static void
4387Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
4388{
4389  slotbuf[0] = 0x3b000;
4390}
4391
4392static void
4393Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
4394{
4395  slotbuf[0] = 0x13b000;
4396}
4397
4398static void
4399Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
4400{
4401  slotbuf[0] = 0x3d000;
4402}
4403
4404static void
4405Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
4406{
4407  slotbuf[0] = 0x3e600;
4408}
4409
4410static void
4411Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
4412{
4413  slotbuf[0] = 0x13e600;
4414}
4415
4416static void
4417Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
4418{
4419  slotbuf[0] = 0x61e600;
4420}
4421
4422static void
4423Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
4424{
4425  slotbuf[0] = 0x3b100;
4426}
4427
4428static void
4429Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
4430{
4431  slotbuf[0] = 0x13b100;
4432}
4433
4434static void
4435Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
4436{
4437  slotbuf[0] = 0x61b100;
4438}
4439
4440static void
4441Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
4442{
4443  slotbuf[0] = 0x3d100;
4444}
4445
4446static void
4447Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
4448{
4449  slotbuf[0] = 0x13d100;
4450}
4451
4452static void
4453Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
4454{
4455  slotbuf[0] = 0x61d100;
4456}
4457
4458static void
4459Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
4460{
4461  slotbuf[0] = 0x3b200;
4462}
4463
4464static void
4465Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
4466{
4467  slotbuf[0] = 0x13b200;
4468}
4469
4470static void
4471Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
4472{
4473  slotbuf[0] = 0x61b200;
4474}
4475
4476static void
4477Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
4478{
4479  slotbuf[0] = 0x3d200;
4480}
4481
4482static void
4483Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
4484{
4485  slotbuf[0] = 0x13d200;
4486}
4487
4488static void
4489Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
4490{
4491  slotbuf[0] = 0x61d200;
4492}
4493
4494static void
4495Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
4496{
4497  slotbuf[0] = 0x3b300;
4498}
4499
4500static void
4501Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
4502{
4503  slotbuf[0] = 0x13b300;
4504}
4505
4506static void
4507Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
4508{
4509  slotbuf[0] = 0x61b300;
4510}
4511
4512static void
4513Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
4514{
4515  slotbuf[0] = 0x3d300;
4516}
4517
4518static void
4519Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
4520{
4521  slotbuf[0] = 0x13d300;
4522}
4523
4524static void
4525Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
4526{
4527  slotbuf[0] = 0x61d300;
4528}
4529
4530static void
4531Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
4532{
4533  slotbuf[0] = 0x3c200;
4534}
4535
4536static void
4537Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
4538{
4539  slotbuf[0] = 0x13c200;
4540}
4541
4542static void
4543Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
4544{
4545  slotbuf[0] = 0x61c200;
4546}
4547
4548static void
4549Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
4550{
4551  slotbuf[0] = 0x3c300;
4552}
4553
4554static void
4555Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
4556{
4557  slotbuf[0] = 0x13c300;
4558}
4559
4560static void
4561Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
4562{
4563  slotbuf[0] = 0x61c300;
4564}
4565
4566static void
4567Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
4568{
4569  slotbuf[0] = 0x3ee00;
4570}
4571
4572static void
4573Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
4574{
4575  slotbuf[0] = 0x13ee00;
4576}
4577
4578static void
4579Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
4580{
4581  slotbuf[0] = 0x61ee00;
4582}
4583
4584static void
4585Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
4586{
4587  slotbuf[0] = 0x3c000;
4588}
4589
4590static void
4591Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
4592{
4593  slotbuf[0] = 0x13c000;
4594}
4595
4596static void
4597Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
4598{
4599  slotbuf[0] = 0x61c000;
4600}
4601
4602static void
4603Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
4604{
4605  slotbuf[0] = 0x3e800;
4606}
4607
4608static void
4609Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
4610{
4611  slotbuf[0] = 0x13e800;
4612}
4613
4614static void
4615Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
4616{
4617  slotbuf[0] = 0x61e800;
4618}
4619
4620static void
4621Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
4622{
4623  slotbuf[0] = 0x3eb00;
4624}
4625
4626static void
4627Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4628{
4629  slotbuf[0] = 0x3e700;
4630}
4631
4632static void
4633Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4634{
4635  slotbuf[0] = 0x13e700;
4636}
4637
4638static void
4639Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
4640{
4641  slotbuf[0] = 0x61e700;
4642}
4643
4644static void
4645Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
4646{
4647  slotbuf[0] = 0xc10000;
4648}
4649
4650static void
4651Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
4652{
4653  slotbuf[0] = 0xd10000;
4654}
4655
4656static void
4657Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
4658{
4659  slotbuf[0] = 0x820000;
4660}
4661
4662static void
4663Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
4664{
4665  slotbuf[0] = 0x3010;
4666}
4667
4668static void
4669Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
4670{
4671  slotbuf[0] = 0x7000;
4672}
4673
4674static void
4675Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
4676{
4677  slotbuf[0] = 0x3e200;
4678}
4679
4680static void
4681Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
4682{
4683  slotbuf[0] = 0x13e200;
4684}
4685
4686static void
4687Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
4688{
4689  slotbuf[0] = 0x13e300;
4690}
4691
4692static void
4693Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
4694{
4695  slotbuf[0] = 0x3e400;
4696}
4697
4698static void
4699Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
4700{
4701  slotbuf[0] = 0x13e400;
4702}
4703
4704static void
4705Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
4706{
4707  slotbuf[0] = 0x61e400;
4708}
4709
4710static void
4711Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
4712{
4713  slotbuf[0] = 0x4000;
4714}
4715
4716static void
4717Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
4718{
4719  slotbuf[0] = 0xf02d;
4720}
4721
4722static void
4723Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4724{
4725  slotbuf[0] = 0x39000;
4726}
4727
4728static void
4729Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4730{
4731  slotbuf[0] = 0x139000;
4732}
4733
4734static void
4735Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4736{
4737  slotbuf[0] = 0x619000;
4738}
4739
4740static void
4741Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4742{
4743  slotbuf[0] = 0x3a000;
4744}
4745
4746static void
4747Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4748{
4749  slotbuf[0] = 0x13a000;
4750}
4751
4752static void
4753Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4754{
4755  slotbuf[0] = 0x61a000;
4756}
4757
4758static void
4759Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4760{
4761  slotbuf[0] = 0x38000;
4762}
4763
4764static void
4765Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4766{
4767  slotbuf[0] = 0x138000;
4768}
4769
4770static void
4771Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4772{
4773  slotbuf[0] = 0x618000;
4774}
4775
4776static void
4777Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
4778{
4779  slotbuf[0] = 0x36000;
4780}
4781
4782static void
4783Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
4784{
4785  slotbuf[0] = 0x136000;
4786}
4787
4788static void
4789Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
4790{
4791  slotbuf[0] = 0x616000;
4792}
4793
4794static void
4795Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
4796{
4797  slotbuf[0] = 0x3e900;
4798}
4799
4800static void
4801Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
4802{
4803  slotbuf[0] = 0x13e900;
4804}
4805
4806static void
4807Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
4808{
4809  slotbuf[0] = 0x61e900;
4810}
4811
4812static void
4813Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
4814{
4815  slotbuf[0] = 0x3ec00;
4816}
4817
4818static void
4819Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
4820{
4821  slotbuf[0] = 0x13ec00;
4822}
4823
4824static void
4825Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
4826{
4827  slotbuf[0] = 0x61ec00;
4828}
4829
4830static void
4831Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
4832{
4833  slotbuf[0] = 0x3ed00;
4834}
4835
4836static void
4837Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
4838{
4839  slotbuf[0] = 0x13ed00;
4840}
4841
4842static void
4843Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
4844{
4845  slotbuf[0] = 0x61ed00;
4846}
4847
4848static void
4849Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
4850{
4851  slotbuf[0] = 0x36800;
4852}
4853
4854static void
4855Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
4856{
4857  slotbuf[0] = 0x136800;
4858}
4859
4860static void
4861Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
4862{
4863  slotbuf[0] = 0x616800;
4864}
4865
4866static void
4867Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
4868{
4869  slotbuf[0] = 0xf1e000;
4870}
4871
4872static void
4873Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
4874{
4875  slotbuf[0] = 0xf1e010;
4876}
4877
4878static void
4879Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
4880{
4881  slotbuf[0] = 0x135900;
4882}
4883
4884static void
4885Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
4886{
4887  slotbuf[0] = 0x3ea00;
4888}
4889
4890static void
4891Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
4892{
4893  slotbuf[0] = 0x13ea00;
4894}
4895
4896static void
4897Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
4898{
4899  slotbuf[0] = 0x61ea00;
4900}
4901
4902static void
4903Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4904{
4905  slotbuf[0] = 0x3f000;
4906}
4907
4908static void
4909Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4910{
4911  slotbuf[0] = 0x13f000;
4912}
4913
4914static void
4915Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4916{
4917  slotbuf[0] = 0x61f000;
4918}
4919
4920static void
4921Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
4922{
4923  slotbuf[0] = 0x50c000;
4924}
4925
4926static void
4927Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
4928{
4929  slotbuf[0] = 0x50d000;
4930}
4931
4932static void
4933Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4934{
4935  slotbuf[0] = 0x50b000;
4936}
4937
4938static void
4939Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
4940{
4941  slotbuf[0] = 0x50f000;
4942}
4943
4944static void
4945Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
4946{
4947  slotbuf[0] = 0x50e000;
4948}
4949
4950static void
4951Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
4952{
4953  slotbuf[0] = 0x504000;
4954}
4955
4956static void
4957Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
4958{
4959  slotbuf[0] = 0x505000;
4960}
4961
4962static void
4963Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
4964{
4965  slotbuf[0] = 0x503000;
4966}
4967
4968static void
4969Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
4970{
4971  slotbuf[0] = 0x507000;
4972}
4973
4974static void
4975Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
4976{
4977  slotbuf[0] = 0x506000;
4978}
4979
4980static void
4981Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
4982{
4983  slotbuf[0] = 0x40e000;
4984}
4985
4986static void
4987Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
4988{
4989  slotbuf[0] = 0x40f000;
4990}
4991
4992static void
4993Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
4994{
4995  slotbuf[0] = 0x406000;
4996}
4997
4998static void
4999Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
5000{
5001  slotbuf[0] = 0x407000;
5002}
5003
5004static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
5005  Opcode_excw_Slot_inst_encode, 0, 0
5006};
5007
5008static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
5009  Opcode_rfe_Slot_inst_encode, 0, 0
5010};
5011
5012static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
5013  Opcode_rfde_Slot_inst_encode, 0, 0
5014};
5015
5016static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
5017  Opcode_syscall_Slot_inst_encode, 0, 0
5018};
5019
5020static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
5021  Opcode_simcall_Slot_inst_encode, 0, 0
5022};
5023
5024static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
5025  0, Opcode_add_n_Slot_inst16a_encode, 0
5026};
5027
5028static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
5029  0, Opcode_addi_n_Slot_inst16a_encode, 0
5030};
5031
5032static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
5033  0, 0, Opcode_beqz_n_Slot_inst16b_encode
5034};
5035
5036static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
5037  0, 0, Opcode_bnez_n_Slot_inst16b_encode
5038};
5039
5040static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
5041  0, 0, Opcode_ill_n_Slot_inst16b_encode
5042};
5043
5044static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
5045  0, Opcode_l32i_n_Slot_inst16a_encode, 0
5046};
5047
5048static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
5049  0, 0, Opcode_mov_n_Slot_inst16b_encode
5050};
5051
5052static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
5053  0, 0, Opcode_movi_n_Slot_inst16b_encode
5054};
5055
5056static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
5057  0, 0, Opcode_nop_n_Slot_inst16b_encode
5058};
5059
5060static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
5061  0, 0, Opcode_ret_n_Slot_inst16b_encode
5062};
5063
5064static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
5065  0, Opcode_s32i_n_Slot_inst16a_encode, 0
5066};
5067
5068static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
5069  Opcode_addi_Slot_inst_encode, 0, 0
5070};
5071
5072static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
5073  Opcode_addmi_Slot_inst_encode, 0, 0
5074};
5075
5076static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
5077  Opcode_add_Slot_inst_encode, 0, 0
5078};
5079
5080static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
5081  Opcode_sub_Slot_inst_encode, 0, 0
5082};
5083
5084static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
5085  Opcode_addx2_Slot_inst_encode, 0, 0
5086};
5087
5088static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
5089  Opcode_addx4_Slot_inst_encode, 0, 0
5090};
5091
5092static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
5093  Opcode_addx8_Slot_inst_encode, 0, 0
5094};
5095
5096static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
5097  Opcode_subx2_Slot_inst_encode, 0, 0
5098};
5099
5100static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
5101  Opcode_subx4_Slot_inst_encode, 0, 0
5102};
5103
5104static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
5105  Opcode_subx8_Slot_inst_encode, 0, 0
5106};
5107
5108static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
5109  Opcode_and_Slot_inst_encode, 0, 0
5110};
5111
5112static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
5113  Opcode_or_Slot_inst_encode, 0, 0
5114};
5115
5116static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
5117  Opcode_xor_Slot_inst_encode, 0, 0
5118};
5119
5120static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
5121  Opcode_beqi_Slot_inst_encode, 0, 0
5122};
5123
5124static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
5125  Opcode_bnei_Slot_inst_encode, 0, 0
5126};
5127
5128static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
5129  Opcode_bgei_Slot_inst_encode, 0, 0
5130};
5131
5132static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
5133  Opcode_blti_Slot_inst_encode, 0, 0
5134};
5135
5136static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
5137  Opcode_bbci_Slot_inst_encode, 0, 0
5138};
5139
5140static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
5141  Opcode_bbsi_Slot_inst_encode, 0, 0
5142};
5143
5144static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
5145  Opcode_bgeui_Slot_inst_encode, 0, 0
5146};
5147
5148static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
5149  Opcode_bltui_Slot_inst_encode, 0, 0
5150};
5151
5152static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
5153  Opcode_beq_Slot_inst_encode, 0, 0
5154};
5155
5156static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
5157  Opcode_bne_Slot_inst_encode, 0, 0
5158};
5159
5160static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
5161  Opcode_bge_Slot_inst_encode, 0, 0
5162};
5163
5164static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
5165  Opcode_blt_Slot_inst_encode, 0, 0
5166};
5167
5168static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
5169  Opcode_bgeu_Slot_inst_encode, 0, 0
5170};
5171
5172static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
5173  Opcode_bltu_Slot_inst_encode, 0, 0
5174};
5175
5176static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
5177  Opcode_bany_Slot_inst_encode, 0, 0
5178};
5179
5180static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
5181  Opcode_bnone_Slot_inst_encode, 0, 0
5182};
5183
5184static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
5185  Opcode_ball_Slot_inst_encode, 0, 0
5186};
5187
5188static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
5189  Opcode_bnall_Slot_inst_encode, 0, 0
5190};
5191
5192static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
5193  Opcode_bbc_Slot_inst_encode, 0, 0
5194};
5195
5196static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
5197  Opcode_bbs_Slot_inst_encode, 0, 0
5198};
5199
5200static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
5201  Opcode_beqz_Slot_inst_encode, 0, 0
5202};
5203
5204static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
5205  Opcode_bnez_Slot_inst_encode, 0, 0
5206};
5207
5208static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
5209  Opcode_bgez_Slot_inst_encode, 0, 0
5210};
5211
5212static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
5213  Opcode_bltz_Slot_inst_encode, 0, 0
5214};
5215
5216static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
5217  Opcode_call0_Slot_inst_encode, 0, 0
5218};
5219
5220static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
5221  Opcode_callx0_Slot_inst_encode, 0, 0
5222};
5223
5224static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
5225  Opcode_extui_Slot_inst_encode, 0, 0
5226};
5227
5228static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
5229  Opcode_ill_Slot_inst_encode, 0, 0
5230};
5231
5232static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
5233  Opcode_j_Slot_inst_encode, 0, 0
5234};
5235
5236static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
5237  Opcode_jx_Slot_inst_encode, 0, 0
5238};
5239
5240static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
5241  Opcode_l16ui_Slot_inst_encode, 0, 0
5242};
5243
5244static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
5245  Opcode_l16si_Slot_inst_encode, 0, 0
5246};
5247
5248static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
5249  Opcode_l32i_Slot_inst_encode, 0, 0
5250};
5251
5252static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
5253  Opcode_l32r_Slot_inst_encode, 0, 0
5254};
5255
5256static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
5257  Opcode_l8ui_Slot_inst_encode, 0, 0
5258};
5259
5260static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
5261  Opcode_movi_Slot_inst_encode, 0, 0
5262};
5263
5264static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
5265  Opcode_moveqz_Slot_inst_encode, 0, 0
5266};
5267
5268static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
5269  Opcode_movnez_Slot_inst_encode, 0, 0
5270};
5271
5272static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
5273  Opcode_movltz_Slot_inst_encode, 0, 0
5274};
5275
5276static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
5277  Opcode_movgez_Slot_inst_encode, 0, 0
5278};
5279
5280static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
5281  Opcode_neg_Slot_inst_encode, 0, 0
5282};
5283
5284static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
5285  Opcode_abs_Slot_inst_encode, 0, 0
5286};
5287
5288static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
5289  Opcode_nop_Slot_inst_encode, 0, 0
5290};
5291
5292static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
5293  Opcode_ret_Slot_inst_encode, 0, 0
5294};
5295
5296static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
5297  Opcode_s16i_Slot_inst_encode, 0, 0
5298};
5299
5300static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
5301  Opcode_s32i_Slot_inst_encode, 0, 0
5302};
5303
5304static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
5305  Opcode_s8i_Slot_inst_encode, 0, 0
5306};
5307
5308static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
5309  Opcode_ssr_Slot_inst_encode, 0, 0
5310};
5311
5312static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
5313  Opcode_ssl_Slot_inst_encode, 0, 0
5314};
5315
5316static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
5317  Opcode_ssa8l_Slot_inst_encode, 0, 0
5318};
5319
5320static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
5321  Opcode_ssa8b_Slot_inst_encode, 0, 0
5322};
5323
5324static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
5325  Opcode_ssai_Slot_inst_encode, 0, 0
5326};
5327
5328static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
5329  Opcode_sll_Slot_inst_encode, 0, 0
5330};
5331
5332static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
5333  Opcode_src_Slot_inst_encode, 0, 0
5334};
5335
5336static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
5337  Opcode_srl_Slot_inst_encode, 0, 0
5338};
5339
5340static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
5341  Opcode_sra_Slot_inst_encode, 0, 0
5342};
5343
5344static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
5345  Opcode_slli_Slot_inst_encode, 0, 0
5346};
5347
5348static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
5349  Opcode_srai_Slot_inst_encode, 0, 0
5350};
5351
5352static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
5353  Opcode_srli_Slot_inst_encode, 0, 0
5354};
5355
5356static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
5357  Opcode_memw_Slot_inst_encode, 0, 0
5358};
5359
5360static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
5361  Opcode_extw_Slot_inst_encode, 0, 0
5362};
5363
5364static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
5365  Opcode_isync_Slot_inst_encode, 0, 0
5366};
5367
5368static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
5369  Opcode_rsync_Slot_inst_encode, 0, 0
5370};
5371
5372static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
5373  Opcode_esync_Slot_inst_encode, 0, 0
5374};
5375
5376static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
5377  Opcode_dsync_Slot_inst_encode, 0, 0
5378};
5379
5380static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
5381  Opcode_rsil_Slot_inst_encode, 0, 0
5382};
5383
5384static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
5385  Opcode_rsr_sar_Slot_inst_encode, 0, 0
5386};
5387
5388static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
5389  Opcode_wsr_sar_Slot_inst_encode, 0, 0
5390};
5391
5392static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
5393  Opcode_xsr_sar_Slot_inst_encode, 0, 0
5394};
5395
5396static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
5397  Opcode_rsr_litbase_Slot_inst_encode, 0, 0
5398};
5399
5400static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
5401  Opcode_wsr_litbase_Slot_inst_encode, 0, 0
5402};
5403
5404static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
5405  Opcode_xsr_litbase_Slot_inst_encode, 0, 0
5406};
5407
5408static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
5409  Opcode_rsr_176_Slot_inst_encode, 0, 0
5410};
5411
5412static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = {
5413  Opcode_wsr_176_Slot_inst_encode, 0, 0
5414};
5415
5416static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
5417  Opcode_rsr_208_Slot_inst_encode, 0, 0
5418};
5419
5420static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
5421  Opcode_rsr_ps_Slot_inst_encode, 0, 0
5422};
5423
5424static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
5425  Opcode_wsr_ps_Slot_inst_encode, 0, 0
5426};
5427
5428static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
5429  Opcode_xsr_ps_Slot_inst_encode, 0, 0
5430};
5431
5432static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
5433  Opcode_rsr_epc1_Slot_inst_encode, 0, 0
5434};
5435
5436static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
5437  Opcode_wsr_epc1_Slot_inst_encode, 0, 0
5438};
5439
5440static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
5441  Opcode_xsr_epc1_Slot_inst_encode, 0, 0
5442};
5443
5444static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
5445  Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
5446};
5447
5448static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
5449  Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
5450};
5451
5452static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
5453  Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
5454};
5455
5456static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
5457  Opcode_rsr_epc2_Slot_inst_encode, 0, 0
5458};
5459
5460static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
5461  Opcode_wsr_epc2_Slot_inst_encode, 0, 0
5462};
5463
5464static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
5465  Opcode_xsr_epc2_Slot_inst_encode, 0, 0
5466};
5467
5468static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
5469  Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
5470};
5471
5472static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
5473  Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
5474};
5475
5476static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
5477  Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
5478};
5479
5480static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
5481  Opcode_rsr_epc3_Slot_inst_encode, 0, 0
5482};
5483
5484static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
5485  Opcode_wsr_epc3_Slot_inst_encode, 0, 0
5486};
5487
5488static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
5489  Opcode_xsr_epc3_Slot_inst_encode, 0, 0
5490};
5491
5492static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
5493  Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
5494};
5495
5496static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
5497  Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
5498};
5499
5500static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
5501  Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
5502};
5503
5504static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
5505  Opcode_rsr_eps2_Slot_inst_encode, 0, 0
5506};
5507
5508static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
5509  Opcode_wsr_eps2_Slot_inst_encode, 0, 0
5510};
5511
5512static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
5513  Opcode_xsr_eps2_Slot_inst_encode, 0, 0
5514};
5515
5516static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
5517  Opcode_rsr_eps3_Slot_inst_encode, 0, 0
5518};
5519
5520static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
5521  Opcode_wsr_eps3_Slot_inst_encode, 0, 0
5522};
5523
5524static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
5525  Opcode_xsr_eps3_Slot_inst_encode, 0, 0
5526};
5527
5528static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
5529  Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
5530};
5531
5532static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
5533  Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
5534};
5535
5536static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
5537  Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
5538};
5539
5540static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
5541  Opcode_rsr_depc_Slot_inst_encode, 0, 0
5542};
5543
5544static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
5545  Opcode_wsr_depc_Slot_inst_encode, 0, 0
5546};
5547
5548static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
5549  Opcode_xsr_depc_Slot_inst_encode, 0, 0
5550};
5551
5552static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
5553  Opcode_rsr_exccause_Slot_inst_encode, 0, 0
5554};
5555
5556static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
5557  Opcode_wsr_exccause_Slot_inst_encode, 0, 0
5558};
5559
5560static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
5561  Opcode_xsr_exccause_Slot_inst_encode, 0, 0
5562};
5563
5564static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
5565  Opcode_rsr_prid_Slot_inst_encode, 0, 0
5566};
5567
5568static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
5569  Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
5570};
5571
5572static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
5573  Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
5574};
5575
5576static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
5577  Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
5578};
5579
5580static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
5581  Opcode_mul16u_Slot_inst_encode, 0, 0
5582};
5583
5584static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
5585  Opcode_mul16s_Slot_inst_encode, 0, 0
5586};
5587
5588static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
5589  Opcode_mull_Slot_inst_encode, 0, 0
5590};
5591
5592static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
5593  Opcode_rfi_Slot_inst_encode, 0, 0
5594};
5595
5596static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
5597  Opcode_waiti_Slot_inst_encode, 0, 0
5598};
5599
5600static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
5601  Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
5602};
5603
5604static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
5605  Opcode_wsr_intset_Slot_inst_encode, 0, 0
5606};
5607
5608static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
5609  Opcode_wsr_intclear_Slot_inst_encode, 0, 0
5610};
5611
5612static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
5613  Opcode_rsr_intenable_Slot_inst_encode, 0, 0
5614};
5615
5616static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
5617  Opcode_wsr_intenable_Slot_inst_encode, 0, 0
5618};
5619
5620static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
5621  Opcode_xsr_intenable_Slot_inst_encode, 0, 0
5622};
5623
5624static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
5625  Opcode_break_Slot_inst_encode, 0, 0
5626};
5627
5628static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
5629  0, 0, Opcode_break_n_Slot_inst16b_encode
5630};
5631
5632static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
5633  Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
5634};
5635
5636static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
5637  Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
5638};
5639
5640static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
5641  Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
5642};
5643
5644static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
5645  Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
5646};
5647
5648static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
5649  Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
5650};
5651
5652static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
5653  Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
5654};
5655
5656static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
5657  Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
5658};
5659
5660static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
5661  Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
5662};
5663
5664static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
5665  Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
5666};
5667
5668static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
5669  Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
5670};
5671
5672static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
5673  Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
5674};
5675
5676static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
5677  Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
5678};
5679
5680static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
5681  Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
5682};
5683
5684static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
5685  Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
5686};
5687
5688static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
5689  Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
5690};
5691
5692static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
5693  Opcode_rsr_icount_Slot_inst_encode, 0, 0
5694};
5695
5696static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
5697  Opcode_wsr_icount_Slot_inst_encode, 0, 0
5698};
5699
5700static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
5701  Opcode_xsr_icount_Slot_inst_encode, 0, 0
5702};
5703
5704static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
5705  Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
5706};
5707
5708static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
5709  Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
5710};
5711
5712static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
5713  Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
5714};
5715
5716static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
5717  Opcode_rsr_ddr_Slot_inst_encode, 0, 0
5718};
5719
5720static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
5721  Opcode_wsr_ddr_Slot_inst_encode, 0, 0
5722};
5723
5724static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
5725  Opcode_xsr_ddr_Slot_inst_encode, 0, 0
5726};
5727
5728static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
5729  Opcode_rfdo_Slot_inst_encode, 0, 0
5730};
5731
5732static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
5733  Opcode_rfdd_Slot_inst_encode, 0, 0
5734};
5735
5736static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
5737  Opcode_wsr_mmid_Slot_inst_encode, 0, 0
5738};
5739
5740static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
5741  Opcode_rsr_ccount_Slot_inst_encode, 0, 0
5742};
5743
5744static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
5745  Opcode_wsr_ccount_Slot_inst_encode, 0, 0
5746};
5747
5748static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
5749  Opcode_xsr_ccount_Slot_inst_encode, 0, 0
5750};
5751
5752static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
5753  Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
5754};
5755
5756static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
5757  Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
5758};
5759
5760static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
5761  Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
5762};
5763
5764static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
5765  Opcode_idtlb_Slot_inst_encode, 0, 0
5766};
5767
5768static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
5769  Opcode_pdtlb_Slot_inst_encode, 0, 0
5770};
5771
5772static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
5773  Opcode_rdtlb0_Slot_inst_encode, 0, 0
5774};
5775
5776static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
5777  Opcode_rdtlb1_Slot_inst_encode, 0, 0
5778};
5779
5780static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
5781  Opcode_wdtlb_Slot_inst_encode, 0, 0
5782};
5783
5784static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
5785  Opcode_iitlb_Slot_inst_encode, 0, 0
5786};
5787
5788static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
5789  Opcode_pitlb_Slot_inst_encode, 0, 0
5790};
5791
5792static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
5793  Opcode_ritlb0_Slot_inst_encode, 0, 0
5794};
5795
5796static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
5797  Opcode_ritlb1_Slot_inst_encode, 0, 0
5798};
5799
5800static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
5801  Opcode_witlb_Slot_inst_encode, 0, 0
5802};
5803
5804static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
5805  Opcode_nsa_Slot_inst_encode, 0, 0
5806};
5807
5808static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
5809  Opcode_nsau_Slot_inst_encode, 0, 0
5810};
5811
5812static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
5813  Opcode_rer_Slot_inst_encode, 0, 0
5814};
5815
5816static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
5817  Opcode_wer_Slot_inst_encode, 0, 0
5818};
5819
5820
5821/* Opcode table.  */
5822
5823static xtensa_opcode_internal opcodes[] = {
5824  { "excw", ICLASS_xt_iclass_excw,
5825    0,
5826    Opcode_excw_encode_fns, 0, 0 },
5827  { "rfe", ICLASS_xt_iclass_rfe,
5828    XTENSA_OPCODE_IS_JUMP,
5829    Opcode_rfe_encode_fns, 0, 0 },
5830  { "rfde", ICLASS_xt_iclass_rfde,
5831    XTENSA_OPCODE_IS_JUMP,
5832    Opcode_rfde_encode_fns, 0, 0 },
5833  { "syscall", ICLASS_xt_iclass_syscall,
5834    0,
5835    Opcode_syscall_encode_fns, 0, 0 },
5836  { "simcall", ICLASS_xt_iclass_simcall,
5837    0,
5838    Opcode_simcall_encode_fns, 0, 0 },
5839  { "add.n", ICLASS_xt_iclass_add_n,
5840    0,
5841    Opcode_add_n_encode_fns, 0, 0 },
5842  { "addi.n", ICLASS_xt_iclass_addi_n,
5843    0,
5844    Opcode_addi_n_encode_fns, 0, 0 },
5845  { "beqz.n", ICLASS_xt_iclass_bz6,
5846    XTENSA_OPCODE_IS_BRANCH,
5847    Opcode_beqz_n_encode_fns, 0, 0 },
5848  { "bnez.n", ICLASS_xt_iclass_bz6,
5849    XTENSA_OPCODE_IS_BRANCH,
5850    Opcode_bnez_n_encode_fns, 0, 0 },
5851  { "ill.n", ICLASS_xt_iclass_ill_n,
5852    0,
5853    Opcode_ill_n_encode_fns, 0, 0 },
5854  { "l32i.n", ICLASS_xt_iclass_loadi4,
5855    0,
5856    Opcode_l32i_n_encode_fns, 0, 0 },
5857  { "mov.n", ICLASS_xt_iclass_mov_n,
5858    0,
5859    Opcode_mov_n_encode_fns, 0, 0 },
5860  { "movi.n", ICLASS_xt_iclass_movi_n,
5861    0,
5862    Opcode_movi_n_encode_fns, 0, 0 },
5863  { "nop.n", ICLASS_xt_iclass_nopn,
5864    0,
5865    Opcode_nop_n_encode_fns, 0, 0 },
5866  { "ret.n", ICLASS_xt_iclass_retn,
5867    XTENSA_OPCODE_IS_JUMP,
5868    Opcode_ret_n_encode_fns, 0, 0 },
5869  { "s32i.n", ICLASS_xt_iclass_storei4,
5870    0,
5871    Opcode_s32i_n_encode_fns, 0, 0 },
5872  { "addi", ICLASS_xt_iclass_addi,
5873    0,
5874    Opcode_addi_encode_fns, 0, 0 },
5875  { "addmi", ICLASS_xt_iclass_addmi,
5876    0,
5877    Opcode_addmi_encode_fns, 0, 0 },
5878  { "add", ICLASS_xt_iclass_addsub,
5879    0,
5880    Opcode_add_encode_fns, 0, 0 },
5881  { "sub", ICLASS_xt_iclass_addsub,
5882    0,
5883    Opcode_sub_encode_fns, 0, 0 },
5884  { "addx2", ICLASS_xt_iclass_addsub,
5885    0,
5886    Opcode_addx2_encode_fns, 0, 0 },
5887  { "addx4", ICLASS_xt_iclass_addsub,
5888    0,
5889    Opcode_addx4_encode_fns, 0, 0 },
5890  { "addx8", ICLASS_xt_iclass_addsub,
5891    0,
5892    Opcode_addx8_encode_fns, 0, 0 },
5893  { "subx2", ICLASS_xt_iclass_addsub,
5894    0,
5895    Opcode_subx2_encode_fns, 0, 0 },
5896  { "subx4", ICLASS_xt_iclass_addsub,
5897    0,
5898    Opcode_subx4_encode_fns, 0, 0 },
5899  { "subx8", ICLASS_xt_iclass_addsub,
5900    0,
5901    Opcode_subx8_encode_fns, 0, 0 },
5902  { "and", ICLASS_xt_iclass_bit,
5903    0,
5904    Opcode_and_encode_fns, 0, 0 },
5905  { "or", ICLASS_xt_iclass_bit,
5906    0,
5907    Opcode_or_encode_fns, 0, 0 },
5908  { "xor", ICLASS_xt_iclass_bit,
5909    0,
5910    Opcode_xor_encode_fns, 0, 0 },
5911  { "beqi", ICLASS_xt_iclass_bsi8,
5912    XTENSA_OPCODE_IS_BRANCH,
5913    Opcode_beqi_encode_fns, 0, 0 },
5914  { "bnei", ICLASS_xt_iclass_bsi8,
5915    XTENSA_OPCODE_IS_BRANCH,
5916    Opcode_bnei_encode_fns, 0, 0 },
5917  { "bgei", ICLASS_xt_iclass_bsi8,
5918    XTENSA_OPCODE_IS_BRANCH,
5919    Opcode_bgei_encode_fns, 0, 0 },
5920  { "blti", ICLASS_xt_iclass_bsi8,
5921    XTENSA_OPCODE_IS_BRANCH,
5922    Opcode_blti_encode_fns, 0, 0 },
5923  { "bbci", ICLASS_xt_iclass_bsi8b,
5924    XTENSA_OPCODE_IS_BRANCH,
5925    Opcode_bbci_encode_fns, 0, 0 },
5926  { "bbsi", ICLASS_xt_iclass_bsi8b,
5927    XTENSA_OPCODE_IS_BRANCH,
5928    Opcode_bbsi_encode_fns, 0, 0 },
5929  { "bgeui", ICLASS_xt_iclass_bsi8u,
5930    XTENSA_OPCODE_IS_BRANCH,
5931    Opcode_bgeui_encode_fns, 0, 0 },
5932  { "bltui", ICLASS_xt_iclass_bsi8u,
5933    XTENSA_OPCODE_IS_BRANCH,
5934    Opcode_bltui_encode_fns, 0, 0 },
5935  { "beq", ICLASS_xt_iclass_bst8,
5936    XTENSA_OPCODE_IS_BRANCH,
5937    Opcode_beq_encode_fns, 0, 0 },
5938  { "bne", ICLASS_xt_iclass_bst8,
5939    XTENSA_OPCODE_IS_BRANCH,
5940    Opcode_bne_encode_fns, 0, 0 },
5941  { "bge", ICLASS_xt_iclass_bst8,
5942    XTENSA_OPCODE_IS_BRANCH,
5943    Opcode_bge_encode_fns, 0, 0 },
5944  { "blt", ICLASS_xt_iclass_bst8,
5945    XTENSA_OPCODE_IS_BRANCH,
5946    Opcode_blt_encode_fns, 0, 0 },
5947  { "bgeu", ICLASS_xt_iclass_bst8,
5948    XTENSA_OPCODE_IS_BRANCH,
5949    Opcode_bgeu_encode_fns, 0, 0 },
5950  { "bltu", ICLASS_xt_iclass_bst8,
5951    XTENSA_OPCODE_IS_BRANCH,
5952    Opcode_bltu_encode_fns, 0, 0 },
5953  { "bany", ICLASS_xt_iclass_bst8,
5954    XTENSA_OPCODE_IS_BRANCH,
5955    Opcode_bany_encode_fns, 0, 0 },
5956  { "bnone", ICLASS_xt_iclass_bst8,
5957    XTENSA_OPCODE_IS_BRANCH,
5958    Opcode_bnone_encode_fns, 0, 0 },
5959  { "ball", ICLASS_xt_iclass_bst8,
5960    XTENSA_OPCODE_IS_BRANCH,
5961    Opcode_ball_encode_fns, 0, 0 },
5962  { "bnall", ICLASS_xt_iclass_bst8,
5963    XTENSA_OPCODE_IS_BRANCH,
5964    Opcode_bnall_encode_fns, 0, 0 },
5965  { "bbc", ICLASS_xt_iclass_bst8,
5966    XTENSA_OPCODE_IS_BRANCH,
5967    Opcode_bbc_encode_fns, 0, 0 },
5968  { "bbs", ICLASS_xt_iclass_bst8,
5969    XTENSA_OPCODE_IS_BRANCH,
5970    Opcode_bbs_encode_fns, 0, 0 },
5971  { "beqz", ICLASS_xt_iclass_bsz12,
5972    XTENSA_OPCODE_IS_BRANCH,
5973    Opcode_beqz_encode_fns, 0, 0 },
5974  { "bnez", ICLASS_xt_iclass_bsz12,
5975    XTENSA_OPCODE_IS_BRANCH,
5976    Opcode_bnez_encode_fns, 0, 0 },
5977  { "bgez", ICLASS_xt_iclass_bsz12,
5978    XTENSA_OPCODE_IS_BRANCH,
5979    Opcode_bgez_encode_fns, 0, 0 },
5980  { "bltz", ICLASS_xt_iclass_bsz12,
5981    XTENSA_OPCODE_IS_BRANCH,
5982    Opcode_bltz_encode_fns, 0, 0 },
5983  { "call0", ICLASS_xt_iclass_call0,
5984    XTENSA_OPCODE_IS_CALL,
5985    Opcode_call0_encode_fns, 0, 0 },
5986  { "callx0", ICLASS_xt_iclass_callx0,
5987    XTENSA_OPCODE_IS_CALL,
5988    Opcode_callx0_encode_fns, 0, 0 },
5989  { "extui", ICLASS_xt_iclass_exti,
5990    0,
5991    Opcode_extui_encode_fns, 0, 0 },
5992  { "ill", ICLASS_xt_iclass_ill,
5993    0,
5994    Opcode_ill_encode_fns, 0, 0 },
5995  { "j", ICLASS_xt_iclass_jump,
5996    XTENSA_OPCODE_IS_JUMP,
5997    Opcode_j_encode_fns, 0, 0 },
5998  { "jx", ICLASS_xt_iclass_jumpx,
5999    XTENSA_OPCODE_IS_JUMP,
6000    Opcode_jx_encode_fns, 0, 0 },
6001  { "l16ui", ICLASS_xt_iclass_l16ui,
6002    0,
6003    Opcode_l16ui_encode_fns, 0, 0 },
6004  { "l16si", ICLASS_xt_iclass_l16si,
6005    0,
6006    Opcode_l16si_encode_fns, 0, 0 },
6007  { "l32i", ICLASS_xt_iclass_l32i,
6008    0,
6009    Opcode_l32i_encode_fns, 0, 0 },
6010  { "l32r", ICLASS_xt_iclass_l32r,
6011    0,
6012    Opcode_l32r_encode_fns, 0, 0 },
6013  { "l8ui", ICLASS_xt_iclass_l8i,
6014    0,
6015    Opcode_l8ui_encode_fns, 0, 0 },
6016  { "movi", ICLASS_xt_iclass_movi,
6017    0,
6018    Opcode_movi_encode_fns, 0, 0 },
6019  { "moveqz", ICLASS_xt_iclass_movz,
6020    0,
6021    Opcode_moveqz_encode_fns, 0, 0 },
6022  { "movnez", ICLASS_xt_iclass_movz,
6023    0,
6024    Opcode_movnez_encode_fns, 0, 0 },
6025  { "movltz", ICLASS_xt_iclass_movz,
6026    0,
6027    Opcode_movltz_encode_fns, 0, 0 },
6028  { "movgez", ICLASS_xt_iclass_movz,
6029    0,
6030    Opcode_movgez_encode_fns, 0, 0 },
6031  { "neg", ICLASS_xt_iclass_neg,
6032    0,
6033    Opcode_neg_encode_fns, 0, 0 },
6034  { "abs", ICLASS_xt_iclass_neg,
6035    0,
6036    Opcode_abs_encode_fns, 0, 0 },
6037  { "nop", ICLASS_xt_iclass_nop,
6038    0,
6039    Opcode_nop_encode_fns, 0, 0 },
6040  { "ret", ICLASS_xt_iclass_return,
6041    XTENSA_OPCODE_IS_JUMP,
6042    Opcode_ret_encode_fns, 0, 0 },
6043  { "s16i", ICLASS_xt_iclass_s16i,
6044    0,
6045    Opcode_s16i_encode_fns, 0, 0 },
6046  { "s32i", ICLASS_xt_iclass_s32i,
6047    0,
6048    Opcode_s32i_encode_fns, 0, 0 },
6049  { "s8i", ICLASS_xt_iclass_s8i,
6050    0,
6051    Opcode_s8i_encode_fns, 0, 0 },
6052  { "ssr", ICLASS_xt_iclass_sar,
6053    0,
6054    Opcode_ssr_encode_fns, 0, 0 },
6055  { "ssl", ICLASS_xt_iclass_sar,
6056    0,
6057    Opcode_ssl_encode_fns, 0, 0 },
6058  { "ssa8l", ICLASS_xt_iclass_sar,
6059    0,
6060    Opcode_ssa8l_encode_fns, 0, 0 },
6061  { "ssa8b", ICLASS_xt_iclass_sar,
6062    0,
6063    Opcode_ssa8b_encode_fns, 0, 0 },
6064  { "ssai", ICLASS_xt_iclass_sari,
6065    0,
6066    Opcode_ssai_encode_fns, 0, 0 },
6067  { "sll", ICLASS_xt_iclass_shifts,
6068    0,
6069    Opcode_sll_encode_fns, 0, 0 },
6070  { "src", ICLASS_xt_iclass_shiftst,
6071    0,
6072    Opcode_src_encode_fns, 0, 0 },
6073  { "srl", ICLASS_xt_iclass_shiftt,
6074    0,
6075    Opcode_srl_encode_fns, 0, 0 },
6076  { "sra", ICLASS_xt_iclass_shiftt,
6077    0,
6078    Opcode_sra_encode_fns, 0, 0 },
6079  { "slli", ICLASS_xt_iclass_slli,
6080    0,
6081    Opcode_slli_encode_fns, 0, 0 },
6082  { "srai", ICLASS_xt_iclass_srai,
6083    0,
6084    Opcode_srai_encode_fns, 0, 0 },
6085  { "srli", ICLASS_xt_iclass_srli,
6086    0,
6087    Opcode_srli_encode_fns, 0, 0 },
6088  { "memw", ICLASS_xt_iclass_memw,
6089    0,
6090    Opcode_memw_encode_fns, 0, 0 },
6091  { "extw", ICLASS_xt_iclass_extw,
6092    0,
6093    Opcode_extw_encode_fns, 0, 0 },
6094  { "isync", ICLASS_xt_iclass_isync,
6095    0,
6096    Opcode_isync_encode_fns, 0, 0 },
6097  { "rsync", ICLASS_xt_iclass_sync,
6098    0,
6099    Opcode_rsync_encode_fns, 0, 0 },
6100  { "esync", ICLASS_xt_iclass_sync,
6101    0,
6102    Opcode_esync_encode_fns, 0, 0 },
6103  { "dsync", ICLASS_xt_iclass_sync,
6104    0,
6105    Opcode_dsync_encode_fns, 0, 0 },
6106  { "rsil", ICLASS_xt_iclass_rsil,
6107    0,
6108    Opcode_rsil_encode_fns, 0, 0 },
6109  { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
6110    0,
6111    Opcode_rsr_sar_encode_fns, 0, 0 },
6112  { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
6113    0,
6114    Opcode_wsr_sar_encode_fns, 0, 0 },
6115  { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
6116    0,
6117    Opcode_xsr_sar_encode_fns, 0, 0 },
6118  { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
6119    0,
6120    Opcode_rsr_litbase_encode_fns, 0, 0 },
6121  { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
6122    0,
6123    Opcode_wsr_litbase_encode_fns, 0, 0 },
6124  { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
6125    0,
6126    Opcode_xsr_litbase_encode_fns, 0, 0 },
6127  { "rsr.176", ICLASS_xt_iclass_rsr_176,
6128    0,
6129    Opcode_rsr_176_encode_fns, 0, 0 },
6130  { "wsr.176", ICLASS_xt_iclass_wsr_176,
6131    0,
6132    Opcode_wsr_176_encode_fns, 0, 0 },
6133  { "rsr.208", ICLASS_xt_iclass_rsr_208,
6134    0,
6135    Opcode_rsr_208_encode_fns, 0, 0 },
6136  { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
6137    0,
6138    Opcode_rsr_ps_encode_fns, 0, 0 },
6139  { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
6140    0,
6141    Opcode_wsr_ps_encode_fns, 0, 0 },
6142  { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
6143    0,
6144    Opcode_xsr_ps_encode_fns, 0, 0 },
6145  { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
6146    0,
6147    Opcode_rsr_epc1_encode_fns, 0, 0 },
6148  { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
6149    0,
6150    Opcode_wsr_epc1_encode_fns, 0, 0 },
6151  { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
6152    0,
6153    Opcode_xsr_epc1_encode_fns, 0, 0 },
6154  { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
6155    0,
6156    Opcode_rsr_excsave1_encode_fns, 0, 0 },
6157  { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
6158    0,
6159    Opcode_wsr_excsave1_encode_fns, 0, 0 },
6160  { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
6161    0,
6162    Opcode_xsr_excsave1_encode_fns, 0, 0 },
6163  { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
6164    0,
6165    Opcode_rsr_epc2_encode_fns, 0, 0 },
6166  { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
6167    0,
6168    Opcode_wsr_epc2_encode_fns, 0, 0 },
6169  { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
6170    0,
6171    Opcode_xsr_epc2_encode_fns, 0, 0 },
6172  { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
6173    0,
6174    Opcode_rsr_excsave2_encode_fns, 0, 0 },
6175  { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
6176    0,
6177    Opcode_wsr_excsave2_encode_fns, 0, 0 },
6178  { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
6179    0,
6180    Opcode_xsr_excsave2_encode_fns, 0, 0 },
6181  { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
6182    0,
6183    Opcode_rsr_epc3_encode_fns, 0, 0 },
6184  { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
6185    0,
6186    Opcode_wsr_epc3_encode_fns, 0, 0 },
6187  { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
6188    0,
6189    Opcode_xsr_epc3_encode_fns, 0, 0 },
6190  { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
6191    0,
6192    Opcode_rsr_excsave3_encode_fns, 0, 0 },
6193  { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
6194    0,
6195    Opcode_wsr_excsave3_encode_fns, 0, 0 },
6196  { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
6197    0,
6198    Opcode_xsr_excsave3_encode_fns, 0, 0 },
6199  { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
6200    0,
6201    Opcode_rsr_eps2_encode_fns, 0, 0 },
6202  { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
6203    0,
6204    Opcode_wsr_eps2_encode_fns, 0, 0 },
6205  { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
6206    0,
6207    Opcode_xsr_eps2_encode_fns, 0, 0 },
6208  { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
6209    0,
6210    Opcode_rsr_eps3_encode_fns, 0, 0 },
6211  { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
6212    0,
6213    Opcode_wsr_eps3_encode_fns, 0, 0 },
6214  { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
6215    0,
6216    Opcode_xsr_eps3_encode_fns, 0, 0 },
6217  { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
6218    0,
6219    Opcode_rsr_excvaddr_encode_fns, 0, 0 },
6220  { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
6221    0,
6222    Opcode_wsr_excvaddr_encode_fns, 0, 0 },
6223  { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
6224    0,
6225    Opcode_xsr_excvaddr_encode_fns, 0, 0 },
6226  { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
6227    0,
6228    Opcode_rsr_depc_encode_fns, 0, 0 },
6229  { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
6230    0,
6231    Opcode_wsr_depc_encode_fns, 0, 0 },
6232  { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
6233    0,
6234    Opcode_xsr_depc_encode_fns, 0, 0 },
6235  { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
6236    0,
6237    Opcode_rsr_exccause_encode_fns, 0, 0 },
6238  { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
6239    0,
6240    Opcode_wsr_exccause_encode_fns, 0, 0 },
6241  { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
6242    0,
6243    Opcode_xsr_exccause_encode_fns, 0, 0 },
6244  { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
6245    0,
6246    Opcode_rsr_prid_encode_fns, 0, 0 },
6247  { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
6248    0,
6249    Opcode_rsr_vecbase_encode_fns, 0, 0 },
6250  { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
6251    0,
6252    Opcode_wsr_vecbase_encode_fns, 0, 0 },
6253  { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
6254    0,
6255    Opcode_xsr_vecbase_encode_fns, 0, 0 },
6256  { "mul16u", ICLASS_xt_mul16,
6257    0,
6258    Opcode_mul16u_encode_fns, 0, 0 },
6259  { "mul16s", ICLASS_xt_mul16,
6260    0,
6261    Opcode_mul16s_encode_fns, 0, 0 },
6262  { "mull", ICLASS_xt_mul32,
6263    0,
6264    Opcode_mull_encode_fns, 0, 0 },
6265  { "rfi", ICLASS_xt_iclass_rfi,
6266    XTENSA_OPCODE_IS_JUMP,
6267    Opcode_rfi_encode_fns, 0, 0 },
6268  { "waiti", ICLASS_xt_iclass_wait,
6269    0,
6270    Opcode_waiti_encode_fns, 0, 0 },
6271  { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
6272    0,
6273    Opcode_rsr_interrupt_encode_fns, 0, 0 },
6274  { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
6275    0,
6276    Opcode_wsr_intset_encode_fns, 0, 0 },
6277  { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
6278    0,
6279    Opcode_wsr_intclear_encode_fns, 0, 0 },
6280  { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
6281    0,
6282    Opcode_rsr_intenable_encode_fns, 0, 0 },
6283  { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
6284    0,
6285    Opcode_wsr_intenable_encode_fns, 0, 0 },
6286  { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
6287    0,
6288    Opcode_xsr_intenable_encode_fns, 0, 0 },
6289  { "break", ICLASS_xt_iclass_break,
6290    0,
6291    Opcode_break_encode_fns, 0, 0 },
6292  { "break.n", ICLASS_xt_iclass_break_n,
6293    0,
6294    Opcode_break_n_encode_fns, 0, 0 },
6295  { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
6296    0,
6297    Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
6298  { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
6299    0,
6300    Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
6301  { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
6302    0,
6303    Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
6304  { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
6305    0,
6306    Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
6307  { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
6308    0,
6309    Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
6310  { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
6311    0,
6312    Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
6313  { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
6314    0,
6315    Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
6316  { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
6317    0,
6318    Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
6319  { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
6320    0,
6321    Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
6322  { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
6323    0,
6324    Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
6325  { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
6326    0,
6327    Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
6328  { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
6329    0,
6330    Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
6331  { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
6332    0,
6333    Opcode_rsr_debugcause_encode_fns, 0, 0 },
6334  { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
6335    0,
6336    Opcode_wsr_debugcause_encode_fns, 0, 0 },
6337  { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
6338    0,
6339    Opcode_xsr_debugcause_encode_fns, 0, 0 },
6340  { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
6341    0,
6342    Opcode_rsr_icount_encode_fns, 0, 0 },
6343  { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
6344    0,
6345    Opcode_wsr_icount_encode_fns, 0, 0 },
6346  { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
6347    0,
6348    Opcode_xsr_icount_encode_fns, 0, 0 },
6349  { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
6350    0,
6351    Opcode_rsr_icountlevel_encode_fns, 0, 0 },
6352  { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
6353    0,
6354    Opcode_wsr_icountlevel_encode_fns, 0, 0 },
6355  { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
6356    0,
6357    Opcode_xsr_icountlevel_encode_fns, 0, 0 },
6358  { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
6359    0,
6360    Opcode_rsr_ddr_encode_fns, 0, 0 },
6361  { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
6362    0,
6363    Opcode_wsr_ddr_encode_fns, 0, 0 },
6364  { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
6365    0,
6366    Opcode_xsr_ddr_encode_fns, 0, 0 },
6367  { "rfdo", ICLASS_xt_iclass_rfdo,
6368    XTENSA_OPCODE_IS_JUMP,
6369    Opcode_rfdo_encode_fns, 0, 0 },
6370  { "rfdd", ICLASS_xt_iclass_rfdd,
6371    XTENSA_OPCODE_IS_JUMP,
6372    Opcode_rfdd_encode_fns, 0, 0 },
6373  { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
6374    0,
6375    Opcode_wsr_mmid_encode_fns, 0, 0 },
6376  { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
6377    0,
6378    Opcode_rsr_ccount_encode_fns, 0, 0 },
6379  { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
6380    0,
6381    Opcode_wsr_ccount_encode_fns, 0, 0 },
6382  { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
6383    0,
6384    Opcode_xsr_ccount_encode_fns, 0, 0 },
6385  { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
6386    0,
6387    Opcode_rsr_ccompare0_encode_fns, 0, 0 },
6388  { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
6389    0,
6390    Opcode_wsr_ccompare0_encode_fns, 0, 0 },
6391  { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
6392    0,
6393    Opcode_xsr_ccompare0_encode_fns, 0, 0 },
6394  { "idtlb", ICLASS_xt_iclass_idtlb,
6395    0,
6396    Opcode_idtlb_encode_fns, 0, 0 },
6397  { "pdtlb", ICLASS_xt_iclass_rdtlb,
6398    0,
6399    Opcode_pdtlb_encode_fns, 0, 0 },
6400  { "rdtlb0", ICLASS_xt_iclass_rdtlb,
6401    0,
6402    Opcode_rdtlb0_encode_fns, 0, 0 },
6403  { "rdtlb1", ICLASS_xt_iclass_rdtlb,
6404    0,
6405    Opcode_rdtlb1_encode_fns, 0, 0 },
6406  { "wdtlb", ICLASS_xt_iclass_wdtlb,
6407    0,
6408    Opcode_wdtlb_encode_fns, 0, 0 },
6409  { "iitlb", ICLASS_xt_iclass_iitlb,
6410    0,
6411    Opcode_iitlb_encode_fns, 0, 0 },
6412  { "pitlb", ICLASS_xt_iclass_ritlb,
6413    0,
6414    Opcode_pitlb_encode_fns, 0, 0 },
6415  { "ritlb0", ICLASS_xt_iclass_ritlb,
6416    0,
6417    Opcode_ritlb0_encode_fns, 0, 0 },
6418  { "ritlb1", ICLASS_xt_iclass_ritlb,
6419    0,
6420    Opcode_ritlb1_encode_fns, 0, 0 },
6421  { "witlb", ICLASS_xt_iclass_witlb,
6422    0,
6423    Opcode_witlb_encode_fns, 0, 0 },
6424  { "nsa", ICLASS_xt_iclass_nsa,
6425    0,
6426    Opcode_nsa_encode_fns, 0, 0 },
6427  { "nsau", ICLASS_xt_iclass_nsa,
6428    0,
6429    Opcode_nsau_encode_fns, 0, 0 },
6430  { "rer", ICLASS_xt_iclass_rer,
6431    0,
6432    Opcode_rer_encode_fns, 0, 0 },
6433  { "wer", ICLASS_xt_iclass_wer,
6434    0,
6435    Opcode_wer_encode_fns, 0, 0 }
6436};
6437
6438enum xtensa_opcode_id {
6439  OPCODE_EXCW,
6440  OPCODE_RFE,
6441  OPCODE_RFDE,
6442  OPCODE_SYSCALL,
6443  OPCODE_SIMCALL,
6444  OPCODE_ADD_N,
6445  OPCODE_ADDI_N,
6446  OPCODE_BEQZ_N,
6447  OPCODE_BNEZ_N,
6448  OPCODE_ILL_N,
6449  OPCODE_L32I_N,
6450  OPCODE_MOV_N,
6451  OPCODE_MOVI_N,
6452  OPCODE_NOP_N,
6453  OPCODE_RET_N,
6454  OPCODE_S32I_N,
6455  OPCODE_ADDI,
6456  OPCODE_ADDMI,
6457  OPCODE_ADD,
6458  OPCODE_SUB,
6459  OPCODE_ADDX2,
6460  OPCODE_ADDX4,
6461  OPCODE_ADDX8,
6462  OPCODE_SUBX2,
6463  OPCODE_SUBX4,
6464  OPCODE_SUBX8,
6465  OPCODE_AND,
6466  OPCODE_OR,
6467  OPCODE_XOR,
6468  OPCODE_BEQI,
6469  OPCODE_BNEI,
6470  OPCODE_BGEI,
6471  OPCODE_BLTI,
6472  OPCODE_BBCI,
6473  OPCODE_BBSI,
6474  OPCODE_BGEUI,
6475  OPCODE_BLTUI,
6476  OPCODE_BEQ,
6477  OPCODE_BNE,
6478  OPCODE_BGE,
6479  OPCODE_BLT,
6480  OPCODE_BGEU,
6481  OPCODE_BLTU,
6482  OPCODE_BANY,
6483  OPCODE_BNONE,
6484  OPCODE_BALL,
6485  OPCODE_BNALL,
6486  OPCODE_BBC,
6487  OPCODE_BBS,
6488  OPCODE_BEQZ,
6489  OPCODE_BNEZ,
6490  OPCODE_BGEZ,
6491  OPCODE_BLTZ,
6492  OPCODE_CALL0,
6493  OPCODE_CALLX0,
6494  OPCODE_EXTUI,
6495  OPCODE_ILL,
6496  OPCODE_J,
6497  OPCODE_JX,
6498  OPCODE_L16UI,
6499  OPCODE_L16SI,
6500  OPCODE_L32I,
6501  OPCODE_L32R,
6502  OPCODE_L8UI,
6503  OPCODE_MOVI,
6504  OPCODE_MOVEQZ,
6505  OPCODE_MOVNEZ,
6506  OPCODE_MOVLTZ,
6507  OPCODE_MOVGEZ,
6508  OPCODE_NEG,
6509  OPCODE_ABS,
6510  OPCODE_NOP,
6511  OPCODE_RET,
6512  OPCODE_S16I,
6513  OPCODE_S32I,
6514  OPCODE_S8I,
6515  OPCODE_SSR,
6516  OPCODE_SSL,
6517  OPCODE_SSA8L,
6518  OPCODE_SSA8B,
6519  OPCODE_SSAI,
6520  OPCODE_SLL,
6521  OPCODE_SRC,
6522  OPCODE_SRL,
6523  OPCODE_SRA,
6524  OPCODE_SLLI,
6525  OPCODE_SRAI,
6526  OPCODE_SRLI,
6527  OPCODE_MEMW,
6528  OPCODE_EXTW,
6529  OPCODE_ISYNC,
6530  OPCODE_RSYNC,
6531  OPCODE_ESYNC,
6532  OPCODE_DSYNC,
6533  OPCODE_RSIL,
6534  OPCODE_RSR_SAR,
6535  OPCODE_WSR_SAR,
6536  OPCODE_XSR_SAR,
6537  OPCODE_RSR_LITBASE,
6538  OPCODE_WSR_LITBASE,
6539  OPCODE_XSR_LITBASE,
6540  OPCODE_RSR_176,
6541  OPCODE_WSR_176,
6542  OPCODE_RSR_208,
6543  OPCODE_RSR_PS,
6544  OPCODE_WSR_PS,
6545  OPCODE_XSR_PS,
6546  OPCODE_RSR_EPC1,
6547  OPCODE_WSR_EPC1,
6548  OPCODE_XSR_EPC1,
6549  OPCODE_RSR_EXCSAVE1,
6550  OPCODE_WSR_EXCSAVE1,
6551  OPCODE_XSR_EXCSAVE1,
6552  OPCODE_RSR_EPC2,
6553  OPCODE_WSR_EPC2,
6554  OPCODE_XSR_EPC2,
6555  OPCODE_RSR_EXCSAVE2,
6556  OPCODE_WSR_EXCSAVE2,
6557  OPCODE_XSR_EXCSAVE2,
6558  OPCODE_RSR_EPC3,
6559  OPCODE_WSR_EPC3,
6560  OPCODE_XSR_EPC3,
6561  OPCODE_RSR_EXCSAVE3,
6562  OPCODE_WSR_EXCSAVE3,
6563  OPCODE_XSR_EXCSAVE3,
6564  OPCODE_RSR_EPS2,
6565  OPCODE_WSR_EPS2,
6566  OPCODE_XSR_EPS2,
6567  OPCODE_RSR_EPS3,
6568  OPCODE_WSR_EPS3,
6569  OPCODE_XSR_EPS3,
6570  OPCODE_RSR_EXCVADDR,
6571  OPCODE_WSR_EXCVADDR,
6572  OPCODE_XSR_EXCVADDR,
6573  OPCODE_RSR_DEPC,
6574  OPCODE_WSR_DEPC,
6575  OPCODE_XSR_DEPC,
6576  OPCODE_RSR_EXCCAUSE,
6577  OPCODE_WSR_EXCCAUSE,
6578  OPCODE_XSR_EXCCAUSE,
6579  OPCODE_RSR_PRID,
6580  OPCODE_RSR_VECBASE,
6581  OPCODE_WSR_VECBASE,
6582  OPCODE_XSR_VECBASE,
6583  OPCODE_MUL16U,
6584  OPCODE_MUL16S,
6585  OPCODE_MULL,
6586  OPCODE_RFI,
6587  OPCODE_WAITI,
6588  OPCODE_RSR_INTERRUPT,
6589  OPCODE_WSR_INTSET,
6590  OPCODE_WSR_INTCLEAR,
6591  OPCODE_RSR_INTENABLE,
6592  OPCODE_WSR_INTENABLE,
6593  OPCODE_XSR_INTENABLE,
6594  OPCODE_BREAK,
6595  OPCODE_BREAK_N,
6596  OPCODE_RSR_DBREAKA0,
6597  OPCODE_WSR_DBREAKA0,
6598  OPCODE_XSR_DBREAKA0,
6599  OPCODE_RSR_DBREAKC0,
6600  OPCODE_WSR_DBREAKC0,
6601  OPCODE_XSR_DBREAKC0,
6602  OPCODE_RSR_IBREAKA0,
6603  OPCODE_WSR_IBREAKA0,
6604  OPCODE_XSR_IBREAKA0,
6605  OPCODE_RSR_IBREAKENABLE,
6606  OPCODE_WSR_IBREAKENABLE,
6607  OPCODE_XSR_IBREAKENABLE,
6608  OPCODE_RSR_DEBUGCAUSE,
6609  OPCODE_WSR_DEBUGCAUSE,
6610  OPCODE_XSR_DEBUGCAUSE,
6611  OPCODE_RSR_ICOUNT,
6612  OPCODE_WSR_ICOUNT,
6613  OPCODE_XSR_ICOUNT,
6614  OPCODE_RSR_ICOUNTLEVEL,
6615  OPCODE_WSR_ICOUNTLEVEL,
6616  OPCODE_XSR_ICOUNTLEVEL,
6617  OPCODE_RSR_DDR,
6618  OPCODE_WSR_DDR,
6619  OPCODE_XSR_DDR,
6620  OPCODE_RFDO,
6621  OPCODE_RFDD,
6622  OPCODE_WSR_MMID,
6623  OPCODE_RSR_CCOUNT,
6624  OPCODE_WSR_CCOUNT,
6625  OPCODE_XSR_CCOUNT,
6626  OPCODE_RSR_CCOMPARE0,
6627  OPCODE_WSR_CCOMPARE0,
6628  OPCODE_XSR_CCOMPARE0,
6629  OPCODE_IDTLB,
6630  OPCODE_PDTLB,
6631  OPCODE_RDTLB0,
6632  OPCODE_RDTLB1,
6633  OPCODE_WDTLB,
6634  OPCODE_IITLB,
6635  OPCODE_PITLB,
6636  OPCODE_RITLB0,
6637  OPCODE_RITLB1,
6638  OPCODE_WITLB,
6639  OPCODE_NSA,
6640  OPCODE_NSAU,
6641  OPCODE_RER,
6642  OPCODE_WER
6643};
6644
6645
6646/* Slot-specific opcode decode functions.  */
6647
6648static int
6649Slot_inst_decode (const xtensa_insnbuf insn)
6650{
6651  switch (Field_op0_Slot_inst_get (insn))
6652    {
6653    case 0:
6654      switch (Field_op1_Slot_inst_get (insn))
6655	{
6656	case 0:
6657	  switch (Field_op2_Slot_inst_get (insn))
6658	    {
6659	    case 0:
6660	      switch (Field_r_Slot_inst_get (insn))
6661		{
6662		case 0:
6663		  switch (Field_m_Slot_inst_get (insn))
6664		    {
6665		    case 0:
6666		      if (Field_s_Slot_inst_get (insn) == 0 &&
6667			  Field_n_Slot_inst_get (insn) == 0)
6668			return OPCODE_ILL;
6669		      break;
6670		    case 2:
6671		      switch (Field_n_Slot_inst_get (insn))
6672			{
6673			case 0:
6674			  return OPCODE_RET;
6675			case 2:
6676			  return OPCODE_JX;
6677			}
6678		      break;
6679		    case 3:
6680		      if (Field_n_Slot_inst_get (insn) == 0)
6681			return OPCODE_CALLX0;
6682		      break;
6683		    }
6684		  break;
6685		case 2:
6686		  if (Field_s_Slot_inst_get (insn) == 0)
6687		    {
6688		      switch (Field_t_Slot_inst_get (insn))
6689			{
6690			case 0:
6691			  return OPCODE_ISYNC;
6692			case 1:
6693			  return OPCODE_RSYNC;
6694			case 2:
6695			  return OPCODE_ESYNC;
6696			case 3:
6697			  return OPCODE_DSYNC;
6698			case 8:
6699			  return OPCODE_EXCW;
6700			case 12:
6701			  return OPCODE_MEMW;
6702			case 13:
6703			  return OPCODE_EXTW;
6704			case 15:
6705			  return OPCODE_NOP;
6706			}
6707		    }
6708		  break;
6709		case 3:
6710		  switch (Field_t_Slot_inst_get (insn))
6711		    {
6712		    case 0:
6713		      switch (Field_s_Slot_inst_get (insn))
6714			{
6715			case 0:
6716			  return OPCODE_RFE;
6717			case 2:
6718			  return OPCODE_RFDE;
6719			}
6720		      break;
6721		    case 1:
6722		      return OPCODE_RFI;
6723		    }
6724		  break;
6725		case 4:
6726		  return OPCODE_BREAK;
6727		case 5:
6728		  switch (Field_s_Slot_inst_get (insn))
6729		    {
6730		    case 0:
6731		      if (Field_t_Slot_inst_get (insn) == 0)
6732			return OPCODE_SYSCALL;
6733		      break;
6734		    case 1:
6735		      if (Field_t_Slot_inst_get (insn) == 0)
6736			return OPCODE_SIMCALL;
6737		      break;
6738		    }
6739		  break;
6740		case 6:
6741		  return OPCODE_RSIL;
6742		case 7:
6743		  if (Field_t_Slot_inst_get (insn) == 0)
6744		    return OPCODE_WAITI;
6745		  break;
6746		}
6747	      break;
6748	    case 1:
6749	      return OPCODE_AND;
6750	    case 2:
6751	      return OPCODE_OR;
6752	    case 3:
6753	      return OPCODE_XOR;
6754	    case 4:
6755	      switch (Field_r_Slot_inst_get (insn))
6756		{
6757		case 0:
6758		  if (Field_t_Slot_inst_get (insn) == 0)
6759		    return OPCODE_SSR;
6760		  break;
6761		case 1:
6762		  if (Field_t_Slot_inst_get (insn) == 0)
6763		    return OPCODE_SSL;
6764		  break;
6765		case 2:
6766		  if (Field_t_Slot_inst_get (insn) == 0)
6767		    return OPCODE_SSA8L;
6768		  break;
6769		case 3:
6770		  if (Field_t_Slot_inst_get (insn) == 0)
6771		    return OPCODE_SSA8B;
6772		  break;
6773		case 4:
6774		  if (Field_thi3_Slot_inst_get (insn) == 0)
6775		    return OPCODE_SSAI;
6776		  break;
6777		case 6:
6778		  return OPCODE_RER;
6779		case 7:
6780		  return OPCODE_WER;
6781		case 14:
6782		  return OPCODE_NSA;
6783		case 15:
6784		  return OPCODE_NSAU;
6785		}
6786	      break;
6787	    case 5:
6788	      switch (Field_r_Slot_inst_get (insn))
6789		{
6790		case 3:
6791		  return OPCODE_RITLB0;
6792		case 4:
6793		  if (Field_t_Slot_inst_get (insn) == 0)
6794		    return OPCODE_IITLB;
6795		  break;
6796		case 5:
6797		  return OPCODE_PITLB;
6798		case 6:
6799		  return OPCODE_WITLB;
6800		case 7:
6801		  return OPCODE_RITLB1;
6802		case 11:
6803		  return OPCODE_RDTLB0;
6804		case 12:
6805		  if (Field_t_Slot_inst_get (insn) == 0)
6806		    return OPCODE_IDTLB;
6807		  break;
6808		case 13:
6809		  return OPCODE_PDTLB;
6810		case 14:
6811		  return OPCODE_WDTLB;
6812		case 15:
6813		  return OPCODE_RDTLB1;
6814		}
6815	      break;
6816	    case 6:
6817	      switch (Field_s_Slot_inst_get (insn))
6818		{
6819		case 0:
6820		  return OPCODE_NEG;
6821		case 1:
6822		  return OPCODE_ABS;
6823		}
6824	      break;
6825	    case 8:
6826	      return OPCODE_ADD;
6827	    case 9:
6828	      return OPCODE_ADDX2;
6829	    case 10:
6830	      return OPCODE_ADDX4;
6831	    case 11:
6832	      return OPCODE_ADDX8;
6833	    case 12:
6834	      return OPCODE_SUB;
6835	    case 13:
6836	      return OPCODE_SUBX2;
6837	    case 14:
6838	      return OPCODE_SUBX4;
6839	    case 15:
6840	      return OPCODE_SUBX8;
6841	    }
6842	  break;
6843	case 1:
6844	  switch (Field_op2_Slot_inst_get (insn))
6845	    {
6846	    case 0:
6847	    case 1:
6848	      return OPCODE_SLLI;
6849	    case 2:
6850	    case 3:
6851	      return OPCODE_SRAI;
6852	    case 4:
6853	      return OPCODE_SRLI;
6854	    case 6:
6855	      switch (Field_sr_Slot_inst_get (insn))
6856		{
6857		case 3:
6858		  return OPCODE_XSR_SAR;
6859		case 5:
6860		  return OPCODE_XSR_LITBASE;
6861		case 96:
6862		  return OPCODE_XSR_IBREAKENABLE;
6863		case 104:
6864		  return OPCODE_XSR_DDR;
6865		case 128:
6866		  return OPCODE_XSR_IBREAKA0;
6867		case 144:
6868		  return OPCODE_XSR_DBREAKA0;
6869		case 160:
6870		  return OPCODE_XSR_DBREAKC0;
6871		case 177:
6872		  return OPCODE_XSR_EPC1;
6873		case 178:
6874		  return OPCODE_XSR_EPC2;
6875		case 179:
6876		  return OPCODE_XSR_EPC3;
6877		case 192:
6878		  return OPCODE_XSR_DEPC;
6879		case 194:
6880		  return OPCODE_XSR_EPS2;
6881		case 195:
6882		  return OPCODE_XSR_EPS3;
6883		case 209:
6884		  return OPCODE_XSR_EXCSAVE1;
6885		case 210:
6886		  return OPCODE_XSR_EXCSAVE2;
6887		case 211:
6888		  return OPCODE_XSR_EXCSAVE3;
6889		case 228:
6890		  return OPCODE_XSR_INTENABLE;
6891		case 230:
6892		  return OPCODE_XSR_PS;
6893		case 231:
6894		  return OPCODE_XSR_VECBASE;
6895		case 232:
6896		  return OPCODE_XSR_EXCCAUSE;
6897		case 233:
6898		  return OPCODE_XSR_DEBUGCAUSE;
6899		case 234:
6900		  return OPCODE_XSR_CCOUNT;
6901		case 236:
6902		  return OPCODE_XSR_ICOUNT;
6903		case 237:
6904		  return OPCODE_XSR_ICOUNTLEVEL;
6905		case 238:
6906		  return OPCODE_XSR_EXCVADDR;
6907		case 240:
6908		  return OPCODE_XSR_CCOMPARE0;
6909		}
6910	      break;
6911	    case 8:
6912	      return OPCODE_SRC;
6913	    case 9:
6914	      if (Field_s_Slot_inst_get (insn) == 0)
6915		return OPCODE_SRL;
6916	      break;
6917	    case 10:
6918	      if (Field_t_Slot_inst_get (insn) == 0)
6919		return OPCODE_SLL;
6920	      break;
6921	    case 11:
6922	      if (Field_s_Slot_inst_get (insn) == 0)
6923		return OPCODE_SRA;
6924	      break;
6925	    case 12:
6926	      return OPCODE_MUL16U;
6927	    case 13:
6928	      return OPCODE_MUL16S;
6929	    case 15:
6930	      switch (Field_r_Slot_inst_get (insn))
6931		{
6932		case 14:
6933		  if (Field_t_Slot_inst_get (insn) == 0)
6934		    return OPCODE_RFDO;
6935		  if (Field_t_Slot_inst_get (insn) == 1)
6936		    return OPCODE_RFDD;
6937		  break;
6938		}
6939	      break;
6940	    }
6941	  break;
6942	case 2:
6943	  if (Field_op2_Slot_inst_get (insn) == 8)
6944	    return OPCODE_MULL;
6945	  break;
6946	case 3:
6947	  switch (Field_op2_Slot_inst_get (insn))
6948	    {
6949	    case 0:
6950	      switch (Field_sr_Slot_inst_get (insn))
6951		{
6952		case 3:
6953		  return OPCODE_RSR_SAR;
6954		case 5:
6955		  return OPCODE_RSR_LITBASE;
6956		case 96:
6957		  return OPCODE_RSR_IBREAKENABLE;
6958		case 104:
6959		  return OPCODE_RSR_DDR;
6960		case 128:
6961		  return OPCODE_RSR_IBREAKA0;
6962		case 144:
6963		  return OPCODE_RSR_DBREAKA0;
6964		case 160:
6965		  return OPCODE_RSR_DBREAKC0;
6966		case 176:
6967		  return OPCODE_RSR_176;
6968		case 177:
6969		  return OPCODE_RSR_EPC1;
6970		case 178:
6971		  return OPCODE_RSR_EPC2;
6972		case 179:
6973		  return OPCODE_RSR_EPC3;
6974		case 192:
6975		  return OPCODE_RSR_DEPC;
6976		case 194:
6977		  return OPCODE_RSR_EPS2;
6978		case 195:
6979		  return OPCODE_RSR_EPS3;
6980		case 208:
6981		  return OPCODE_RSR_208;
6982		case 209:
6983		  return OPCODE_RSR_EXCSAVE1;
6984		case 210:
6985		  return OPCODE_RSR_EXCSAVE2;
6986		case 211:
6987		  return OPCODE_RSR_EXCSAVE3;
6988		case 226:
6989		  return OPCODE_RSR_INTERRUPT;
6990		case 228:
6991		  return OPCODE_RSR_INTENABLE;
6992		case 230:
6993		  return OPCODE_RSR_PS;
6994		case 231:
6995		  return OPCODE_RSR_VECBASE;
6996		case 232:
6997		  return OPCODE_RSR_EXCCAUSE;
6998		case 233:
6999		  return OPCODE_RSR_DEBUGCAUSE;
7000		case 234:
7001		  return OPCODE_RSR_CCOUNT;
7002		case 235:
7003		  return OPCODE_RSR_PRID;
7004		case 236:
7005		  return OPCODE_RSR_ICOUNT;
7006		case 237:
7007		  return OPCODE_RSR_ICOUNTLEVEL;
7008		case 238:
7009		  return OPCODE_RSR_EXCVADDR;
7010		case 240:
7011		  return OPCODE_RSR_CCOMPARE0;
7012		}
7013	      break;
7014	    case 1:
7015	      switch (Field_sr_Slot_inst_get (insn))
7016		{
7017		case 3:
7018		  return OPCODE_WSR_SAR;
7019		case 5:
7020		  return OPCODE_WSR_LITBASE;
7021		case 89:
7022		  return OPCODE_WSR_MMID;
7023		case 96:
7024		  return OPCODE_WSR_IBREAKENABLE;
7025		case 104:
7026		  return OPCODE_WSR_DDR;
7027		case 128:
7028		  return OPCODE_WSR_IBREAKA0;
7029		case 144:
7030		  return OPCODE_WSR_DBREAKA0;
7031		case 160:
7032		  return OPCODE_WSR_DBREAKC0;
7033		case 176:
7034		  return OPCODE_WSR_176;
7035		case 177:
7036		  return OPCODE_WSR_EPC1;
7037		case 178:
7038		  return OPCODE_WSR_EPC2;
7039		case 179:
7040		  return OPCODE_WSR_EPC3;
7041		case 192:
7042		  return OPCODE_WSR_DEPC;
7043		case 194:
7044		  return OPCODE_WSR_EPS2;
7045		case 195:
7046		  return OPCODE_WSR_EPS3;
7047		case 209:
7048		  return OPCODE_WSR_EXCSAVE1;
7049		case 210:
7050		  return OPCODE_WSR_EXCSAVE2;
7051		case 211:
7052		  return OPCODE_WSR_EXCSAVE3;
7053		case 226:
7054		  return OPCODE_WSR_INTSET;
7055		case 227:
7056		  return OPCODE_WSR_INTCLEAR;
7057		case 228:
7058		  return OPCODE_WSR_INTENABLE;
7059		case 230:
7060		  return OPCODE_WSR_PS;
7061		case 231:
7062		  return OPCODE_WSR_VECBASE;
7063		case 232:
7064		  return OPCODE_WSR_EXCCAUSE;
7065		case 233:
7066		  return OPCODE_WSR_DEBUGCAUSE;
7067		case 234:
7068		  return OPCODE_WSR_CCOUNT;
7069		case 236:
7070		  return OPCODE_WSR_ICOUNT;
7071		case 237:
7072		  return OPCODE_WSR_ICOUNTLEVEL;
7073		case 238:
7074		  return OPCODE_WSR_EXCVADDR;
7075		case 240:
7076		  return OPCODE_WSR_CCOMPARE0;
7077		}
7078	      break;
7079	    case 8:
7080	      return OPCODE_MOVEQZ;
7081	    case 9:
7082	      return OPCODE_MOVNEZ;
7083	    case 10:
7084	      return OPCODE_MOVLTZ;
7085	    case 11:
7086	      return OPCODE_MOVGEZ;
7087	    }
7088	  break;
7089	case 4:
7090	case 5:
7091	  return OPCODE_EXTUI;
7092	}
7093      break;
7094    case 1:
7095      return OPCODE_L32R;
7096    case 2:
7097      switch (Field_r_Slot_inst_get (insn))
7098	{
7099	case 0:
7100	  return OPCODE_L8UI;
7101	case 1:
7102	  return OPCODE_L16UI;
7103	case 2:
7104	  return OPCODE_L32I;
7105	case 4:
7106	  return OPCODE_S8I;
7107	case 5:
7108	  return OPCODE_S16I;
7109	case 6:
7110	  return OPCODE_S32I;
7111	case 9:
7112	  return OPCODE_L16SI;
7113	case 10:
7114	  return OPCODE_MOVI;
7115	case 12:
7116	  return OPCODE_ADDI;
7117	case 13:
7118	  return OPCODE_ADDMI;
7119	}
7120      break;
7121    case 5:
7122      if (Field_n_Slot_inst_get (insn) == 0)
7123	return OPCODE_CALL0;
7124      break;
7125    case 6:
7126      switch (Field_n_Slot_inst_get (insn))
7127	{
7128	case 0:
7129	  return OPCODE_J;
7130	case 1:
7131	  switch (Field_m_Slot_inst_get (insn))
7132	    {
7133	    case 0:
7134	      return OPCODE_BEQZ;
7135	    case 1:
7136	      return OPCODE_BNEZ;
7137	    case 2:
7138	      return OPCODE_BLTZ;
7139	    case 3:
7140	      return OPCODE_BGEZ;
7141	    }
7142	  break;
7143	case 2:
7144	  switch (Field_m_Slot_inst_get (insn))
7145	    {
7146	    case 0:
7147	      return OPCODE_BEQI;
7148	    case 1:
7149	      return OPCODE_BNEI;
7150	    case 2:
7151	      return OPCODE_BLTI;
7152	    case 3:
7153	      return OPCODE_BGEI;
7154	    }
7155	  break;
7156	case 3:
7157	  switch (Field_m_Slot_inst_get (insn))
7158	    {
7159	    case 2:
7160	      return OPCODE_BLTUI;
7161	    case 3:
7162	      return OPCODE_BGEUI;
7163	    }
7164	  break;
7165	}
7166      break;
7167    case 7:
7168      switch (Field_r_Slot_inst_get (insn))
7169	{
7170	case 0:
7171	  return OPCODE_BNONE;
7172	case 1:
7173	  return OPCODE_BEQ;
7174	case 2:
7175	  return OPCODE_BLT;
7176	case 3:
7177	  return OPCODE_BLTU;
7178	case 4:
7179	  return OPCODE_BALL;
7180	case 5:
7181	  return OPCODE_BBC;
7182	case 6:
7183	case 7:
7184	  return OPCODE_BBCI;
7185	case 8:
7186	  return OPCODE_BANY;
7187	case 9:
7188	  return OPCODE_BNE;
7189	case 10:
7190	  return OPCODE_BGE;
7191	case 11:
7192	  return OPCODE_BGEU;
7193	case 12:
7194	  return OPCODE_BNALL;
7195	case 13:
7196	  return OPCODE_BBS;
7197	case 14:
7198	case 15:
7199	  return OPCODE_BBSI;
7200	}
7201      break;
7202    }
7203  return XTENSA_UNDEFINED;
7204}
7205
7206static int
7207Slot_inst16a_decode (const xtensa_insnbuf insn)
7208{
7209  switch (Field_op0_Slot_inst16a_get (insn))
7210    {
7211    case 8:
7212      return OPCODE_L32I_N;
7213    case 9:
7214      return OPCODE_S32I_N;
7215    case 10:
7216      return OPCODE_ADD_N;
7217    case 11:
7218      return OPCODE_ADDI_N;
7219    }
7220  return XTENSA_UNDEFINED;
7221}
7222
7223static int
7224Slot_inst16b_decode (const xtensa_insnbuf insn)
7225{
7226  switch (Field_op0_Slot_inst16b_get (insn))
7227    {
7228    case 12:
7229      switch (Field_i_Slot_inst16b_get (insn))
7230	{
7231	case 0:
7232	  return OPCODE_MOVI_N;
7233	case 1:
7234	  switch (Field_z_Slot_inst16b_get (insn))
7235	    {
7236	    case 0:
7237	      return OPCODE_BEQZ_N;
7238	    case 1:
7239	      return OPCODE_BNEZ_N;
7240	    }
7241	  break;
7242	}
7243      break;
7244    case 13:
7245      switch (Field_r_Slot_inst16b_get (insn))
7246	{
7247	case 0:
7248	  return OPCODE_MOV_N;
7249	case 15:
7250	  switch (Field_t_Slot_inst16b_get (insn))
7251	    {
7252	    case 0:
7253	      return OPCODE_RET_N;
7254	    case 2:
7255	      return OPCODE_BREAK_N;
7256	    case 3:
7257	      if (Field_s_Slot_inst16b_get (insn) == 0)
7258		return OPCODE_NOP_N;
7259	      break;
7260	    case 6:
7261	      if (Field_s_Slot_inst16b_get (insn) == 0)
7262		return OPCODE_ILL_N;
7263	      break;
7264	    }
7265	  break;
7266	}
7267      break;
7268    }
7269  return XTENSA_UNDEFINED;
7270}
7271
7272
7273/* Instruction slots.  */
7274
7275static void
7276Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
7277			    xtensa_insnbuf slotbuf)
7278{
7279  slotbuf[0] = (insn[0] & 0xffffff);
7280}
7281
7282static void
7283Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
7284			    const xtensa_insnbuf slotbuf)
7285{
7286  insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
7287}
7288
7289static void
7290Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
7291				xtensa_insnbuf slotbuf)
7292{
7293  slotbuf[0] = (insn[0] & 0xffff);
7294}
7295
7296static void
7297Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
7298				const xtensa_insnbuf slotbuf)
7299{
7300  insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
7301}
7302
7303static void
7304Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
7305				xtensa_insnbuf slotbuf)
7306{
7307  slotbuf[0] = (insn[0] & 0xffff);
7308}
7309
7310static void
7311Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
7312				const xtensa_insnbuf slotbuf)
7313{
7314  insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
7315}
7316
7317static xtensa_get_field_fn
7318Slot_inst_get_field_fns[] = {
7319  Field_t_Slot_inst_get,
7320  Field_bbi4_Slot_inst_get,
7321  Field_bbi_Slot_inst_get,
7322  Field_imm12_Slot_inst_get,
7323  Field_imm8_Slot_inst_get,
7324  Field_s_Slot_inst_get,
7325  Field_imm12b_Slot_inst_get,
7326  Field_imm16_Slot_inst_get,
7327  Field_m_Slot_inst_get,
7328  Field_n_Slot_inst_get,
7329  Field_offset_Slot_inst_get,
7330  Field_op0_Slot_inst_get,
7331  Field_op1_Slot_inst_get,
7332  Field_op2_Slot_inst_get,
7333  Field_r_Slot_inst_get,
7334  Field_sa4_Slot_inst_get,
7335  Field_sae4_Slot_inst_get,
7336  Field_sae_Slot_inst_get,
7337  Field_sal_Slot_inst_get,
7338  Field_sargt_Slot_inst_get,
7339  Field_sas4_Slot_inst_get,
7340  Field_sas_Slot_inst_get,
7341  Field_sr_Slot_inst_get,
7342  Field_st_Slot_inst_get,
7343  Field_thi3_Slot_inst_get,
7344  Field_imm4_Slot_inst_get,
7345  0,
7346  0,
7347  0,
7348  0,
7349  0,
7350  0,
7351  0,
7352  0,
7353  Field_xt_wbr15_imm_Slot_inst_get,
7354  Field_xt_wbr18_imm_Slot_inst_get,
7355  Implicit_Field_ar0_get
7356};
7357
7358static xtensa_set_field_fn
7359Slot_inst_set_field_fns[] = {
7360  Field_t_Slot_inst_set,
7361  Field_bbi4_Slot_inst_set,
7362  Field_bbi_Slot_inst_set,
7363  Field_imm12_Slot_inst_set,
7364  Field_imm8_Slot_inst_set,
7365  Field_s_Slot_inst_set,
7366  Field_imm12b_Slot_inst_set,
7367  Field_imm16_Slot_inst_set,
7368  Field_m_Slot_inst_set,
7369  Field_n_Slot_inst_set,
7370  Field_offset_Slot_inst_set,
7371  Field_op0_Slot_inst_set,
7372  Field_op1_Slot_inst_set,
7373  Field_op2_Slot_inst_set,
7374  Field_r_Slot_inst_set,
7375  Field_sa4_Slot_inst_set,
7376  Field_sae4_Slot_inst_set,
7377  Field_sae_Slot_inst_set,
7378  Field_sal_Slot_inst_set,
7379  Field_sargt_Slot_inst_set,
7380  Field_sas4_Slot_inst_set,
7381  Field_sas_Slot_inst_set,
7382  Field_sr_Slot_inst_set,
7383  Field_st_Slot_inst_set,
7384  Field_thi3_Slot_inst_set,
7385  Field_imm4_Slot_inst_set,
7386  0,
7387  0,
7388  0,
7389  0,
7390  0,
7391  0,
7392  0,
7393  0,
7394  Field_xt_wbr15_imm_Slot_inst_set,
7395  Field_xt_wbr18_imm_Slot_inst_set,
7396  Implicit_Field_set
7397};
7398
7399static xtensa_get_field_fn
7400Slot_inst16a_get_field_fns[] = {
7401  Field_t_Slot_inst16a_get,
7402  0,
7403  0,
7404  0,
7405  0,
7406  Field_s_Slot_inst16a_get,
7407  0,
7408  0,
7409  0,
7410  0,
7411  0,
7412  Field_op0_Slot_inst16a_get,
7413  0,
7414  0,
7415  Field_r_Slot_inst16a_get,
7416  0,
7417  0,
7418  0,
7419  0,
7420  0,
7421  0,
7422  0,
7423  Field_sr_Slot_inst16a_get,
7424  Field_st_Slot_inst16a_get,
7425  0,
7426  Field_imm4_Slot_inst16a_get,
7427  Field_i_Slot_inst16a_get,
7428  Field_imm6lo_Slot_inst16a_get,
7429  Field_imm6hi_Slot_inst16a_get,
7430  Field_imm7lo_Slot_inst16a_get,
7431  Field_imm7hi_Slot_inst16a_get,
7432  Field_z_Slot_inst16a_get,
7433  Field_imm6_Slot_inst16a_get,
7434  Field_imm7_Slot_inst16a_get,
7435  0,
7436  0,
7437  Implicit_Field_ar0_get
7438};
7439
7440static xtensa_set_field_fn
7441Slot_inst16a_set_field_fns[] = {
7442  Field_t_Slot_inst16a_set,
7443  0,
7444  0,
7445  0,
7446  0,
7447  Field_s_Slot_inst16a_set,
7448  0,
7449  0,
7450  0,
7451  0,
7452  0,
7453  Field_op0_Slot_inst16a_set,
7454  0,
7455  0,
7456  Field_r_Slot_inst16a_set,
7457  0,
7458  0,
7459  0,
7460  0,
7461  0,
7462  0,
7463  0,
7464  Field_sr_Slot_inst16a_set,
7465  Field_st_Slot_inst16a_set,
7466  0,
7467  Field_imm4_Slot_inst16a_set,
7468  Field_i_Slot_inst16a_set,
7469  Field_imm6lo_Slot_inst16a_set,
7470  Field_imm6hi_Slot_inst16a_set,
7471  Field_imm7lo_Slot_inst16a_set,
7472  Field_imm7hi_Slot_inst16a_set,
7473  Field_z_Slot_inst16a_set,
7474  Field_imm6_Slot_inst16a_set,
7475  Field_imm7_Slot_inst16a_set,
7476  0,
7477  0,
7478  Implicit_Field_set
7479};
7480
7481static xtensa_get_field_fn
7482Slot_inst16b_get_field_fns[] = {
7483  Field_t_Slot_inst16b_get,
7484  0,
7485  0,
7486  0,
7487  0,
7488  Field_s_Slot_inst16b_get,
7489  0,
7490  0,
7491  0,
7492  0,
7493  0,
7494  Field_op0_Slot_inst16b_get,
7495  0,
7496  0,
7497  Field_r_Slot_inst16b_get,
7498  0,
7499  0,
7500  0,
7501  0,
7502  0,
7503  0,
7504  0,
7505  Field_sr_Slot_inst16b_get,
7506  Field_st_Slot_inst16b_get,
7507  0,
7508  Field_imm4_Slot_inst16b_get,
7509  Field_i_Slot_inst16b_get,
7510  Field_imm6lo_Slot_inst16b_get,
7511  Field_imm6hi_Slot_inst16b_get,
7512  Field_imm7lo_Slot_inst16b_get,
7513  Field_imm7hi_Slot_inst16b_get,
7514  Field_z_Slot_inst16b_get,
7515  Field_imm6_Slot_inst16b_get,
7516  Field_imm7_Slot_inst16b_get,
7517  0,
7518  0,
7519  Implicit_Field_ar0_get
7520};
7521
7522static xtensa_set_field_fn
7523Slot_inst16b_set_field_fns[] = {
7524  Field_t_Slot_inst16b_set,
7525  0,
7526  0,
7527  0,
7528  0,
7529  Field_s_Slot_inst16b_set,
7530  0,
7531  0,
7532  0,
7533  0,
7534  0,
7535  Field_op0_Slot_inst16b_set,
7536  0,
7537  0,
7538  Field_r_Slot_inst16b_set,
7539  0,
7540  0,
7541  0,
7542  0,
7543  0,
7544  0,
7545  0,
7546  Field_sr_Slot_inst16b_set,
7547  Field_st_Slot_inst16b_set,
7548  0,
7549  Field_imm4_Slot_inst16b_set,
7550  Field_i_Slot_inst16b_set,
7551  Field_imm6lo_Slot_inst16b_set,
7552  Field_imm6hi_Slot_inst16b_set,
7553  Field_imm7lo_Slot_inst16b_set,
7554  Field_imm7hi_Slot_inst16b_set,
7555  Field_z_Slot_inst16b_set,
7556  Field_imm6_Slot_inst16b_set,
7557  Field_imm7_Slot_inst16b_set,
7558  0,
7559  0,
7560  Implicit_Field_set
7561};
7562
7563static xtensa_slot_internal slots[] = {
7564  { "Inst", "x24", 0,
7565    Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
7566    Slot_inst_get_field_fns, Slot_inst_set_field_fns,
7567    Slot_inst_decode, "nop" },
7568  { "Inst16a", "x16a", 0,
7569    Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
7570    Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
7571    Slot_inst16a_decode, "" },
7572  { "Inst16b", "x16b", 0,
7573    Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
7574    Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
7575    Slot_inst16b_decode, "nop.n" }
7576};
7577
7578
7579/* Instruction formats.  */
7580
7581static void
7582Format_x24_encode (xtensa_insnbuf insn)
7583{
7584  insn[0] = 0;
7585}
7586
7587static void
7588Format_x16a_encode (xtensa_insnbuf insn)
7589{
7590  insn[0] = 0x8;
7591}
7592
7593static void
7594Format_x16b_encode (xtensa_insnbuf insn)
7595{
7596  insn[0] = 0xc;
7597}
7598
7599static int Format_x24_slots[] = { 0 };
7600
7601static int Format_x16a_slots[] = { 1 };
7602
7603static int Format_x16b_slots[] = { 2 };
7604
7605static xtensa_format_internal formats[] = {
7606  { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
7607  { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
7608  { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
7609};
7610
7611
7612static int
7613format_decoder (const xtensa_insnbuf insn)
7614{
7615  if ((insn[0] & 0x8) == 0)
7616    return 0; /* x24 */
7617  if ((insn[0] & 0xc) == 0x8)
7618    return 1; /* x16a */
7619  if ((insn[0] & 0xe) == 0xc)
7620    return 2; /* x16b */
7621  return -1;
7622}
7623
7624static int length_table[16] = {
7625  3,
7626  3,
7627  3,
7628  3,
7629  3,
7630  3,
7631  3,
7632  3,
7633  2,
7634  2,
7635  2,
7636  2,
7637  2,
7638  2,
7639  -1,
7640  -1
7641};
7642
7643static int
7644length_decoder (const unsigned char *insn)
7645{
7646  int op0 = insn[0] & 0xf;
7647  return length_table[op0];
7648}
7649
7650
7651/* Top-level ISA structure.  */
7652
7653static xtensa_isa_internal xtensa_modules = {
7654  0 /* little-endian */,
7655  3 /* insn_size */, 0,
7656  3, formats, format_decoder, length_decoder,
7657  3, slots,
7658  37 /* num_fields */,
7659  65, operands,
7660  159, iclasses,
7661  204, opcodes, 0,
7662  1, regfiles,
7663  NUM_STATES, states, 0,
7664  NUM_SYSREGS, sysregs, 0,
7665  { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
7666  0, interfaces, 0,
7667  0, funcUnits, 0
7668};
7669