1*c621b414SMax Filippov /* 2*c621b414SMax Filippov * xtensa/config/core-matmap.h -- Memory access and translation mapping 3*c621b414SMax Filippov * parameters (CHAL) of the Xtensa processor core configuration. 4*c621b414SMax Filippov * 5*c621b414SMax Filippov * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes 6*c621b414SMax Filippov * this file) for more details. 7*c621b414SMax Filippov * 8*c621b414SMax Filippov * In the Xtensa processor products released to date, all parameters 9*c621b414SMax Filippov * defined in this file are derivable (at least in theory) from 10*c621b414SMax Filippov * information contained in the core-isa.h header file. 11*c621b414SMax Filippov * In particular, the following core configuration parameters are relevant: 12*c621b414SMax Filippov * XCHAL_HAVE_CACHEATTR 13*c621b414SMax Filippov * XCHAL_HAVE_MIMIC_CACHEATTR 14*c621b414SMax Filippov * XCHAL_HAVE_XLT_CACHEATTR 15*c621b414SMax Filippov * XCHAL_HAVE_PTP_MMU 16*c621b414SMax Filippov * XCHAL_ITLB_ARF_ENTRIES_LOG2 17*c621b414SMax Filippov * XCHAL_DTLB_ARF_ENTRIES_LOG2 18*c621b414SMax Filippov * XCHAL_DCACHE_IS_WRITEBACK 19*c621b414SMax Filippov * XCHAL_ICACHE_SIZE (presence of I-cache) 20*c621b414SMax Filippov * XCHAL_DCACHE_SIZE (presence of D-cache) 21*c621b414SMax Filippov * XCHAL_HW_VERSION_MAJOR 22*c621b414SMax Filippov * XCHAL_HW_VERSION_MINOR 23*c621b414SMax Filippov */ 24*c621b414SMax Filippov 25*c621b414SMax Filippov /* Copyright (c) 1999-2010 Tensilica Inc. 26*c621b414SMax Filippov 27*c621b414SMax Filippov Permission is hereby granted, free of charge, to any person obtaining 28*c621b414SMax Filippov a copy of this software and associated documentation files (the 29*c621b414SMax Filippov "Software"), to deal in the Software without restriction, including 30*c621b414SMax Filippov without limitation the rights to use, copy, modify, merge, publish, 31*c621b414SMax Filippov distribute, sublicense, and/or sell copies of the Software, and to 32*c621b414SMax Filippov permit persons to whom the Software is furnished to do so, subject to 33*c621b414SMax Filippov the following conditions: 34*c621b414SMax Filippov 35*c621b414SMax Filippov The above copyright notice and this permission notice shall be included 36*c621b414SMax Filippov in all copies or substantial portions of the Software. 37*c621b414SMax Filippov 38*c621b414SMax Filippov THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39*c621b414SMax Filippov EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 40*c621b414SMax Filippov MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 41*c621b414SMax Filippov IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 42*c621b414SMax Filippov CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 43*c621b414SMax Filippov TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 44*c621b414SMax Filippov SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 45*c621b414SMax Filippov 46*c621b414SMax Filippov #ifndef XTENSA_CONFIG_CORE_MATMAP_H 47*c621b414SMax Filippov #define XTENSA_CONFIG_CORE_MATMAP_H 48*c621b414SMax Filippov 49*c621b414SMax Filippov /*---------------------------------------------------------------------- 50*c621b414SMax Filippov CACHE (MEMORY ACCESS) ATTRIBUTES 51*c621b414SMax Filippov ----------------------------------------------------------------------*/ 52*c621b414SMax Filippov 53*c621b414SMax Filippov 54*c621b414SMax Filippov /* Cache Attribute encodings -- lists of access modes for each cache attribute: */ 55*c621b414SMax Filippov #define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ 56*c621b414SMax Filippov XTHAL_FAM_CACHED XCHAL_SEP \ 57*c621b414SMax Filippov XTHAL_FAM_BYPASS XCHAL_SEP \ 58*c621b414SMax Filippov XTHAL_FAM_CACHED XCHAL_SEP \ 59*c621b414SMax Filippov XTHAL_FAM_CACHED XCHAL_SEP \ 60*c621b414SMax Filippov XTHAL_FAM_CACHED XCHAL_SEP \ 61*c621b414SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 62*c621b414SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 63*c621b414SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 64*c621b414SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 65*c621b414SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 66*c621b414SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 67*c621b414SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 68*c621b414SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 69*c621b414SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 70*c621b414SMax Filippov XTHAL_FAM_EXCEPTION 71*c621b414SMax Filippov #define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \ 72*c621b414SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 73*c621b414SMax Filippov XTHAL_LAM_BYPASSG XCHAL_SEP \ 74*c621b414SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 75*c621b414SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 76*c621b414SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 77*c621b414SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 78*c621b414SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 79*c621b414SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 80*c621b414SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 81*c621b414SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 82*c621b414SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 83*c621b414SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 84*c621b414SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 85*c621b414SMax Filippov XTHAL_LAM_ISOLATE XCHAL_SEP \ 86*c621b414SMax Filippov XTHAL_LAM_EXCEPTION 87*c621b414SMax Filippov #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \ 88*c621b414SMax Filippov XTHAL_SAM_WRITETHRU XCHAL_SEP \ 89*c621b414SMax Filippov XTHAL_SAM_BYPASS XCHAL_SEP \ 90*c621b414SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 91*c621b414SMax Filippov XTHAL_SAM_WRITEBACK XCHAL_SEP \ 92*c621b414SMax Filippov XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \ 93*c621b414SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 94*c621b414SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 95*c621b414SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 96*c621b414SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 97*c621b414SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 98*c621b414SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 99*c621b414SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 100*c621b414SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 101*c621b414SMax Filippov XTHAL_SAM_ISOLATE XCHAL_SEP \ 102*c621b414SMax Filippov XTHAL_SAM_EXCEPTION 103*c621b414SMax Filippov 104*c621b414SMax Filippov 105*c621b414SMax Filippov /* 106*c621b414SMax Filippov * Specific encoded cache attribute values of general interest. 107*c621b414SMax Filippov * If a specific cache mode is not available, the closest available 108*c621b414SMax Filippov * one is returned instead (eg. writethru instead of writeback, 109*c621b414SMax Filippov * bypass instead of writethru). 110*c621b414SMax Filippov */ 111*c621b414SMax Filippov #define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ 112*c621b414SMax Filippov #define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */ 113*c621b414SMax Filippov #define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */ 114*c621b414SMax Filippov #define XCHAL_CA_WRITEBACK_NOALLOC 4 /* cache enabled (write-back no-allocate) mode */ 115*c621b414SMax Filippov #define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ 116*c621b414SMax Filippov #define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */ 117*c621b414SMax Filippov 118*c621b414SMax Filippov 119*c621b414SMax Filippov /*---------------------------------------------------------------------- 120*c621b414SMax Filippov MMU 121*c621b414SMax Filippov ----------------------------------------------------------------------*/ 122*c621b414SMax Filippov 123*c621b414SMax Filippov /* 124*c621b414SMax Filippov * General notes on MMU parameters. 125*c621b414SMax Filippov * 126*c621b414SMax Filippov * Terminology: 127*c621b414SMax Filippov * ASID = address-space ID (acts as an "extension" of virtual addresses) 128*c621b414SMax Filippov * VPN = virtual page number 129*c621b414SMax Filippov * PPN = physical page number 130*c621b414SMax Filippov * CA = encoded cache attribute (access modes) 131*c621b414SMax Filippov * TLB = translation look-aside buffer (term is stretched somewhat here) 132*c621b414SMax Filippov * I = instruction (fetch accesses) 133*c621b414SMax Filippov * D = data (load and store accesses) 134*c621b414SMax Filippov * way = each TLB (ITLB and DTLB) consists of a number of "ways" 135*c621b414SMax Filippov * that simultaneously match the virtual address of an access; 136*c621b414SMax Filippov * a TLB successfully translates a virtual address if exactly 137*c621b414SMax Filippov * one way matches the vaddr; if none match, it is a miss; 138*c621b414SMax Filippov * if multiple match, one gets a "multihit" exception; 139*c621b414SMax Filippov * each way can be independently configured in terms of number of 140*c621b414SMax Filippov * entries, page sizes, which fields are writable or constant, etc. 141*c621b414SMax Filippov * set = group of contiguous ways with exactly identical parameters 142*c621b414SMax Filippov * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE 143*c621b414SMax Filippov * from the page table and storing it in one of the auto-refill ways; 144*c621b414SMax Filippov * if this PTE load also misses, a miss exception is posted for s/w. 145*c621b414SMax Filippov * min-wired = a "min-wired" way can be used to map a single (minimum-sized) 146*c621b414SMax Filippov * page arbitrarily under program control; it has a single entry, 147*c621b414SMax Filippov * is non-auto-refill (some other way(s) must be auto-refill), 148*c621b414SMax Filippov * all its fields (VPN, PPN, ASID, CA) are all writable, and it 149*c621b414SMax Filippov * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current 150*c621b414SMax Filippov * restriction is that this be the only page size it supports). 151*c621b414SMax Filippov * 152*c621b414SMax Filippov * TLB way entries are virtually indexed. 153*c621b414SMax Filippov * TLB ways that support multiple page sizes: 154*c621b414SMax Filippov * - must have all writable VPN and PPN fields; 155*c621b414SMax Filippov * - can only use one page size at any given time (eg. setup at startup), 156*c621b414SMax Filippov * selected by the respective ITLBCFG or DTLBCFG special register, 157*c621b414SMax Filippov * whose bits n*4+3 .. n*4 index the list of page sizes for way n 158*c621b414SMax Filippov * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); 159*c621b414SMax Filippov * this list may be sparse for auto-refill ways because auto-refill 160*c621b414SMax Filippov * ways have independent lists of supported page sizes sharing a 161*c621b414SMax Filippov * common encoding with PTE entries; the encoding is the index into 162*c621b414SMax Filippov * this list; unsupported sizes for a given way are zero in the list; 163*c621b414SMax Filippov * selecting unsupported sizes results in undefined hardware behaviour; 164*c621b414SMax Filippov * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). 165*c621b414SMax Filippov */ 166*c621b414SMax Filippov 167*c621b414SMax Filippov #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ 168*c621b414SMax Filippov #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ 169*c621b414SMax Filippov #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ 170*c621b414SMax Filippov #define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ 171*c621b414SMax Filippov #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ 172*c621b414SMax Filippov #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ 173*c621b414SMax Filippov 174*c621b414SMax Filippov 175*c621b414SMax Filippov /*** Instruction TLB: ***/ 176*c621b414SMax Filippov 177*c621b414SMax Filippov #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ 178*c621b414SMax Filippov #define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ 179*c621b414SMax Filippov #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ 180*c621b414SMax Filippov #define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ 181*c621b414SMax Filippov 182*c621b414SMax Filippov /* Way set to which each way belongs: */ 183*c621b414SMax Filippov #define XCHAL_ITLB_WAY0_SET 0 184*c621b414SMax Filippov 185*c621b414SMax Filippov /* Ways sets that are used by hardware auto-refill (ARF): */ 186*c621b414SMax Filippov #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ 187*c621b414SMax Filippov 188*c621b414SMax Filippov /* Way sets that are "min-wired" (see terminology comment above): */ 189*c621b414SMax Filippov #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ 190*c621b414SMax Filippov 191*c621b414SMax Filippov 192*c621b414SMax Filippov /* ITLB way set 0 (group of ways 0 thru 0): */ 193*c621b414SMax Filippov #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ 194*c621b414SMax Filippov #define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ 195*c621b414SMax Filippov #define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ 196*c621b414SMax Filippov #define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ 197*c621b414SMax Filippov #define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 198*c621b414SMax Filippov #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ 199*c621b414SMax Filippov #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ 200*c621b414SMax Filippov #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ 201*c621b414SMax Filippov #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ 202*c621b414SMax Filippov #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; 203*c621b414SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 204*c621b414SMax Filippov #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 205*c621b414SMax Filippov #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ 206*c621b414SMax Filippov #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 207*c621b414SMax Filippov #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 208*c621b414SMax Filippov #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 209*c621b414SMax Filippov #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 210*c621b414SMax Filippov #define XCHAL_ITLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 211*c621b414SMax Filippov #define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 212*c621b414SMax Filippov /* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ 213*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 214*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 215*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 216*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 217*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 218*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 219*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 220*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 221*c621b414SMax Filippov /* Reset PPN values for each entry of ITLB way set 0 (because SET0_PPN_RESET is non-zero): */ 222*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E0_PPN_RESET 0x00000000 223*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E1_PPN_RESET 0x20000000 224*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E2_PPN_RESET 0x40000000 225*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E3_PPN_RESET 0x60000000 226*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E4_PPN_RESET 0x80000000 227*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E5_PPN_RESET 0xA0000000 228*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E6_PPN_RESET 0xC0000000 229*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E7_PPN_RESET 0xE0000000 230*c621b414SMax Filippov /* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ 231*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 232*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 233*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 234*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 235*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 236*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 237*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 238*c621b414SMax Filippov #define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 239*c621b414SMax Filippov 240*c621b414SMax Filippov 241*c621b414SMax Filippov /*** Data TLB: ***/ 242*c621b414SMax Filippov 243*c621b414SMax Filippov #define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ 244*c621b414SMax Filippov #define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ 245*c621b414SMax Filippov #define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ 246*c621b414SMax Filippov #define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ 247*c621b414SMax Filippov 248*c621b414SMax Filippov /* Way set to which each way belongs: */ 249*c621b414SMax Filippov #define XCHAL_DTLB_WAY0_SET 0 250*c621b414SMax Filippov 251*c621b414SMax Filippov /* Ways sets that are used by hardware auto-refill (ARF): */ 252*c621b414SMax Filippov #define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ 253*c621b414SMax Filippov 254*c621b414SMax Filippov /* Way sets that are "min-wired" (see terminology comment above): */ 255*c621b414SMax Filippov #define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ 256*c621b414SMax Filippov 257*c621b414SMax Filippov 258*c621b414SMax Filippov /* DTLB way set 0 (group of ways 0 thru 0): */ 259*c621b414SMax Filippov #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ 260*c621b414SMax Filippov #define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ 261*c621b414SMax Filippov #define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ 262*c621b414SMax Filippov #define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ 263*c621b414SMax Filippov #define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 264*c621b414SMax Filippov #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ 265*c621b414SMax Filippov #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ 266*c621b414SMax Filippov #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ 267*c621b414SMax Filippov #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ 268*c621b414SMax Filippov #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; 269*c621b414SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 270*c621b414SMax Filippov #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 271*c621b414SMax Filippov #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ 272*c621b414SMax Filippov #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 273*c621b414SMax Filippov #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 274*c621b414SMax Filippov #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 275*c621b414SMax Filippov #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 276*c621b414SMax Filippov #define XCHAL_DTLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 277*c621b414SMax Filippov #define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 278*c621b414SMax Filippov /* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ 279*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 280*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 281*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 282*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 283*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 284*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 285*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 286*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 287*c621b414SMax Filippov /* Reset PPN values for each entry of DTLB way set 0 (because SET0_PPN_RESET is non-zero): */ 288*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E0_PPN_RESET 0x00000000 289*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E1_PPN_RESET 0x20000000 290*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E2_PPN_RESET 0x40000000 291*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E3_PPN_RESET 0x60000000 292*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E4_PPN_RESET 0x80000000 293*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E5_PPN_RESET 0xA0000000 294*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E6_PPN_RESET 0xC0000000 295*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E7_PPN_RESET 0xE0000000 296*c621b414SMax Filippov /* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ 297*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 298*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 299*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 300*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 301*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 302*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 303*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 304*c621b414SMax Filippov #define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 305*c621b414SMax Filippov 306*c621b414SMax Filippov 307*c621b414SMax Filippov 308*c621b414SMax Filippov 309*c621b414SMax Filippov #endif /* XTENSA_CONFIG_CORE_MATMAP_H */ 310*c621b414SMax Filippov 311