1 /*
2  * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3  *				processor CORE configuration
4  *
5  *  See <xtensa/config/core.h>, which includes this file, for more details.
6  */
7 
8 /* Xtensa processor core configuration information.
9 
10    Copyright (c) 1999-2010 Tensilica Inc.
11 
12    Permission is hereby granted, free of charge, to any person obtaining
13    a copy of this software and associated documentation files (the
14    "Software"), to deal in the Software without restriction, including
15    without limitation the rights to use, copy, modify, merge, publish,
16    distribute, sublicense, and/or sell copies of the Software, and to
17    permit persons to whom the Software is furnished to do so, subject to
18    the following conditions:
19 
20    The above copyright notice and this permission notice shall be included
21    in all copies or substantial portions of the Software.
22 
23    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
26    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
27    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
28    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
29    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
30 
31 #ifndef XTENSA_CORE_DSP3400_CORE_ISA_H
32 #define XTENSA_CORE_DSP3400_CORE_ISA_H
33 
34 /****************************************************************************
35 	    Parameters Useful for Any Code, USER or PRIVILEGED
36  ****************************************************************************/
37 
38 /*
39  *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
40  *  configured, and a value of 0 otherwise.  These macros are always defined.
41  */
42 
43 
44 /*----------------------------------------------------------------------
45 				ISA
46   ----------------------------------------------------------------------*/
47 
48 #define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
49 #define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
50 #define XCHAL_NUM_AREGS			32	/* num of physical addr regs */
51 #define XCHAL_NUM_AREGS_LOG2		5	/* log2(XCHAL_NUM_AREGS) */
52 #define XCHAL_MAX_INSTRUCTION_SIZE	8	/* max instr bytes (3..8) */
53 #define XCHAL_HAVE_DEBUG		1	/* debug option */
54 #define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
56 #define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
57 #define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
58 #define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
59 #define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
60 #define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
61 #define XCHAL_HAVE_MUL32		0	/* MULL instruction */
62 #define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
63 #define XCHAL_HAVE_DIV32		0	/* QUOS/QUOU/REMS/REMU instructions */
64 #define XCHAL_HAVE_L32R			1	/* L32R instruction */
65 #define XCHAL_HAVE_ABSOLUTE_LITERALS	1	/* non-PC-rel (extended) L32R */
66 #define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
67 #define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
68 #define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
69 #define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
70 #define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
71 #define XCHAL_HAVE_ABS			1	/* ABS instruction */
72 /*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
73 /*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
74 #define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
75 #define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
76 #define XCHAL_HAVE_SPECULATION		0	/* speculation */
77 #define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
78 #define XCHAL_NUM_CONTEXTS		1	/* */
79 #define XCHAL_NUM_MISC_REGS		0	/* num of scratch regs (0..4) */
80 #define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
81 #define XCHAL_HAVE_PRID			1	/* processor ID register */
82 #define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
83 #define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
84 #define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
85 #define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
86 #define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
87 #define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
88 #define XCHAL_CP_MAXCFG			4	/* max allowed cp id plus one */
89 #define XCHAL_HAVE_MAC16		0	/* MAC16 package */
90 #define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
91 #define XCHAL_HAVE_FP			1	/* floating point pkg */
92 #define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
93 #define XCHAL_HAVE_DFP_accel		0	/* double precision FP acceleration pkg */
94 #define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
95 #define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
96 #define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
97 #define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
98 #define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
99 #define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
100 #define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
101 #define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
102 #define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
103 #define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
104 #define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
105 #define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
106 #define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
107 
108 
109 /*----------------------------------------------------------------------
110 				MISC
111   ----------------------------------------------------------------------*/
112 
113 #define XCHAL_NUM_WRITEBUFFER_ENTRIES	8	/* size of write buffer */
114 #define XCHAL_INST_FETCH_WIDTH		8	/* instr-fetch width in bytes */
115 #define XCHAL_DATA_WIDTH		16	/* data width in bytes */
116 /*  In T1050, applies to selected core load and store instructions (see ISA): */
117 #define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
118 #define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
119 #define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
120 #define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
121 
122 #define XCHAL_SW_VERSION		800002	/* sw version of this header */
123 
124 #define XCHAL_CORE_ID			"dsp3400_RC2"	/* alphanum core name
125 						   (CoreID) set in the Xtensa
126 						   Processor Generator */
127 
128 #define XCHAL_BUILD_UNIQUE_ID		0x0002DC22	/* 22-bit sw build ID */
129 
130 /*
131  *  These definitions describe the hardware targeted by this software.
132  */
133 #define XCHAL_HW_CONFIGID0		0xC3F3DBFE	/* ConfigID hi 32 bits*/
134 #define XCHAL_HW_CONFIGID1		0x1082C3B0	/* ConfigID lo 32 bits*/
135 #define XCHAL_HW_VERSION_NAME		"LX3.0.1"	/* full version name */
136 #define XCHAL_HW_VERSION_MAJOR		2300	/* major ver# of targeted hw */
137 #define XCHAL_HW_VERSION_MINOR		1	/* minor ver# of targeted hw */
138 #define XCHAL_HW_VERSION		230001	/* major*100+minor */
139 #define XCHAL_HW_REL_LX3		1
140 #define XCHAL_HW_REL_LX3_0		1
141 #define XCHAL_HW_REL_LX3_0_1		1
142 #define XCHAL_HW_CONFIGID_RELIABLE	1
143 /*  If software targets a *range* of hardware versions, these are the bounds: */
144 #define XCHAL_HW_MIN_VERSION_MAJOR	2300	/* major v of earliest tgt hw */
145 #define XCHAL_HW_MIN_VERSION_MINOR	1	/* minor v of earliest tgt hw */
146 #define XCHAL_HW_MIN_VERSION		230001	/* earliest targeted hw */
147 #define XCHAL_HW_MAX_VERSION_MAJOR	2300	/* major v of latest tgt hw */
148 #define XCHAL_HW_MAX_VERSION_MINOR	1	/* minor v of latest tgt hw */
149 #define XCHAL_HW_MAX_VERSION		230001	/* latest targeted hw */
150 
151 
152 /*----------------------------------------------------------------------
153 				CACHE
154   ----------------------------------------------------------------------*/
155 
156 #define XCHAL_ICACHE_LINESIZE		32	/* I-cache line size in bytes */
157 #define XCHAL_DCACHE_LINESIZE		32	/* D-cache line size in bytes */
158 #define XCHAL_ICACHE_LINEWIDTH		5	/* log2(I line size in bytes) */
159 #define XCHAL_DCACHE_LINEWIDTH		5	/* log2(D line size in bytes) */
160 
161 #define XCHAL_ICACHE_SIZE		8192	/* I-cache size in bytes or 0 */
162 #define XCHAL_DCACHE_SIZE		8192	/* D-cache size in bytes or 0 */
163 
164 #define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
165 #define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
166 
167 #define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
168 
169 
170 
171 
172 /****************************************************************************
173     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
174  ****************************************************************************/
175 
176 
177 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
178 
179 /*----------------------------------------------------------------------
180 				CACHE
181   ----------------------------------------------------------------------*/
182 
183 #define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
184 
185 /*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
186 
187 /*  Number of cache sets in log2(lines per way):  */
188 #define XCHAL_ICACHE_SETWIDTH		7
189 #define XCHAL_DCACHE_SETWIDTH		7
190 
191 /*  Cache set associativity (number of ways):  */
192 #define XCHAL_ICACHE_WAYS		2
193 #define XCHAL_DCACHE_WAYS		2
194 
195 /*  Cache features:  */
196 #define XCHAL_ICACHE_LINE_LOCKABLE	1
197 #define XCHAL_DCACHE_LINE_LOCKABLE	1
198 #define XCHAL_ICACHE_ECC_PARITY		0
199 #define XCHAL_DCACHE_ECC_PARITY		0
200 
201 /*  Cache access size in bytes (affects operation of SICW instruction):  */
202 #define XCHAL_ICACHE_ACCESS_SIZE	8
203 #define XCHAL_DCACHE_ACCESS_SIZE	16
204 
205 /*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
206 #define XCHAL_CA_BITS			4
207 
208 
209 /*----------------------------------------------------------------------
210 			INTERNAL I/D RAM/ROMs and XLMI
211   ----------------------------------------------------------------------*/
212 
213 #define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
214 #define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
215 #define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
216 #define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
217 #define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
218 #define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
219 
220 /*  Instruction RAM 0:  */
221 #define XCHAL_INSTRAM0_VADDR		0x5FFE0000
222 #define XCHAL_INSTRAM0_PADDR		0x5FFE0000
223 #define XCHAL_INSTRAM0_SIZE		65536
224 #define XCHAL_INSTRAM0_ECC_PARITY	0
225 
226 /*  Instruction RAM 1:  */
227 #define XCHAL_INSTRAM1_VADDR		0x5FFF0000
228 #define XCHAL_INSTRAM1_PADDR		0x5FFF0000
229 #define XCHAL_INSTRAM1_SIZE		65536
230 #define XCHAL_INSTRAM1_ECC_PARITY	0
231 
232 /*  Data RAM 0:  */
233 #define XCHAL_DATARAM0_VADDR		0x5FFD0000
234 #define XCHAL_DATARAM0_PADDR		0x5FFD0000
235 #define XCHAL_DATARAM0_SIZE		32768
236 #define XCHAL_DATARAM0_ECC_PARITY	0
237 
238 /*  Data RAM 1:  */
239 #define XCHAL_DATARAM1_VADDR		0x5FFD8000
240 #define XCHAL_DATARAM1_PADDR		0x5FFD8000
241 #define XCHAL_DATARAM1_SIZE		32768
242 #define XCHAL_DATARAM1_ECC_PARITY	0
243 
244 
245 /*----------------------------------------------------------------------
246 			INTERRUPTS and TIMERS
247   ----------------------------------------------------------------------*/
248 
249 #define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
250 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
251 #define XCHAL_HAVE_NMI			0	/* non-maskable interrupt */
252 #define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
253 #define XCHAL_NUM_TIMERS		2	/* number of CCOMPAREn regs */
254 #define XCHAL_NUM_INTERRUPTS		13	/* number of interrupts */
255 #define XCHAL_NUM_INTERRUPTS_LOG2	4	/* ceil(log2(NUM_INTERRUPTS)) */
256 #define XCHAL_NUM_EXTINTERRUPTS		9	/* num of external interrupts */
257 #define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
258 						   (not including level zero) */
259 #define XCHAL_EXCM_LEVEL		4	/* level masked by PS.EXCM */
260 	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
261 
262 /*  Masks of interrupts at each interrupt level:  */
263 #define XCHAL_INTLEVEL1_MASK		0x00001200
264 #define XCHAL_INTLEVEL2_MASK		0x00000980
265 #define XCHAL_INTLEVEL3_MASK		0x00000460
266 #define XCHAL_INTLEVEL4_MASK		0x00000019
267 #define XCHAL_INTLEVEL5_MASK		0x00000006
268 #define XCHAL_INTLEVEL6_MASK		0x00000000
269 #define XCHAL_INTLEVEL7_MASK		0x00000000
270 
271 /*  Masks of interrupts at each range 1..n of interrupt levels:  */
272 #define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x00001200
273 #define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x00001B80
274 #define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x00001FE0
275 #define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x00001FF9
276 #define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x00001FFF
277 #define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x00001FFF
278 #define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x00001FFF
279 
280 /*  Level of each interrupt:  */
281 #define XCHAL_INT0_LEVEL		4
282 #define XCHAL_INT1_LEVEL		5
283 #define XCHAL_INT2_LEVEL		5
284 #define XCHAL_INT3_LEVEL		4
285 #define XCHAL_INT4_LEVEL		4
286 #define XCHAL_INT5_LEVEL		3
287 #define XCHAL_INT6_LEVEL		3
288 #define XCHAL_INT7_LEVEL		2
289 #define XCHAL_INT8_LEVEL		2
290 #define XCHAL_INT9_LEVEL		1
291 #define XCHAL_INT10_LEVEL		3
292 #define XCHAL_INT11_LEVEL		2
293 #define XCHAL_INT12_LEVEL		1
294 #define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
295 #define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
296 
297 /*  Type of each interrupt:  */
298 #define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_TIMER
299 #define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
300 #define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
301 #define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
302 #define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
303 #define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
304 #define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
305 #define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
306 #define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
307 #define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
308 #define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_SOFTWARE
309 #define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_TIMER
310 #define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_WRITE_ERROR
311 
312 /*  Masks of interrupts for each type of interrupt:  */
313 #define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFFFE000
314 #define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000400
315 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x00000000
316 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x000003FE
317 #define XCHAL_INTTYPE_MASK_TIMER	0x00000801
318 #define XCHAL_INTTYPE_MASK_NMI		0x00000000
319 #define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00001000
320 
321 /*  Interrupt numbers assigned to specific interrupt sources:  */
322 #define XCHAL_TIMER0_INTERRUPT		0	/* CCOMPARE0 */
323 #define XCHAL_TIMER1_INTERRUPT		11	/* CCOMPARE1 */
324 #define XCHAL_TIMER2_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
325 #define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
326 #define XCHAL_WRITE_ERROR_INTERRUPT	12	/* write-error interrupt */
327 
328 /*  Interrupt numbers for levels at which only one interrupt is configured:  */
329 /*  (There are many interrupts each at level(s) 1, 2, 3, 4, 5.)  */
330 
331 
332 /*
333  *  External interrupt vectors/levels.
334  *  These macros describe how Xtensa processor interrupt numbers
335  *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
336  *  map to external BInterrupt<n> pins, for those interrupts
337  *  configured as external (level-triggered, edge-triggered, or NMI).
338  *  See the Xtensa processor databook for more details.
339  */
340 
341 /*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
342 #define XCHAL_EXTINT0_NUM		1	/* (intlevel 5) */
343 #define XCHAL_EXTINT1_NUM		2	/* (intlevel 5) */
344 #define XCHAL_EXTINT2_NUM		3	/* (intlevel 4) */
345 #define XCHAL_EXTINT3_NUM		4	/* (intlevel 4) */
346 #define XCHAL_EXTINT4_NUM		5	/* (intlevel 3) */
347 #define XCHAL_EXTINT5_NUM		6	/* (intlevel 3) */
348 #define XCHAL_EXTINT6_NUM		7	/* (intlevel 2) */
349 #define XCHAL_EXTINT7_NUM		8	/* (intlevel 2) */
350 #define XCHAL_EXTINT8_NUM		9	/* (intlevel 1) */
351 
352 
353 /*----------------------------------------------------------------------
354 			EXCEPTIONS and VECTORS
355   ----------------------------------------------------------------------*/
356 
357 #define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
358 						   number: 1 == XEA1 (old)
359 							   2 == XEA2 (new)
360 							   0 == XEAX (extern) */
361 #define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
362 #define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
363 #define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
364 #define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
365 #define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
366 #define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
367 #define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
368 #define XCHAL_VECBASE_RESET_VADDR	0x5FFE0400  /* VECBASE reset value */
369 #define XCHAL_VECBASE_RESET_PADDR	0x5FFE0400
370 #define XCHAL_RESET_VECBASE_OVERLAP	0
371 
372 #define XCHAL_RESET_VECTOR0_VADDR	0x5FFE0000
373 #define XCHAL_RESET_VECTOR0_PADDR	0x5FFE0000
374 #define XCHAL_RESET_VECTOR1_VADDR	0xFFFF1000
375 #define XCHAL_RESET_VECTOR1_PADDR	0xFFFF1000
376 #define XCHAL_RESET_VECTOR_VADDR	0x5FFE0000
377 #define XCHAL_RESET_VECTOR_PADDR	0x5FFE0000
378 #define XCHAL_USER_VECOFS		0x0000023C
379 #define XCHAL_USER_VECTOR_VADDR		0x5FFE063C
380 #define XCHAL_USER_VECTOR_PADDR		0x5FFE063C
381 #define XCHAL_KERNEL_VECOFS		0x0000021C
382 #define XCHAL_KERNEL_VECTOR_VADDR	0x5FFE061C
383 #define XCHAL_KERNEL_VECTOR_PADDR	0x5FFE061C
384 #define XCHAL_DOUBLEEXC_VECOFS		0x0000025C
385 #define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x5FFE065C
386 #define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x5FFE065C
387 #define XCHAL_WINDOW_OF4_VECOFS		0x00000000
388 #define XCHAL_WINDOW_UF4_VECOFS		0x00000040
389 #define XCHAL_WINDOW_OF8_VECOFS		0x00000080
390 #define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
391 #define XCHAL_WINDOW_OF12_VECOFS	0x00000100
392 #define XCHAL_WINDOW_UF12_VECOFS	0x00000140
393 #define XCHAL_WINDOW_VECTORS_VADDR	0x5FFE0400
394 #define XCHAL_WINDOW_VECTORS_PADDR	0x5FFE0400
395 #define XCHAL_INTLEVEL2_VECOFS		0x0000017C
396 #define XCHAL_INTLEVEL2_VECTOR_VADDR	0x5FFE057C
397 #define XCHAL_INTLEVEL2_VECTOR_PADDR	0x5FFE057C
398 #define XCHAL_INTLEVEL3_VECOFS		0x0000019C
399 #define XCHAL_INTLEVEL3_VECTOR_VADDR	0x5FFE059C
400 #define XCHAL_INTLEVEL3_VECTOR_PADDR	0x5FFE059C
401 #define XCHAL_INTLEVEL4_VECOFS		0x000001BC
402 #define XCHAL_INTLEVEL4_VECTOR_VADDR	0x5FFE05BC
403 #define XCHAL_INTLEVEL4_VECTOR_PADDR	0x5FFE05BC
404 #define XCHAL_INTLEVEL5_VECOFS		0x000001DC
405 #define XCHAL_INTLEVEL5_VECTOR_VADDR	0x5FFE05DC
406 #define XCHAL_INTLEVEL5_VECTOR_PADDR	0x5FFE05DC
407 #define XCHAL_INTLEVEL6_VECOFS		0x000001FC
408 #define XCHAL_INTLEVEL6_VECTOR_VADDR	0x5FFE05FC
409 #define XCHAL_INTLEVEL6_VECTOR_PADDR	0x5FFE05FC
410 #define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
411 #define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
412 #define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
413 
414 
415 /*----------------------------------------------------------------------
416 				DEBUG
417   ----------------------------------------------------------------------*/
418 
419 #define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
420 #define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
421 #define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
422 #define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option */
423 
424 
425 /*----------------------------------------------------------------------
426 				MMU
427   ----------------------------------------------------------------------*/
428 
429 /*  See core-matmap.h header file for more details.  */
430 
431 #define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
432 #define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
433 #define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
434 #define XCHAL_HAVE_IDENTITY_MAP		0	/* vaddr == paddr always */
435 #define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
436 #define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
437 #define XCHAL_HAVE_XLT_CACHEATTR	1	/* region prot. w/translation */
438 #define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
439 						   [autorefill] and protection)
440 						   usable for an MMU-based OS */
441 /*  If none of the above last 4 are set, it's a custom TLB configuration.  */
442 
443 #define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
444 #define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
445 #define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
446 
447 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
448 
449 
450 #endif /* XTENSA_CORE_DSP3400_CORE_ISA_H */
451