xref: /openbmc/qemu/target/xtensa/core-dc233c.c (revision 4ea5fe99)
1fcf5ef2aSThomas Huth /*
2fcf5ef2aSThomas Huth  * Copyright (c) 2012, Max Filippov, Open Source and Linux Lab.
3fcf5ef2aSThomas Huth  * All rights reserved.
4fcf5ef2aSThomas Huth  *
5fcf5ef2aSThomas Huth  * Redistribution and use in source and binary forms, with or without
6fcf5ef2aSThomas Huth  * modification, are permitted provided that the following conditions are met:
7fcf5ef2aSThomas Huth  *     * Redistributions of source code must retain the above copyright
8fcf5ef2aSThomas Huth  *       notice, this list of conditions and the following disclaimer.
9fcf5ef2aSThomas Huth  *     * Redistributions in binary form must reproduce the above copyright
10fcf5ef2aSThomas Huth  *       notice, this list of conditions and the following disclaimer in the
11fcf5ef2aSThomas Huth  *       documentation and/or other materials provided with the distribution.
12fcf5ef2aSThomas Huth  *     * Neither the name of the Open Source and Linux Lab nor the
13fcf5ef2aSThomas Huth  *       names of its contributors may be used to endorse or promote products
14fcf5ef2aSThomas Huth  *       derived from this software without specific prior written permission.
15fcf5ef2aSThomas Huth  *
16fcf5ef2aSThomas Huth  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17fcf5ef2aSThomas Huth  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18fcf5ef2aSThomas Huth  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19fcf5ef2aSThomas Huth  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20fcf5ef2aSThomas Huth  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21fcf5ef2aSThomas Huth  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22fcf5ef2aSThomas Huth  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23fcf5ef2aSThomas Huth  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24fcf5ef2aSThomas Huth  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25fcf5ef2aSThomas Huth  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26fcf5ef2aSThomas Huth  */
27fcf5ef2aSThomas Huth 
28fcf5ef2aSThomas Huth #include "qemu/osdep.h"
29fcf5ef2aSThomas Huth #include "cpu.h"
30*4ea5fe99SAlex Bennée #include "gdbstub/helpers.h"
31fcf5ef2aSThomas Huth #include "qemu/host-utils.h"
32fcf5ef2aSThomas Huth 
33fcf5ef2aSThomas Huth #include "core-dc233c/core-isa.h"
34fcf5ef2aSThomas Huth #include "overlay_tool.h"
35fcf5ef2aSThomas Huth 
36e763684fSMax Filippov #define xtensa_modules xtensa_modules_dc233c
37139c1837SPaolo Bonzini #include "core-dc233c/xtensa-modules.c.inc"
38e763684fSMax Filippov 
39fcf5ef2aSThomas Huth static XtensaConfig dc233c __attribute__((unused)) = {
40fcf5ef2aSThomas Huth     .name = "dc233c",
41fcf5ef2aSThomas Huth     .gdb_regmap = {
42fcf5ef2aSThomas Huth         .reg = {
43139c1837SPaolo Bonzini #include "core-dc233c/gdb-config.c.inc"
44fcf5ef2aSThomas Huth         }
45fcf5ef2aSThomas Huth     },
46e763684fSMax Filippov     .isa_internal = &xtensa_modules,
47fcf5ef2aSThomas Huth     .clock_freq_khz = 10000,
48fcf5ef2aSThomas Huth     DEFAULT_SECTIONS
49fcf5ef2aSThomas Huth };
50fcf5ef2aSThomas Huth 
51fcf5ef2aSThomas Huth REGISTER_CORE(dc233c)
52