1/* Xtensa configuration-specific ISA information. 2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc. 3 4 This file is part of BFD, the Binary File Descriptor library. 5 6 This program is free software; you can redistribute it and/or 7 modify it under the terms of the GNU General Public License as 8 published by the Free Software Foundation; either version 2 of the 9 License, or (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21#include "qemu/osdep.h" 22#include "xtensa-isa.h" 23#include "xtensa-isa-internal.h" 24 25 26/* Sysregs. */ 27 28static xtensa_sysreg_internal sysregs[] = { 29 { "LBEG", 0, 0 }, 30 { "LEND", 1, 0 }, 31 { "LCOUNT", 2, 0 }, 32 { "ACCLO", 16, 0 }, 33 { "ACCHI", 17, 0 }, 34 { "M0", 32, 0 }, 35 { "M1", 33, 0 }, 36 { "M2", 34, 0 }, 37 { "M3", 35, 0 }, 38 { "PTEVADDR", 83, 0 }, 39 { "MMID", 89, 0 }, 40 { "DDR", 104, 0 }, 41 { "176", 176, 0 }, 42 { "208", 208, 0 }, 43 { "INTERRUPT", 226, 0 }, 44 { "INTCLEAR", 227, 0 }, 45 { "CCOUNT", 234, 0 }, 46 { "PRID", 235, 0 }, 47 { "ICOUNT", 236, 0 }, 48 { "CCOMPARE0", 240, 0 }, 49 { "CCOMPARE1", 241, 0 }, 50 { "CCOMPARE2", 242, 0 }, 51 { "VECBASE", 231, 0 }, 52 { "EPC1", 177, 0 }, 53 { "EPC2", 178, 0 }, 54 { "EPC3", 179, 0 }, 55 { "EPC4", 180, 0 }, 56 { "EPC5", 181, 0 }, 57 { "EPC6", 182, 0 }, 58 { "EPC7", 183, 0 }, 59 { "EXCSAVE1", 209, 0 }, 60 { "EXCSAVE2", 210, 0 }, 61 { "EXCSAVE3", 211, 0 }, 62 { "EXCSAVE4", 212, 0 }, 63 { "EXCSAVE5", 213, 0 }, 64 { "EXCSAVE6", 214, 0 }, 65 { "EXCSAVE7", 215, 0 }, 66 { "EPS2", 194, 0 }, 67 { "EPS3", 195, 0 }, 68 { "EPS4", 196, 0 }, 69 { "EPS5", 197, 0 }, 70 { "EPS6", 198, 0 }, 71 { "EPS7", 199, 0 }, 72 { "EXCCAUSE", 232, 0 }, 73 { "DEPC", 192, 0 }, 74 { "EXCVADDR", 238, 0 }, 75 { "WINDOWBASE", 72, 0 }, 76 { "WINDOWSTART", 73, 0 }, 77 { "SAR", 3, 0 }, 78 { "LITBASE", 5, 0 }, 79 { "PS", 230, 0 }, 80 { "MISC0", 244, 0 }, 81 { "MISC1", 245, 0 }, 82 { "INTENABLE", 228, 0 }, 83 { "DBREAKA0", 144, 0 }, 84 { "DBREAKC0", 160, 0 }, 85 { "DBREAKA1", 145, 0 }, 86 { "DBREAKC1", 161, 0 }, 87 { "IBREAKA0", 128, 0 }, 88 { "IBREAKA1", 129, 0 }, 89 { "IBREAKENABLE", 96, 0 }, 90 { "ICOUNTLEVEL", 237, 0 }, 91 { "DEBUGCAUSE", 233, 0 }, 92 { "RASID", 90, 0 }, 93 { "ITLBCFG", 91, 0 }, 94 { "DTLBCFG", 92, 0 }, 95 { "CPENABLE", 224, 0 }, 96 { "SCOMPARE1", 12, 0 }, 97 { "THREADPTR", 231, 1 }, 98 { "EXPSTATE", 230, 1 } 99}; 100 101#define NUM_SYSREGS 70 102#define MAX_SPECIAL_REG 245 103#define MAX_USER_REG 231 104 105 106/* Processor states. */ 107 108static xtensa_state_internal states[] = { 109 { "LCOUNT", 32, 0 }, 110 { "PC", 32, 0 }, 111 { "ICOUNT", 32, 0 }, 112 { "DDR", 32, 0 }, 113 { "INTERRUPT", 22, 0 }, 114 { "CCOUNT", 32, 0 }, 115 { "XTSYNC", 1, 0 }, 116 { "VECBASE", 22, 0 }, 117 { "EPC1", 32, 0 }, 118 { "EPC2", 32, 0 }, 119 { "EPC3", 32, 0 }, 120 { "EPC4", 32, 0 }, 121 { "EPC5", 32, 0 }, 122 { "EPC6", 32, 0 }, 123 { "EPC7", 32, 0 }, 124 { "EXCSAVE1", 32, 0 }, 125 { "EXCSAVE2", 32, 0 }, 126 { "EXCSAVE3", 32, 0 }, 127 { "EXCSAVE4", 32, 0 }, 128 { "EXCSAVE5", 32, 0 }, 129 { "EXCSAVE6", 32, 0 }, 130 { "EXCSAVE7", 32, 0 }, 131 { "EPS2", 15, 0 }, 132 { "EPS3", 15, 0 }, 133 { "EPS4", 15, 0 }, 134 { "EPS5", 15, 0 }, 135 { "EPS6", 15, 0 }, 136 { "EPS7", 15, 0 }, 137 { "EXCCAUSE", 6, 0 }, 138 { "PSINTLEVEL", 4, 0 }, 139 { "PSUM", 1, 0 }, 140 { "PSWOE", 1, 0 }, 141 { "PSRING", 2, 0 }, 142 { "PSEXCM", 1, 0 }, 143 { "DEPC", 32, 0 }, 144 { "EXCVADDR", 32, 0 }, 145 { "WindowBase", 3, 0 }, 146 { "WindowStart", 8, 0 }, 147 { "PSCALLINC", 2, 0 }, 148 { "PSOWB", 4, 0 }, 149 { "LBEG", 32, 0 }, 150 { "LEND", 32, 0 }, 151 { "SAR", 6, 0 }, 152 { "THREADPTR", 32, 0 }, 153 { "LITBADDR", 20, 0 }, 154 { "LITBEN", 1, 0 }, 155 { "MISC0", 32, 0 }, 156 { "MISC1", 32, 0 }, 157 { "ACC", 40, 0 }, 158 { "InOCDMode", 1, 0 }, 159 { "INTENABLE", 22, 0 }, 160 { "DBREAKA0", 32, 0 }, 161 { "DBREAKC0", 8, 0 }, 162 { "DBREAKA1", 32, 0 }, 163 { "DBREAKC1", 8, 0 }, 164 { "IBREAKA0", 32, 0 }, 165 { "IBREAKA1", 32, 0 }, 166 { "IBREAKENABLE", 2, 0 }, 167 { "ICOUNTLEVEL", 4, 0 }, 168 { "DEBUGCAUSE", 6, 0 }, 169 { "DBNUM", 4, 0 }, 170 { "CCOMPARE0", 32, 0 }, 171 { "CCOMPARE1", 32, 0 }, 172 { "CCOMPARE2", 32, 0 }, 173 { "ASID3", 8, 0 }, 174 { "ASID2", 8, 0 }, 175 { "ASID1", 8, 0 }, 176 { "INSTPGSZID4", 2, 0 }, 177 { "DATAPGSZID4", 2, 0 }, 178 { "PTBASE", 10, 0 }, 179 { "CPENABLE", 8, 0 }, 180 { "SCOMPARE1", 32, 0 }, 181 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } 182}; 183 184#define NUM_STATES 73 185 186/* Macros for xtensa_state numbers (for use in iclasses because the 187 state numbers are not available when the iclass table is generated). */ 188 189#define STATE_LCOUNT 0 190#define STATE_PC 1 191#define STATE_ICOUNT 2 192#define STATE_DDR 3 193#define STATE_INTERRUPT 4 194#define STATE_CCOUNT 5 195#define STATE_XTSYNC 6 196#define STATE_VECBASE 7 197#define STATE_EPC1 8 198#define STATE_EPC2 9 199#define STATE_EPC3 10 200#define STATE_EPC4 11 201#define STATE_EPC5 12 202#define STATE_EPC6 13 203#define STATE_EPC7 14 204#define STATE_EXCSAVE1 15 205#define STATE_EXCSAVE2 16 206#define STATE_EXCSAVE3 17 207#define STATE_EXCSAVE4 18 208#define STATE_EXCSAVE5 19 209#define STATE_EXCSAVE6 20 210#define STATE_EXCSAVE7 21 211#define STATE_EPS2 22 212#define STATE_EPS3 23 213#define STATE_EPS4 24 214#define STATE_EPS5 25 215#define STATE_EPS6 26 216#define STATE_EPS7 27 217#define STATE_EXCCAUSE 28 218#define STATE_PSINTLEVEL 29 219#define STATE_PSUM 30 220#define STATE_PSWOE 31 221#define STATE_PSRING 32 222#define STATE_PSEXCM 33 223#define STATE_DEPC 34 224#define STATE_EXCVADDR 35 225#define STATE_WindowBase 36 226#define STATE_WindowStart 37 227#define STATE_PSCALLINC 38 228#define STATE_PSOWB 39 229#define STATE_LBEG 40 230#define STATE_LEND 41 231#define STATE_SAR 42 232#define STATE_THREADPTR 43 233#define STATE_LITBADDR 44 234#define STATE_LITBEN 45 235#define STATE_MISC0 46 236#define STATE_MISC1 47 237#define STATE_ACC 48 238#define STATE_InOCDMode 49 239#define STATE_INTENABLE 50 240#define STATE_DBREAKA0 51 241#define STATE_DBREAKC0 52 242#define STATE_DBREAKA1 53 243#define STATE_DBREAKC1 54 244#define STATE_IBREAKA0 55 245#define STATE_IBREAKA1 56 246#define STATE_IBREAKENABLE 57 247#define STATE_ICOUNTLEVEL 58 248#define STATE_DEBUGCAUSE 59 249#define STATE_DBNUM 60 250#define STATE_CCOMPARE0 61 251#define STATE_CCOMPARE1 62 252#define STATE_CCOMPARE2 63 253#define STATE_ASID3 64 254#define STATE_ASID2 65 255#define STATE_ASID1 66 256#define STATE_INSTPGSZID4 67 257#define STATE_DATAPGSZID4 68 258#define STATE_PTBASE 69 259#define STATE_CPENABLE 70 260#define STATE_SCOMPARE1 71 261#define STATE_EXPSTATE 72 262 263 264/* Field definitions. */ 265 266static unsigned 267Field_t_Slot_inst_get (const xtensa_insnbuf insn) 268{ 269 unsigned tie_t = 0; 270 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 271 return tie_t; 272} 273 274static void 275Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 276{ 277 uint32 tie_t; 278 tie_t = (val << 28) >> 28; 279 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 280} 281 282static unsigned 283Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) 284{ 285 unsigned tie_t = 0; 286 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 287 return tie_t; 288} 289 290static void 291Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 292{ 293 uint32 tie_t; 294 tie_t = (val << 28) >> 28; 295 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 296} 297 298static unsigned 299Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) 300{ 301 unsigned tie_t = 0; 302 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 303 return tie_t; 304} 305 306static void 307Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 308{ 309 uint32 tie_t; 310 tie_t = (val << 28) >> 28; 311 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 312} 313 314static unsigned 315Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) 316{ 317 unsigned tie_t = 0; 318 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); 319 return tie_t; 320} 321 322static void 323Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 324{ 325 uint32 tie_t; 326 tie_t = (val << 31) >> 31; 327 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); 328} 329 330static unsigned 331Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) 332{ 333 unsigned tie_t = 0; 334 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); 335 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 336 return tie_t; 337} 338 339static void 340Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 341{ 342 uint32 tie_t; 343 tie_t = (val << 28) >> 28; 344 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 345 tie_t = (val << 27) >> 31; 346 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); 347} 348 349static unsigned 350Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) 351{ 352 unsigned tie_t = 0; 353 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); 354 return tie_t; 355} 356 357static void 358Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 359{ 360 uint32 tie_t; 361 tie_t = (val << 20) >> 20; 362 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); 363} 364 365static unsigned 366Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) 367{ 368 unsigned tie_t = 0; 369 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); 370 return tie_t; 371} 372 373static void 374Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 375{ 376 uint32 tie_t; 377 tie_t = (val << 24) >> 24; 378 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); 379} 380 381static unsigned 382Field_s_Slot_inst_get (const xtensa_insnbuf insn) 383{ 384 unsigned tie_t = 0; 385 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 386 return tie_t; 387} 388 389static void 390Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 391{ 392 uint32 tie_t; 393 tie_t = (val << 28) >> 28; 394 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 395} 396 397static unsigned 398Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) 399{ 400 unsigned tie_t = 0; 401 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 402 return tie_t; 403} 404 405static void 406Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 407{ 408 uint32 tie_t; 409 tie_t = (val << 28) >> 28; 410 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 411} 412 413static unsigned 414Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) 415{ 416 unsigned tie_t = 0; 417 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 418 return tie_t; 419} 420 421static void 422Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 423{ 424 uint32 tie_t; 425 tie_t = (val << 28) >> 28; 426 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 427} 428 429static unsigned 430Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) 431{ 432 unsigned tie_t = 0; 433 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 434 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); 435 return tie_t; 436} 437 438static void 439Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 440{ 441 uint32 tie_t; 442 tie_t = (val << 24) >> 24; 443 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); 444 tie_t = (val << 20) >> 28; 445 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 446} 447 448static unsigned 449Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) 450{ 451 unsigned tie_t = 0; 452 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); 453 return tie_t; 454} 455 456static void 457Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 458{ 459 uint32 tie_t; 460 tie_t = (val << 16) >> 16; 461 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); 462} 463 464static unsigned 465Field_m_Slot_inst_get (const xtensa_insnbuf insn) 466{ 467 unsigned tie_t = 0; 468 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); 469 return tie_t; 470} 471 472static void 473Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 474{ 475 uint32 tie_t; 476 tie_t = (val << 30) >> 30; 477 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); 478} 479 480static unsigned 481Field_n_Slot_inst_get (const xtensa_insnbuf insn) 482{ 483 unsigned tie_t = 0; 484 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 485 return tie_t; 486} 487 488static void 489Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 490{ 491 uint32 tie_t; 492 tie_t = (val << 30) >> 30; 493 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 494} 495 496static unsigned 497Field_offset_Slot_inst_get (const xtensa_insnbuf insn) 498{ 499 unsigned tie_t = 0; 500 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); 501 return tie_t; 502} 503 504static void 505Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 506{ 507 uint32 tie_t; 508 tie_t = (val << 14) >> 14; 509 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); 510} 511 512static unsigned 513Field_op0_Slot_inst_get (const xtensa_insnbuf insn) 514{ 515 unsigned tie_t = 0; 516 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 517 return tie_t; 518} 519 520static void 521Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 522{ 523 uint32 tie_t; 524 tie_t = (val << 28) >> 28; 525 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 526} 527 528static unsigned 529Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) 530{ 531 unsigned tie_t = 0; 532 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 533 return tie_t; 534} 535 536static void 537Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 538{ 539 uint32 tie_t; 540 tie_t = (val << 28) >> 28; 541 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 542} 543 544static unsigned 545Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) 546{ 547 unsigned tie_t = 0; 548 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 549 return tie_t; 550} 551 552static void 553Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 554{ 555 uint32 tie_t; 556 tie_t = (val << 28) >> 28; 557 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 558} 559 560static unsigned 561Field_op1_Slot_inst_get (const xtensa_insnbuf insn) 562{ 563 unsigned tie_t = 0; 564 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 565 return tie_t; 566} 567 568static void 569Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 570{ 571 uint32 tie_t; 572 tie_t = (val << 28) >> 28; 573 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 574} 575 576static unsigned 577Field_op2_Slot_inst_get (const xtensa_insnbuf insn) 578{ 579 unsigned tie_t = 0; 580 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); 581 return tie_t; 582} 583 584static void 585Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 586{ 587 uint32 tie_t; 588 tie_t = (val << 28) >> 28; 589 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); 590} 591 592static unsigned 593Field_r_Slot_inst_get (const xtensa_insnbuf insn) 594{ 595 unsigned tie_t = 0; 596 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 597 return tie_t; 598} 599 600static void 601Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 602{ 603 uint32 tie_t; 604 tie_t = (val << 28) >> 28; 605 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 606} 607 608static unsigned 609Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) 610{ 611 unsigned tie_t = 0; 612 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 613 return tie_t; 614} 615 616static void 617Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 618{ 619 uint32 tie_t; 620 tie_t = (val << 28) >> 28; 621 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 622} 623 624static unsigned 625Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) 626{ 627 unsigned tie_t = 0; 628 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 629 return tie_t; 630} 631 632static void 633Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 634{ 635 uint32 tie_t; 636 tie_t = (val << 28) >> 28; 637 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 638} 639 640static unsigned 641Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) 642{ 643 unsigned tie_t = 0; 644 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 645 return tie_t; 646} 647 648static void 649Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 650{ 651 uint32 tie_t; 652 tie_t = (val << 31) >> 31; 653 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 654} 655 656static unsigned 657Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) 658{ 659 unsigned tie_t = 0; 660 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 661 return tie_t; 662} 663 664static void 665Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 666{ 667 uint32 tie_t; 668 tie_t = (val << 31) >> 31; 669 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 670} 671 672static unsigned 673Field_sae_Slot_inst_get (const xtensa_insnbuf insn) 674{ 675 unsigned tie_t = 0; 676 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 677 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 678 return tie_t; 679} 680 681static void 682Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 683{ 684 uint32 tie_t; 685 tie_t = (val << 28) >> 28; 686 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 687 tie_t = (val << 27) >> 31; 688 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 689} 690 691static unsigned 692Field_sal_Slot_inst_get (const xtensa_insnbuf insn) 693{ 694 unsigned tie_t = 0; 695 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 696 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 697 return tie_t; 698} 699 700static void 701Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 702{ 703 uint32 tie_t; 704 tie_t = (val << 28) >> 28; 705 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 706 tie_t = (val << 27) >> 31; 707 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 708} 709 710static unsigned 711Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) 712{ 713 unsigned tie_t = 0; 714 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 715 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 716 return tie_t; 717} 718 719static void 720Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 721{ 722 uint32 tie_t; 723 tie_t = (val << 28) >> 28; 724 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 725 tie_t = (val << 27) >> 31; 726 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 727} 728 729static unsigned 730Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) 731{ 732 unsigned tie_t = 0; 733 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 734 return tie_t; 735} 736 737static void 738Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 739{ 740 uint32 tie_t; 741 tie_t = (val << 31) >> 31; 742 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 743} 744 745static unsigned 746Field_sas_Slot_inst_get (const xtensa_insnbuf insn) 747{ 748 unsigned tie_t = 0; 749 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 750 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 751 return tie_t; 752} 753 754static void 755Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 756{ 757 uint32 tie_t; 758 tie_t = (val << 28) >> 28; 759 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 760 tie_t = (val << 27) >> 31; 761 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 762} 763 764static unsigned 765Field_sr_Slot_inst_get (const xtensa_insnbuf insn) 766{ 767 unsigned tie_t = 0; 768 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 769 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 770 return tie_t; 771} 772 773static void 774Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 775{ 776 uint32 tie_t; 777 tie_t = (val << 28) >> 28; 778 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 779 tie_t = (val << 24) >> 28; 780 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 781} 782 783static unsigned 784Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) 785{ 786 unsigned tie_t = 0; 787 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 788 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 789 return tie_t; 790} 791 792static void 793Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 794{ 795 uint32 tie_t; 796 tie_t = (val << 28) >> 28; 797 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 798 tie_t = (val << 24) >> 28; 799 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 800} 801 802static unsigned 803Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) 804{ 805 unsigned tie_t = 0; 806 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 807 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 808 return tie_t; 809} 810 811static void 812Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 813{ 814 uint32 tie_t; 815 tie_t = (val << 28) >> 28; 816 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 817 tie_t = (val << 24) >> 28; 818 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 819} 820 821static unsigned 822Field_st_Slot_inst_get (const xtensa_insnbuf insn) 823{ 824 unsigned tie_t = 0; 825 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 826 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 827 return tie_t; 828} 829 830static void 831Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 832{ 833 uint32 tie_t; 834 tie_t = (val << 28) >> 28; 835 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 836 tie_t = (val << 24) >> 28; 837 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 838} 839 840static unsigned 841Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) 842{ 843 unsigned tie_t = 0; 844 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 845 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 846 return tie_t; 847} 848 849static void 850Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 851{ 852 uint32 tie_t; 853 tie_t = (val << 28) >> 28; 854 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 855 tie_t = (val << 24) >> 28; 856 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 857} 858 859static unsigned 860Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) 861{ 862 unsigned tie_t = 0; 863 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 864 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 865 return tie_t; 866} 867 868static void 869Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 870{ 871 uint32 tie_t; 872 tie_t = (val << 28) >> 28; 873 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 874 tie_t = (val << 24) >> 28; 875 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 876} 877 878static unsigned 879Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) 880{ 881 unsigned tie_t = 0; 882 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); 883 return tie_t; 884} 885 886static void 887Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 888{ 889 uint32 tie_t; 890 tie_t = (val << 29) >> 29; 891 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); 892} 893 894static unsigned 895Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) 896{ 897 unsigned tie_t = 0; 898 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 899 return tie_t; 900} 901 902static void 903Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 904{ 905 uint32 tie_t; 906 tie_t = (val << 28) >> 28; 907 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 908} 909 910static unsigned 911Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) 912{ 913 unsigned tie_t = 0; 914 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 915 return tie_t; 916} 917 918static void 919Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 920{ 921 uint32 tie_t; 922 tie_t = (val << 28) >> 28; 923 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 924} 925 926static unsigned 927Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) 928{ 929 unsigned tie_t = 0; 930 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 931 return tie_t; 932} 933 934static void 935Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 936{ 937 uint32 tie_t; 938 tie_t = (val << 28) >> 28; 939 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 940} 941 942static unsigned 943Field_mn_Slot_inst_get (const xtensa_insnbuf insn) 944{ 945 unsigned tie_t = 0; 946 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); 947 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 948 return tie_t; 949} 950 951static void 952Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 953{ 954 uint32 tie_t; 955 tie_t = (val << 30) >> 30; 956 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 957 tie_t = (val << 28) >> 30; 958 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); 959} 960 961static unsigned 962Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) 963{ 964 unsigned tie_t = 0; 965 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 966 return tie_t; 967} 968 969static void 970Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 971{ 972 uint32 tie_t; 973 tie_t = (val << 31) >> 31; 974 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 975} 976 977static unsigned 978Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) 979{ 980 unsigned tie_t = 0; 981 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 982 return tie_t; 983} 984 985static void 986Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 987{ 988 uint32 tie_t; 989 tie_t = (val << 31) >> 31; 990 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 991} 992 993static unsigned 994Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) 995{ 996 unsigned tie_t = 0; 997 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 998 return tie_t; 999} 1000 1001static void 1002Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1003{ 1004 uint32 tie_t; 1005 tie_t = (val << 28) >> 28; 1006 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1007} 1008 1009static unsigned 1010Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) 1011{ 1012 unsigned tie_t = 0; 1013 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1014 return tie_t; 1015} 1016 1017static void 1018Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1019{ 1020 uint32 tie_t; 1021 tie_t = (val << 28) >> 28; 1022 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1023} 1024 1025static unsigned 1026Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) 1027{ 1028 unsigned tie_t = 0; 1029 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1030 return tie_t; 1031} 1032 1033static void 1034Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1035{ 1036 uint32 tie_t; 1037 tie_t = (val << 30) >> 30; 1038 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1039} 1040 1041static unsigned 1042Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1043{ 1044 unsigned tie_t = 0; 1045 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1046 return tie_t; 1047} 1048 1049static void 1050Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1051{ 1052 uint32 tie_t; 1053 tie_t = (val << 30) >> 30; 1054 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1055} 1056 1057static unsigned 1058Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) 1059{ 1060 unsigned tie_t = 0; 1061 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1062 return tie_t; 1063} 1064 1065static void 1066Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1067{ 1068 uint32 tie_t; 1069 tie_t = (val << 28) >> 28; 1070 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1071} 1072 1073static unsigned 1074Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) 1075{ 1076 unsigned tie_t = 0; 1077 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1078 return tie_t; 1079} 1080 1081static void 1082Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1083{ 1084 uint32 tie_t; 1085 tie_t = (val << 28) >> 28; 1086 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1087} 1088 1089static unsigned 1090Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) 1091{ 1092 unsigned tie_t = 0; 1093 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1094 return tie_t; 1095} 1096 1097static void 1098Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1099{ 1100 uint32 tie_t; 1101 tie_t = (val << 29) >> 29; 1102 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1103} 1104 1105static unsigned 1106Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1107{ 1108 unsigned tie_t = 0; 1109 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1110 return tie_t; 1111} 1112 1113static void 1114Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1115{ 1116 uint32 tie_t; 1117 tie_t = (val << 29) >> 29; 1118 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1119} 1120 1121static unsigned 1122Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) 1123{ 1124 unsigned tie_t = 0; 1125 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1126 return tie_t; 1127} 1128 1129static void 1130Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1131{ 1132 uint32 tie_t; 1133 tie_t = (val << 31) >> 31; 1134 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1135} 1136 1137static unsigned 1138Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) 1139{ 1140 unsigned tie_t = 0; 1141 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1142 return tie_t; 1143} 1144 1145static void 1146Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1147{ 1148 uint32 tie_t; 1149 tie_t = (val << 31) >> 31; 1150 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1151} 1152 1153static unsigned 1154Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) 1155{ 1156 unsigned tie_t = 0; 1157 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1158 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1159 return tie_t; 1160} 1161 1162static void 1163Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1164{ 1165 uint32 tie_t; 1166 tie_t = (val << 28) >> 28; 1167 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1168 tie_t = (val << 26) >> 30; 1169 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1170} 1171 1172static unsigned 1173Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) 1174{ 1175 unsigned tie_t = 0; 1176 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1177 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1178 return tie_t; 1179} 1180 1181static void 1182Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1183{ 1184 uint32 tie_t; 1185 tie_t = (val << 28) >> 28; 1186 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1187 tie_t = (val << 26) >> 30; 1188 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1189} 1190 1191static unsigned 1192Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) 1193{ 1194 unsigned tie_t = 0; 1195 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1196 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1197 return tie_t; 1198} 1199 1200static void 1201Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1202{ 1203 uint32 tie_t; 1204 tie_t = (val << 28) >> 28; 1205 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1206 tie_t = (val << 25) >> 29; 1207 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1208} 1209 1210static unsigned 1211Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) 1212{ 1213 unsigned tie_t = 0; 1214 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1215 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1216 return tie_t; 1217} 1218 1219static void 1220Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1221{ 1222 uint32 tie_t; 1223 tie_t = (val << 28) >> 28; 1224 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1225 tie_t = (val << 25) >> 29; 1226 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1227} 1228 1229static unsigned 1230Field_r3_Slot_inst_get (const xtensa_insnbuf insn) 1231{ 1232 unsigned tie_t = 0; 1233 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 1234 return tie_t; 1235} 1236 1237static void 1238Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1239{ 1240 uint32 tie_t; 1241 tie_t = (val << 31) >> 31; 1242 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 1243} 1244 1245static unsigned 1246Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) 1247{ 1248 unsigned tie_t = 0; 1249 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1250 return tie_t; 1251} 1252 1253static void 1254Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1255{ 1256 uint32 tie_t; 1257 tie_t = (val << 31) >> 31; 1258 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1259} 1260 1261static unsigned 1262Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) 1263{ 1264 unsigned tie_t = 0; 1265 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 1266 return tie_t; 1267} 1268 1269static void 1270Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1271{ 1272 uint32 tie_t; 1273 tie_t = (val << 30) >> 30; 1274 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 1275} 1276 1277static unsigned 1278Field_t3_Slot_inst_get (const xtensa_insnbuf insn) 1279{ 1280 unsigned tie_t = 0; 1281 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 1282 return tie_t; 1283} 1284 1285static void 1286Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1287{ 1288 uint32 tie_t; 1289 tie_t = (val << 31) >> 31; 1290 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 1291} 1292 1293static unsigned 1294Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) 1295{ 1296 unsigned tie_t = 0; 1297 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1298 return tie_t; 1299} 1300 1301static void 1302Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1303{ 1304 uint32 tie_t; 1305 tie_t = (val << 31) >> 31; 1306 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1307} 1308 1309static unsigned 1310Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) 1311{ 1312 unsigned tie_t = 0; 1313 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1314 return tie_t; 1315} 1316 1317static void 1318Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1319{ 1320 uint32 tie_t; 1321 tie_t = (val << 30) >> 30; 1322 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1323} 1324 1325static unsigned 1326Field_w_Slot_inst_get (const xtensa_insnbuf insn) 1327{ 1328 unsigned tie_t = 0; 1329 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 1330 return tie_t; 1331} 1332 1333static void 1334Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1335{ 1336 uint32 tie_t; 1337 tie_t = (val << 30) >> 30; 1338 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 1339} 1340 1341static unsigned 1342Field_y_Slot_inst_get (const xtensa_insnbuf insn) 1343{ 1344 unsigned tie_t = 0; 1345 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1346 return tie_t; 1347} 1348 1349static void 1350Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1351{ 1352 uint32 tie_t; 1353 tie_t = (val << 31) >> 31; 1354 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1355} 1356 1357static unsigned 1358Field_x_Slot_inst_get (const xtensa_insnbuf insn) 1359{ 1360 unsigned tie_t = 0; 1361 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1362 return tie_t; 1363} 1364 1365static void 1366Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1367{ 1368 uint32 tie_t; 1369 tie_t = (val << 31) >> 31; 1370 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1371} 1372 1373static unsigned 1374Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) 1375{ 1376 unsigned tie_t = 0; 1377 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); 1378 return tie_t; 1379} 1380 1381static void 1382Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1383{ 1384 uint32 tie_t; 1385 tie_t = (val << 17) >> 17; 1386 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); 1387} 1388 1389static unsigned 1390Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) 1391{ 1392 unsigned tie_t = 0; 1393 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); 1394 return tie_t; 1395} 1396 1397static void 1398Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1399{ 1400 uint32 tie_t; 1401 tie_t = (val << 14) >> 14; 1402 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); 1403} 1404 1405static unsigned 1406Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) 1407{ 1408 unsigned tie_t = 0; 1409 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 1410 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 1411 return tie_t; 1412} 1413 1414static void 1415Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1416{ 1417 uint32 tie_t; 1418 tie_t = (val << 28) >> 28; 1419 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 1420 tie_t = (val << 27) >> 31; 1421 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 1422} 1423 1424static unsigned 1425Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) 1426{ 1427 unsigned tie_t = 0; 1428 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 1429 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 1430 return tie_t; 1431} 1432 1433static void 1434Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1435{ 1436 uint32 tie_t; 1437 tie_t = (val << 28) >> 28; 1438 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 1439 tie_t = (val << 27) >> 31; 1440 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 1441} 1442 1443static unsigned 1444Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) 1445{ 1446 unsigned tie_t = 0; 1447 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 1448 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 1449 return tie_t; 1450} 1451 1452static void 1453Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1454{ 1455 uint32 tie_t; 1456 tie_t = (val << 28) >> 28; 1457 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 1458 tie_t = (val << 27) >> 31; 1459 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 1460} 1461 1462static unsigned 1463Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) 1464{ 1465 unsigned tie_t = 0; 1466 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 1467 return tie_t; 1468} 1469 1470static void 1471Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1472{ 1473 uint32 tie_t; 1474 tie_t = (val << 29) >> 29; 1475 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 1476} 1477 1478static unsigned 1479Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) 1480{ 1481 unsigned tie_t = 0; 1482 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 1483 return tie_t; 1484} 1485 1486static void 1487Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1488{ 1489 uint32 tie_t; 1490 tie_t = (val << 29) >> 29; 1491 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 1492} 1493 1494static unsigned 1495Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) 1496{ 1497 unsigned tie_t = 0; 1498 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 1499 return tie_t; 1500} 1501 1502static void 1503Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1504{ 1505 uint32 tie_t; 1506 tie_t = (val << 29) >> 29; 1507 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 1508} 1509 1510static void 1511Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, 1512 uint32 val ATTRIBUTE_UNUSED) 1513{ 1514 /* Do nothing. */ 1515} 1516 1517static unsigned 1518Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1519{ 1520 return 0; 1521} 1522 1523static unsigned 1524Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1525{ 1526 return 4; 1527} 1528 1529static unsigned 1530Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1531{ 1532 return 8; 1533} 1534 1535static unsigned 1536Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1537{ 1538 return 12; 1539} 1540 1541static unsigned 1542Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1543{ 1544 return 0; 1545} 1546 1547static unsigned 1548Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1549{ 1550 return 1; 1551} 1552 1553static unsigned 1554Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1555{ 1556 return 2; 1557} 1558 1559static unsigned 1560Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1561{ 1562 return 3; 1563} 1564 1565 1566/* Functional units. */ 1567 1568static xtensa_funcUnit_internal funcUnits[] = { 1569 1570}; 1571 1572 1573/* Register files. */ 1574 1575static xtensa_regfile_internal regfiles[] = { 1576 { "AR", "a", 0, 32, 32 }, 1577 { "MR", "m", 1, 32, 4 } 1578}; 1579 1580 1581/* Interfaces. */ 1582 1583static xtensa_interface_internal interfaces[] = { 1584 { "IMPWIRE", 32, 0, 0, 'i' } 1585}; 1586 1587 1588/* Constant tables. */ 1589 1590/* constant table ai4c */ 1591static const unsigned CONST_TBL_ai4c_0[] = { 1592 0xffffffff, 1593 0x1, 1594 0x2, 1595 0x3, 1596 0x4, 1597 0x5, 1598 0x6, 1599 0x7, 1600 0x8, 1601 0x9, 1602 0xa, 1603 0xb, 1604 0xc, 1605 0xd, 1606 0xe, 1607 0xf, 1608 0 1609}; 1610 1611/* constant table b4c */ 1612static const unsigned CONST_TBL_b4c_0[] = { 1613 0xffffffff, 1614 0x1, 1615 0x2, 1616 0x3, 1617 0x4, 1618 0x5, 1619 0x6, 1620 0x7, 1621 0x8, 1622 0xa, 1623 0xc, 1624 0x10, 1625 0x20, 1626 0x40, 1627 0x80, 1628 0x100, 1629 0 1630}; 1631 1632/* constant table b4cu */ 1633static const unsigned CONST_TBL_b4cu_0[] = { 1634 0x8000, 1635 0x10000, 1636 0x2, 1637 0x3, 1638 0x4, 1639 0x5, 1640 0x6, 1641 0x7, 1642 0x8, 1643 0xa, 1644 0xc, 1645 0x10, 1646 0x20, 1647 0x40, 1648 0x80, 1649 0x100, 1650 0 1651}; 1652 1653 1654/* Instruction operands. */ 1655 1656static int 1657Operand_soffsetx4_decode (uint32 *valp) 1658{ 1659 unsigned soffsetx4_0, offset_0; 1660 offset_0 = *valp & 0x3ffff; 1661 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); 1662 *valp = soffsetx4_0; 1663 return 0; 1664} 1665 1666static int 1667Operand_soffsetx4_encode (uint32 *valp) 1668{ 1669 unsigned offset_0, soffsetx4_0; 1670 soffsetx4_0 = *valp; 1671 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; 1672 *valp = offset_0; 1673 return 0; 1674} 1675 1676static int 1677Operand_soffsetx4_ator (uint32 *valp, uint32 pc) 1678{ 1679 *valp -= (pc & ~0x3); 1680 return 0; 1681} 1682 1683static int 1684Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) 1685{ 1686 *valp += (pc & ~0x3); 1687 return 0; 1688} 1689 1690static int 1691Operand_uimm12x8_decode (uint32 *valp) 1692{ 1693 unsigned uimm12x8_0, imm12_0; 1694 imm12_0 = *valp & 0xfff; 1695 uimm12x8_0 = imm12_0 << 3; 1696 *valp = uimm12x8_0; 1697 return 0; 1698} 1699 1700static int 1701Operand_uimm12x8_encode (uint32 *valp) 1702{ 1703 unsigned imm12_0, uimm12x8_0; 1704 uimm12x8_0 = *valp; 1705 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); 1706 *valp = imm12_0; 1707 return 0; 1708} 1709 1710static int 1711Operand_simm4_decode (uint32 *valp) 1712{ 1713 unsigned simm4_0, mn_0; 1714 mn_0 = *valp & 0xf; 1715 simm4_0 = ((int) mn_0 << 28) >> 28; 1716 *valp = simm4_0; 1717 return 0; 1718} 1719 1720static int 1721Operand_simm4_encode (uint32 *valp) 1722{ 1723 unsigned mn_0, simm4_0; 1724 simm4_0 = *valp; 1725 mn_0 = (simm4_0 & 0xf); 1726 *valp = mn_0; 1727 return 0; 1728} 1729 1730static int 1731Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) 1732{ 1733 return 0; 1734} 1735 1736static int 1737Operand_arr_encode (uint32 *valp) 1738{ 1739 return (*valp & ~0xf) != 0; 1740} 1741 1742static int 1743Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) 1744{ 1745 return 0; 1746} 1747 1748static int 1749Operand_ars_encode (uint32 *valp) 1750{ 1751 return (*valp & ~0xf) != 0; 1752} 1753 1754static int 1755Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) 1756{ 1757 return 0; 1758} 1759 1760static int 1761Operand_art_encode (uint32 *valp) 1762{ 1763 return (*valp & ~0xf) != 0; 1764} 1765 1766static int 1767Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) 1768{ 1769 return 0; 1770} 1771 1772static int 1773Operand_ar0_encode (uint32 *valp) 1774{ 1775 return (*valp & ~0x1f) != 0; 1776} 1777 1778static int 1779Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) 1780{ 1781 return 0; 1782} 1783 1784static int 1785Operand_ar4_encode (uint32 *valp) 1786{ 1787 return (*valp & ~0x1f) != 0; 1788} 1789 1790static int 1791Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) 1792{ 1793 return 0; 1794} 1795 1796static int 1797Operand_ar8_encode (uint32 *valp) 1798{ 1799 return (*valp & ~0x1f) != 0; 1800} 1801 1802static int 1803Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) 1804{ 1805 return 0; 1806} 1807 1808static int 1809Operand_ar12_encode (uint32 *valp) 1810{ 1811 return (*valp & ~0x1f) != 0; 1812} 1813 1814static int 1815Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) 1816{ 1817 return 0; 1818} 1819 1820static int 1821Operand_ars_entry_encode (uint32 *valp) 1822{ 1823 return (*valp & ~0x1f) != 0; 1824} 1825 1826static int 1827Operand_immrx4_decode (uint32 *valp) 1828{ 1829 unsigned immrx4_0, r_0; 1830 r_0 = *valp & 0xf; 1831 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; 1832 *valp = immrx4_0; 1833 return 0; 1834} 1835 1836static int 1837Operand_immrx4_encode (uint32 *valp) 1838{ 1839 unsigned r_0, immrx4_0; 1840 immrx4_0 = *valp; 1841 r_0 = ((immrx4_0 >> 2) & 0xf); 1842 *valp = r_0; 1843 return 0; 1844} 1845 1846static int 1847Operand_lsi4x4_decode (uint32 *valp) 1848{ 1849 unsigned lsi4x4_0, r_0; 1850 r_0 = *valp & 0xf; 1851 lsi4x4_0 = r_0 << 2; 1852 *valp = lsi4x4_0; 1853 return 0; 1854} 1855 1856static int 1857Operand_lsi4x4_encode (uint32 *valp) 1858{ 1859 unsigned r_0, lsi4x4_0; 1860 lsi4x4_0 = *valp; 1861 r_0 = ((lsi4x4_0 >> 2) & 0xf); 1862 *valp = r_0; 1863 return 0; 1864} 1865 1866static int 1867Operand_simm7_decode (uint32 *valp) 1868{ 1869 unsigned simm7_0, imm7_0; 1870 imm7_0 = *valp & 0x7f; 1871 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; 1872 *valp = simm7_0; 1873 return 0; 1874} 1875 1876static int 1877Operand_simm7_encode (uint32 *valp) 1878{ 1879 unsigned imm7_0, simm7_0; 1880 simm7_0 = *valp; 1881 imm7_0 = (simm7_0 & 0x7f); 1882 *valp = imm7_0; 1883 return 0; 1884} 1885 1886static int 1887Operand_uimm6_decode (uint32 *valp) 1888{ 1889 unsigned uimm6_0, imm6_0; 1890 imm6_0 = *valp & 0x3f; 1891 uimm6_0 = 0x4 + (((0) << 6) | imm6_0); 1892 *valp = uimm6_0; 1893 return 0; 1894} 1895 1896static int 1897Operand_uimm6_encode (uint32 *valp) 1898{ 1899 unsigned imm6_0, uimm6_0; 1900 uimm6_0 = *valp; 1901 imm6_0 = (uimm6_0 - 0x4) & 0x3f; 1902 *valp = imm6_0; 1903 return 0; 1904} 1905 1906static int 1907Operand_uimm6_ator (uint32 *valp, uint32 pc) 1908{ 1909 *valp -= pc; 1910 return 0; 1911} 1912 1913static int 1914Operand_uimm6_rtoa (uint32 *valp, uint32 pc) 1915{ 1916 *valp += pc; 1917 return 0; 1918} 1919 1920static int 1921Operand_ai4const_decode (uint32 *valp) 1922{ 1923 unsigned ai4const_0, t_0; 1924 t_0 = *valp & 0xf; 1925 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; 1926 *valp = ai4const_0; 1927 return 0; 1928} 1929 1930static int 1931Operand_ai4const_encode (uint32 *valp) 1932{ 1933 unsigned t_0, ai4const_0; 1934 ai4const_0 = *valp; 1935 switch (ai4const_0) 1936 { 1937 case 0xffffffff: t_0 = 0; break; 1938 case 0x1: t_0 = 0x1; break; 1939 case 0x2: t_0 = 0x2; break; 1940 case 0x3: t_0 = 0x3; break; 1941 case 0x4: t_0 = 0x4; break; 1942 case 0x5: t_0 = 0x5; break; 1943 case 0x6: t_0 = 0x6; break; 1944 case 0x7: t_0 = 0x7; break; 1945 case 0x8: t_0 = 0x8; break; 1946 case 0x9: t_0 = 0x9; break; 1947 case 0xa: t_0 = 0xa; break; 1948 case 0xb: t_0 = 0xb; break; 1949 case 0xc: t_0 = 0xc; break; 1950 case 0xd: t_0 = 0xd; break; 1951 case 0xe: t_0 = 0xe; break; 1952 default: t_0 = 0xf; break; 1953 } 1954 *valp = t_0; 1955 return 0; 1956} 1957 1958static int 1959Operand_b4const_decode (uint32 *valp) 1960{ 1961 unsigned b4const_0, r_0; 1962 r_0 = *valp & 0xf; 1963 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; 1964 *valp = b4const_0; 1965 return 0; 1966} 1967 1968static int 1969Operand_b4const_encode (uint32 *valp) 1970{ 1971 unsigned r_0, b4const_0; 1972 b4const_0 = *valp; 1973 switch (b4const_0) 1974 { 1975 case 0xffffffff: r_0 = 0; break; 1976 case 0x1: r_0 = 0x1; break; 1977 case 0x2: r_0 = 0x2; break; 1978 case 0x3: r_0 = 0x3; break; 1979 case 0x4: r_0 = 0x4; break; 1980 case 0x5: r_0 = 0x5; break; 1981 case 0x6: r_0 = 0x6; break; 1982 case 0x7: r_0 = 0x7; break; 1983 case 0x8: r_0 = 0x8; break; 1984 case 0xa: r_0 = 0x9; break; 1985 case 0xc: r_0 = 0xa; break; 1986 case 0x10: r_0 = 0xb; break; 1987 case 0x20: r_0 = 0xc; break; 1988 case 0x40: r_0 = 0xd; break; 1989 case 0x80: r_0 = 0xe; break; 1990 default: r_0 = 0xf; break; 1991 } 1992 *valp = r_0; 1993 return 0; 1994} 1995 1996static int 1997Operand_b4constu_decode (uint32 *valp) 1998{ 1999 unsigned b4constu_0, r_0; 2000 r_0 = *valp & 0xf; 2001 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; 2002 *valp = b4constu_0; 2003 return 0; 2004} 2005 2006static int 2007Operand_b4constu_encode (uint32 *valp) 2008{ 2009 unsigned r_0, b4constu_0; 2010 b4constu_0 = *valp; 2011 switch (b4constu_0) 2012 { 2013 case 0x8000: r_0 = 0; break; 2014 case 0x10000: r_0 = 0x1; break; 2015 case 0x2: r_0 = 0x2; break; 2016 case 0x3: r_0 = 0x3; break; 2017 case 0x4: r_0 = 0x4; break; 2018 case 0x5: r_0 = 0x5; break; 2019 case 0x6: r_0 = 0x6; break; 2020 case 0x7: r_0 = 0x7; break; 2021 case 0x8: r_0 = 0x8; break; 2022 case 0xa: r_0 = 0x9; break; 2023 case 0xc: r_0 = 0xa; break; 2024 case 0x10: r_0 = 0xb; break; 2025 case 0x20: r_0 = 0xc; break; 2026 case 0x40: r_0 = 0xd; break; 2027 case 0x80: r_0 = 0xe; break; 2028 default: r_0 = 0xf; break; 2029 } 2030 *valp = r_0; 2031 return 0; 2032} 2033 2034static int 2035Operand_uimm8_decode (uint32 *valp) 2036{ 2037 unsigned uimm8_0, imm8_0; 2038 imm8_0 = *valp & 0xff; 2039 uimm8_0 = imm8_0; 2040 *valp = uimm8_0; 2041 return 0; 2042} 2043 2044static int 2045Operand_uimm8_encode (uint32 *valp) 2046{ 2047 unsigned imm8_0, uimm8_0; 2048 uimm8_0 = *valp; 2049 imm8_0 = (uimm8_0 & 0xff); 2050 *valp = imm8_0; 2051 return 0; 2052} 2053 2054static int 2055Operand_uimm8x2_decode (uint32 *valp) 2056{ 2057 unsigned uimm8x2_0, imm8_0; 2058 imm8_0 = *valp & 0xff; 2059 uimm8x2_0 = imm8_0 << 1; 2060 *valp = uimm8x2_0; 2061 return 0; 2062} 2063 2064static int 2065Operand_uimm8x2_encode (uint32 *valp) 2066{ 2067 unsigned imm8_0, uimm8x2_0; 2068 uimm8x2_0 = *valp; 2069 imm8_0 = ((uimm8x2_0 >> 1) & 0xff); 2070 *valp = imm8_0; 2071 return 0; 2072} 2073 2074static int 2075Operand_uimm8x4_decode (uint32 *valp) 2076{ 2077 unsigned uimm8x4_0, imm8_0; 2078 imm8_0 = *valp & 0xff; 2079 uimm8x4_0 = imm8_0 << 2; 2080 *valp = uimm8x4_0; 2081 return 0; 2082} 2083 2084static int 2085Operand_uimm8x4_encode (uint32 *valp) 2086{ 2087 unsigned imm8_0, uimm8x4_0; 2088 uimm8x4_0 = *valp; 2089 imm8_0 = ((uimm8x4_0 >> 2) & 0xff); 2090 *valp = imm8_0; 2091 return 0; 2092} 2093 2094static int 2095Operand_uimm4x16_decode (uint32 *valp) 2096{ 2097 unsigned uimm4x16_0, op2_0; 2098 op2_0 = *valp & 0xf; 2099 uimm4x16_0 = op2_0 << 4; 2100 *valp = uimm4x16_0; 2101 return 0; 2102} 2103 2104static int 2105Operand_uimm4x16_encode (uint32 *valp) 2106{ 2107 unsigned op2_0, uimm4x16_0; 2108 uimm4x16_0 = *valp; 2109 op2_0 = ((uimm4x16_0 >> 4) & 0xf); 2110 *valp = op2_0; 2111 return 0; 2112} 2113 2114static int 2115Operand_simm8_decode (uint32 *valp) 2116{ 2117 unsigned simm8_0, imm8_0; 2118 imm8_0 = *valp & 0xff; 2119 simm8_0 = ((int) imm8_0 << 24) >> 24; 2120 *valp = simm8_0; 2121 return 0; 2122} 2123 2124static int 2125Operand_simm8_encode (uint32 *valp) 2126{ 2127 unsigned imm8_0, simm8_0; 2128 simm8_0 = *valp; 2129 imm8_0 = (simm8_0 & 0xff); 2130 *valp = imm8_0; 2131 return 0; 2132} 2133 2134static int 2135Operand_simm8x256_decode (uint32 *valp) 2136{ 2137 unsigned simm8x256_0, imm8_0; 2138 imm8_0 = *valp & 0xff; 2139 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; 2140 *valp = simm8x256_0; 2141 return 0; 2142} 2143 2144static int 2145Operand_simm8x256_encode (uint32 *valp) 2146{ 2147 unsigned imm8_0, simm8x256_0; 2148 simm8x256_0 = *valp; 2149 imm8_0 = ((simm8x256_0 >> 8) & 0xff); 2150 *valp = imm8_0; 2151 return 0; 2152} 2153 2154static int 2155Operand_simm12b_decode (uint32 *valp) 2156{ 2157 unsigned simm12b_0, imm12b_0; 2158 imm12b_0 = *valp & 0xfff; 2159 simm12b_0 = ((int) imm12b_0 << 20) >> 20; 2160 *valp = simm12b_0; 2161 return 0; 2162} 2163 2164static int 2165Operand_simm12b_encode (uint32 *valp) 2166{ 2167 unsigned imm12b_0, simm12b_0; 2168 simm12b_0 = *valp; 2169 imm12b_0 = (simm12b_0 & 0xfff); 2170 *valp = imm12b_0; 2171 return 0; 2172} 2173 2174static int 2175Operand_msalp32_decode (uint32 *valp) 2176{ 2177 unsigned msalp32_0, sal_0; 2178 sal_0 = *valp & 0x1f; 2179 msalp32_0 = 0x20 - sal_0; 2180 *valp = msalp32_0; 2181 return 0; 2182} 2183 2184static int 2185Operand_msalp32_encode (uint32 *valp) 2186{ 2187 unsigned sal_0, msalp32_0; 2188 msalp32_0 = *valp; 2189 sal_0 = (0x20 - msalp32_0) & 0x1f; 2190 *valp = sal_0; 2191 return 0; 2192} 2193 2194static int 2195Operand_op2p1_decode (uint32 *valp) 2196{ 2197 unsigned op2p1_0, op2_0; 2198 op2_0 = *valp & 0xf; 2199 op2p1_0 = op2_0 + 0x1; 2200 *valp = op2p1_0; 2201 return 0; 2202} 2203 2204static int 2205Operand_op2p1_encode (uint32 *valp) 2206{ 2207 unsigned op2_0, op2p1_0; 2208 op2p1_0 = *valp; 2209 op2_0 = (op2p1_0 - 0x1) & 0xf; 2210 *valp = op2_0; 2211 return 0; 2212} 2213 2214static int 2215Operand_label8_decode (uint32 *valp) 2216{ 2217 unsigned label8_0, imm8_0; 2218 imm8_0 = *valp & 0xff; 2219 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); 2220 *valp = label8_0; 2221 return 0; 2222} 2223 2224static int 2225Operand_label8_encode (uint32 *valp) 2226{ 2227 unsigned imm8_0, label8_0; 2228 label8_0 = *valp; 2229 imm8_0 = (label8_0 - 0x4) & 0xff; 2230 *valp = imm8_0; 2231 return 0; 2232} 2233 2234static int 2235Operand_label8_ator (uint32 *valp, uint32 pc) 2236{ 2237 *valp -= pc; 2238 return 0; 2239} 2240 2241static int 2242Operand_label8_rtoa (uint32 *valp, uint32 pc) 2243{ 2244 *valp += pc; 2245 return 0; 2246} 2247 2248static int 2249Operand_ulabel8_decode (uint32 *valp) 2250{ 2251 unsigned ulabel8_0, imm8_0; 2252 imm8_0 = *valp & 0xff; 2253 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); 2254 *valp = ulabel8_0; 2255 return 0; 2256} 2257 2258static int 2259Operand_ulabel8_encode (uint32 *valp) 2260{ 2261 unsigned imm8_0, ulabel8_0; 2262 ulabel8_0 = *valp; 2263 imm8_0 = (ulabel8_0 - 0x4) & 0xff; 2264 *valp = imm8_0; 2265 return 0; 2266} 2267 2268static int 2269Operand_ulabel8_ator (uint32 *valp, uint32 pc) 2270{ 2271 *valp -= pc; 2272 return 0; 2273} 2274 2275static int 2276Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) 2277{ 2278 *valp += pc; 2279 return 0; 2280} 2281 2282static int 2283Operand_label12_decode (uint32 *valp) 2284{ 2285 unsigned label12_0, imm12_0; 2286 imm12_0 = *valp & 0xfff; 2287 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); 2288 *valp = label12_0; 2289 return 0; 2290} 2291 2292static int 2293Operand_label12_encode (uint32 *valp) 2294{ 2295 unsigned imm12_0, label12_0; 2296 label12_0 = *valp; 2297 imm12_0 = (label12_0 - 0x4) & 0xfff; 2298 *valp = imm12_0; 2299 return 0; 2300} 2301 2302static int 2303Operand_label12_ator (uint32 *valp, uint32 pc) 2304{ 2305 *valp -= pc; 2306 return 0; 2307} 2308 2309static int 2310Operand_label12_rtoa (uint32 *valp, uint32 pc) 2311{ 2312 *valp += pc; 2313 return 0; 2314} 2315 2316static int 2317Operand_soffset_decode (uint32 *valp) 2318{ 2319 unsigned soffset_0, offset_0; 2320 offset_0 = *valp & 0x3ffff; 2321 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); 2322 *valp = soffset_0; 2323 return 0; 2324} 2325 2326static int 2327Operand_soffset_encode (uint32 *valp) 2328{ 2329 unsigned offset_0, soffset_0; 2330 soffset_0 = *valp; 2331 offset_0 = (soffset_0 - 0x4) & 0x3ffff; 2332 *valp = offset_0; 2333 return 0; 2334} 2335 2336static int 2337Operand_soffset_ator (uint32 *valp, uint32 pc) 2338{ 2339 *valp -= pc; 2340 return 0; 2341} 2342 2343static int 2344Operand_soffset_rtoa (uint32 *valp, uint32 pc) 2345{ 2346 *valp += pc; 2347 return 0; 2348} 2349 2350static int 2351Operand_uimm16x4_decode (uint32 *valp) 2352{ 2353 unsigned uimm16x4_0, imm16_0; 2354 imm16_0 = *valp & 0xffff; 2355 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; 2356 *valp = uimm16x4_0; 2357 return 0; 2358} 2359 2360static int 2361Operand_uimm16x4_encode (uint32 *valp) 2362{ 2363 unsigned imm16_0, uimm16x4_0; 2364 uimm16x4_0 = *valp; 2365 imm16_0 = (uimm16x4_0 >> 2) & 0xffff; 2366 *valp = imm16_0; 2367 return 0; 2368} 2369 2370static int 2371Operand_uimm16x4_ator (uint32 *valp, uint32 pc) 2372{ 2373 *valp -= ((pc + 3) & ~0x3); 2374 return 0; 2375} 2376 2377static int 2378Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) 2379{ 2380 *valp += ((pc + 3) & ~0x3); 2381 return 0; 2382} 2383 2384static int 2385Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) 2386{ 2387 return 0; 2388} 2389 2390static int 2391Operand_mx_encode (uint32 *valp) 2392{ 2393 return (*valp & ~0x3) != 0; 2394} 2395 2396static int 2397Operand_my_decode (uint32 *valp) 2398{ 2399 *valp += 2; 2400 return 0; 2401} 2402 2403static int 2404Operand_my_encode (uint32 *valp) 2405{ 2406 int error; 2407 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); 2408 *valp = *valp & 1; 2409 return error; 2410} 2411 2412static int 2413Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) 2414{ 2415 return 0; 2416} 2417 2418static int 2419Operand_mw_encode (uint32 *valp) 2420{ 2421 return (*valp & ~0x3) != 0; 2422} 2423 2424static int 2425Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) 2426{ 2427 return 0; 2428} 2429 2430static int 2431Operand_mr0_encode (uint32 *valp) 2432{ 2433 return (*valp & ~0x3) != 0; 2434} 2435 2436static int 2437Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) 2438{ 2439 return 0; 2440} 2441 2442static int 2443Operand_mr1_encode (uint32 *valp) 2444{ 2445 return (*valp & ~0x3) != 0; 2446} 2447 2448static int 2449Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) 2450{ 2451 return 0; 2452} 2453 2454static int 2455Operand_mr2_encode (uint32 *valp) 2456{ 2457 return (*valp & ~0x3) != 0; 2458} 2459 2460static int 2461Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) 2462{ 2463 return 0; 2464} 2465 2466static int 2467Operand_mr3_encode (uint32 *valp) 2468{ 2469 return (*valp & ~0x3) != 0; 2470} 2471 2472static int 2473Operand_immt_decode (uint32 *valp) 2474{ 2475 unsigned immt_0, t_0; 2476 t_0 = *valp & 0xf; 2477 immt_0 = t_0; 2478 *valp = immt_0; 2479 return 0; 2480} 2481 2482static int 2483Operand_immt_encode (uint32 *valp) 2484{ 2485 unsigned t_0, immt_0; 2486 immt_0 = *valp; 2487 t_0 = immt_0 & 0xf; 2488 *valp = t_0; 2489 return 0; 2490} 2491 2492static int 2493Operand_imms_decode (uint32 *valp) 2494{ 2495 unsigned imms_0, s_0; 2496 s_0 = *valp & 0xf; 2497 imms_0 = s_0; 2498 *valp = imms_0; 2499 return 0; 2500} 2501 2502static int 2503Operand_imms_encode (uint32 *valp) 2504{ 2505 unsigned s_0, imms_0; 2506 imms_0 = *valp; 2507 s_0 = imms_0 & 0xf; 2508 *valp = s_0; 2509 return 0; 2510} 2511 2512static int 2513Operand_tp7_decode (uint32 *valp) 2514{ 2515 unsigned tp7_0, t_0; 2516 t_0 = *valp & 0xf; 2517 tp7_0 = t_0 + 0x7; 2518 *valp = tp7_0; 2519 return 0; 2520} 2521 2522static int 2523Operand_tp7_encode (uint32 *valp) 2524{ 2525 unsigned t_0, tp7_0; 2526 tp7_0 = *valp; 2527 t_0 = (tp7_0 - 0x7) & 0xf; 2528 *valp = t_0; 2529 return 0; 2530} 2531 2532static int 2533Operand_xt_wbr15_label_decode (uint32 *valp) 2534{ 2535 unsigned xt_wbr15_label_0, xt_wbr15_imm_0; 2536 xt_wbr15_imm_0 = *valp & 0x7fff; 2537 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); 2538 *valp = xt_wbr15_label_0; 2539 return 0; 2540} 2541 2542static int 2543Operand_xt_wbr15_label_encode (uint32 *valp) 2544{ 2545 unsigned xt_wbr15_imm_0, xt_wbr15_label_0; 2546 xt_wbr15_label_0 = *valp; 2547 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; 2548 *valp = xt_wbr15_imm_0; 2549 return 0; 2550} 2551 2552static int 2553Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) 2554{ 2555 *valp -= pc; 2556 return 0; 2557} 2558 2559static int 2560Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) 2561{ 2562 *valp += pc; 2563 return 0; 2564} 2565 2566static int 2567Operand_xt_wbr18_label_decode (uint32 *valp) 2568{ 2569 unsigned xt_wbr18_label_0, xt_wbr18_imm_0; 2570 xt_wbr18_imm_0 = *valp & 0x3ffff; 2571 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); 2572 *valp = xt_wbr18_label_0; 2573 return 0; 2574} 2575 2576static int 2577Operand_xt_wbr18_label_encode (uint32 *valp) 2578{ 2579 unsigned xt_wbr18_imm_0, xt_wbr18_label_0; 2580 xt_wbr18_label_0 = *valp; 2581 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; 2582 *valp = xt_wbr18_imm_0; 2583 return 0; 2584} 2585 2586static int 2587Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) 2588{ 2589 *valp -= pc; 2590 return 0; 2591} 2592 2593static int 2594Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) 2595{ 2596 *valp += pc; 2597 return 0; 2598} 2599 2600static xtensa_operand_internal operands[] = { 2601 { "soffsetx4", 10, -1, 0, 2602 XTENSA_OPERAND_IS_PCRELATIVE, 2603 Operand_soffsetx4_encode, Operand_soffsetx4_decode, 2604 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, 2605 { "uimm12x8", 3, -1, 0, 2606 0, 2607 Operand_uimm12x8_encode, Operand_uimm12x8_decode, 2608 0, 0 }, 2609 { "simm4", 26, -1, 0, 2610 0, 2611 Operand_simm4_encode, Operand_simm4_decode, 2612 0, 0 }, 2613 { "arr", 14, 0, 1, 2614 XTENSA_OPERAND_IS_REGISTER, 2615 Operand_arr_encode, Operand_arr_decode, 2616 0, 0 }, 2617 { "ars", 5, 0, 1, 2618 XTENSA_OPERAND_IS_REGISTER, 2619 Operand_ars_encode, Operand_ars_decode, 2620 0, 0 }, 2621 { "*ars_invisible", 5, 0, 1, 2622 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2623 Operand_ars_encode, Operand_ars_decode, 2624 0, 0 }, 2625 { "art", 0, 0, 1, 2626 XTENSA_OPERAND_IS_REGISTER, 2627 Operand_art_encode, Operand_art_decode, 2628 0, 0 }, 2629 { "ar0", 48, 0, 1, 2630 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2631 Operand_ar0_encode, Operand_ar0_decode, 2632 0, 0 }, 2633 { "ar4", 49, 0, 1, 2634 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2635 Operand_ar4_encode, Operand_ar4_decode, 2636 0, 0 }, 2637 { "ar8", 50, 0, 1, 2638 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2639 Operand_ar8_encode, Operand_ar8_decode, 2640 0, 0 }, 2641 { "ar12", 51, 0, 1, 2642 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2643 Operand_ar12_encode, Operand_ar12_decode, 2644 0, 0 }, 2645 { "ars_entry", 5, 0, 1, 2646 XTENSA_OPERAND_IS_REGISTER, 2647 Operand_ars_entry_encode, Operand_ars_entry_decode, 2648 0, 0 }, 2649 { "immrx4", 14, -1, 0, 2650 0, 2651 Operand_immrx4_encode, Operand_immrx4_decode, 2652 0, 0 }, 2653 { "lsi4x4", 14, -1, 0, 2654 0, 2655 Operand_lsi4x4_encode, Operand_lsi4x4_decode, 2656 0, 0 }, 2657 { "simm7", 34, -1, 0, 2658 0, 2659 Operand_simm7_encode, Operand_simm7_decode, 2660 0, 0 }, 2661 { "uimm6", 33, -1, 0, 2662 XTENSA_OPERAND_IS_PCRELATIVE, 2663 Operand_uimm6_encode, Operand_uimm6_decode, 2664 Operand_uimm6_ator, Operand_uimm6_rtoa }, 2665 { "ai4const", 0, -1, 0, 2666 0, 2667 Operand_ai4const_encode, Operand_ai4const_decode, 2668 0, 0 }, 2669 { "b4const", 14, -1, 0, 2670 0, 2671 Operand_b4const_encode, Operand_b4const_decode, 2672 0, 0 }, 2673 { "b4constu", 14, -1, 0, 2674 0, 2675 Operand_b4constu_encode, Operand_b4constu_decode, 2676 0, 0 }, 2677 { "uimm8", 4, -1, 0, 2678 0, 2679 Operand_uimm8_encode, Operand_uimm8_decode, 2680 0, 0 }, 2681 { "uimm8x2", 4, -1, 0, 2682 0, 2683 Operand_uimm8x2_encode, Operand_uimm8x2_decode, 2684 0, 0 }, 2685 { "uimm8x4", 4, -1, 0, 2686 0, 2687 Operand_uimm8x4_encode, Operand_uimm8x4_decode, 2688 0, 0 }, 2689 { "uimm4x16", 13, -1, 0, 2690 0, 2691 Operand_uimm4x16_encode, Operand_uimm4x16_decode, 2692 0, 0 }, 2693 { "simm8", 4, -1, 0, 2694 0, 2695 Operand_simm8_encode, Operand_simm8_decode, 2696 0, 0 }, 2697 { "simm8x256", 4, -1, 0, 2698 0, 2699 Operand_simm8x256_encode, Operand_simm8x256_decode, 2700 0, 0 }, 2701 { "simm12b", 6, -1, 0, 2702 0, 2703 Operand_simm12b_encode, Operand_simm12b_decode, 2704 0, 0 }, 2705 { "msalp32", 18, -1, 0, 2706 0, 2707 Operand_msalp32_encode, Operand_msalp32_decode, 2708 0, 0 }, 2709 { "op2p1", 13, -1, 0, 2710 0, 2711 Operand_op2p1_encode, Operand_op2p1_decode, 2712 0, 0 }, 2713 { "label8", 4, -1, 0, 2714 XTENSA_OPERAND_IS_PCRELATIVE, 2715 Operand_label8_encode, Operand_label8_decode, 2716 Operand_label8_ator, Operand_label8_rtoa }, 2717 { "ulabel8", 4, -1, 0, 2718 XTENSA_OPERAND_IS_PCRELATIVE, 2719 Operand_ulabel8_encode, Operand_ulabel8_decode, 2720 Operand_ulabel8_ator, Operand_ulabel8_rtoa }, 2721 { "label12", 3, -1, 0, 2722 XTENSA_OPERAND_IS_PCRELATIVE, 2723 Operand_label12_encode, Operand_label12_decode, 2724 Operand_label12_ator, Operand_label12_rtoa }, 2725 { "soffset", 10, -1, 0, 2726 XTENSA_OPERAND_IS_PCRELATIVE, 2727 Operand_soffset_encode, Operand_soffset_decode, 2728 Operand_soffset_ator, Operand_soffset_rtoa }, 2729 { "uimm16x4", 7, -1, 0, 2730 XTENSA_OPERAND_IS_PCRELATIVE, 2731 Operand_uimm16x4_encode, Operand_uimm16x4_decode, 2732 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, 2733 { "mx", 43, 1, 1, 2734 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, 2735 Operand_mx_encode, Operand_mx_decode, 2736 0, 0 }, 2737 { "my", 42, 1, 1, 2738 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, 2739 Operand_my_encode, Operand_my_decode, 2740 0, 0 }, 2741 { "mw", 41, 1, 1, 2742 XTENSA_OPERAND_IS_REGISTER, 2743 Operand_mw_encode, Operand_mw_decode, 2744 0, 0 }, 2745 { "mr0", 52, 1, 1, 2746 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2747 Operand_mr0_encode, Operand_mr0_decode, 2748 0, 0 }, 2749 { "mr1", 53, 1, 1, 2750 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2751 Operand_mr1_encode, Operand_mr1_decode, 2752 0, 0 }, 2753 { "mr2", 54, 1, 1, 2754 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2755 Operand_mr2_encode, Operand_mr2_decode, 2756 0, 0 }, 2757 { "mr3", 55, 1, 1, 2758 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2759 Operand_mr3_encode, Operand_mr3_decode, 2760 0, 0 }, 2761 { "immt", 0, -1, 0, 2762 0, 2763 Operand_immt_encode, Operand_immt_decode, 2764 0, 0 }, 2765 { "imms", 5, -1, 0, 2766 0, 2767 Operand_imms_encode, Operand_imms_decode, 2768 0, 0 }, 2769 { "tp7", 0, -1, 0, 2770 0, 2771 Operand_tp7_encode, Operand_tp7_decode, 2772 0, 0 }, 2773 { "xt_wbr15_label", 44, -1, 0, 2774 XTENSA_OPERAND_IS_PCRELATIVE, 2775 Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, 2776 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, 2777 { "xt_wbr18_label", 45, -1, 0, 2778 XTENSA_OPERAND_IS_PCRELATIVE, 2779 Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, 2780 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, 2781 { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, 2782 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, 2783 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, 2784 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, 2785 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, 2786 { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, 2787 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, 2788 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, 2789 { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, 2790 { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, 2791 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, 2792 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, 2793 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, 2794 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, 2795 { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, 2796 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, 2797 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, 2798 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, 2799 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, 2800 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, 2801 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, 2802 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, 2803 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, 2804 { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, 2805 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, 2806 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, 2807 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, 2808 { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, 2809 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, 2810 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, 2811 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, 2812 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, 2813 { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, 2814 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, 2815 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }, 2816 { "r3", 35, -1, 0, 0, 0, 0, 0, 0 }, 2817 { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 }, 2818 { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 }, 2819 { "t3", 38, -1, 0, 0, 0, 0, 0, 0 }, 2820 { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 }, 2821 { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 }, 2822 { "w", 41, -1, 0, 0, 0, 0, 0, 0 }, 2823 { "y", 42, -1, 0, 0, 0, 0, 0, 0 }, 2824 { "x", 43, -1, 0, 0, 0, 0, 0, 0 }, 2825 { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 }, 2826 { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 }, 2827 { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 }, 2828 { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 } 2829}; 2830 2831 2832/* Iclass table. */ 2833 2834static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { 2835 { { STATE_PSRING }, 'i' }, 2836 { { STATE_PSEXCM }, 'm' }, 2837 { { STATE_EPC1 }, 'i' } 2838}; 2839 2840static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { 2841 { { STATE_PSEXCM }, 'i' }, 2842 { { STATE_PSRING }, 'i' }, 2843 { { STATE_DEPC }, 'i' } 2844}; 2845 2846static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { 2847 { { 0 /* soffsetx4 */ }, 'i' }, 2848 { { 10 /* ar12 */ }, 'o' } 2849}; 2850 2851static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { 2852 { { STATE_PSCALLINC }, 'o' } 2853}; 2854 2855static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { 2856 { { 0 /* soffsetx4 */ }, 'i' }, 2857 { { 9 /* ar8 */ }, 'o' } 2858}; 2859 2860static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { 2861 { { STATE_PSCALLINC }, 'o' } 2862}; 2863 2864static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { 2865 { { 0 /* soffsetx4 */ }, 'i' }, 2866 { { 8 /* ar4 */ }, 'o' } 2867}; 2868 2869static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { 2870 { { STATE_PSCALLINC }, 'o' } 2871}; 2872 2873static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { 2874 { { 4 /* ars */ }, 'i' }, 2875 { { 10 /* ar12 */ }, 'o' } 2876}; 2877 2878static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { 2879 { { STATE_PSCALLINC }, 'o' } 2880}; 2881 2882static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { 2883 { { 4 /* ars */ }, 'i' }, 2884 { { 9 /* ar8 */ }, 'o' } 2885}; 2886 2887static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { 2888 { { STATE_PSCALLINC }, 'o' } 2889}; 2890 2891static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { 2892 { { 4 /* ars */ }, 'i' }, 2893 { { 8 /* ar4 */ }, 'o' } 2894}; 2895 2896static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { 2897 { { STATE_PSCALLINC }, 'o' } 2898}; 2899 2900static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { 2901 { { 11 /* ars_entry */ }, 's' }, 2902 { { 4 /* ars */ }, 'i' }, 2903 { { 1 /* uimm12x8 */ }, 'i' } 2904}; 2905 2906static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { 2907 { { STATE_PSCALLINC }, 'i' }, 2908 { { STATE_PSEXCM }, 'i' }, 2909 { { STATE_PSWOE }, 'i' }, 2910 { { STATE_WindowBase }, 'm' }, 2911 { { STATE_WindowStart }, 'm' } 2912}; 2913 2914static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { 2915 { { 6 /* art */ }, 'o' }, 2916 { { 4 /* ars */ }, 'i' } 2917}; 2918 2919static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { 2920 { { STATE_WindowBase }, 'i' }, 2921 { { STATE_WindowStart }, 'i' } 2922}; 2923 2924static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { 2925 { { 2 /* simm4 */ }, 'i' } 2926}; 2927 2928static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { 2929 { { STATE_PSEXCM }, 'i' }, 2930 { { STATE_PSRING }, 'i' }, 2931 { { STATE_WindowBase }, 'm' } 2932}; 2933 2934static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { 2935 { { 5 /* *ars_invisible */ }, 'i' } 2936}; 2937 2938static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { 2939 { { STATE_WindowBase }, 'm' }, 2940 { { STATE_WindowStart }, 'm' }, 2941 { { STATE_PSEXCM }, 'i' }, 2942 { { STATE_PSWOE }, 'i' } 2943}; 2944 2945static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { 2946 { { STATE_EPC1 }, 'i' }, 2947 { { STATE_PSEXCM }, 'm' }, 2948 { { STATE_PSRING }, 'i' }, 2949 { { STATE_WindowBase }, 'm' }, 2950 { { STATE_WindowStart }, 'm' }, 2951 { { STATE_PSOWB }, 'i' } 2952}; 2953 2954static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { 2955 { { 6 /* art */ }, 'o' }, 2956 { { 4 /* ars */ }, 'i' }, 2957 { { 12 /* immrx4 */ }, 'i' } 2958}; 2959 2960static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { 2961 { { STATE_PSEXCM }, 'i' }, 2962 { { STATE_PSRING }, 'i' } 2963}; 2964 2965static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { 2966 { { 6 /* art */ }, 'i' }, 2967 { { 4 /* ars */ }, 'i' }, 2968 { { 12 /* immrx4 */ }, 'i' } 2969}; 2970 2971static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { 2972 { { STATE_PSEXCM }, 'i' }, 2973 { { STATE_PSRING }, 'i' } 2974}; 2975 2976static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { 2977 { { 6 /* art */ }, 'o' } 2978}; 2979 2980static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { 2981 { { STATE_PSEXCM }, 'i' }, 2982 { { STATE_PSRING }, 'i' }, 2983 { { STATE_WindowBase }, 'i' } 2984}; 2985 2986static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { 2987 { { 6 /* art */ }, 'i' } 2988}; 2989 2990static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { 2991 { { STATE_PSEXCM }, 'i' }, 2992 { { STATE_PSRING }, 'i' }, 2993 { { STATE_WindowBase }, 'o' } 2994}; 2995 2996static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { 2997 { { 6 /* art */ }, 'm' } 2998}; 2999 3000static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { 3001 { { STATE_PSEXCM }, 'i' }, 3002 { { STATE_PSRING }, 'i' }, 3003 { { STATE_WindowBase }, 'm' } 3004}; 3005 3006static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { 3007 { { 6 /* art */ }, 'o' } 3008}; 3009 3010static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { 3011 { { STATE_PSEXCM }, 'i' }, 3012 { { STATE_PSRING }, 'i' }, 3013 { { STATE_WindowStart }, 'i' } 3014}; 3015 3016static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { 3017 { { 6 /* art */ }, 'i' } 3018}; 3019 3020static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { 3021 { { STATE_PSEXCM }, 'i' }, 3022 { { STATE_PSRING }, 'i' }, 3023 { { STATE_WindowStart }, 'o' } 3024}; 3025 3026static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { 3027 { { 6 /* art */ }, 'm' } 3028}; 3029 3030static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { 3031 { { STATE_PSEXCM }, 'i' }, 3032 { { STATE_PSRING }, 'i' }, 3033 { { STATE_WindowStart }, 'm' } 3034}; 3035 3036static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { 3037 { { 3 /* arr */ }, 'o' }, 3038 { { 4 /* ars */ }, 'i' }, 3039 { { 6 /* art */ }, 'i' } 3040}; 3041 3042static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { 3043 { { 3 /* arr */ }, 'o' }, 3044 { { 4 /* ars */ }, 'i' }, 3045 { { 16 /* ai4const */ }, 'i' } 3046}; 3047 3048static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { 3049 { { 4 /* ars */ }, 'i' }, 3050 { { 15 /* uimm6 */ }, 'i' } 3051}; 3052 3053static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { 3054 { { 6 /* art */ }, 'o' }, 3055 { { 4 /* ars */ }, 'i' }, 3056 { { 13 /* lsi4x4 */ }, 'i' } 3057}; 3058 3059static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { 3060 { { 6 /* art */ }, 'o' }, 3061 { { 4 /* ars */ }, 'i' } 3062}; 3063 3064static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { 3065 { { 4 /* ars */ }, 'o' }, 3066 { { 14 /* simm7 */ }, 'i' } 3067}; 3068 3069static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { 3070 { { 5 /* *ars_invisible */ }, 'i' } 3071}; 3072 3073static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { 3074 { { 6 /* art */ }, 'i' }, 3075 { { 4 /* ars */ }, 'i' }, 3076 { { 13 /* lsi4x4 */ }, 'i' } 3077}; 3078 3079static xtensa_arg_internal Iclass_rur_threadptr_args[] = { 3080 { { 3 /* arr */ }, 'o' } 3081}; 3082 3083static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { 3084 { { STATE_THREADPTR }, 'i' } 3085}; 3086 3087static xtensa_arg_internal Iclass_wur_threadptr_args[] = { 3088 { { 6 /* art */ }, 'i' } 3089}; 3090 3091static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { 3092 { { STATE_THREADPTR }, 'o' } 3093}; 3094 3095static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { 3096 { { 6 /* art */ }, 'o' }, 3097 { { 4 /* ars */ }, 'i' }, 3098 { { 23 /* simm8 */ }, 'i' } 3099}; 3100 3101static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { 3102 { { 6 /* art */ }, 'o' }, 3103 { { 4 /* ars */ }, 'i' }, 3104 { { 24 /* simm8x256 */ }, 'i' } 3105}; 3106 3107static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { 3108 { { 3 /* arr */ }, 'o' }, 3109 { { 4 /* ars */ }, 'i' }, 3110 { { 6 /* art */ }, 'i' } 3111}; 3112 3113static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { 3114 { { 3 /* arr */ }, 'o' }, 3115 { { 4 /* ars */ }, 'i' }, 3116 { { 6 /* art */ }, 'i' } 3117}; 3118 3119static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { 3120 { { 4 /* ars */ }, 'i' }, 3121 { { 17 /* b4const */ }, 'i' }, 3122 { { 28 /* label8 */ }, 'i' } 3123}; 3124 3125static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { 3126 { { 4 /* ars */ }, 'i' }, 3127 { { 47 /* bbi */ }, 'i' }, 3128 { { 28 /* label8 */ }, 'i' } 3129}; 3130 3131static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { 3132 { { 4 /* ars */ }, 'i' }, 3133 { { 18 /* b4constu */ }, 'i' }, 3134 { { 28 /* label8 */ }, 'i' } 3135}; 3136 3137static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { 3138 { { 4 /* ars */ }, 'i' }, 3139 { { 6 /* art */ }, 'i' }, 3140 { { 28 /* label8 */ }, 'i' } 3141}; 3142 3143static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { 3144 { { 4 /* ars */ }, 'i' }, 3145 { { 30 /* label12 */ }, 'i' } 3146}; 3147 3148static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { 3149 { { 0 /* soffsetx4 */ }, 'i' }, 3150 { { 7 /* ar0 */ }, 'o' } 3151}; 3152 3153static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { 3154 { { 4 /* ars */ }, 'i' }, 3155 { { 7 /* ar0 */ }, 'o' } 3156}; 3157 3158static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { 3159 { { 3 /* arr */ }, 'o' }, 3160 { { 6 /* art */ }, 'i' }, 3161 { { 62 /* sae */ }, 'i' }, 3162 { { 27 /* op2p1 */ }, 'i' } 3163}; 3164 3165static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { 3166 { { 31 /* soffset */ }, 'i' } 3167}; 3168 3169static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { 3170 { { 4 /* ars */ }, 'i' } 3171}; 3172 3173static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { 3174 { { 6 /* art */ }, 'o' }, 3175 { { 4 /* ars */ }, 'i' }, 3176 { { 20 /* uimm8x2 */ }, 'i' } 3177}; 3178 3179static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { 3180 { { 6 /* art */ }, 'o' }, 3181 { { 4 /* ars */ }, 'i' }, 3182 { { 20 /* uimm8x2 */ }, 'i' } 3183}; 3184 3185static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { 3186 { { 6 /* art */ }, 'o' }, 3187 { { 4 /* ars */ }, 'i' }, 3188 { { 21 /* uimm8x4 */ }, 'i' } 3189}; 3190 3191static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { 3192 { { 6 /* art */ }, 'o' }, 3193 { { 32 /* uimm16x4 */ }, 'i' } 3194}; 3195 3196static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { 3197 { { STATE_LITBADDR }, 'i' }, 3198 { { STATE_LITBEN }, 'i' } 3199}; 3200 3201static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { 3202 { { 6 /* art */ }, 'o' }, 3203 { { 4 /* ars */ }, 'i' }, 3204 { { 19 /* uimm8 */ }, 'i' } 3205}; 3206 3207static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { 3208 { { 4 /* ars */ }, 'i' }, 3209 { { 29 /* ulabel8 */ }, 'i' } 3210}; 3211 3212static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { 3213 { { STATE_LBEG }, 'o' }, 3214 { { STATE_LEND }, 'o' }, 3215 { { STATE_LCOUNT }, 'o' } 3216}; 3217 3218static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { 3219 { { 4 /* ars */ }, 'i' }, 3220 { { 29 /* ulabel8 */ }, 'i' } 3221}; 3222 3223static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { 3224 { { STATE_LBEG }, 'o' }, 3225 { { STATE_LEND }, 'o' }, 3226 { { STATE_LCOUNT }, 'o' } 3227}; 3228 3229static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { 3230 { { 6 /* art */ }, 'o' }, 3231 { { 25 /* simm12b */ }, 'i' } 3232}; 3233 3234static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { 3235 { { 3 /* arr */ }, 'm' }, 3236 { { 4 /* ars */ }, 'i' }, 3237 { { 6 /* art */ }, 'i' } 3238}; 3239 3240static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { 3241 { { 3 /* arr */ }, 'o' }, 3242 { { 6 /* art */ }, 'i' } 3243}; 3244 3245static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { 3246 { { 5 /* *ars_invisible */ }, 'i' } 3247}; 3248 3249static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { 3250 { { 6 /* art */ }, 'i' }, 3251 { { 4 /* ars */ }, 'i' }, 3252 { { 20 /* uimm8x2 */ }, 'i' } 3253}; 3254 3255static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { 3256 { { 6 /* art */ }, 'i' }, 3257 { { 4 /* ars */ }, 'i' }, 3258 { { 21 /* uimm8x4 */ }, 'i' } 3259}; 3260 3261static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { 3262 { { 6 /* art */ }, 'i' }, 3263 { { 4 /* ars */ }, 'i' }, 3264 { { 19 /* uimm8 */ }, 'i' } 3265}; 3266 3267static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { 3268 { { 4 /* ars */ }, 'i' } 3269}; 3270 3271static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { 3272 { { STATE_SAR }, 'o' } 3273}; 3274 3275static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { 3276 { { 66 /* sas */ }, 'i' } 3277}; 3278 3279static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { 3280 { { STATE_SAR }, 'o' } 3281}; 3282 3283static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { 3284 { { 3 /* arr */ }, 'o' }, 3285 { { 4 /* ars */ }, 'i' } 3286}; 3287 3288static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { 3289 { { STATE_SAR }, 'i' } 3290}; 3291 3292static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { 3293 { { 3 /* arr */ }, 'o' }, 3294 { { 4 /* ars */ }, 'i' }, 3295 { { 6 /* art */ }, 'i' } 3296}; 3297 3298static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { 3299 { { STATE_SAR }, 'i' } 3300}; 3301 3302static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { 3303 { { 3 /* arr */ }, 'o' }, 3304 { { 6 /* art */ }, 'i' } 3305}; 3306 3307static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { 3308 { { STATE_SAR }, 'i' } 3309}; 3310 3311static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { 3312 { { 3 /* arr */ }, 'o' }, 3313 { { 4 /* ars */ }, 'i' }, 3314 { { 26 /* msalp32 */ }, 'i' } 3315}; 3316 3317static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { 3318 { { 3 /* arr */ }, 'o' }, 3319 { { 6 /* art */ }, 'i' }, 3320 { { 64 /* sargt */ }, 'i' } 3321}; 3322 3323static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { 3324 { { 3 /* arr */ }, 'o' }, 3325 { { 6 /* art */ }, 'i' }, 3326 { { 50 /* s */ }, 'i' } 3327}; 3328 3329static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { 3330 { { STATE_XTSYNC }, 'i' } 3331}; 3332 3333static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { 3334 { { 6 /* art */ }, 'o' }, 3335 { { 50 /* s */ }, 'i' } 3336}; 3337 3338static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { 3339 { { STATE_PSWOE }, 'i' }, 3340 { { STATE_PSCALLINC }, 'i' }, 3341 { { STATE_PSOWB }, 'i' }, 3342 { { STATE_PSRING }, 'i' }, 3343 { { STATE_PSUM }, 'i' }, 3344 { { STATE_PSEXCM }, 'i' }, 3345 { { STATE_PSINTLEVEL }, 'm' } 3346}; 3347 3348static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { 3349 { { 6 /* art */ }, 'o' } 3350}; 3351 3352static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { 3353 { { STATE_LEND }, 'i' } 3354}; 3355 3356static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { 3357 { { 6 /* art */ }, 'i' } 3358}; 3359 3360static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { 3361 { { STATE_LEND }, 'o' } 3362}; 3363 3364static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { 3365 { { 6 /* art */ }, 'm' } 3366}; 3367 3368static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { 3369 { { STATE_LEND }, 'm' } 3370}; 3371 3372static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { 3373 { { 6 /* art */ }, 'o' } 3374}; 3375 3376static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { 3377 { { STATE_LCOUNT }, 'i' } 3378}; 3379 3380static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { 3381 { { 6 /* art */ }, 'i' } 3382}; 3383 3384static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { 3385 { { STATE_XTSYNC }, 'o' }, 3386 { { STATE_LCOUNT }, 'o' } 3387}; 3388 3389static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { 3390 { { 6 /* art */ }, 'm' } 3391}; 3392 3393static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { 3394 { { STATE_XTSYNC }, 'o' }, 3395 { { STATE_LCOUNT }, 'm' } 3396}; 3397 3398static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { 3399 { { 6 /* art */ }, 'o' } 3400}; 3401 3402static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { 3403 { { STATE_LBEG }, 'i' } 3404}; 3405 3406static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { 3407 { { 6 /* art */ }, 'i' } 3408}; 3409 3410static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { 3411 { { STATE_LBEG }, 'o' } 3412}; 3413 3414static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { 3415 { { 6 /* art */ }, 'm' } 3416}; 3417 3418static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { 3419 { { STATE_LBEG }, 'm' } 3420}; 3421 3422static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { 3423 { { 6 /* art */ }, 'o' } 3424}; 3425 3426static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { 3427 { { STATE_SAR }, 'i' } 3428}; 3429 3430static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { 3431 { { 6 /* art */ }, 'i' } 3432}; 3433 3434static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { 3435 { { STATE_SAR }, 'o' }, 3436 { { STATE_XTSYNC }, 'o' } 3437}; 3438 3439static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { 3440 { { 6 /* art */ }, 'm' } 3441}; 3442 3443static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { 3444 { { STATE_SAR }, 'm' } 3445}; 3446 3447static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { 3448 { { 6 /* art */ }, 'o' } 3449}; 3450 3451static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { 3452 { { STATE_LITBADDR }, 'i' }, 3453 { { STATE_LITBEN }, 'i' } 3454}; 3455 3456static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { 3457 { { 6 /* art */ }, 'i' } 3458}; 3459 3460static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { 3461 { { STATE_LITBADDR }, 'o' }, 3462 { { STATE_LITBEN }, 'o' } 3463}; 3464 3465static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { 3466 { { 6 /* art */ }, 'm' } 3467}; 3468 3469static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { 3470 { { STATE_LITBADDR }, 'm' }, 3471 { { STATE_LITBEN }, 'm' } 3472}; 3473 3474static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { 3475 { { 6 /* art */ }, 'o' } 3476}; 3477 3478static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { 3479 { { STATE_PSEXCM }, 'i' }, 3480 { { STATE_PSRING }, 'i' } 3481}; 3482 3483static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { 3484 { { 6 /* art */ }, 'o' } 3485}; 3486 3487static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { 3488 { { STATE_PSEXCM }, 'i' }, 3489 { { STATE_PSRING }, 'i' } 3490}; 3491 3492static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { 3493 { { 6 /* art */ }, 'o' } 3494}; 3495 3496static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { 3497 { { STATE_PSWOE }, 'i' }, 3498 { { STATE_PSCALLINC }, 'i' }, 3499 { { STATE_PSOWB }, 'i' }, 3500 { { STATE_PSRING }, 'i' }, 3501 { { STATE_PSUM }, 'i' }, 3502 { { STATE_PSEXCM }, 'i' }, 3503 { { STATE_PSINTLEVEL }, 'i' } 3504}; 3505 3506static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { 3507 { { 6 /* art */ }, 'i' } 3508}; 3509 3510static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { 3511 { { STATE_PSWOE }, 'o' }, 3512 { { STATE_PSCALLINC }, 'o' }, 3513 { { STATE_PSOWB }, 'o' }, 3514 { { STATE_PSRING }, 'm' }, 3515 { { STATE_PSUM }, 'o' }, 3516 { { STATE_PSEXCM }, 'm' }, 3517 { { STATE_PSINTLEVEL }, 'o' } 3518}; 3519 3520static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { 3521 { { 6 /* art */ }, 'm' } 3522}; 3523 3524static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { 3525 { { STATE_PSWOE }, 'm' }, 3526 { { STATE_PSCALLINC }, 'm' }, 3527 { { STATE_PSOWB }, 'm' }, 3528 { { STATE_PSRING }, 'm' }, 3529 { { STATE_PSUM }, 'm' }, 3530 { { STATE_PSEXCM }, 'm' }, 3531 { { STATE_PSINTLEVEL }, 'm' } 3532}; 3533 3534static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { 3535 { { 6 /* art */ }, 'o' } 3536}; 3537 3538static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { 3539 { { STATE_PSEXCM }, 'i' }, 3540 { { STATE_PSRING }, 'i' }, 3541 { { STATE_EPC1 }, 'i' } 3542}; 3543 3544static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { 3545 { { 6 /* art */ }, 'i' } 3546}; 3547 3548static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { 3549 { { STATE_PSEXCM }, 'i' }, 3550 { { STATE_PSRING }, 'i' }, 3551 { { STATE_EPC1 }, 'o' } 3552}; 3553 3554static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { 3555 { { 6 /* art */ }, 'm' } 3556}; 3557 3558static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { 3559 { { STATE_PSEXCM }, 'i' }, 3560 { { STATE_PSRING }, 'i' }, 3561 { { STATE_EPC1 }, 'm' } 3562}; 3563 3564static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { 3565 { { 6 /* art */ }, 'o' } 3566}; 3567 3568static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { 3569 { { STATE_PSEXCM }, 'i' }, 3570 { { STATE_PSRING }, 'i' }, 3571 { { STATE_EXCSAVE1 }, 'i' } 3572}; 3573 3574static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { 3575 { { 6 /* art */ }, 'i' } 3576}; 3577 3578static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { 3579 { { STATE_PSEXCM }, 'i' }, 3580 { { STATE_PSRING }, 'i' }, 3581 { { STATE_EXCSAVE1 }, 'o' } 3582}; 3583 3584static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { 3585 { { 6 /* art */ }, 'm' } 3586}; 3587 3588static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { 3589 { { STATE_PSEXCM }, 'i' }, 3590 { { STATE_PSRING }, 'i' }, 3591 { { STATE_EXCSAVE1 }, 'm' } 3592}; 3593 3594static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { 3595 { { 6 /* art */ }, 'o' } 3596}; 3597 3598static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { 3599 { { STATE_PSEXCM }, 'i' }, 3600 { { STATE_PSRING }, 'i' }, 3601 { { STATE_EPC2 }, 'i' } 3602}; 3603 3604static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { 3605 { { 6 /* art */ }, 'i' } 3606}; 3607 3608static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { 3609 { { STATE_PSEXCM }, 'i' }, 3610 { { STATE_PSRING }, 'i' }, 3611 { { STATE_EPC2 }, 'o' } 3612}; 3613 3614static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { 3615 { { 6 /* art */ }, 'm' } 3616}; 3617 3618static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { 3619 { { STATE_PSEXCM }, 'i' }, 3620 { { STATE_PSRING }, 'i' }, 3621 { { STATE_EPC2 }, 'm' } 3622}; 3623 3624static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { 3625 { { 6 /* art */ }, 'o' } 3626}; 3627 3628static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { 3629 { { STATE_PSEXCM }, 'i' }, 3630 { { STATE_PSRING }, 'i' }, 3631 { { STATE_EXCSAVE2 }, 'i' } 3632}; 3633 3634static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { 3635 { { 6 /* art */ }, 'i' } 3636}; 3637 3638static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { 3639 { { STATE_PSEXCM }, 'i' }, 3640 { { STATE_PSRING }, 'i' }, 3641 { { STATE_EXCSAVE2 }, 'o' } 3642}; 3643 3644static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { 3645 { { 6 /* art */ }, 'm' } 3646}; 3647 3648static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { 3649 { { STATE_PSEXCM }, 'i' }, 3650 { { STATE_PSRING }, 'i' }, 3651 { { STATE_EXCSAVE2 }, 'm' } 3652}; 3653 3654static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { 3655 { { 6 /* art */ }, 'o' } 3656}; 3657 3658static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { 3659 { { STATE_PSEXCM }, 'i' }, 3660 { { STATE_PSRING }, 'i' }, 3661 { { STATE_EPC3 }, 'i' } 3662}; 3663 3664static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { 3665 { { 6 /* art */ }, 'i' } 3666}; 3667 3668static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { 3669 { { STATE_PSEXCM }, 'i' }, 3670 { { STATE_PSRING }, 'i' }, 3671 { { STATE_EPC3 }, 'o' } 3672}; 3673 3674static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { 3675 { { 6 /* art */ }, 'm' } 3676}; 3677 3678static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { 3679 { { STATE_PSEXCM }, 'i' }, 3680 { { STATE_PSRING }, 'i' }, 3681 { { STATE_EPC3 }, 'm' } 3682}; 3683 3684static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { 3685 { { 6 /* art */ }, 'o' } 3686}; 3687 3688static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { 3689 { { STATE_PSEXCM }, 'i' }, 3690 { { STATE_PSRING }, 'i' }, 3691 { { STATE_EXCSAVE3 }, 'i' } 3692}; 3693 3694static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { 3695 { { 6 /* art */ }, 'i' } 3696}; 3697 3698static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { 3699 { { STATE_PSEXCM }, 'i' }, 3700 { { STATE_PSRING }, 'i' }, 3701 { { STATE_EXCSAVE3 }, 'o' } 3702}; 3703 3704static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { 3705 { { 6 /* art */ }, 'm' } 3706}; 3707 3708static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { 3709 { { STATE_PSEXCM }, 'i' }, 3710 { { STATE_PSRING }, 'i' }, 3711 { { STATE_EXCSAVE3 }, 'm' } 3712}; 3713 3714static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { 3715 { { 6 /* art */ }, 'o' } 3716}; 3717 3718static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { 3719 { { STATE_PSEXCM }, 'i' }, 3720 { { STATE_PSRING }, 'i' }, 3721 { { STATE_EPC4 }, 'i' } 3722}; 3723 3724static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { 3725 { { 6 /* art */ }, 'i' } 3726}; 3727 3728static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { 3729 { { STATE_PSEXCM }, 'i' }, 3730 { { STATE_PSRING }, 'i' }, 3731 { { STATE_EPC4 }, 'o' } 3732}; 3733 3734static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { 3735 { { 6 /* art */ }, 'm' } 3736}; 3737 3738static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { 3739 { { STATE_PSEXCM }, 'i' }, 3740 { { STATE_PSRING }, 'i' }, 3741 { { STATE_EPC4 }, 'm' } 3742}; 3743 3744static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { 3745 { { 6 /* art */ }, 'o' } 3746}; 3747 3748static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { 3749 { { STATE_PSEXCM }, 'i' }, 3750 { { STATE_PSRING }, 'i' }, 3751 { { STATE_EXCSAVE4 }, 'i' } 3752}; 3753 3754static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { 3755 { { 6 /* art */ }, 'i' } 3756}; 3757 3758static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { 3759 { { STATE_PSEXCM }, 'i' }, 3760 { { STATE_PSRING }, 'i' }, 3761 { { STATE_EXCSAVE4 }, 'o' } 3762}; 3763 3764static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { 3765 { { 6 /* art */ }, 'm' } 3766}; 3767 3768static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { 3769 { { STATE_PSEXCM }, 'i' }, 3770 { { STATE_PSRING }, 'i' }, 3771 { { STATE_EXCSAVE4 }, 'm' } 3772}; 3773 3774static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { 3775 { { 6 /* art */ }, 'o' } 3776}; 3777 3778static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { 3779 { { STATE_PSEXCM }, 'i' }, 3780 { { STATE_PSRING }, 'i' }, 3781 { { STATE_EPC5 }, 'i' } 3782}; 3783 3784static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { 3785 { { 6 /* art */ }, 'i' } 3786}; 3787 3788static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { 3789 { { STATE_PSEXCM }, 'i' }, 3790 { { STATE_PSRING }, 'i' }, 3791 { { STATE_EPC5 }, 'o' } 3792}; 3793 3794static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { 3795 { { 6 /* art */ }, 'm' } 3796}; 3797 3798static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { 3799 { { STATE_PSEXCM }, 'i' }, 3800 { { STATE_PSRING }, 'i' }, 3801 { { STATE_EPC5 }, 'm' } 3802}; 3803 3804static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { 3805 { { 6 /* art */ }, 'o' } 3806}; 3807 3808static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { 3809 { { STATE_PSEXCM }, 'i' }, 3810 { { STATE_PSRING }, 'i' }, 3811 { { STATE_EXCSAVE5 }, 'i' } 3812}; 3813 3814static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { 3815 { { 6 /* art */ }, 'i' } 3816}; 3817 3818static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { 3819 { { STATE_PSEXCM }, 'i' }, 3820 { { STATE_PSRING }, 'i' }, 3821 { { STATE_EXCSAVE5 }, 'o' } 3822}; 3823 3824static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { 3825 { { 6 /* art */ }, 'm' } 3826}; 3827 3828static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { 3829 { { STATE_PSEXCM }, 'i' }, 3830 { { STATE_PSRING }, 'i' }, 3831 { { STATE_EXCSAVE5 }, 'm' } 3832}; 3833 3834static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { 3835 { { 6 /* art */ }, 'o' } 3836}; 3837 3838static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { 3839 { { STATE_PSEXCM }, 'i' }, 3840 { { STATE_PSRING }, 'i' }, 3841 { { STATE_EPC6 }, 'i' } 3842}; 3843 3844static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { 3845 { { 6 /* art */ }, 'i' } 3846}; 3847 3848static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { 3849 { { STATE_PSEXCM }, 'i' }, 3850 { { STATE_PSRING }, 'i' }, 3851 { { STATE_EPC6 }, 'o' } 3852}; 3853 3854static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { 3855 { { 6 /* art */ }, 'm' } 3856}; 3857 3858static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { 3859 { { STATE_PSEXCM }, 'i' }, 3860 { { STATE_PSRING }, 'i' }, 3861 { { STATE_EPC6 }, 'm' } 3862}; 3863 3864static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { 3865 { { 6 /* art */ }, 'o' } 3866}; 3867 3868static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { 3869 { { STATE_PSEXCM }, 'i' }, 3870 { { STATE_PSRING }, 'i' }, 3871 { { STATE_EXCSAVE6 }, 'i' } 3872}; 3873 3874static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { 3875 { { 6 /* art */ }, 'i' } 3876}; 3877 3878static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { 3879 { { STATE_PSEXCM }, 'i' }, 3880 { { STATE_PSRING }, 'i' }, 3881 { { STATE_EXCSAVE6 }, 'o' } 3882}; 3883 3884static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { 3885 { { 6 /* art */ }, 'm' } 3886}; 3887 3888static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { 3889 { { STATE_PSEXCM }, 'i' }, 3890 { { STATE_PSRING }, 'i' }, 3891 { { STATE_EXCSAVE6 }, 'm' } 3892}; 3893 3894static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { 3895 { { 6 /* art */ }, 'o' } 3896}; 3897 3898static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { 3899 { { STATE_PSEXCM }, 'i' }, 3900 { { STATE_PSRING }, 'i' }, 3901 { { STATE_EPC7 }, 'i' } 3902}; 3903 3904static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { 3905 { { 6 /* art */ }, 'i' } 3906}; 3907 3908static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { 3909 { { STATE_PSEXCM }, 'i' }, 3910 { { STATE_PSRING }, 'i' }, 3911 { { STATE_EPC7 }, 'o' } 3912}; 3913 3914static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { 3915 { { 6 /* art */ }, 'm' } 3916}; 3917 3918static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { 3919 { { STATE_PSEXCM }, 'i' }, 3920 { { STATE_PSRING }, 'i' }, 3921 { { STATE_EPC7 }, 'm' } 3922}; 3923 3924static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { 3925 { { 6 /* art */ }, 'o' } 3926}; 3927 3928static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { 3929 { { STATE_PSEXCM }, 'i' }, 3930 { { STATE_PSRING }, 'i' }, 3931 { { STATE_EXCSAVE7 }, 'i' } 3932}; 3933 3934static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { 3935 { { 6 /* art */ }, 'i' } 3936}; 3937 3938static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { 3939 { { STATE_PSEXCM }, 'i' }, 3940 { { STATE_PSRING }, 'i' }, 3941 { { STATE_EXCSAVE7 }, 'o' } 3942}; 3943 3944static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { 3945 { { 6 /* art */ }, 'm' } 3946}; 3947 3948static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { 3949 { { STATE_PSEXCM }, 'i' }, 3950 { { STATE_PSRING }, 'i' }, 3951 { { STATE_EXCSAVE7 }, 'm' } 3952}; 3953 3954static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { 3955 { { 6 /* art */ }, 'o' } 3956}; 3957 3958static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { 3959 { { STATE_PSEXCM }, 'i' }, 3960 { { STATE_PSRING }, 'i' }, 3961 { { STATE_EPS2 }, 'i' } 3962}; 3963 3964static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { 3965 { { 6 /* art */ }, 'i' } 3966}; 3967 3968static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { 3969 { { STATE_PSEXCM }, 'i' }, 3970 { { STATE_PSRING }, 'i' }, 3971 { { STATE_EPS2 }, 'o' } 3972}; 3973 3974static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { 3975 { { 6 /* art */ }, 'm' } 3976}; 3977 3978static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { 3979 { { STATE_PSEXCM }, 'i' }, 3980 { { STATE_PSRING }, 'i' }, 3981 { { STATE_EPS2 }, 'm' } 3982}; 3983 3984static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { 3985 { { 6 /* art */ }, 'o' } 3986}; 3987 3988static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { 3989 { { STATE_PSEXCM }, 'i' }, 3990 { { STATE_PSRING }, 'i' }, 3991 { { STATE_EPS3 }, 'i' } 3992}; 3993 3994static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { 3995 { { 6 /* art */ }, 'i' } 3996}; 3997 3998static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { 3999 { { STATE_PSEXCM }, 'i' }, 4000 { { STATE_PSRING }, 'i' }, 4001 { { STATE_EPS3 }, 'o' } 4002}; 4003 4004static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { 4005 { { 6 /* art */ }, 'm' } 4006}; 4007 4008static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { 4009 { { STATE_PSEXCM }, 'i' }, 4010 { { STATE_PSRING }, 'i' }, 4011 { { STATE_EPS3 }, 'm' } 4012}; 4013 4014static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { 4015 { { 6 /* art */ }, 'o' } 4016}; 4017 4018static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { 4019 { { STATE_PSEXCM }, 'i' }, 4020 { { STATE_PSRING }, 'i' }, 4021 { { STATE_EPS4 }, 'i' } 4022}; 4023 4024static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { 4025 { { 6 /* art */ }, 'i' } 4026}; 4027 4028static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { 4029 { { STATE_PSEXCM }, 'i' }, 4030 { { STATE_PSRING }, 'i' }, 4031 { { STATE_EPS4 }, 'o' } 4032}; 4033 4034static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { 4035 { { 6 /* art */ }, 'm' } 4036}; 4037 4038static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { 4039 { { STATE_PSEXCM }, 'i' }, 4040 { { STATE_PSRING }, 'i' }, 4041 { { STATE_EPS4 }, 'm' } 4042}; 4043 4044static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { 4045 { { 6 /* art */ }, 'o' } 4046}; 4047 4048static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { 4049 { { STATE_PSEXCM }, 'i' }, 4050 { { STATE_PSRING }, 'i' }, 4051 { { STATE_EPS5 }, 'i' } 4052}; 4053 4054static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { 4055 { { 6 /* art */ }, 'i' } 4056}; 4057 4058static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { 4059 { { STATE_PSEXCM }, 'i' }, 4060 { { STATE_PSRING }, 'i' }, 4061 { { STATE_EPS5 }, 'o' } 4062}; 4063 4064static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { 4065 { { 6 /* art */ }, 'm' } 4066}; 4067 4068static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { 4069 { { STATE_PSEXCM }, 'i' }, 4070 { { STATE_PSRING }, 'i' }, 4071 { { STATE_EPS5 }, 'm' } 4072}; 4073 4074static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { 4075 { { 6 /* art */ }, 'o' } 4076}; 4077 4078static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { 4079 { { STATE_PSEXCM }, 'i' }, 4080 { { STATE_PSRING }, 'i' }, 4081 { { STATE_EPS6 }, 'i' } 4082}; 4083 4084static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { 4085 { { 6 /* art */ }, 'i' } 4086}; 4087 4088static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { 4089 { { STATE_PSEXCM }, 'i' }, 4090 { { STATE_PSRING }, 'i' }, 4091 { { STATE_EPS6 }, 'o' } 4092}; 4093 4094static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { 4095 { { 6 /* art */ }, 'm' } 4096}; 4097 4098static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { 4099 { { STATE_PSEXCM }, 'i' }, 4100 { { STATE_PSRING }, 'i' }, 4101 { { STATE_EPS6 }, 'm' } 4102}; 4103 4104static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { 4105 { { 6 /* art */ }, 'o' } 4106}; 4107 4108static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { 4109 { { STATE_PSEXCM }, 'i' }, 4110 { { STATE_PSRING }, 'i' }, 4111 { { STATE_EPS7 }, 'i' } 4112}; 4113 4114static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { 4115 { { 6 /* art */ }, 'i' } 4116}; 4117 4118static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { 4119 { { STATE_PSEXCM }, 'i' }, 4120 { { STATE_PSRING }, 'i' }, 4121 { { STATE_EPS7 }, 'o' } 4122}; 4123 4124static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { 4125 { { 6 /* art */ }, 'm' } 4126}; 4127 4128static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { 4129 { { STATE_PSEXCM }, 'i' }, 4130 { { STATE_PSRING }, 'i' }, 4131 { { STATE_EPS7 }, 'm' } 4132}; 4133 4134static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { 4135 { { 6 /* art */ }, 'o' } 4136}; 4137 4138static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { 4139 { { STATE_PSEXCM }, 'i' }, 4140 { { STATE_PSRING }, 'i' }, 4141 { { STATE_EXCVADDR }, 'i' } 4142}; 4143 4144static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { 4145 { { 6 /* art */ }, 'i' } 4146}; 4147 4148static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { 4149 { { STATE_PSEXCM }, 'i' }, 4150 { { STATE_PSRING }, 'i' }, 4151 { { STATE_EXCVADDR }, 'o' } 4152}; 4153 4154static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { 4155 { { 6 /* art */ }, 'm' } 4156}; 4157 4158static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { 4159 { { STATE_PSEXCM }, 'i' }, 4160 { { STATE_PSRING }, 'i' }, 4161 { { STATE_EXCVADDR }, 'm' } 4162}; 4163 4164static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { 4165 { { 6 /* art */ }, 'o' } 4166}; 4167 4168static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { 4169 { { STATE_PSEXCM }, 'i' }, 4170 { { STATE_PSRING }, 'i' }, 4171 { { STATE_DEPC }, 'i' } 4172}; 4173 4174static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { 4175 { { 6 /* art */ }, 'i' } 4176}; 4177 4178static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { 4179 { { STATE_PSEXCM }, 'i' }, 4180 { { STATE_PSRING }, 'i' }, 4181 { { STATE_DEPC }, 'o' } 4182}; 4183 4184static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { 4185 { { 6 /* art */ }, 'm' } 4186}; 4187 4188static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { 4189 { { STATE_PSEXCM }, 'i' }, 4190 { { STATE_PSRING }, 'i' }, 4191 { { STATE_DEPC }, 'm' } 4192}; 4193 4194static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { 4195 { { 6 /* art */ }, 'o' } 4196}; 4197 4198static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { 4199 { { STATE_PSEXCM }, 'i' }, 4200 { { STATE_PSRING }, 'i' }, 4201 { { STATE_EXCCAUSE }, 'i' }, 4202 { { STATE_XTSYNC }, 'i' } 4203}; 4204 4205static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { 4206 { { 6 /* art */ }, 'i' } 4207}; 4208 4209static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { 4210 { { STATE_PSEXCM }, 'i' }, 4211 { { STATE_PSRING }, 'i' }, 4212 { { STATE_EXCCAUSE }, 'o' } 4213}; 4214 4215static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { 4216 { { 6 /* art */ }, 'm' } 4217}; 4218 4219static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { 4220 { { STATE_PSEXCM }, 'i' }, 4221 { { STATE_PSRING }, 'i' }, 4222 { { STATE_EXCCAUSE }, 'm' } 4223}; 4224 4225static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { 4226 { { 6 /* art */ }, 'o' } 4227}; 4228 4229static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { 4230 { { STATE_PSEXCM }, 'i' }, 4231 { { STATE_PSRING }, 'i' }, 4232 { { STATE_MISC0 }, 'i' } 4233}; 4234 4235static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { 4236 { { 6 /* art */ }, 'i' } 4237}; 4238 4239static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { 4240 { { STATE_PSEXCM }, 'i' }, 4241 { { STATE_PSRING }, 'i' }, 4242 { { STATE_MISC0 }, 'o' } 4243}; 4244 4245static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { 4246 { { 6 /* art */ }, 'm' } 4247}; 4248 4249static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { 4250 { { STATE_PSEXCM }, 'i' }, 4251 { { STATE_PSRING }, 'i' }, 4252 { { STATE_MISC0 }, 'm' } 4253}; 4254 4255static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { 4256 { { 6 /* art */ }, 'o' } 4257}; 4258 4259static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { 4260 { { STATE_PSEXCM }, 'i' }, 4261 { { STATE_PSRING }, 'i' }, 4262 { { STATE_MISC1 }, 'i' } 4263}; 4264 4265static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { 4266 { { 6 /* art */ }, 'i' } 4267}; 4268 4269static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { 4270 { { STATE_PSEXCM }, 'i' }, 4271 { { STATE_PSRING }, 'i' }, 4272 { { STATE_MISC1 }, 'o' } 4273}; 4274 4275static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { 4276 { { 6 /* art */ }, 'm' } 4277}; 4278 4279static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { 4280 { { STATE_PSEXCM }, 'i' }, 4281 { { STATE_PSRING }, 'i' }, 4282 { { STATE_MISC1 }, 'm' } 4283}; 4284 4285static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { 4286 { { 6 /* art */ }, 'o' } 4287}; 4288 4289static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { 4290 { { STATE_PSEXCM }, 'i' }, 4291 { { STATE_PSRING }, 'i' } 4292}; 4293 4294static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { 4295 { { 6 /* art */ }, 'o' } 4296}; 4297 4298static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { 4299 { { STATE_PSEXCM }, 'i' }, 4300 { { STATE_PSRING }, 'i' }, 4301 { { STATE_VECBASE }, 'i' } 4302}; 4303 4304static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { 4305 { { 6 /* art */ }, 'i' } 4306}; 4307 4308static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { 4309 { { STATE_PSEXCM }, 'i' }, 4310 { { STATE_PSRING }, 'i' }, 4311 { { STATE_VECBASE }, 'o' } 4312}; 4313 4314static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { 4315 { { 6 /* art */ }, 'm' } 4316}; 4317 4318static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { 4319 { { STATE_PSEXCM }, 'i' }, 4320 { { STATE_PSRING }, 'i' }, 4321 { { STATE_VECBASE }, 'm' } 4322}; 4323 4324static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { 4325 { { 4 /* ars */ }, 'i' }, 4326 { { 6 /* art */ }, 'i' } 4327}; 4328 4329static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { 4330 { { STATE_ACC }, 'o' } 4331}; 4332 4333static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { 4334 { { 4 /* ars */ }, 'i' }, 4335 { { 34 /* my */ }, 'i' } 4336}; 4337 4338static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { 4339 { { STATE_ACC }, 'o' } 4340}; 4341 4342static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { 4343 { { 33 /* mx */ }, 'i' }, 4344 { { 6 /* art */ }, 'i' } 4345}; 4346 4347static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { 4348 { { STATE_ACC }, 'o' } 4349}; 4350 4351static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { 4352 { { 33 /* mx */ }, 'i' }, 4353 { { 34 /* my */ }, 'i' } 4354}; 4355 4356static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { 4357 { { STATE_ACC }, 'o' } 4358}; 4359 4360static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { 4361 { { 4 /* ars */ }, 'i' }, 4362 { { 6 /* art */ }, 'i' } 4363}; 4364 4365static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { 4366 { { STATE_ACC }, 'm' } 4367}; 4368 4369static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { 4370 { { 4 /* ars */ }, 'i' }, 4371 { { 34 /* my */ }, 'i' } 4372}; 4373 4374static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { 4375 { { STATE_ACC }, 'm' } 4376}; 4377 4378static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { 4379 { { 33 /* mx */ }, 'i' }, 4380 { { 6 /* art */ }, 'i' } 4381}; 4382 4383static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { 4384 { { STATE_ACC }, 'm' } 4385}; 4386 4387static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { 4388 { { 33 /* mx */ }, 'i' }, 4389 { { 34 /* my */ }, 'i' } 4390}; 4391 4392static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { 4393 { { STATE_ACC }, 'm' } 4394}; 4395 4396static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { 4397 { { 35 /* mw */ }, 'o' }, 4398 { { 4 /* ars */ }, 'm' }, 4399 { { 33 /* mx */ }, 'i' }, 4400 { { 6 /* art */ }, 'i' } 4401}; 4402 4403static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { 4404 { { STATE_ACC }, 'm' } 4405}; 4406 4407static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { 4408 { { 35 /* mw */ }, 'o' }, 4409 { { 4 /* ars */ }, 'm' }, 4410 { { 33 /* mx */ }, 'i' }, 4411 { { 34 /* my */ }, 'i' } 4412}; 4413 4414static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { 4415 { { STATE_ACC }, 'm' } 4416}; 4417 4418static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { 4419 { { 35 /* mw */ }, 'o' }, 4420 { { 4 /* ars */ }, 'm' } 4421}; 4422 4423static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { 4424 { { 3 /* arr */ }, 'o' }, 4425 { { 4 /* ars */ }, 'i' }, 4426 { { 6 /* art */ }, 'i' } 4427}; 4428 4429static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { 4430 { { 6 /* art */ }, 'o' }, 4431 { { 36 /* mr0 */ }, 'i' } 4432}; 4433 4434static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { 4435 { { 6 /* art */ }, 'i' }, 4436 { { 36 /* mr0 */ }, 'o' } 4437}; 4438 4439static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { 4440 { { 6 /* art */ }, 'm' }, 4441 { { 36 /* mr0 */ }, 'm' } 4442}; 4443 4444static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { 4445 { { 6 /* art */ }, 'o' }, 4446 { { 37 /* mr1 */ }, 'i' } 4447}; 4448 4449static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { 4450 { { 6 /* art */ }, 'i' }, 4451 { { 37 /* mr1 */ }, 'o' } 4452}; 4453 4454static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { 4455 { { 6 /* art */ }, 'm' }, 4456 { { 37 /* mr1 */ }, 'm' } 4457}; 4458 4459static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { 4460 { { 6 /* art */ }, 'o' }, 4461 { { 38 /* mr2 */ }, 'i' } 4462}; 4463 4464static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { 4465 { { 6 /* art */ }, 'i' }, 4466 { { 38 /* mr2 */ }, 'o' } 4467}; 4468 4469static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { 4470 { { 6 /* art */ }, 'm' }, 4471 { { 38 /* mr2 */ }, 'm' } 4472}; 4473 4474static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { 4475 { { 6 /* art */ }, 'o' }, 4476 { { 39 /* mr3 */ }, 'i' } 4477}; 4478 4479static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { 4480 { { 6 /* art */ }, 'i' }, 4481 { { 39 /* mr3 */ }, 'o' } 4482}; 4483 4484static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { 4485 { { 6 /* art */ }, 'm' }, 4486 { { 39 /* mr3 */ }, 'm' } 4487}; 4488 4489static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { 4490 { { 6 /* art */ }, 'o' } 4491}; 4492 4493static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { 4494 { { STATE_ACC }, 'i' } 4495}; 4496 4497static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { 4498 { { 6 /* art */ }, 'i' } 4499}; 4500 4501static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { 4502 { { STATE_ACC }, 'm' } 4503}; 4504 4505static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { 4506 { { 6 /* art */ }, 'm' } 4507}; 4508 4509static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { 4510 { { STATE_ACC }, 'm' } 4511}; 4512 4513static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { 4514 { { 6 /* art */ }, 'o' } 4515}; 4516 4517static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { 4518 { { STATE_ACC }, 'i' } 4519}; 4520 4521static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { 4522 { { 6 /* art */ }, 'i' } 4523}; 4524 4525static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { 4526 { { STATE_ACC }, 'm' } 4527}; 4528 4529static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { 4530 { { 6 /* art */ }, 'm' } 4531}; 4532 4533static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { 4534 { { STATE_ACC }, 'm' } 4535}; 4536 4537static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { 4538 { { 50 /* s */ }, 'i' } 4539}; 4540 4541static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { 4542 { { STATE_PSWOE }, 'o' }, 4543 { { STATE_PSCALLINC }, 'o' }, 4544 { { STATE_PSOWB }, 'o' }, 4545 { { STATE_PSRING }, 'm' }, 4546 { { STATE_PSUM }, 'o' }, 4547 { { STATE_PSEXCM }, 'm' }, 4548 { { STATE_PSINTLEVEL }, 'o' }, 4549 { { STATE_EPC1 }, 'i' }, 4550 { { STATE_EPC2 }, 'i' }, 4551 { { STATE_EPC3 }, 'i' }, 4552 { { STATE_EPC4 }, 'i' }, 4553 { { STATE_EPC5 }, 'i' }, 4554 { { STATE_EPC6 }, 'i' }, 4555 { { STATE_EPC7 }, 'i' }, 4556 { { STATE_EPS2 }, 'i' }, 4557 { { STATE_EPS3 }, 'i' }, 4558 { { STATE_EPS4 }, 'i' }, 4559 { { STATE_EPS5 }, 'i' }, 4560 { { STATE_EPS6 }, 'i' }, 4561 { { STATE_EPS7 }, 'i' }, 4562 { { STATE_InOCDMode }, 'm' } 4563}; 4564 4565static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { 4566 { { 50 /* s */ }, 'i' } 4567}; 4568 4569static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { 4570 { { STATE_PSEXCM }, 'i' }, 4571 { { STATE_PSRING }, 'i' }, 4572 { { STATE_PSINTLEVEL }, 'o' } 4573}; 4574 4575static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { 4576 { { 6 /* art */ }, 'o' } 4577}; 4578 4579static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { 4580 { { STATE_PSEXCM }, 'i' }, 4581 { { STATE_PSRING }, 'i' }, 4582 { { STATE_INTERRUPT }, 'i' } 4583}; 4584 4585static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { 4586 { { 6 /* art */ }, 'i' } 4587}; 4588 4589static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { 4590 { { STATE_PSEXCM }, 'i' }, 4591 { { STATE_PSRING }, 'i' }, 4592 { { STATE_XTSYNC }, 'o' }, 4593 { { STATE_INTERRUPT }, 'm' } 4594}; 4595 4596static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { 4597 { { 6 /* art */ }, 'i' } 4598}; 4599 4600static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { 4601 { { STATE_PSEXCM }, 'i' }, 4602 { { STATE_PSRING }, 'i' }, 4603 { { STATE_XTSYNC }, 'o' }, 4604 { { STATE_INTERRUPT }, 'm' } 4605}; 4606 4607static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { 4608 { { 6 /* art */ }, 'o' } 4609}; 4610 4611static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { 4612 { { STATE_PSEXCM }, 'i' }, 4613 { { STATE_PSRING }, 'i' }, 4614 { { STATE_INTENABLE }, 'i' } 4615}; 4616 4617static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { 4618 { { 6 /* art */ }, 'i' } 4619}; 4620 4621static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { 4622 { { STATE_PSEXCM }, 'i' }, 4623 { { STATE_PSRING }, 'i' }, 4624 { { STATE_INTENABLE }, 'o' } 4625}; 4626 4627static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { 4628 { { 6 /* art */ }, 'm' } 4629}; 4630 4631static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { 4632 { { STATE_PSEXCM }, 'i' }, 4633 { { STATE_PSRING }, 'i' }, 4634 { { STATE_INTENABLE }, 'm' } 4635}; 4636 4637static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { 4638 { { 41 /* imms */ }, 'i' }, 4639 { { 40 /* immt */ }, 'i' } 4640}; 4641 4642static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { 4643 { { STATE_PSEXCM }, 'i' }, 4644 { { STATE_PSINTLEVEL }, 'i' } 4645}; 4646 4647static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { 4648 { { 41 /* imms */ }, 'i' } 4649}; 4650 4651static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { 4652 { { STATE_PSEXCM }, 'i' }, 4653 { { STATE_PSINTLEVEL }, 'i' } 4654}; 4655 4656static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { 4657 { { 6 /* art */ }, 'o' } 4658}; 4659 4660static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { 4661 { { STATE_PSEXCM }, 'i' }, 4662 { { STATE_PSRING }, 'i' }, 4663 { { STATE_DBREAKA0 }, 'i' } 4664}; 4665 4666static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { 4667 { { 6 /* art */ }, 'i' } 4668}; 4669 4670static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { 4671 { { STATE_PSEXCM }, 'i' }, 4672 { { STATE_PSRING }, 'i' }, 4673 { { STATE_DBREAKA0 }, 'o' }, 4674 { { STATE_XTSYNC }, 'o' } 4675}; 4676 4677static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { 4678 { { 6 /* art */ }, 'm' } 4679}; 4680 4681static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { 4682 { { STATE_PSEXCM }, 'i' }, 4683 { { STATE_PSRING }, 'i' }, 4684 { { STATE_DBREAKA0 }, 'm' }, 4685 { { STATE_XTSYNC }, 'o' } 4686}; 4687 4688static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { 4689 { { 6 /* art */ }, 'o' } 4690}; 4691 4692static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { 4693 { { STATE_PSEXCM }, 'i' }, 4694 { { STATE_PSRING }, 'i' }, 4695 { { STATE_DBREAKC0 }, 'i' } 4696}; 4697 4698static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { 4699 { { 6 /* art */ }, 'i' } 4700}; 4701 4702static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { 4703 { { STATE_PSEXCM }, 'i' }, 4704 { { STATE_PSRING }, 'i' }, 4705 { { STATE_DBREAKC0 }, 'o' }, 4706 { { STATE_XTSYNC }, 'o' } 4707}; 4708 4709static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { 4710 { { 6 /* art */ }, 'm' } 4711}; 4712 4713static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { 4714 { { STATE_PSEXCM }, 'i' }, 4715 { { STATE_PSRING }, 'i' }, 4716 { { STATE_DBREAKC0 }, 'm' }, 4717 { { STATE_XTSYNC }, 'o' } 4718}; 4719 4720static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { 4721 { { 6 /* art */ }, 'o' } 4722}; 4723 4724static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { 4725 { { STATE_PSEXCM }, 'i' }, 4726 { { STATE_PSRING }, 'i' }, 4727 { { STATE_DBREAKA1 }, 'i' } 4728}; 4729 4730static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { 4731 { { 6 /* art */ }, 'i' } 4732}; 4733 4734static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { 4735 { { STATE_PSEXCM }, 'i' }, 4736 { { STATE_PSRING }, 'i' }, 4737 { { STATE_DBREAKA1 }, 'o' }, 4738 { { STATE_XTSYNC }, 'o' } 4739}; 4740 4741static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { 4742 { { 6 /* art */ }, 'm' } 4743}; 4744 4745static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { 4746 { { STATE_PSEXCM }, 'i' }, 4747 { { STATE_PSRING }, 'i' }, 4748 { { STATE_DBREAKA1 }, 'm' }, 4749 { { STATE_XTSYNC }, 'o' } 4750}; 4751 4752static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { 4753 { { 6 /* art */ }, 'o' } 4754}; 4755 4756static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { 4757 { { STATE_PSEXCM }, 'i' }, 4758 { { STATE_PSRING }, 'i' }, 4759 { { STATE_DBREAKC1 }, 'i' } 4760}; 4761 4762static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { 4763 { { 6 /* art */ }, 'i' } 4764}; 4765 4766static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { 4767 { { STATE_PSEXCM }, 'i' }, 4768 { { STATE_PSRING }, 'i' }, 4769 { { STATE_DBREAKC1 }, 'o' }, 4770 { { STATE_XTSYNC }, 'o' } 4771}; 4772 4773static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { 4774 { { 6 /* art */ }, 'm' } 4775}; 4776 4777static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { 4778 { { STATE_PSEXCM }, 'i' }, 4779 { { STATE_PSRING }, 'i' }, 4780 { { STATE_DBREAKC1 }, 'm' }, 4781 { { STATE_XTSYNC }, 'o' } 4782}; 4783 4784static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { 4785 { { 6 /* art */ }, 'o' } 4786}; 4787 4788static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { 4789 { { STATE_PSEXCM }, 'i' }, 4790 { { STATE_PSRING }, 'i' }, 4791 { { STATE_IBREAKA0 }, 'i' } 4792}; 4793 4794static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { 4795 { { 6 /* art */ }, 'i' } 4796}; 4797 4798static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { 4799 { { STATE_PSEXCM }, 'i' }, 4800 { { STATE_PSRING }, 'i' }, 4801 { { STATE_IBREAKA0 }, 'o' } 4802}; 4803 4804static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { 4805 { { 6 /* art */ }, 'm' } 4806}; 4807 4808static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { 4809 { { STATE_PSEXCM }, 'i' }, 4810 { { STATE_PSRING }, 'i' }, 4811 { { STATE_IBREAKA0 }, 'm' } 4812}; 4813 4814static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { 4815 { { 6 /* art */ }, 'o' } 4816}; 4817 4818static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { 4819 { { STATE_PSEXCM }, 'i' }, 4820 { { STATE_PSRING }, 'i' }, 4821 { { STATE_IBREAKA1 }, 'i' } 4822}; 4823 4824static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { 4825 { { 6 /* art */ }, 'i' } 4826}; 4827 4828static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { 4829 { { STATE_PSEXCM }, 'i' }, 4830 { { STATE_PSRING }, 'i' }, 4831 { { STATE_IBREAKA1 }, 'o' } 4832}; 4833 4834static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { 4835 { { 6 /* art */ }, 'm' } 4836}; 4837 4838static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { 4839 { { STATE_PSEXCM }, 'i' }, 4840 { { STATE_PSRING }, 'i' }, 4841 { { STATE_IBREAKA1 }, 'm' } 4842}; 4843 4844static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { 4845 { { 6 /* art */ }, 'o' } 4846}; 4847 4848static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { 4849 { { STATE_PSEXCM }, 'i' }, 4850 { { STATE_PSRING }, 'i' }, 4851 { { STATE_IBREAKENABLE }, 'i' } 4852}; 4853 4854static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { 4855 { { 6 /* art */ }, 'i' } 4856}; 4857 4858static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { 4859 { { STATE_PSEXCM }, 'i' }, 4860 { { STATE_PSRING }, 'i' }, 4861 { { STATE_IBREAKENABLE }, 'o' } 4862}; 4863 4864static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { 4865 { { 6 /* art */ }, 'm' } 4866}; 4867 4868static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { 4869 { { STATE_PSEXCM }, 'i' }, 4870 { { STATE_PSRING }, 'i' }, 4871 { { STATE_IBREAKENABLE }, 'm' } 4872}; 4873 4874static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { 4875 { { 6 /* art */ }, 'o' } 4876}; 4877 4878static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { 4879 { { STATE_PSEXCM }, 'i' }, 4880 { { STATE_PSRING }, 'i' }, 4881 { { STATE_DEBUGCAUSE }, 'i' }, 4882 { { STATE_DBNUM }, 'i' } 4883}; 4884 4885static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { 4886 { { 6 /* art */ }, 'i' } 4887}; 4888 4889static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { 4890 { { STATE_PSEXCM }, 'i' }, 4891 { { STATE_PSRING }, 'i' }, 4892 { { STATE_DEBUGCAUSE }, 'o' }, 4893 { { STATE_DBNUM }, 'o' } 4894}; 4895 4896static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { 4897 { { 6 /* art */ }, 'm' } 4898}; 4899 4900static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { 4901 { { STATE_PSEXCM }, 'i' }, 4902 { { STATE_PSRING }, 'i' }, 4903 { { STATE_DEBUGCAUSE }, 'm' }, 4904 { { STATE_DBNUM }, 'm' } 4905}; 4906 4907static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { 4908 { { 6 /* art */ }, 'o' } 4909}; 4910 4911static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { 4912 { { STATE_PSEXCM }, 'i' }, 4913 { { STATE_PSRING }, 'i' }, 4914 { { STATE_ICOUNT }, 'i' } 4915}; 4916 4917static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { 4918 { { 6 /* art */ }, 'i' } 4919}; 4920 4921static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { 4922 { { STATE_PSEXCM }, 'i' }, 4923 { { STATE_PSRING }, 'i' }, 4924 { { STATE_XTSYNC }, 'o' }, 4925 { { STATE_ICOUNT }, 'o' } 4926}; 4927 4928static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { 4929 { { 6 /* art */ }, 'm' } 4930}; 4931 4932static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { 4933 { { STATE_PSEXCM }, 'i' }, 4934 { { STATE_PSRING }, 'i' }, 4935 { { STATE_XTSYNC }, 'o' }, 4936 { { STATE_ICOUNT }, 'm' } 4937}; 4938 4939static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { 4940 { { 6 /* art */ }, 'o' } 4941}; 4942 4943static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { 4944 { { STATE_PSEXCM }, 'i' }, 4945 { { STATE_PSRING }, 'i' }, 4946 { { STATE_ICOUNTLEVEL }, 'i' } 4947}; 4948 4949static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { 4950 { { 6 /* art */ }, 'i' } 4951}; 4952 4953static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { 4954 { { STATE_PSEXCM }, 'i' }, 4955 { { STATE_PSRING }, 'i' }, 4956 { { STATE_ICOUNTLEVEL }, 'o' } 4957}; 4958 4959static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { 4960 { { 6 /* art */ }, 'm' } 4961}; 4962 4963static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { 4964 { { STATE_PSEXCM }, 'i' }, 4965 { { STATE_PSRING }, 'i' }, 4966 { { STATE_ICOUNTLEVEL }, 'm' } 4967}; 4968 4969static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { 4970 { { 6 /* art */ }, 'o' } 4971}; 4972 4973static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { 4974 { { STATE_PSEXCM }, 'i' }, 4975 { { STATE_PSRING }, 'i' }, 4976 { { STATE_DDR }, 'i' } 4977}; 4978 4979static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { 4980 { { 6 /* art */ }, 'i' } 4981}; 4982 4983static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { 4984 { { STATE_PSEXCM }, 'i' }, 4985 { { STATE_PSRING }, 'i' }, 4986 { { STATE_XTSYNC }, 'o' }, 4987 { { STATE_DDR }, 'o' } 4988}; 4989 4990static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { 4991 { { 6 /* art */ }, 'm' } 4992}; 4993 4994static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { 4995 { { STATE_PSEXCM }, 'i' }, 4996 { { STATE_PSRING }, 'i' }, 4997 { { STATE_XTSYNC }, 'o' }, 4998 { { STATE_DDR }, 'm' } 4999}; 5000 5001static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { 5002 { { 41 /* imms */ }, 'i' } 5003}; 5004 5005static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { 5006 { { STATE_InOCDMode }, 'm' }, 5007 { { STATE_EPC6 }, 'i' }, 5008 { { STATE_PSWOE }, 'o' }, 5009 { { STATE_PSCALLINC }, 'o' }, 5010 { { STATE_PSOWB }, 'o' }, 5011 { { STATE_PSRING }, 'o' }, 5012 { { STATE_PSUM }, 'o' }, 5013 { { STATE_PSEXCM }, 'o' }, 5014 { { STATE_PSINTLEVEL }, 'o' }, 5015 { { STATE_EPS6 }, 'i' } 5016}; 5017 5018static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { 5019 { { STATE_InOCDMode }, 'm' } 5020}; 5021 5022static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { 5023 { { 6 /* art */ }, 'i' } 5024}; 5025 5026static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { 5027 { { STATE_PSEXCM }, 'i' }, 5028 { { STATE_PSRING }, 'i' }, 5029 { { STATE_XTSYNC }, 'o' } 5030}; 5031 5032static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { 5033 { { 6 /* art */ }, 'o' } 5034}; 5035 5036static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { 5037 { { STATE_PSEXCM }, 'i' }, 5038 { { STATE_PSRING }, 'i' }, 5039 { { STATE_CCOUNT }, 'i' } 5040}; 5041 5042static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { 5043 { { 6 /* art */ }, 'i' } 5044}; 5045 5046static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { 5047 { { STATE_PSEXCM }, 'i' }, 5048 { { STATE_PSRING }, 'i' }, 5049 { { STATE_XTSYNC }, 'o' }, 5050 { { STATE_CCOUNT }, 'o' } 5051}; 5052 5053static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { 5054 { { 6 /* art */ }, 'm' } 5055}; 5056 5057static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { 5058 { { STATE_PSEXCM }, 'i' }, 5059 { { STATE_PSRING }, 'i' }, 5060 { { STATE_XTSYNC }, 'o' }, 5061 { { STATE_CCOUNT }, 'm' } 5062}; 5063 5064static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { 5065 { { 6 /* art */ }, 'o' } 5066}; 5067 5068static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { 5069 { { STATE_PSEXCM }, 'i' }, 5070 { { STATE_PSRING }, 'i' }, 5071 { { STATE_CCOMPARE0 }, 'i' } 5072}; 5073 5074static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { 5075 { { 6 /* art */ }, 'i' } 5076}; 5077 5078static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { 5079 { { STATE_PSEXCM }, 'i' }, 5080 { { STATE_PSRING }, 'i' }, 5081 { { STATE_CCOMPARE0 }, 'o' }, 5082 { { STATE_INTERRUPT }, 'm' } 5083}; 5084 5085static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { 5086 { { 6 /* art */ }, 'm' } 5087}; 5088 5089static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { 5090 { { STATE_PSEXCM }, 'i' }, 5091 { { STATE_PSRING }, 'i' }, 5092 { { STATE_CCOMPARE0 }, 'm' }, 5093 { { STATE_INTERRUPT }, 'm' } 5094}; 5095 5096static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { 5097 { { 6 /* art */ }, 'o' } 5098}; 5099 5100static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { 5101 { { STATE_PSEXCM }, 'i' }, 5102 { { STATE_PSRING }, 'i' }, 5103 { { STATE_CCOMPARE1 }, 'i' } 5104}; 5105 5106static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { 5107 { { 6 /* art */ }, 'i' } 5108}; 5109 5110static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { 5111 { { STATE_PSEXCM }, 'i' }, 5112 { { STATE_PSRING }, 'i' }, 5113 { { STATE_CCOMPARE1 }, 'o' }, 5114 { { STATE_INTERRUPT }, 'm' } 5115}; 5116 5117static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { 5118 { { 6 /* art */ }, 'm' } 5119}; 5120 5121static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { 5122 { { STATE_PSEXCM }, 'i' }, 5123 { { STATE_PSRING }, 'i' }, 5124 { { STATE_CCOMPARE1 }, 'm' }, 5125 { { STATE_INTERRUPT }, 'm' } 5126}; 5127 5128static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { 5129 { { 6 /* art */ }, 'o' } 5130}; 5131 5132static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { 5133 { { STATE_PSEXCM }, 'i' }, 5134 { { STATE_PSRING }, 'i' }, 5135 { { STATE_CCOMPARE2 }, 'i' } 5136}; 5137 5138static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { 5139 { { 6 /* art */ }, 'i' } 5140}; 5141 5142static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { 5143 { { STATE_PSEXCM }, 'i' }, 5144 { { STATE_PSRING }, 'i' }, 5145 { { STATE_CCOMPARE2 }, 'o' }, 5146 { { STATE_INTERRUPT }, 'm' } 5147}; 5148 5149static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { 5150 { { 6 /* art */ }, 'm' } 5151}; 5152 5153static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { 5154 { { STATE_PSEXCM }, 'i' }, 5155 { { STATE_PSRING }, 'i' }, 5156 { { STATE_CCOMPARE2 }, 'm' }, 5157 { { STATE_INTERRUPT }, 'm' } 5158}; 5159 5160static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { 5161 { { 4 /* ars */ }, 'i' }, 5162 { { 21 /* uimm8x4 */ }, 'i' } 5163}; 5164 5165static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { 5166 { { 4 /* ars */ }, 'i' }, 5167 { { 22 /* uimm4x16 */ }, 'i' } 5168}; 5169 5170static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { 5171 { { STATE_PSEXCM }, 'i' }, 5172 { { STATE_PSRING }, 'i' } 5173}; 5174 5175static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { 5176 { { 4 /* ars */ }, 'i' }, 5177 { { 21 /* uimm8x4 */ }, 'i' } 5178}; 5179 5180static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { 5181 { { STATE_PSEXCM }, 'i' }, 5182 { { STATE_PSRING }, 'i' } 5183}; 5184 5185static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { 5186 { { 6 /* art */ }, 'o' }, 5187 { { 4 /* ars */ }, 'i' } 5188}; 5189 5190static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { 5191 { { STATE_PSEXCM }, 'i' }, 5192 { { STATE_PSRING }, 'i' } 5193}; 5194 5195static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { 5196 { { 6 /* art */ }, 'i' }, 5197 { { 4 /* ars */ }, 'i' } 5198}; 5199 5200static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { 5201 { { STATE_PSEXCM }, 'i' }, 5202 { { STATE_PSRING }, 'i' } 5203}; 5204 5205static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { 5206 { { 4 /* ars */ }, 'i' }, 5207 { { 21 /* uimm8x4 */ }, 'i' } 5208}; 5209 5210static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { 5211 { { 4 /* ars */ }, 'i' }, 5212 { { 22 /* uimm4x16 */ }, 'i' } 5213}; 5214 5215static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { 5216 { { STATE_PSEXCM }, 'i' }, 5217 { { STATE_PSRING }, 'i' } 5218}; 5219 5220static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { 5221 { { 4 /* ars */ }, 'i' }, 5222 { { 21 /* uimm8x4 */ }, 'i' } 5223}; 5224 5225static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { 5226 { { STATE_PSEXCM }, 'i' }, 5227 { { STATE_PSRING }, 'i' } 5228}; 5229 5230static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { 5231 { { 4 /* ars */ }, 'i' }, 5232 { { 21 /* uimm8x4 */ }, 'i' } 5233}; 5234 5235static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { 5236 { { 4 /* ars */ }, 'i' }, 5237 { { 22 /* uimm4x16 */ }, 'i' } 5238}; 5239 5240static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { 5241 { { STATE_PSEXCM }, 'i' }, 5242 { { STATE_PSRING }, 'i' } 5243}; 5244 5245static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { 5246 { { 6 /* art */ }, 'i' }, 5247 { { 4 /* ars */ }, 'i' } 5248}; 5249 5250static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { 5251 { { STATE_PSEXCM }, 'i' }, 5252 { { STATE_PSRING }, 'i' } 5253}; 5254 5255static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { 5256 { { 6 /* art */ }, 'o' }, 5257 { { 4 /* ars */ }, 'i' } 5258}; 5259 5260static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { 5261 { { STATE_PSEXCM }, 'i' }, 5262 { { STATE_PSRING }, 'i' } 5263}; 5264 5265static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { 5266 { { 6 /* art */ }, 'i' } 5267}; 5268 5269static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { 5270 { { STATE_PSEXCM }, 'i' }, 5271 { { STATE_PSRING }, 'i' }, 5272 { { STATE_PTBASE }, 'o' }, 5273 { { STATE_XTSYNC }, 'o' } 5274}; 5275 5276static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { 5277 { { 6 /* art */ }, 'o' } 5278}; 5279 5280static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { 5281 { { STATE_PSEXCM }, 'i' }, 5282 { { STATE_PSRING }, 'i' }, 5283 { { STATE_PTBASE }, 'i' }, 5284 { { STATE_EXCVADDR }, 'i' } 5285}; 5286 5287static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { 5288 { { 6 /* art */ }, 'm' } 5289}; 5290 5291static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { 5292 { { STATE_PSEXCM }, 'i' }, 5293 { { STATE_PSRING }, 'i' }, 5294 { { STATE_PTBASE }, 'm' }, 5295 { { STATE_EXCVADDR }, 'i' }, 5296 { { STATE_XTSYNC }, 'o' } 5297}; 5298 5299static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { 5300 { { 6 /* art */ }, 'o' } 5301}; 5302 5303static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { 5304 { { STATE_PSEXCM }, 'i' }, 5305 { { STATE_PSRING }, 'i' }, 5306 { { STATE_ASID3 }, 'i' }, 5307 { { STATE_ASID2 }, 'i' }, 5308 { { STATE_ASID1 }, 'i' } 5309}; 5310 5311static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { 5312 { { 6 /* art */ }, 'i' } 5313}; 5314 5315static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { 5316 { { STATE_XTSYNC }, 'o' }, 5317 { { STATE_PSEXCM }, 'i' }, 5318 { { STATE_PSRING }, 'i' }, 5319 { { STATE_ASID3 }, 'o' }, 5320 { { STATE_ASID2 }, 'o' }, 5321 { { STATE_ASID1 }, 'o' } 5322}; 5323 5324static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { 5325 { { 6 /* art */ }, 'm' } 5326}; 5327 5328static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { 5329 { { STATE_XTSYNC }, 'o' }, 5330 { { STATE_PSEXCM }, 'i' }, 5331 { { STATE_PSRING }, 'i' }, 5332 { { STATE_ASID3 }, 'm' }, 5333 { { STATE_ASID2 }, 'm' }, 5334 { { STATE_ASID1 }, 'm' } 5335}; 5336 5337static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { 5338 { { 6 /* art */ }, 'o' } 5339}; 5340 5341static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { 5342 { { STATE_PSEXCM }, 'i' }, 5343 { { STATE_PSRING }, 'i' }, 5344 { { STATE_INSTPGSZID4 }, 'i' } 5345}; 5346 5347static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { 5348 { { 6 /* art */ }, 'i' } 5349}; 5350 5351static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { 5352 { { STATE_XTSYNC }, 'o' }, 5353 { { STATE_PSEXCM }, 'i' }, 5354 { { STATE_PSRING }, 'i' }, 5355 { { STATE_INSTPGSZID4 }, 'o' } 5356}; 5357 5358static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { 5359 { { 6 /* art */ }, 'm' } 5360}; 5361 5362static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { 5363 { { STATE_XTSYNC }, 'o' }, 5364 { { STATE_PSEXCM }, 'i' }, 5365 { { STATE_PSRING }, 'i' }, 5366 { { STATE_INSTPGSZID4 }, 'm' } 5367}; 5368 5369static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { 5370 { { 6 /* art */ }, 'o' } 5371}; 5372 5373static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { 5374 { { STATE_PSEXCM }, 'i' }, 5375 { { STATE_PSRING }, 'i' }, 5376 { { STATE_DATAPGSZID4 }, 'i' } 5377}; 5378 5379static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { 5380 { { 6 /* art */ }, 'i' } 5381}; 5382 5383static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { 5384 { { STATE_XTSYNC }, 'o' }, 5385 { { STATE_PSEXCM }, 'i' }, 5386 { { STATE_PSRING }, 'i' }, 5387 { { STATE_DATAPGSZID4 }, 'o' } 5388}; 5389 5390static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { 5391 { { 6 /* art */ }, 'm' } 5392}; 5393 5394static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { 5395 { { STATE_XTSYNC }, 'o' }, 5396 { { STATE_PSEXCM }, 'i' }, 5397 { { STATE_PSRING }, 'i' }, 5398 { { STATE_DATAPGSZID4 }, 'm' } 5399}; 5400 5401static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { 5402 { { 4 /* ars */ }, 'i' } 5403}; 5404 5405static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { 5406 { { STATE_PSEXCM }, 'i' }, 5407 { { STATE_PSRING }, 'i' }, 5408 { { STATE_XTSYNC }, 'o' } 5409}; 5410 5411static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { 5412 { { 6 /* art */ }, 'o' }, 5413 { { 4 /* ars */ }, 'i' } 5414}; 5415 5416static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { 5417 { { STATE_PSEXCM }, 'i' }, 5418 { { STATE_PSRING }, 'i' } 5419}; 5420 5421static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { 5422 { { 6 /* art */ }, 'i' }, 5423 { { 4 /* ars */ }, 'i' } 5424}; 5425 5426static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { 5427 { { STATE_PSEXCM }, 'i' }, 5428 { { STATE_PSRING }, 'i' }, 5429 { { STATE_XTSYNC }, 'o' } 5430}; 5431 5432static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { 5433 { { 4 /* ars */ }, 'i' } 5434}; 5435 5436static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { 5437 { { STATE_PSEXCM }, 'i' }, 5438 { { STATE_PSRING }, 'i' } 5439}; 5440 5441static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { 5442 { { 6 /* art */ }, 'o' }, 5443 { { 4 /* ars */ }, 'i' } 5444}; 5445 5446static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { 5447 { { STATE_PSEXCM }, 'i' }, 5448 { { STATE_PSRING }, 'i' } 5449}; 5450 5451static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { 5452 { { 6 /* art */ }, 'i' }, 5453 { { 4 /* ars */ }, 'i' } 5454}; 5455 5456static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { 5457 { { STATE_PSEXCM }, 'i' }, 5458 { { STATE_PSRING }, 'i' } 5459}; 5460 5461static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { 5462 { { STATE_PTBASE }, 'i' }, 5463 { { STATE_EXCVADDR }, 'i' } 5464}; 5465 5466static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { 5467 { { STATE_EXCVADDR }, 'i' } 5468}; 5469 5470static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { 5471 { { STATE_EXCVADDR }, 'i' } 5472}; 5473 5474static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { 5475 { { 6 /* art */ }, 'o' } 5476}; 5477 5478static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { 5479 { { STATE_PSEXCM }, 'i' }, 5480 { { STATE_PSRING }, 'i' }, 5481 { { STATE_CPENABLE }, 'i' } 5482}; 5483 5484static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { 5485 { { 6 /* art */ }, 'i' } 5486}; 5487 5488static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { 5489 { { STATE_PSEXCM }, 'i' }, 5490 { { STATE_PSRING }, 'i' }, 5491 { { STATE_CPENABLE }, 'o' } 5492}; 5493 5494static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { 5495 { { 6 /* art */ }, 'm' } 5496}; 5497 5498static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { 5499 { { STATE_PSEXCM }, 'i' }, 5500 { { STATE_PSRING }, 'i' }, 5501 { { STATE_CPENABLE }, 'm' } 5502}; 5503 5504static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { 5505 { { 3 /* arr */ }, 'o' }, 5506 { { 4 /* ars */ }, 'i' }, 5507 { { 42 /* tp7 */ }, 'i' } 5508}; 5509 5510static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { 5511 { { 3 /* arr */ }, 'o' }, 5512 { { 4 /* ars */ }, 'i' }, 5513 { { 6 /* art */ }, 'i' } 5514}; 5515 5516static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { 5517 { { 6 /* art */ }, 'o' }, 5518 { { 4 /* ars */ }, 'i' } 5519}; 5520 5521static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { 5522 { { 3 /* arr */ }, 'o' }, 5523 { { 4 /* ars */ }, 'i' }, 5524 { { 42 /* tp7 */ }, 'i' } 5525}; 5526 5527static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { 5528 { { 6 /* art */ }, 'o' }, 5529 { { 4 /* ars */ }, 'i' }, 5530 { { 21 /* uimm8x4 */ }, 'i' } 5531}; 5532 5533static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { 5534 { { 6 /* art */ }, 'i' }, 5535 { { 4 /* ars */ }, 'i' }, 5536 { { 21 /* uimm8x4 */ }, 'i' } 5537}; 5538 5539static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { 5540 { { 6 /* art */ }, 'm' }, 5541 { { 4 /* ars */ }, 'i' }, 5542 { { 21 /* uimm8x4 */ }, 'i' } 5543}; 5544 5545static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { 5546 { { STATE_SCOMPARE1 }, 'i' }, 5547 { { STATE_SCOMPARE1 }, 'i' } 5548}; 5549 5550static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { 5551 { { 6 /* art */ }, 'o' } 5552}; 5553 5554static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { 5555 { { STATE_SCOMPARE1 }, 'i' } 5556}; 5557 5558static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { 5559 { { 6 /* art */ }, 'i' } 5560}; 5561 5562static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { 5563 { { STATE_SCOMPARE1 }, 'o' } 5564}; 5565 5566static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { 5567 { { 6 /* art */ }, 'm' } 5568}; 5569 5570static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { 5571 { { STATE_SCOMPARE1 }, 'm' } 5572}; 5573 5574static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { 5575 { { 3 /* arr */ }, 'o' }, 5576 { { 4 /* ars */ }, 'i' }, 5577 { { 6 /* art */ }, 'i' } 5578}; 5579 5580static xtensa_arg_internal Iclass_xt_mul32_args[] = { 5581 { { 3 /* arr */ }, 'o' }, 5582 { { 4 /* ars */ }, 'i' }, 5583 { { 6 /* art */ }, 'i' } 5584}; 5585 5586static xtensa_arg_internal Iclass_rur_expstate_args[] = { 5587 { { 3 /* arr */ }, 'o' } 5588}; 5589 5590static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { 5591 { { STATE_EXPSTATE }, 'i' }, 5592 { { STATE_CPENABLE }, 'i' } 5593}; 5594 5595static xtensa_arg_internal Iclass_wur_expstate_args[] = { 5596 { { 6 /* art */ }, 'i' } 5597}; 5598 5599static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { 5600 { { STATE_EXPSTATE }, 'o' }, 5601 { { STATE_CPENABLE }, 'i' } 5602}; 5603 5604static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { 5605 { { 6 /* art */ }, 'o' } 5606}; 5607 5608static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { 5609 { { STATE_CPENABLE }, 'i' } 5610}; 5611 5612static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { 5613 0 /* IMPWIRE */ 5614}; 5615 5616static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { 5617 { { 91 /* bitindex */ }, 'i' } 5618}; 5619 5620static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { 5621 { { STATE_EXPSTATE }, 'm' }, 5622 { { STATE_CPENABLE }, 'i' } 5623}; 5624 5625static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { 5626 { { 91 /* bitindex */ }, 'i' } 5627}; 5628 5629static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { 5630 { { STATE_EXPSTATE }, 'm' }, 5631 { { STATE_CPENABLE }, 'i' } 5632}; 5633 5634static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { 5635 { { 6 /* art */ }, 'i' }, 5636 { { 4 /* ars */ }, 'i' } 5637}; 5638 5639static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { 5640 { { STATE_EXPSTATE }, 'm' }, 5641 { { STATE_CPENABLE }, 'i' } 5642}; 5643 5644static xtensa_iclass_internal iclasses[] = { 5645 { 0, 0 /* xt_iclass_excw */, 5646 0, 0, 0, 0 }, 5647 { 0, 0 /* xt_iclass_rfe */, 5648 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, 5649 { 0, 0 /* xt_iclass_rfde */, 5650 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, 5651 { 0, 0 /* xt_iclass_syscall */, 5652 0, 0, 0, 0 }, 5653 { 0, 0 /* xt_iclass_simcall */, 5654 0, 0, 0, 0 }, 5655 { 2, Iclass_xt_iclass_call12_args, 5656 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, 5657 { 2, Iclass_xt_iclass_call8_args, 5658 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, 5659 { 2, Iclass_xt_iclass_call4_args, 5660 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, 5661 { 2, Iclass_xt_iclass_callx12_args, 5662 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, 5663 { 2, Iclass_xt_iclass_callx8_args, 5664 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, 5665 { 2, Iclass_xt_iclass_callx4_args, 5666 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, 5667 { 3, Iclass_xt_iclass_entry_args, 5668 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, 5669 { 2, Iclass_xt_iclass_movsp_args, 5670 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, 5671 { 1, Iclass_xt_iclass_rotw_args, 5672 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, 5673 { 1, Iclass_xt_iclass_retw_args, 5674 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, 5675 { 0, 0 /* xt_iclass_rfwou */, 5676 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, 5677 { 3, Iclass_xt_iclass_l32e_args, 5678 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, 5679 { 3, Iclass_xt_iclass_s32e_args, 5680 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, 5681 { 1, Iclass_xt_iclass_rsr_windowbase_args, 5682 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, 5683 { 1, Iclass_xt_iclass_wsr_windowbase_args, 5684 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, 5685 { 1, Iclass_xt_iclass_xsr_windowbase_args, 5686 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, 5687 { 1, Iclass_xt_iclass_rsr_windowstart_args, 5688 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, 5689 { 1, Iclass_xt_iclass_wsr_windowstart_args, 5690 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, 5691 { 1, Iclass_xt_iclass_xsr_windowstart_args, 5692 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, 5693 { 3, Iclass_xt_iclass_add_n_args, 5694 0, 0, 0, 0 }, 5695 { 3, Iclass_xt_iclass_addi_n_args, 5696 0, 0, 0, 0 }, 5697 { 2, Iclass_xt_iclass_bz6_args, 5698 0, 0, 0, 0 }, 5699 { 0, 0 /* xt_iclass_ill_n */, 5700 0, 0, 0, 0 }, 5701 { 3, Iclass_xt_iclass_loadi4_args, 5702 0, 0, 0, 0 }, 5703 { 2, Iclass_xt_iclass_mov_n_args, 5704 0, 0, 0, 0 }, 5705 { 2, Iclass_xt_iclass_movi_n_args, 5706 0, 0, 0, 0 }, 5707 { 0, 0 /* xt_iclass_nopn */, 5708 0, 0, 0, 0 }, 5709 { 1, Iclass_xt_iclass_retn_args, 5710 0, 0, 0, 0 }, 5711 { 3, Iclass_xt_iclass_storei4_args, 5712 0, 0, 0, 0 }, 5713 { 1, Iclass_rur_threadptr_args, 5714 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, 5715 { 1, Iclass_wur_threadptr_args, 5716 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, 5717 { 3, Iclass_xt_iclass_addi_args, 5718 0, 0, 0, 0 }, 5719 { 3, Iclass_xt_iclass_addmi_args, 5720 0, 0, 0, 0 }, 5721 { 3, Iclass_xt_iclass_addsub_args, 5722 0, 0, 0, 0 }, 5723 { 3, Iclass_xt_iclass_bit_args, 5724 0, 0, 0, 0 }, 5725 { 3, Iclass_xt_iclass_bsi8_args, 5726 0, 0, 0, 0 }, 5727 { 3, Iclass_xt_iclass_bsi8b_args, 5728 0, 0, 0, 0 }, 5729 { 3, Iclass_xt_iclass_bsi8u_args, 5730 0, 0, 0, 0 }, 5731 { 3, Iclass_xt_iclass_bst8_args, 5732 0, 0, 0, 0 }, 5733 { 2, Iclass_xt_iclass_bsz12_args, 5734 0, 0, 0, 0 }, 5735 { 2, Iclass_xt_iclass_call0_args, 5736 0, 0, 0, 0 }, 5737 { 2, Iclass_xt_iclass_callx0_args, 5738 0, 0, 0, 0 }, 5739 { 4, Iclass_xt_iclass_exti_args, 5740 0, 0, 0, 0 }, 5741 { 0, 0 /* xt_iclass_ill */, 5742 0, 0, 0, 0 }, 5743 { 1, Iclass_xt_iclass_jump_args, 5744 0, 0, 0, 0 }, 5745 { 1, Iclass_xt_iclass_jumpx_args, 5746 0, 0, 0, 0 }, 5747 { 3, Iclass_xt_iclass_l16ui_args, 5748 0, 0, 0, 0 }, 5749 { 3, Iclass_xt_iclass_l16si_args, 5750 0, 0, 0, 0 }, 5751 { 3, Iclass_xt_iclass_l32i_args, 5752 0, 0, 0, 0 }, 5753 { 2, Iclass_xt_iclass_l32r_args, 5754 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, 5755 { 3, Iclass_xt_iclass_l8i_args, 5756 0, 0, 0, 0 }, 5757 { 2, Iclass_xt_iclass_loop_args, 5758 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, 5759 { 2, Iclass_xt_iclass_loopz_args, 5760 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, 5761 { 2, Iclass_xt_iclass_movi_args, 5762 0, 0, 0, 0 }, 5763 { 3, Iclass_xt_iclass_movz_args, 5764 0, 0, 0, 0 }, 5765 { 2, Iclass_xt_iclass_neg_args, 5766 0, 0, 0, 0 }, 5767 { 0, 0 /* xt_iclass_nop */, 5768 0, 0, 0, 0 }, 5769 { 1, Iclass_xt_iclass_return_args, 5770 0, 0, 0, 0 }, 5771 { 3, Iclass_xt_iclass_s16i_args, 5772 0, 0, 0, 0 }, 5773 { 3, Iclass_xt_iclass_s32i_args, 5774 0, 0, 0, 0 }, 5775 { 3, Iclass_xt_iclass_s8i_args, 5776 0, 0, 0, 0 }, 5777 { 1, Iclass_xt_iclass_sar_args, 5778 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, 5779 { 1, Iclass_xt_iclass_sari_args, 5780 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, 5781 { 2, Iclass_xt_iclass_shifts_args, 5782 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, 5783 { 3, Iclass_xt_iclass_shiftst_args, 5784 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, 5785 { 2, Iclass_xt_iclass_shiftt_args, 5786 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, 5787 { 3, Iclass_xt_iclass_slli_args, 5788 0, 0, 0, 0 }, 5789 { 3, Iclass_xt_iclass_srai_args, 5790 0, 0, 0, 0 }, 5791 { 3, Iclass_xt_iclass_srli_args, 5792 0, 0, 0, 0 }, 5793 { 0, 0 /* xt_iclass_memw */, 5794 0, 0, 0, 0 }, 5795 { 0, 0 /* xt_iclass_extw */, 5796 0, 0, 0, 0 }, 5797 { 0, 0 /* xt_iclass_isync */, 5798 0, 0, 0, 0 }, 5799 { 0, 0 /* xt_iclass_sync */, 5800 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, 5801 { 2, Iclass_xt_iclass_rsil_args, 5802 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, 5803 { 1, Iclass_xt_iclass_rsr_lend_args, 5804 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, 5805 { 1, Iclass_xt_iclass_wsr_lend_args, 5806 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, 5807 { 1, Iclass_xt_iclass_xsr_lend_args, 5808 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, 5809 { 1, Iclass_xt_iclass_rsr_lcount_args, 5810 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, 5811 { 1, Iclass_xt_iclass_wsr_lcount_args, 5812 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, 5813 { 1, Iclass_xt_iclass_xsr_lcount_args, 5814 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, 5815 { 1, Iclass_xt_iclass_rsr_lbeg_args, 5816 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, 5817 { 1, Iclass_xt_iclass_wsr_lbeg_args, 5818 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, 5819 { 1, Iclass_xt_iclass_xsr_lbeg_args, 5820 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, 5821 { 1, Iclass_xt_iclass_rsr_sar_args, 5822 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, 5823 { 1, Iclass_xt_iclass_wsr_sar_args, 5824 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, 5825 { 1, Iclass_xt_iclass_xsr_sar_args, 5826 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, 5827 { 1, Iclass_xt_iclass_rsr_litbase_args, 5828 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, 5829 { 1, Iclass_xt_iclass_wsr_litbase_args, 5830 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, 5831 { 1, Iclass_xt_iclass_xsr_litbase_args, 5832 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, 5833 { 1, Iclass_xt_iclass_rsr_176_args, 5834 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, 5835 { 1, Iclass_xt_iclass_rsr_208_args, 5836 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, 5837 { 1, Iclass_xt_iclass_rsr_ps_args, 5838 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, 5839 { 1, Iclass_xt_iclass_wsr_ps_args, 5840 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, 5841 { 1, Iclass_xt_iclass_xsr_ps_args, 5842 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, 5843 { 1, Iclass_xt_iclass_rsr_epc1_args, 5844 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, 5845 { 1, Iclass_xt_iclass_wsr_epc1_args, 5846 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, 5847 { 1, Iclass_xt_iclass_xsr_epc1_args, 5848 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, 5849 { 1, Iclass_xt_iclass_rsr_excsave1_args, 5850 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, 5851 { 1, Iclass_xt_iclass_wsr_excsave1_args, 5852 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, 5853 { 1, Iclass_xt_iclass_xsr_excsave1_args, 5854 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, 5855 { 1, Iclass_xt_iclass_rsr_epc2_args, 5856 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, 5857 { 1, Iclass_xt_iclass_wsr_epc2_args, 5858 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, 5859 { 1, Iclass_xt_iclass_xsr_epc2_args, 5860 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, 5861 { 1, Iclass_xt_iclass_rsr_excsave2_args, 5862 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, 5863 { 1, Iclass_xt_iclass_wsr_excsave2_args, 5864 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, 5865 { 1, Iclass_xt_iclass_xsr_excsave2_args, 5866 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, 5867 { 1, Iclass_xt_iclass_rsr_epc3_args, 5868 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, 5869 { 1, Iclass_xt_iclass_wsr_epc3_args, 5870 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, 5871 { 1, Iclass_xt_iclass_xsr_epc3_args, 5872 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, 5873 { 1, Iclass_xt_iclass_rsr_excsave3_args, 5874 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, 5875 { 1, Iclass_xt_iclass_wsr_excsave3_args, 5876 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, 5877 { 1, Iclass_xt_iclass_xsr_excsave3_args, 5878 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, 5879 { 1, Iclass_xt_iclass_rsr_epc4_args, 5880 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, 5881 { 1, Iclass_xt_iclass_wsr_epc4_args, 5882 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, 5883 { 1, Iclass_xt_iclass_xsr_epc4_args, 5884 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, 5885 { 1, Iclass_xt_iclass_rsr_excsave4_args, 5886 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, 5887 { 1, Iclass_xt_iclass_wsr_excsave4_args, 5888 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, 5889 { 1, Iclass_xt_iclass_xsr_excsave4_args, 5890 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, 5891 { 1, Iclass_xt_iclass_rsr_epc5_args, 5892 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, 5893 { 1, Iclass_xt_iclass_wsr_epc5_args, 5894 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, 5895 { 1, Iclass_xt_iclass_xsr_epc5_args, 5896 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, 5897 { 1, Iclass_xt_iclass_rsr_excsave5_args, 5898 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, 5899 { 1, Iclass_xt_iclass_wsr_excsave5_args, 5900 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, 5901 { 1, Iclass_xt_iclass_xsr_excsave5_args, 5902 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, 5903 { 1, Iclass_xt_iclass_rsr_epc6_args, 5904 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, 5905 { 1, Iclass_xt_iclass_wsr_epc6_args, 5906 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, 5907 { 1, Iclass_xt_iclass_xsr_epc6_args, 5908 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, 5909 { 1, Iclass_xt_iclass_rsr_excsave6_args, 5910 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, 5911 { 1, Iclass_xt_iclass_wsr_excsave6_args, 5912 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, 5913 { 1, Iclass_xt_iclass_xsr_excsave6_args, 5914 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, 5915 { 1, Iclass_xt_iclass_rsr_epc7_args, 5916 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, 5917 { 1, Iclass_xt_iclass_wsr_epc7_args, 5918 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, 5919 { 1, Iclass_xt_iclass_xsr_epc7_args, 5920 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, 5921 { 1, Iclass_xt_iclass_rsr_excsave7_args, 5922 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, 5923 { 1, Iclass_xt_iclass_wsr_excsave7_args, 5924 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, 5925 { 1, Iclass_xt_iclass_xsr_excsave7_args, 5926 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, 5927 { 1, Iclass_xt_iclass_rsr_eps2_args, 5928 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, 5929 { 1, Iclass_xt_iclass_wsr_eps2_args, 5930 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, 5931 { 1, Iclass_xt_iclass_xsr_eps2_args, 5932 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, 5933 { 1, Iclass_xt_iclass_rsr_eps3_args, 5934 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, 5935 { 1, Iclass_xt_iclass_wsr_eps3_args, 5936 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, 5937 { 1, Iclass_xt_iclass_xsr_eps3_args, 5938 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, 5939 { 1, Iclass_xt_iclass_rsr_eps4_args, 5940 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, 5941 { 1, Iclass_xt_iclass_wsr_eps4_args, 5942 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, 5943 { 1, Iclass_xt_iclass_xsr_eps4_args, 5944 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, 5945 { 1, Iclass_xt_iclass_rsr_eps5_args, 5946 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, 5947 { 1, Iclass_xt_iclass_wsr_eps5_args, 5948 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, 5949 { 1, Iclass_xt_iclass_xsr_eps5_args, 5950 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, 5951 { 1, Iclass_xt_iclass_rsr_eps6_args, 5952 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, 5953 { 1, Iclass_xt_iclass_wsr_eps6_args, 5954 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, 5955 { 1, Iclass_xt_iclass_xsr_eps6_args, 5956 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, 5957 { 1, Iclass_xt_iclass_rsr_eps7_args, 5958 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, 5959 { 1, Iclass_xt_iclass_wsr_eps7_args, 5960 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, 5961 { 1, Iclass_xt_iclass_xsr_eps7_args, 5962 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, 5963 { 1, Iclass_xt_iclass_rsr_excvaddr_args, 5964 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, 5965 { 1, Iclass_xt_iclass_wsr_excvaddr_args, 5966 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, 5967 { 1, Iclass_xt_iclass_xsr_excvaddr_args, 5968 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, 5969 { 1, Iclass_xt_iclass_rsr_depc_args, 5970 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, 5971 { 1, Iclass_xt_iclass_wsr_depc_args, 5972 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, 5973 { 1, Iclass_xt_iclass_xsr_depc_args, 5974 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, 5975 { 1, Iclass_xt_iclass_rsr_exccause_args, 5976 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, 5977 { 1, Iclass_xt_iclass_wsr_exccause_args, 5978 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, 5979 { 1, Iclass_xt_iclass_xsr_exccause_args, 5980 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, 5981 { 1, Iclass_xt_iclass_rsr_misc0_args, 5982 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, 5983 { 1, Iclass_xt_iclass_wsr_misc0_args, 5984 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, 5985 { 1, Iclass_xt_iclass_xsr_misc0_args, 5986 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, 5987 { 1, Iclass_xt_iclass_rsr_misc1_args, 5988 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, 5989 { 1, Iclass_xt_iclass_wsr_misc1_args, 5990 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, 5991 { 1, Iclass_xt_iclass_xsr_misc1_args, 5992 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, 5993 { 1, Iclass_xt_iclass_rsr_prid_args, 5994 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, 5995 { 1, Iclass_xt_iclass_rsr_vecbase_args, 5996 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, 5997 { 1, Iclass_xt_iclass_wsr_vecbase_args, 5998 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, 5999 { 1, Iclass_xt_iclass_xsr_vecbase_args, 6000 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, 6001 { 2, Iclass_xt_iclass_mac16_aa_args, 6002 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, 6003 { 2, Iclass_xt_iclass_mac16_ad_args, 6004 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, 6005 { 2, Iclass_xt_iclass_mac16_da_args, 6006 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, 6007 { 2, Iclass_xt_iclass_mac16_dd_args, 6008 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, 6009 { 2, Iclass_xt_iclass_mac16a_aa_args, 6010 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, 6011 { 2, Iclass_xt_iclass_mac16a_ad_args, 6012 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, 6013 { 2, Iclass_xt_iclass_mac16a_da_args, 6014 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, 6015 { 2, Iclass_xt_iclass_mac16a_dd_args, 6016 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, 6017 { 4, Iclass_xt_iclass_mac16al_da_args, 6018 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, 6019 { 4, Iclass_xt_iclass_mac16al_dd_args, 6020 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, 6021 { 2, Iclass_xt_iclass_mac16_l_args, 6022 0, 0, 0, 0 }, 6023 { 3, Iclass_xt_iclass_mul16_args, 6024 0, 0, 0, 0 }, 6025 { 2, Iclass_xt_iclass_rsr_m0_args, 6026 0, 0, 0, 0 }, 6027 { 2, Iclass_xt_iclass_wsr_m0_args, 6028 0, 0, 0, 0 }, 6029 { 2, Iclass_xt_iclass_xsr_m0_args, 6030 0, 0, 0, 0 }, 6031 { 2, Iclass_xt_iclass_rsr_m1_args, 6032 0, 0, 0, 0 }, 6033 { 2, Iclass_xt_iclass_wsr_m1_args, 6034 0, 0, 0, 0 }, 6035 { 2, Iclass_xt_iclass_xsr_m1_args, 6036 0, 0, 0, 0 }, 6037 { 2, Iclass_xt_iclass_rsr_m2_args, 6038 0, 0, 0, 0 }, 6039 { 2, Iclass_xt_iclass_wsr_m2_args, 6040 0, 0, 0, 0 }, 6041 { 2, Iclass_xt_iclass_xsr_m2_args, 6042 0, 0, 0, 0 }, 6043 { 2, Iclass_xt_iclass_rsr_m3_args, 6044 0, 0, 0, 0 }, 6045 { 2, Iclass_xt_iclass_wsr_m3_args, 6046 0, 0, 0, 0 }, 6047 { 2, Iclass_xt_iclass_xsr_m3_args, 6048 0, 0, 0, 0 }, 6049 { 1, Iclass_xt_iclass_rsr_acclo_args, 6050 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, 6051 { 1, Iclass_xt_iclass_wsr_acclo_args, 6052 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, 6053 { 1, Iclass_xt_iclass_xsr_acclo_args, 6054 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, 6055 { 1, Iclass_xt_iclass_rsr_acchi_args, 6056 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, 6057 { 1, Iclass_xt_iclass_wsr_acchi_args, 6058 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, 6059 { 1, Iclass_xt_iclass_xsr_acchi_args, 6060 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, 6061 { 1, Iclass_xt_iclass_rfi_args, 6062 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, 6063 { 1, Iclass_xt_iclass_wait_args, 6064 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, 6065 { 1, Iclass_xt_iclass_rsr_interrupt_args, 6066 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, 6067 { 1, Iclass_xt_iclass_wsr_intset_args, 6068 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, 6069 { 1, Iclass_xt_iclass_wsr_intclear_args, 6070 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, 6071 { 1, Iclass_xt_iclass_rsr_intenable_args, 6072 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, 6073 { 1, Iclass_xt_iclass_wsr_intenable_args, 6074 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, 6075 { 1, Iclass_xt_iclass_xsr_intenable_args, 6076 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, 6077 { 2, Iclass_xt_iclass_break_args, 6078 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, 6079 { 1, Iclass_xt_iclass_break_n_args, 6080 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, 6081 { 1, Iclass_xt_iclass_rsr_dbreaka0_args, 6082 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, 6083 { 1, Iclass_xt_iclass_wsr_dbreaka0_args, 6084 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, 6085 { 1, Iclass_xt_iclass_xsr_dbreaka0_args, 6086 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, 6087 { 1, Iclass_xt_iclass_rsr_dbreakc0_args, 6088 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, 6089 { 1, Iclass_xt_iclass_wsr_dbreakc0_args, 6090 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, 6091 { 1, Iclass_xt_iclass_xsr_dbreakc0_args, 6092 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, 6093 { 1, Iclass_xt_iclass_rsr_dbreaka1_args, 6094 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, 6095 { 1, Iclass_xt_iclass_wsr_dbreaka1_args, 6096 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, 6097 { 1, Iclass_xt_iclass_xsr_dbreaka1_args, 6098 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, 6099 { 1, Iclass_xt_iclass_rsr_dbreakc1_args, 6100 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, 6101 { 1, Iclass_xt_iclass_wsr_dbreakc1_args, 6102 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, 6103 { 1, Iclass_xt_iclass_xsr_dbreakc1_args, 6104 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, 6105 { 1, Iclass_xt_iclass_rsr_ibreaka0_args, 6106 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, 6107 { 1, Iclass_xt_iclass_wsr_ibreaka0_args, 6108 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, 6109 { 1, Iclass_xt_iclass_xsr_ibreaka0_args, 6110 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, 6111 { 1, Iclass_xt_iclass_rsr_ibreaka1_args, 6112 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, 6113 { 1, Iclass_xt_iclass_wsr_ibreaka1_args, 6114 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, 6115 { 1, Iclass_xt_iclass_xsr_ibreaka1_args, 6116 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, 6117 { 1, Iclass_xt_iclass_rsr_ibreakenable_args, 6118 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, 6119 { 1, Iclass_xt_iclass_wsr_ibreakenable_args, 6120 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, 6121 { 1, Iclass_xt_iclass_xsr_ibreakenable_args, 6122 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, 6123 { 1, Iclass_xt_iclass_rsr_debugcause_args, 6124 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, 6125 { 1, Iclass_xt_iclass_wsr_debugcause_args, 6126 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, 6127 { 1, Iclass_xt_iclass_xsr_debugcause_args, 6128 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, 6129 { 1, Iclass_xt_iclass_rsr_icount_args, 6130 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, 6131 { 1, Iclass_xt_iclass_wsr_icount_args, 6132 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, 6133 { 1, Iclass_xt_iclass_xsr_icount_args, 6134 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, 6135 { 1, Iclass_xt_iclass_rsr_icountlevel_args, 6136 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, 6137 { 1, Iclass_xt_iclass_wsr_icountlevel_args, 6138 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, 6139 { 1, Iclass_xt_iclass_xsr_icountlevel_args, 6140 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, 6141 { 1, Iclass_xt_iclass_rsr_ddr_args, 6142 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, 6143 { 1, Iclass_xt_iclass_wsr_ddr_args, 6144 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, 6145 { 1, Iclass_xt_iclass_xsr_ddr_args, 6146 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, 6147 { 1, Iclass_xt_iclass_rfdo_args, 6148 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, 6149 { 0, 0 /* xt_iclass_rfdd */, 6150 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, 6151 { 1, Iclass_xt_iclass_wsr_mmid_args, 6152 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, 6153 { 1, Iclass_xt_iclass_rsr_ccount_args, 6154 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, 6155 { 1, Iclass_xt_iclass_wsr_ccount_args, 6156 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, 6157 { 1, Iclass_xt_iclass_xsr_ccount_args, 6158 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, 6159 { 1, Iclass_xt_iclass_rsr_ccompare0_args, 6160 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, 6161 { 1, Iclass_xt_iclass_wsr_ccompare0_args, 6162 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, 6163 { 1, Iclass_xt_iclass_xsr_ccompare0_args, 6164 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, 6165 { 1, Iclass_xt_iclass_rsr_ccompare1_args, 6166 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, 6167 { 1, Iclass_xt_iclass_wsr_ccompare1_args, 6168 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, 6169 { 1, Iclass_xt_iclass_xsr_ccompare1_args, 6170 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, 6171 { 1, Iclass_xt_iclass_rsr_ccompare2_args, 6172 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, 6173 { 1, Iclass_xt_iclass_wsr_ccompare2_args, 6174 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, 6175 { 1, Iclass_xt_iclass_xsr_ccompare2_args, 6176 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, 6177 { 2, Iclass_xt_iclass_icache_args, 6178 0, 0, 0, 0 }, 6179 { 2, Iclass_xt_iclass_icache_lock_args, 6180 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, 6181 { 2, Iclass_xt_iclass_icache_inv_args, 6182 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, 6183 { 2, Iclass_xt_iclass_licx_args, 6184 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, 6185 { 2, Iclass_xt_iclass_sicx_args, 6186 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, 6187 { 2, Iclass_xt_iclass_dcache_args, 6188 0, 0, 0, 0 }, 6189 { 2, Iclass_xt_iclass_dcache_ind_args, 6190 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, 6191 { 2, Iclass_xt_iclass_dcache_inv_args, 6192 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, 6193 { 2, Iclass_xt_iclass_dpf_args, 6194 0, 0, 0, 0 }, 6195 { 2, Iclass_xt_iclass_dcache_lock_args, 6196 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, 6197 { 2, Iclass_xt_iclass_sdct_args, 6198 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, 6199 { 2, Iclass_xt_iclass_ldct_args, 6200 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, 6201 { 1, Iclass_xt_iclass_wsr_ptevaddr_args, 6202 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, 6203 { 1, Iclass_xt_iclass_rsr_ptevaddr_args, 6204 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, 6205 { 1, Iclass_xt_iclass_xsr_ptevaddr_args, 6206 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, 6207 { 1, Iclass_xt_iclass_rsr_rasid_args, 6208 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, 6209 { 1, Iclass_xt_iclass_wsr_rasid_args, 6210 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, 6211 { 1, Iclass_xt_iclass_xsr_rasid_args, 6212 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, 6213 { 1, Iclass_xt_iclass_rsr_itlbcfg_args, 6214 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, 6215 { 1, Iclass_xt_iclass_wsr_itlbcfg_args, 6216 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, 6217 { 1, Iclass_xt_iclass_xsr_itlbcfg_args, 6218 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, 6219 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, 6220 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, 6221 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, 6222 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, 6223 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, 6224 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, 6225 { 1, Iclass_xt_iclass_idtlb_args, 6226 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, 6227 { 2, Iclass_xt_iclass_rdtlb_args, 6228 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, 6229 { 2, Iclass_xt_iclass_wdtlb_args, 6230 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, 6231 { 1, Iclass_xt_iclass_iitlb_args, 6232 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, 6233 { 2, Iclass_xt_iclass_ritlb_args, 6234 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, 6235 { 2, Iclass_xt_iclass_witlb_args, 6236 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, 6237 { 0, 0 /* xt_iclass_ldpte */, 6238 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, 6239 { 0, 0 /* xt_iclass_hwwitlba */, 6240 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, 6241 { 0, 0 /* xt_iclass_hwwdtlba */, 6242 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, 6243 { 1, Iclass_xt_iclass_rsr_cpenable_args, 6244 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, 6245 { 1, Iclass_xt_iclass_wsr_cpenable_args, 6246 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, 6247 { 1, Iclass_xt_iclass_xsr_cpenable_args, 6248 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, 6249 { 3, Iclass_xt_iclass_clamp_args, 6250 0, 0, 0, 0 }, 6251 { 3, Iclass_xt_iclass_minmax_args, 6252 0, 0, 0, 0 }, 6253 { 2, Iclass_xt_iclass_nsa_args, 6254 0, 0, 0, 0 }, 6255 { 3, Iclass_xt_iclass_sx_args, 6256 0, 0, 0, 0 }, 6257 { 3, Iclass_xt_iclass_l32ai_args, 6258 0, 0, 0, 0 }, 6259 { 3, Iclass_xt_iclass_s32ri_args, 6260 0, 0, 0, 0 }, 6261 { 3, Iclass_xt_iclass_s32c1i_args, 6262 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, 6263 { 1, Iclass_xt_iclass_rsr_scompare1_args, 6264 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, 6265 { 1, Iclass_xt_iclass_wsr_scompare1_args, 6266 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, 6267 { 1, Iclass_xt_iclass_xsr_scompare1_args, 6268 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, 6269 { 3, Iclass_xt_iclass_div_args, 6270 0, 0, 0, 0 }, 6271 { 3, Iclass_xt_mul32_args, 6272 0, 0, 0, 0 }, 6273 { 1, Iclass_rur_expstate_args, 6274 2, Iclass_rur_expstate_stateArgs, 0, 0 }, 6275 { 1, Iclass_wur_expstate_args, 6276 2, Iclass_wur_expstate_stateArgs, 0, 0 }, 6277 { 1, Iclass_iclass_READ_IMPWIRE_args, 6278 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, 6279 { 1, Iclass_iclass_SETB_EXPSTATE_args, 6280 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, 6281 { 1, Iclass_iclass_CLRB_EXPSTATE_args, 6282 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, 6283 { 2, Iclass_iclass_WRMSK_EXPSTATE_args, 6284 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } 6285}; 6286 6287 6288/* Opcode encodings. */ 6289 6290static void 6291Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6292{ 6293 slotbuf[0] = 0x2080; 6294} 6295 6296static void 6297Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) 6298{ 6299 slotbuf[0] = 0x3000; 6300} 6301 6302static void 6303Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) 6304{ 6305 slotbuf[0] = 0x3200; 6306} 6307 6308static void 6309Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) 6310{ 6311 slotbuf[0] = 0x5000; 6312} 6313 6314static void 6315Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) 6316{ 6317 slotbuf[0] = 0x5100; 6318} 6319 6320static void 6321Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) 6322{ 6323 slotbuf[0] = 0x35; 6324} 6325 6326static void 6327Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6328{ 6329 slotbuf[0] = 0x25; 6330} 6331 6332static void 6333Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6334{ 6335 slotbuf[0] = 0x15; 6336} 6337 6338static void 6339Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) 6340{ 6341 slotbuf[0] = 0xf0; 6342} 6343 6344static void 6345Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6346{ 6347 slotbuf[0] = 0xe0; 6348} 6349 6350static void 6351Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6352{ 6353 slotbuf[0] = 0xd0; 6354} 6355 6356static void 6357Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) 6358{ 6359 slotbuf[0] = 0x36; 6360} 6361 6362static void 6363Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) 6364{ 6365 slotbuf[0] = 0x1000; 6366} 6367 6368static void 6369Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6370{ 6371 slotbuf[0] = 0x408000; 6372} 6373 6374static void 6375Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6376{ 6377 slotbuf[0] = 0x90; 6378} 6379 6380static void 6381Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6382{ 6383 slotbuf[0] = 0xf01d; 6384} 6385 6386static void 6387Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 6388{ 6389 slotbuf[0] = 0x3400; 6390} 6391 6392static void 6393Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) 6394{ 6395 slotbuf[0] = 0x3500; 6396} 6397 6398static void 6399Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 6400{ 6401 slotbuf[0] = 0x90000; 6402} 6403 6404static void 6405Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 6406{ 6407 slotbuf[0] = 0x490000; 6408} 6409 6410static void 6411Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 6412{ 6413 slotbuf[0] = 0x34800; 6414} 6415 6416static void 6417Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 6418{ 6419 slotbuf[0] = 0x134800; 6420} 6421 6422static void 6423Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 6424{ 6425 slotbuf[0] = 0x614800; 6426} 6427 6428static void 6429Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 6430{ 6431 slotbuf[0] = 0x34900; 6432} 6433 6434static void 6435Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 6436{ 6437 slotbuf[0] = 0x134900; 6438} 6439 6440static void 6441Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 6442{ 6443 slotbuf[0] = 0x614900; 6444} 6445 6446static void 6447Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6448{ 6449 slotbuf[0] = 0xa; 6450} 6451 6452static void 6453Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6454{ 6455 slotbuf[0] = 0xb; 6456} 6457 6458static void 6459Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6460{ 6461 slotbuf[0] = 0x8c; 6462} 6463 6464static void 6465Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6466{ 6467 slotbuf[0] = 0xcc; 6468} 6469 6470static void 6471Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6472{ 6473 slotbuf[0] = 0xf06d; 6474} 6475 6476static void 6477Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6478{ 6479 slotbuf[0] = 0x8; 6480} 6481 6482static void 6483Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6484{ 6485 slotbuf[0] = 0xd; 6486} 6487 6488static void 6489Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6490{ 6491 slotbuf[0] = 0xc; 6492} 6493 6494static void 6495Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6496{ 6497 slotbuf[0] = 0xf03d; 6498} 6499 6500static void 6501Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6502{ 6503 slotbuf[0] = 0xf00d; 6504} 6505 6506static void 6507Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6508{ 6509 slotbuf[0] = 0x9; 6510} 6511 6512static void 6513Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6514{ 6515 slotbuf[0] = 0xe30e70; 6516} 6517 6518static void 6519Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6520{ 6521 slotbuf[0] = 0xf3e700; 6522} 6523 6524static void 6525Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6526{ 6527 slotbuf[0] = 0xc002; 6528} 6529 6530static void 6531Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6532{ 6533 slotbuf[0] = 0xd002; 6534} 6535 6536static void 6537Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) 6538{ 6539 slotbuf[0] = 0x800000; 6540} 6541 6542static void 6543Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) 6544{ 6545 slotbuf[0] = 0xc00000; 6546} 6547 6548static void 6549Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6550{ 6551 slotbuf[0] = 0x900000; 6552} 6553 6554static void 6555Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6556{ 6557 slotbuf[0] = 0xa00000; 6558} 6559 6560static void 6561Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6562{ 6563 slotbuf[0] = 0xb00000; 6564} 6565 6566static void 6567Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6568{ 6569 slotbuf[0] = 0xd00000; 6570} 6571 6572static void 6573Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6574{ 6575 slotbuf[0] = 0xe00000; 6576} 6577 6578static void 6579Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6580{ 6581 slotbuf[0] = 0xf00000; 6582} 6583 6584static void 6585Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) 6586{ 6587 slotbuf[0] = 0x100000; 6588} 6589 6590static void 6591Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) 6592{ 6593 slotbuf[0] = 0x200000; 6594} 6595 6596static void 6597Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) 6598{ 6599 slotbuf[0] = 0x300000; 6600} 6601 6602static void 6603Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6604{ 6605 slotbuf[0] = 0x26; 6606} 6607 6608static void 6609Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) 6610{ 6611 slotbuf[0] = 0x66; 6612} 6613 6614static void 6615Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) 6616{ 6617 slotbuf[0] = 0xe6; 6618} 6619 6620static void 6621Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) 6622{ 6623 slotbuf[0] = 0xa6; 6624} 6625 6626static void 6627Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) 6628{ 6629 slotbuf[0] = 0x6007; 6630} 6631 6632static void 6633Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6634{ 6635 slotbuf[0] = 0xe007; 6636} 6637 6638static void 6639Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6640{ 6641 slotbuf[0] = 0xf6; 6642} 6643 6644static void 6645Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6646{ 6647 slotbuf[0] = 0xb6; 6648} 6649 6650static void 6651Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) 6652{ 6653 slotbuf[0] = 0x1007; 6654} 6655 6656static void 6657Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) 6658{ 6659 slotbuf[0] = 0x9007; 6660} 6661 6662static void 6663Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) 6664{ 6665 slotbuf[0] = 0xa007; 6666} 6667 6668static void 6669Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) 6670{ 6671 slotbuf[0] = 0x2007; 6672} 6673 6674static void 6675Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) 6676{ 6677 slotbuf[0] = 0xb007; 6678} 6679 6680static void 6681Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) 6682{ 6683 slotbuf[0] = 0x3007; 6684} 6685 6686static void 6687Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) 6688{ 6689 slotbuf[0] = 0x8007; 6690} 6691 6692static void 6693Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) 6694{ 6695 slotbuf[0] = 0x7; 6696} 6697 6698static void 6699Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) 6700{ 6701 slotbuf[0] = 0x4007; 6702} 6703 6704static void 6705Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) 6706{ 6707 slotbuf[0] = 0xc007; 6708} 6709 6710static void 6711Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) 6712{ 6713 slotbuf[0] = 0x5007; 6714} 6715 6716static void 6717Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) 6718{ 6719 slotbuf[0] = 0xd007; 6720} 6721 6722static void 6723Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6724{ 6725 slotbuf[0] = 0x16; 6726} 6727 6728static void 6729Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6730{ 6731 slotbuf[0] = 0x56; 6732} 6733 6734static void 6735Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6736{ 6737 slotbuf[0] = 0xd6; 6738} 6739 6740static void 6741Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6742{ 6743 slotbuf[0] = 0x96; 6744} 6745 6746static void 6747Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6748{ 6749 slotbuf[0] = 0x5; 6750} 6751 6752static void 6753Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6754{ 6755 slotbuf[0] = 0xc0; 6756} 6757 6758static void 6759Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6760{ 6761 slotbuf[0] = 0x40000; 6762} 6763 6764static void 6765Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) 6766{ 6767 slotbuf[0] = 0; 6768} 6769 6770static void 6771Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) 6772{ 6773 slotbuf[0] = 0x6; 6774} 6775 6776static void 6777Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) 6778{ 6779 slotbuf[0] = 0xa0; 6780} 6781 6782static void 6783Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6784{ 6785 slotbuf[0] = 0x1002; 6786} 6787 6788static void 6789Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) 6790{ 6791 slotbuf[0] = 0x9002; 6792} 6793 6794static void 6795Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6796{ 6797 slotbuf[0] = 0x2002; 6798} 6799 6800static void 6801Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) 6802{ 6803 slotbuf[0] = 0x1; 6804} 6805 6806static void 6807Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6808{ 6809 slotbuf[0] = 0x2; 6810} 6811 6812static void 6813Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) 6814{ 6815 slotbuf[0] = 0x8076; 6816} 6817 6818static void 6819Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6820{ 6821 slotbuf[0] = 0x9076; 6822} 6823 6824static void 6825Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6826{ 6827 slotbuf[0] = 0xa076; 6828} 6829 6830static void 6831Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6832{ 6833 slotbuf[0] = 0xa002; 6834} 6835 6836static void 6837Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6838{ 6839 slotbuf[0] = 0x830000; 6840} 6841 6842static void 6843Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6844{ 6845 slotbuf[0] = 0x930000; 6846} 6847 6848static void 6849Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6850{ 6851 slotbuf[0] = 0xa30000; 6852} 6853 6854static void 6855Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6856{ 6857 slotbuf[0] = 0xb30000; 6858} 6859 6860static void 6861Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6862{ 6863 slotbuf[0] = 0x600000; 6864} 6865 6866static void 6867Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) 6868{ 6869 slotbuf[0] = 0x600100; 6870} 6871 6872static void 6873Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) 6874{ 6875 slotbuf[0] = 0x20f0; 6876} 6877 6878static void 6879Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) 6880{ 6881 slotbuf[0] = 0x80; 6882} 6883 6884static void 6885Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6886{ 6887 slotbuf[0] = 0x5002; 6888} 6889 6890static void 6891Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6892{ 6893 slotbuf[0] = 0x6002; 6894} 6895 6896static void 6897Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6898{ 6899 slotbuf[0] = 0x4002; 6900} 6901 6902static void 6903Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6904{ 6905 slotbuf[0] = 0x400000; 6906} 6907 6908static void 6909Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) 6910{ 6911 slotbuf[0] = 0x401000; 6912} 6913 6914static void 6915Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) 6916{ 6917 slotbuf[0] = 0x402000; 6918} 6919 6920static void 6921Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) 6922{ 6923 slotbuf[0] = 0x403000; 6924} 6925 6926static void 6927Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) 6928{ 6929 slotbuf[0] = 0x404000; 6930} 6931 6932static void 6933Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) 6934{ 6935 slotbuf[0] = 0xa10000; 6936} 6937 6938static void 6939Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) 6940{ 6941 slotbuf[0] = 0x810000; 6942} 6943 6944static void 6945Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) 6946{ 6947 slotbuf[0] = 0x910000; 6948} 6949 6950static void 6951Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) 6952{ 6953 slotbuf[0] = 0xb10000; 6954} 6955 6956static void 6957Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) 6958{ 6959 slotbuf[0] = 0x10000; 6960} 6961 6962static void 6963Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) 6964{ 6965 slotbuf[0] = 0x210000; 6966} 6967 6968static void 6969Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) 6970{ 6971 slotbuf[0] = 0x410000; 6972} 6973 6974static void 6975Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6976{ 6977 slotbuf[0] = 0x20c0; 6978} 6979 6980static void 6981Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6982{ 6983 slotbuf[0] = 0x20d0; 6984} 6985 6986static void 6987Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) 6988{ 6989 slotbuf[0] = 0x2000; 6990} 6991 6992static void 6993Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 6994{ 6995 slotbuf[0] = 0x2010; 6996} 6997 6998static void 6999Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) 7000{ 7001 slotbuf[0] = 0x2020; 7002} 7003 7004static void 7005Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 7006{ 7007 slotbuf[0] = 0x2030; 7008} 7009 7010static void 7011Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) 7012{ 7013 slotbuf[0] = 0x6000; 7014} 7015 7016static void 7017Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 7018{ 7019 slotbuf[0] = 0x30100; 7020} 7021 7022static void 7023Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 7024{ 7025 slotbuf[0] = 0x130100; 7026} 7027 7028static void 7029Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 7030{ 7031 slotbuf[0] = 0x610100; 7032} 7033 7034static void 7035Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 7036{ 7037 slotbuf[0] = 0x30200; 7038} 7039 7040static void 7041Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 7042{ 7043 slotbuf[0] = 0x130200; 7044} 7045 7046static void 7047Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 7048{ 7049 slotbuf[0] = 0x610200; 7050} 7051 7052static void 7053Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 7054{ 7055 slotbuf[0] = 0x30000; 7056} 7057 7058static void 7059Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 7060{ 7061 slotbuf[0] = 0x130000; 7062} 7063 7064static void 7065Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 7066{ 7067 slotbuf[0] = 0x610000; 7068} 7069 7070static void 7071Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 7072{ 7073 slotbuf[0] = 0x30300; 7074} 7075 7076static void 7077Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 7078{ 7079 slotbuf[0] = 0x130300; 7080} 7081 7082static void 7083Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 7084{ 7085 slotbuf[0] = 0x610300; 7086} 7087 7088static void 7089Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7090{ 7091 slotbuf[0] = 0x30500; 7092} 7093 7094static void 7095Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7096{ 7097 slotbuf[0] = 0x130500; 7098} 7099 7100static void 7101Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7102{ 7103 slotbuf[0] = 0x610500; 7104} 7105 7106static void 7107Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) 7108{ 7109 slotbuf[0] = 0x3b000; 7110} 7111 7112static void 7113Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) 7114{ 7115 slotbuf[0] = 0x3d000; 7116} 7117 7118static void 7119Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 7120{ 7121 slotbuf[0] = 0x3e600; 7122} 7123 7124static void 7125Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 7126{ 7127 slotbuf[0] = 0x13e600; 7128} 7129 7130static void 7131Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 7132{ 7133 slotbuf[0] = 0x61e600; 7134} 7135 7136static void 7137Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7138{ 7139 slotbuf[0] = 0x3b100; 7140} 7141 7142static void 7143Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7144{ 7145 slotbuf[0] = 0x13b100; 7146} 7147 7148static void 7149Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7150{ 7151 slotbuf[0] = 0x61b100; 7152} 7153 7154static void 7155Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7156{ 7157 slotbuf[0] = 0x3d100; 7158} 7159 7160static void 7161Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7162{ 7163 slotbuf[0] = 0x13d100; 7164} 7165 7166static void 7167Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7168{ 7169 slotbuf[0] = 0x61d100; 7170} 7171 7172static void 7173Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7174{ 7175 slotbuf[0] = 0x3b200; 7176} 7177 7178static void 7179Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7180{ 7181 slotbuf[0] = 0x13b200; 7182} 7183 7184static void 7185Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7186{ 7187 slotbuf[0] = 0x61b200; 7188} 7189 7190static void 7191Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7192{ 7193 slotbuf[0] = 0x3d200; 7194} 7195 7196static void 7197Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7198{ 7199 slotbuf[0] = 0x13d200; 7200} 7201 7202static void 7203Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7204{ 7205 slotbuf[0] = 0x61d200; 7206} 7207 7208static void 7209Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7210{ 7211 slotbuf[0] = 0x3b300; 7212} 7213 7214static void 7215Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7216{ 7217 slotbuf[0] = 0x13b300; 7218} 7219 7220static void 7221Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7222{ 7223 slotbuf[0] = 0x61b300; 7224} 7225 7226static void 7227Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7228{ 7229 slotbuf[0] = 0x3d300; 7230} 7231 7232static void 7233Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7234{ 7235 slotbuf[0] = 0x13d300; 7236} 7237 7238static void 7239Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7240{ 7241 slotbuf[0] = 0x61d300; 7242} 7243 7244static void 7245Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7246{ 7247 slotbuf[0] = 0x3b400; 7248} 7249 7250static void 7251Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7252{ 7253 slotbuf[0] = 0x13b400; 7254} 7255 7256static void 7257Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7258{ 7259 slotbuf[0] = 0x61b400; 7260} 7261 7262static void 7263Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7264{ 7265 slotbuf[0] = 0x3d400; 7266} 7267 7268static void 7269Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7270{ 7271 slotbuf[0] = 0x13d400; 7272} 7273 7274static void 7275Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7276{ 7277 slotbuf[0] = 0x61d400; 7278} 7279 7280static void 7281Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7282{ 7283 slotbuf[0] = 0x3b500; 7284} 7285 7286static void 7287Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7288{ 7289 slotbuf[0] = 0x13b500; 7290} 7291 7292static void 7293Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7294{ 7295 slotbuf[0] = 0x61b500; 7296} 7297 7298static void 7299Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7300{ 7301 slotbuf[0] = 0x3d500; 7302} 7303 7304static void 7305Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7306{ 7307 slotbuf[0] = 0x13d500; 7308} 7309 7310static void 7311Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7312{ 7313 slotbuf[0] = 0x61d500; 7314} 7315 7316static void 7317Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7318{ 7319 slotbuf[0] = 0x3b600; 7320} 7321 7322static void 7323Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7324{ 7325 slotbuf[0] = 0x13b600; 7326} 7327 7328static void 7329Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7330{ 7331 slotbuf[0] = 0x61b600; 7332} 7333 7334static void 7335Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7336{ 7337 slotbuf[0] = 0x3d600; 7338} 7339 7340static void 7341Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7342{ 7343 slotbuf[0] = 0x13d600; 7344} 7345 7346static void 7347Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7348{ 7349 slotbuf[0] = 0x61d600; 7350} 7351 7352static void 7353Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7354{ 7355 slotbuf[0] = 0x3b700; 7356} 7357 7358static void 7359Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7360{ 7361 slotbuf[0] = 0x13b700; 7362} 7363 7364static void 7365Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7366{ 7367 slotbuf[0] = 0x61b700; 7368} 7369 7370static void 7371Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7372{ 7373 slotbuf[0] = 0x3d700; 7374} 7375 7376static void 7377Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7378{ 7379 slotbuf[0] = 0x13d700; 7380} 7381 7382static void 7383Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7384{ 7385 slotbuf[0] = 0x61d700; 7386} 7387 7388static void 7389Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7390{ 7391 slotbuf[0] = 0x3c200; 7392} 7393 7394static void 7395Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7396{ 7397 slotbuf[0] = 0x13c200; 7398} 7399 7400static void 7401Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7402{ 7403 slotbuf[0] = 0x61c200; 7404} 7405 7406static void 7407Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7408{ 7409 slotbuf[0] = 0x3c300; 7410} 7411 7412static void 7413Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7414{ 7415 slotbuf[0] = 0x13c300; 7416} 7417 7418static void 7419Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7420{ 7421 slotbuf[0] = 0x61c300; 7422} 7423 7424static void 7425Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7426{ 7427 slotbuf[0] = 0x3c400; 7428} 7429 7430static void 7431Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7432{ 7433 slotbuf[0] = 0x13c400; 7434} 7435 7436static void 7437Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7438{ 7439 slotbuf[0] = 0x61c400; 7440} 7441 7442static void 7443Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7444{ 7445 slotbuf[0] = 0x3c500; 7446} 7447 7448static void 7449Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7450{ 7451 slotbuf[0] = 0x13c500; 7452} 7453 7454static void 7455Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7456{ 7457 slotbuf[0] = 0x61c500; 7458} 7459 7460static void 7461Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7462{ 7463 slotbuf[0] = 0x3c600; 7464} 7465 7466static void 7467Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7468{ 7469 slotbuf[0] = 0x13c600; 7470} 7471 7472static void 7473Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7474{ 7475 slotbuf[0] = 0x61c600; 7476} 7477 7478static void 7479Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7480{ 7481 slotbuf[0] = 0x3c700; 7482} 7483 7484static void 7485Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7486{ 7487 slotbuf[0] = 0x13c700; 7488} 7489 7490static void 7491Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7492{ 7493 slotbuf[0] = 0x61c700; 7494} 7495 7496static void 7497Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 7498{ 7499 slotbuf[0] = 0x3ee00; 7500} 7501 7502static void 7503Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 7504{ 7505 slotbuf[0] = 0x13ee00; 7506} 7507 7508static void 7509Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 7510{ 7511 slotbuf[0] = 0x61ee00; 7512} 7513 7514static void 7515Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7516{ 7517 slotbuf[0] = 0x3c000; 7518} 7519 7520static void 7521Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7522{ 7523 slotbuf[0] = 0x13c000; 7524} 7525 7526static void 7527Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7528{ 7529 slotbuf[0] = 0x61c000; 7530} 7531 7532static void 7533Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 7534{ 7535 slotbuf[0] = 0x3e800; 7536} 7537 7538static void 7539Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 7540{ 7541 slotbuf[0] = 0x13e800; 7542} 7543 7544static void 7545Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 7546{ 7547 slotbuf[0] = 0x61e800; 7548} 7549 7550static void 7551Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7552{ 7553 slotbuf[0] = 0x3f400; 7554} 7555 7556static void 7557Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7558{ 7559 slotbuf[0] = 0x13f400; 7560} 7561 7562static void 7563Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7564{ 7565 slotbuf[0] = 0x61f400; 7566} 7567 7568static void 7569Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7570{ 7571 slotbuf[0] = 0x3f500; 7572} 7573 7574static void 7575Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7576{ 7577 slotbuf[0] = 0x13f500; 7578} 7579 7580static void 7581Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7582{ 7583 slotbuf[0] = 0x61f500; 7584} 7585 7586static void 7587Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) 7588{ 7589 slotbuf[0] = 0x3eb00; 7590} 7591 7592static void 7593Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7594{ 7595 slotbuf[0] = 0x3e700; 7596} 7597 7598static void 7599Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7600{ 7601 slotbuf[0] = 0x13e700; 7602} 7603 7604static void 7605Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7606{ 7607 slotbuf[0] = 0x61e700; 7608} 7609 7610static void 7611Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7612{ 7613 slotbuf[0] = 0x740004; 7614} 7615 7616static void 7617Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7618{ 7619 slotbuf[0] = 0x750004; 7620} 7621 7622static void 7623Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7624{ 7625 slotbuf[0] = 0x760004; 7626} 7627 7628static void 7629Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7630{ 7631 slotbuf[0] = 0x770004; 7632} 7633 7634static void 7635Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7636{ 7637 slotbuf[0] = 0x700004; 7638} 7639 7640static void 7641Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7642{ 7643 slotbuf[0] = 0x710004; 7644} 7645 7646static void 7647Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7648{ 7649 slotbuf[0] = 0x720004; 7650} 7651 7652static void 7653Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7654{ 7655 slotbuf[0] = 0x730004; 7656} 7657 7658static void 7659Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7660{ 7661 slotbuf[0] = 0x340004; 7662} 7663 7664static void 7665Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7666{ 7667 slotbuf[0] = 0x350004; 7668} 7669 7670static void 7671Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7672{ 7673 slotbuf[0] = 0x360004; 7674} 7675 7676static void 7677Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7678{ 7679 slotbuf[0] = 0x370004; 7680} 7681 7682static void 7683Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7684{ 7685 slotbuf[0] = 0x640004; 7686} 7687 7688static void 7689Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7690{ 7691 slotbuf[0] = 0x650004; 7692} 7693 7694static void 7695Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7696{ 7697 slotbuf[0] = 0x660004; 7698} 7699 7700static void 7701Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7702{ 7703 slotbuf[0] = 0x670004; 7704} 7705 7706static void 7707Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7708{ 7709 slotbuf[0] = 0x240004; 7710} 7711 7712static void 7713Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7714{ 7715 slotbuf[0] = 0x250004; 7716} 7717 7718static void 7719Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7720{ 7721 slotbuf[0] = 0x260004; 7722} 7723 7724static void 7725Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7726{ 7727 slotbuf[0] = 0x270004; 7728} 7729 7730static void 7731Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7732{ 7733 slotbuf[0] = 0x780004; 7734} 7735 7736static void 7737Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7738{ 7739 slotbuf[0] = 0x790004; 7740} 7741 7742static void 7743Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7744{ 7745 slotbuf[0] = 0x7a0004; 7746} 7747 7748static void 7749Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7750{ 7751 slotbuf[0] = 0x7b0004; 7752} 7753 7754static void 7755Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7756{ 7757 slotbuf[0] = 0x7c0004; 7758} 7759 7760static void 7761Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7762{ 7763 slotbuf[0] = 0x7d0004; 7764} 7765 7766static void 7767Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7768{ 7769 slotbuf[0] = 0x7e0004; 7770} 7771 7772static void 7773Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7774{ 7775 slotbuf[0] = 0x7f0004; 7776} 7777 7778static void 7779Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7780{ 7781 slotbuf[0] = 0x380004; 7782} 7783 7784static void 7785Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7786{ 7787 slotbuf[0] = 0x390004; 7788} 7789 7790static void 7791Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7792{ 7793 slotbuf[0] = 0x3a0004; 7794} 7795 7796static void 7797Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7798{ 7799 slotbuf[0] = 0x3b0004; 7800} 7801 7802static void 7803Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7804{ 7805 slotbuf[0] = 0x3c0004; 7806} 7807 7808static void 7809Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7810{ 7811 slotbuf[0] = 0x3d0004; 7812} 7813 7814static void 7815Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7816{ 7817 slotbuf[0] = 0x3e0004; 7818} 7819 7820static void 7821Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7822{ 7823 slotbuf[0] = 0x3f0004; 7824} 7825 7826static void 7827Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7828{ 7829 slotbuf[0] = 0x680004; 7830} 7831 7832static void 7833Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7834{ 7835 slotbuf[0] = 0x690004; 7836} 7837 7838static void 7839Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7840{ 7841 slotbuf[0] = 0x6a0004; 7842} 7843 7844static void 7845Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7846{ 7847 slotbuf[0] = 0x6b0004; 7848} 7849 7850static void 7851Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7852{ 7853 slotbuf[0] = 0x6c0004; 7854} 7855 7856static void 7857Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7858{ 7859 slotbuf[0] = 0x6d0004; 7860} 7861 7862static void 7863Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7864{ 7865 slotbuf[0] = 0x6e0004; 7866} 7867 7868static void 7869Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7870{ 7871 slotbuf[0] = 0x6f0004; 7872} 7873 7874static void 7875Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7876{ 7877 slotbuf[0] = 0x280004; 7878} 7879 7880static void 7881Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7882{ 7883 slotbuf[0] = 0x290004; 7884} 7885 7886static void 7887Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7888{ 7889 slotbuf[0] = 0x2a0004; 7890} 7891 7892static void 7893Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7894{ 7895 slotbuf[0] = 0x2b0004; 7896} 7897 7898static void 7899Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7900{ 7901 slotbuf[0] = 0x2c0004; 7902} 7903 7904static void 7905Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7906{ 7907 slotbuf[0] = 0x2d0004; 7908} 7909 7910static void 7911Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7912{ 7913 slotbuf[0] = 0x2e0004; 7914} 7915 7916static void 7917Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7918{ 7919 slotbuf[0] = 0x2f0004; 7920} 7921 7922static void 7923Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7924{ 7925 slotbuf[0] = 0x580004; 7926} 7927 7928static void 7929Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7930{ 7931 slotbuf[0] = 0x480004; 7932} 7933 7934static void 7935Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7936{ 7937 slotbuf[0] = 0x590004; 7938} 7939 7940static void 7941Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7942{ 7943 slotbuf[0] = 0x490004; 7944} 7945 7946static void 7947Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7948{ 7949 slotbuf[0] = 0x5a0004; 7950} 7951 7952static void 7953Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7954{ 7955 slotbuf[0] = 0x4a0004; 7956} 7957 7958static void 7959Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7960{ 7961 slotbuf[0] = 0x5b0004; 7962} 7963 7964static void 7965Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7966{ 7967 slotbuf[0] = 0x4b0004; 7968} 7969 7970static void 7971Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7972{ 7973 slotbuf[0] = 0x180004; 7974} 7975 7976static void 7977Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7978{ 7979 slotbuf[0] = 0x80004; 7980} 7981 7982static void 7983Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7984{ 7985 slotbuf[0] = 0x190004; 7986} 7987 7988static void 7989Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7990{ 7991 slotbuf[0] = 0x90004; 7992} 7993 7994static void 7995Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7996{ 7997 slotbuf[0] = 0x1a0004; 7998} 7999 8000static void 8001Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8002{ 8003 slotbuf[0] = 0xa0004; 8004} 8005 8006static void 8007Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8008{ 8009 slotbuf[0] = 0x1b0004; 8010} 8011 8012static void 8013Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8014{ 8015 slotbuf[0] = 0xb0004; 8016} 8017 8018static void 8019Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8020{ 8021 slotbuf[0] = 0x900004; 8022} 8023 8024static void 8025Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8026{ 8027 slotbuf[0] = 0x800004; 8028} 8029 8030static void 8031Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) 8032{ 8033 slotbuf[0] = 0xc10000; 8034} 8035 8036static void 8037Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) 8038{ 8039 slotbuf[0] = 0xd10000; 8040} 8041 8042static void 8043Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8044{ 8045 slotbuf[0] = 0x32000; 8046} 8047 8048static void 8049Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8050{ 8051 slotbuf[0] = 0x132000; 8052} 8053 8054static void 8055Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8056{ 8057 slotbuf[0] = 0x612000; 8058} 8059 8060static void 8061Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8062{ 8063 slotbuf[0] = 0x32100; 8064} 8065 8066static void 8067Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8068{ 8069 slotbuf[0] = 0x132100; 8070} 8071 8072static void 8073Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8074{ 8075 slotbuf[0] = 0x612100; 8076} 8077 8078static void 8079Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8080{ 8081 slotbuf[0] = 0x32200; 8082} 8083 8084static void 8085Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8086{ 8087 slotbuf[0] = 0x132200; 8088} 8089 8090static void 8091Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8092{ 8093 slotbuf[0] = 0x612200; 8094} 8095 8096static void 8097Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 8098{ 8099 slotbuf[0] = 0x32300; 8100} 8101 8102static void 8103Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 8104{ 8105 slotbuf[0] = 0x132300; 8106} 8107 8108static void 8109Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 8110{ 8111 slotbuf[0] = 0x612300; 8112} 8113 8114static void 8115Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8116{ 8117 slotbuf[0] = 0x31000; 8118} 8119 8120static void 8121Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8122{ 8123 slotbuf[0] = 0x131000; 8124} 8125 8126static void 8127Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8128{ 8129 slotbuf[0] = 0x611000; 8130} 8131 8132static void 8133Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8134{ 8135 slotbuf[0] = 0x31100; 8136} 8137 8138static void 8139Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8140{ 8141 slotbuf[0] = 0x131100; 8142} 8143 8144static void 8145Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8146{ 8147 slotbuf[0] = 0x611100; 8148} 8149 8150static void 8151Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8152{ 8153 slotbuf[0] = 0x3010; 8154} 8155 8156static void 8157Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) 8158{ 8159 slotbuf[0] = 0x7000; 8160} 8161 8162static void 8163Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) 8164{ 8165 slotbuf[0] = 0x3e200; 8166} 8167 8168static void 8169Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) 8170{ 8171 slotbuf[0] = 0x13e200; 8172} 8173 8174static void 8175Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) 8176{ 8177 slotbuf[0] = 0x13e300; 8178} 8179 8180static void 8181Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8182{ 8183 slotbuf[0] = 0x3e400; 8184} 8185 8186static void 8187Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8188{ 8189 slotbuf[0] = 0x13e400; 8190} 8191 8192static void 8193Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8194{ 8195 slotbuf[0] = 0x61e400; 8196} 8197 8198static void 8199Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) 8200{ 8201 slotbuf[0] = 0x4000; 8202} 8203 8204static void 8205Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 8206{ 8207 slotbuf[0] = 0xf02d; 8208} 8209 8210static void 8211Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8212{ 8213 slotbuf[0] = 0x39000; 8214} 8215 8216static void 8217Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8218{ 8219 slotbuf[0] = 0x139000; 8220} 8221 8222static void 8223Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8224{ 8225 slotbuf[0] = 0x619000; 8226} 8227 8228static void 8229Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8230{ 8231 slotbuf[0] = 0x3a000; 8232} 8233 8234static void 8235Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8236{ 8237 slotbuf[0] = 0x13a000; 8238} 8239 8240static void 8241Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8242{ 8243 slotbuf[0] = 0x61a000; 8244} 8245 8246static void 8247Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8248{ 8249 slotbuf[0] = 0x39100; 8250} 8251 8252static void 8253Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8254{ 8255 slotbuf[0] = 0x139100; 8256} 8257 8258static void 8259Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8260{ 8261 slotbuf[0] = 0x619100; 8262} 8263 8264static void 8265Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8266{ 8267 slotbuf[0] = 0x3a100; 8268} 8269 8270static void 8271Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8272{ 8273 slotbuf[0] = 0x13a100; 8274} 8275 8276static void 8277Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8278{ 8279 slotbuf[0] = 0x61a100; 8280} 8281 8282static void 8283Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8284{ 8285 slotbuf[0] = 0x38000; 8286} 8287 8288static void 8289Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8290{ 8291 slotbuf[0] = 0x138000; 8292} 8293 8294static void 8295Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8296{ 8297 slotbuf[0] = 0x618000; 8298} 8299 8300static void 8301Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8302{ 8303 slotbuf[0] = 0x38100; 8304} 8305 8306static void 8307Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8308{ 8309 slotbuf[0] = 0x138100; 8310} 8311 8312static void 8313Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8314{ 8315 slotbuf[0] = 0x618100; 8316} 8317 8318static void 8319Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8320{ 8321 slotbuf[0] = 0x36000; 8322} 8323 8324static void 8325Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8326{ 8327 slotbuf[0] = 0x136000; 8328} 8329 8330static void 8331Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8332{ 8333 slotbuf[0] = 0x616000; 8334} 8335 8336static void 8337Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 8338{ 8339 slotbuf[0] = 0x3e900; 8340} 8341 8342static void 8343Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 8344{ 8345 slotbuf[0] = 0x13e900; 8346} 8347 8348static void 8349Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 8350{ 8351 slotbuf[0] = 0x61e900; 8352} 8353 8354static void 8355Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8356{ 8357 slotbuf[0] = 0x3ec00; 8358} 8359 8360static void 8361Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8362{ 8363 slotbuf[0] = 0x13ec00; 8364} 8365 8366static void 8367Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8368{ 8369 slotbuf[0] = 0x61ec00; 8370} 8371 8372static void 8373Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 8374{ 8375 slotbuf[0] = 0x3ed00; 8376} 8377 8378static void 8379Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 8380{ 8381 slotbuf[0] = 0x13ed00; 8382} 8383 8384static void 8385Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 8386{ 8387 slotbuf[0] = 0x61ed00; 8388} 8389 8390static void 8391Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8392{ 8393 slotbuf[0] = 0x36800; 8394} 8395 8396static void 8397Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8398{ 8399 slotbuf[0] = 0x136800; 8400} 8401 8402static void 8403Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8404{ 8405 slotbuf[0] = 0x616800; 8406} 8407 8408static void 8409Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8410{ 8411 slotbuf[0] = 0xf1e000; 8412} 8413 8414static void 8415Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) 8416{ 8417 slotbuf[0] = 0xf1e010; 8418} 8419 8420static void 8421Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) 8422{ 8423 slotbuf[0] = 0x135900; 8424} 8425 8426static void 8427Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8428{ 8429 slotbuf[0] = 0x3ea00; 8430} 8431 8432static void 8433Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8434{ 8435 slotbuf[0] = 0x13ea00; 8436} 8437 8438static void 8439Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8440{ 8441 slotbuf[0] = 0x61ea00; 8442} 8443 8444static void 8445Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8446{ 8447 slotbuf[0] = 0x3f000; 8448} 8449 8450static void 8451Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8452{ 8453 slotbuf[0] = 0x13f000; 8454} 8455 8456static void 8457Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8458{ 8459 slotbuf[0] = 0x61f000; 8460} 8461 8462static void 8463Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8464{ 8465 slotbuf[0] = 0x3f100; 8466} 8467 8468static void 8469Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8470{ 8471 slotbuf[0] = 0x13f100; 8472} 8473 8474static void 8475Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8476{ 8477 slotbuf[0] = 0x61f100; 8478} 8479 8480static void 8481Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8482{ 8483 slotbuf[0] = 0x3f200; 8484} 8485 8486static void 8487Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8488{ 8489 slotbuf[0] = 0x13f200; 8490} 8491 8492static void 8493Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8494{ 8495 slotbuf[0] = 0x61f200; 8496} 8497 8498static void 8499Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) 8500{ 8501 slotbuf[0] = 0x70c2; 8502} 8503 8504static void 8505Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8506{ 8507 slotbuf[0] = 0x70e2; 8508} 8509 8510static void 8511Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8512{ 8513 slotbuf[0] = 0x70d2; 8514} 8515 8516static void 8517Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8518{ 8519 slotbuf[0] = 0x270d2; 8520} 8521 8522static void 8523Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8524{ 8525 slotbuf[0] = 0x370d2; 8526} 8527 8528static void 8529Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) 8530{ 8531 slotbuf[0] = 0x70f2; 8532} 8533 8534static void 8535Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) 8536{ 8537 slotbuf[0] = 0xf10000; 8538} 8539 8540static void 8541Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) 8542{ 8543 slotbuf[0] = 0xf12000; 8544} 8545 8546static void 8547Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) 8548{ 8549 slotbuf[0] = 0xf11000; 8550} 8551 8552static void 8553Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) 8554{ 8555 slotbuf[0] = 0xf13000; 8556} 8557 8558static void 8559Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8560{ 8561 slotbuf[0] = 0x7042; 8562} 8563 8564static void 8565Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8566{ 8567 slotbuf[0] = 0x7052; 8568} 8569 8570static void 8571Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8572{ 8573 slotbuf[0] = 0x47082; 8574} 8575 8576static void 8577Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8578{ 8579 slotbuf[0] = 0x57082; 8580} 8581 8582static void 8583Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8584{ 8585 slotbuf[0] = 0x7062; 8586} 8587 8588static void 8589Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) 8590{ 8591 slotbuf[0] = 0x7072; 8592} 8593 8594static void 8595Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8596{ 8597 slotbuf[0] = 0x7002; 8598} 8599 8600static void 8601Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) 8602{ 8603 slotbuf[0] = 0x7012; 8604} 8605 8606static void 8607Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) 8608{ 8609 slotbuf[0] = 0x7022; 8610} 8611 8612static void 8613Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8614{ 8615 slotbuf[0] = 0x7032; 8616} 8617 8618static void 8619Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8620{ 8621 slotbuf[0] = 0x7082; 8622} 8623 8624static void 8625Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8626{ 8627 slotbuf[0] = 0x27082; 8628} 8629 8630static void 8631Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8632{ 8633 slotbuf[0] = 0x37082; 8634} 8635 8636static void 8637Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) 8638{ 8639 slotbuf[0] = 0xf19000; 8640} 8641 8642static void 8643Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) 8644{ 8645 slotbuf[0] = 0xf18000; 8646} 8647 8648static void 8649Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8650{ 8651 slotbuf[0] = 0x135300; 8652} 8653 8654static void 8655Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8656{ 8657 slotbuf[0] = 0x35300; 8658} 8659 8660static void 8661Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8662{ 8663 slotbuf[0] = 0x615300; 8664} 8665 8666static void 8667Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 8668{ 8669 slotbuf[0] = 0x35a00; 8670} 8671 8672static void 8673Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 8674{ 8675 slotbuf[0] = 0x135a00; 8676} 8677 8678static void 8679Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 8680{ 8681 slotbuf[0] = 0x615a00; 8682} 8683 8684static void 8685Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8686{ 8687 slotbuf[0] = 0x35b00; 8688} 8689 8690static void 8691Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8692{ 8693 slotbuf[0] = 0x135b00; 8694} 8695 8696static void 8697Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8698{ 8699 slotbuf[0] = 0x615b00; 8700} 8701 8702static void 8703Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8704{ 8705 slotbuf[0] = 0x35c00; 8706} 8707 8708static void 8709Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8710{ 8711 slotbuf[0] = 0x135c00; 8712} 8713 8714static void 8715Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8716{ 8717 slotbuf[0] = 0x615c00; 8718} 8719 8720static void 8721Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8722{ 8723 slotbuf[0] = 0x50c000; 8724} 8725 8726static void 8727Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8728{ 8729 slotbuf[0] = 0x50d000; 8730} 8731 8732static void 8733Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8734{ 8735 slotbuf[0] = 0x50b000; 8736} 8737 8738static void 8739Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8740{ 8741 slotbuf[0] = 0x50f000; 8742} 8743 8744static void 8745Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8746{ 8747 slotbuf[0] = 0x50e000; 8748} 8749 8750static void 8751Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8752{ 8753 slotbuf[0] = 0x504000; 8754} 8755 8756static void 8757Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8758{ 8759 slotbuf[0] = 0x505000; 8760} 8761 8762static void 8763Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8764{ 8765 slotbuf[0] = 0x503000; 8766} 8767 8768static void 8769Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8770{ 8771 slotbuf[0] = 0x507000; 8772} 8773 8774static void 8775Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8776{ 8777 slotbuf[0] = 0x506000; 8778} 8779 8780static void 8781Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) 8782{ 8783 slotbuf[0] = 0xf1f000; 8784} 8785 8786static void 8787Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 8788{ 8789 slotbuf[0] = 0x501000; 8790} 8791 8792static void 8793Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 8794{ 8795 slotbuf[0] = 0x509000; 8796} 8797 8798static void 8799Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8800{ 8801 slotbuf[0] = 0x3e000; 8802} 8803 8804static void 8805Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8806{ 8807 slotbuf[0] = 0x13e000; 8808} 8809 8810static void 8811Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8812{ 8813 slotbuf[0] = 0x61e000; 8814} 8815 8816static void 8817Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) 8818{ 8819 slotbuf[0] = 0x330000; 8820} 8821 8822static void 8823Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) 8824{ 8825 slotbuf[0] = 0x430000; 8826} 8827 8828static void 8829Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) 8830{ 8831 slotbuf[0] = 0x530000; 8832} 8833 8834static void 8835Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8836{ 8837 slotbuf[0] = 0x630000; 8838} 8839 8840static void 8841Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8842{ 8843 slotbuf[0] = 0x730000; 8844} 8845 8846static void 8847Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) 8848{ 8849 slotbuf[0] = 0x40e000; 8850} 8851 8852static void 8853Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) 8854{ 8855 slotbuf[0] = 0x40f000; 8856} 8857 8858static void 8859Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) 8860{ 8861 slotbuf[0] = 0x230000; 8862} 8863 8864static void 8865Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) 8866{ 8867 slotbuf[0] = 0xb002; 8868} 8869 8870static void 8871Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) 8872{ 8873 slotbuf[0] = 0xf002; 8874} 8875 8876static void 8877Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) 8878{ 8879 slotbuf[0] = 0xe002; 8880} 8881 8882static void 8883Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8884{ 8885 slotbuf[0] = 0x30c00; 8886} 8887 8888static void 8889Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8890{ 8891 slotbuf[0] = 0x130c00; 8892} 8893 8894static void 8895Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8896{ 8897 slotbuf[0] = 0x610c00; 8898} 8899 8900static void 8901Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) 8902{ 8903 slotbuf[0] = 0xc20000; 8904} 8905 8906static void 8907Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) 8908{ 8909 slotbuf[0] = 0xd20000; 8910} 8911 8912static void 8913Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8914{ 8915 slotbuf[0] = 0xe20000; 8916} 8917 8918static void 8919Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) 8920{ 8921 slotbuf[0] = 0xf20000; 8922} 8923 8924static void 8925Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) 8926{ 8927 slotbuf[0] = 0x820000; 8928} 8929 8930static void 8931Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8932{ 8933 slotbuf[0] = 0xe30e60; 8934} 8935 8936static void 8937Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8938{ 8939 slotbuf[0] = 0xf3e600; 8940} 8941 8942static void 8943Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) 8944{ 8945 slotbuf[0] = 0xe0000; 8946} 8947 8948static void 8949Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8950{ 8951 slotbuf[0] = 0xe1000; 8952} 8953 8954static void 8955Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8956{ 8957 slotbuf[0] = 0xe1200; 8958} 8959 8960static void 8961Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8962{ 8963 slotbuf[0] = 0xe2000; 8964} 8965 8966static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { 8967 Opcode_excw_Slot_inst_encode, 0, 0 8968}; 8969 8970static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { 8971 Opcode_rfe_Slot_inst_encode, 0, 0 8972}; 8973 8974static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { 8975 Opcode_rfde_Slot_inst_encode, 0, 0 8976}; 8977 8978static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { 8979 Opcode_syscall_Slot_inst_encode, 0, 0 8980}; 8981 8982static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { 8983 Opcode_simcall_Slot_inst_encode, 0, 0 8984}; 8985 8986static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { 8987 Opcode_call12_Slot_inst_encode, 0, 0 8988}; 8989 8990static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { 8991 Opcode_call8_Slot_inst_encode, 0, 0 8992}; 8993 8994static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { 8995 Opcode_call4_Slot_inst_encode, 0, 0 8996}; 8997 8998static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { 8999 Opcode_callx12_Slot_inst_encode, 0, 0 9000}; 9001 9002static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { 9003 Opcode_callx8_Slot_inst_encode, 0, 0 9004}; 9005 9006static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { 9007 Opcode_callx4_Slot_inst_encode, 0, 0 9008}; 9009 9010static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { 9011 Opcode_entry_Slot_inst_encode, 0, 0 9012}; 9013 9014static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { 9015 Opcode_movsp_Slot_inst_encode, 0, 0 9016}; 9017 9018static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { 9019 Opcode_rotw_Slot_inst_encode, 0, 0 9020}; 9021 9022static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { 9023 Opcode_retw_Slot_inst_encode, 0, 0 9024}; 9025 9026static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { 9027 0, 0, Opcode_retw_n_Slot_inst16b_encode 9028}; 9029 9030static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { 9031 Opcode_rfwo_Slot_inst_encode, 0, 0 9032}; 9033 9034static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { 9035 Opcode_rfwu_Slot_inst_encode, 0, 0 9036}; 9037 9038static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { 9039 Opcode_l32e_Slot_inst_encode, 0, 0 9040}; 9041 9042static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { 9043 Opcode_s32e_Slot_inst_encode, 0, 0 9044}; 9045 9046static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { 9047 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 9048}; 9049 9050static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { 9051 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 9052}; 9053 9054static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { 9055 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 9056}; 9057 9058static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { 9059 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 9060}; 9061 9062static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { 9063 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 9064}; 9065 9066static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { 9067 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 9068}; 9069 9070static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { 9071 0, Opcode_add_n_Slot_inst16a_encode, 0 9072}; 9073 9074static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { 9075 0, Opcode_addi_n_Slot_inst16a_encode, 0 9076}; 9077 9078static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { 9079 0, 0, Opcode_beqz_n_Slot_inst16b_encode 9080}; 9081 9082static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { 9083 0, 0, Opcode_bnez_n_Slot_inst16b_encode 9084}; 9085 9086static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { 9087 0, 0, Opcode_ill_n_Slot_inst16b_encode 9088}; 9089 9090static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { 9091 0, Opcode_l32i_n_Slot_inst16a_encode, 0 9092}; 9093 9094static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { 9095 0, 0, Opcode_mov_n_Slot_inst16b_encode 9096}; 9097 9098static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { 9099 0, 0, Opcode_movi_n_Slot_inst16b_encode 9100}; 9101 9102static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { 9103 0, 0, Opcode_nop_n_Slot_inst16b_encode 9104}; 9105 9106static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { 9107 0, 0, Opcode_ret_n_Slot_inst16b_encode 9108}; 9109 9110static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { 9111 0, Opcode_s32i_n_Slot_inst16a_encode, 0 9112}; 9113 9114static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { 9115 Opcode_rur_threadptr_Slot_inst_encode, 0, 0 9116}; 9117 9118static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { 9119 Opcode_wur_threadptr_Slot_inst_encode, 0, 0 9120}; 9121 9122static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { 9123 Opcode_addi_Slot_inst_encode, 0, 0 9124}; 9125 9126static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { 9127 Opcode_addmi_Slot_inst_encode, 0, 0 9128}; 9129 9130static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { 9131 Opcode_add_Slot_inst_encode, 0, 0 9132}; 9133 9134static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { 9135 Opcode_sub_Slot_inst_encode, 0, 0 9136}; 9137 9138static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { 9139 Opcode_addx2_Slot_inst_encode, 0, 0 9140}; 9141 9142static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { 9143 Opcode_addx4_Slot_inst_encode, 0, 0 9144}; 9145 9146static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { 9147 Opcode_addx8_Slot_inst_encode, 0, 0 9148}; 9149 9150static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { 9151 Opcode_subx2_Slot_inst_encode, 0, 0 9152}; 9153 9154static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { 9155 Opcode_subx4_Slot_inst_encode, 0, 0 9156}; 9157 9158static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { 9159 Opcode_subx8_Slot_inst_encode, 0, 0 9160}; 9161 9162static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { 9163 Opcode_and_Slot_inst_encode, 0, 0 9164}; 9165 9166static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { 9167 Opcode_or_Slot_inst_encode, 0, 0 9168}; 9169 9170static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { 9171 Opcode_xor_Slot_inst_encode, 0, 0 9172}; 9173 9174static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { 9175 Opcode_beqi_Slot_inst_encode, 0, 0 9176}; 9177 9178static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { 9179 Opcode_bnei_Slot_inst_encode, 0, 0 9180}; 9181 9182static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { 9183 Opcode_bgei_Slot_inst_encode, 0, 0 9184}; 9185 9186static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { 9187 Opcode_blti_Slot_inst_encode, 0, 0 9188}; 9189 9190static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { 9191 Opcode_bbci_Slot_inst_encode, 0, 0 9192}; 9193 9194static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { 9195 Opcode_bbsi_Slot_inst_encode, 0, 0 9196}; 9197 9198static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { 9199 Opcode_bgeui_Slot_inst_encode, 0, 0 9200}; 9201 9202static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { 9203 Opcode_bltui_Slot_inst_encode, 0, 0 9204}; 9205 9206static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { 9207 Opcode_beq_Slot_inst_encode, 0, 0 9208}; 9209 9210static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { 9211 Opcode_bne_Slot_inst_encode, 0, 0 9212}; 9213 9214static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { 9215 Opcode_bge_Slot_inst_encode, 0, 0 9216}; 9217 9218static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { 9219 Opcode_blt_Slot_inst_encode, 0, 0 9220}; 9221 9222static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { 9223 Opcode_bgeu_Slot_inst_encode, 0, 0 9224}; 9225 9226static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { 9227 Opcode_bltu_Slot_inst_encode, 0, 0 9228}; 9229 9230static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { 9231 Opcode_bany_Slot_inst_encode, 0, 0 9232}; 9233 9234static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { 9235 Opcode_bnone_Slot_inst_encode, 0, 0 9236}; 9237 9238static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { 9239 Opcode_ball_Slot_inst_encode, 0, 0 9240}; 9241 9242static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { 9243 Opcode_bnall_Slot_inst_encode, 0, 0 9244}; 9245 9246static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { 9247 Opcode_bbc_Slot_inst_encode, 0, 0 9248}; 9249 9250static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { 9251 Opcode_bbs_Slot_inst_encode, 0, 0 9252}; 9253 9254static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { 9255 Opcode_beqz_Slot_inst_encode, 0, 0 9256}; 9257 9258static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { 9259 Opcode_bnez_Slot_inst_encode, 0, 0 9260}; 9261 9262static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { 9263 Opcode_bgez_Slot_inst_encode, 0, 0 9264}; 9265 9266static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { 9267 Opcode_bltz_Slot_inst_encode, 0, 0 9268}; 9269 9270static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { 9271 Opcode_call0_Slot_inst_encode, 0, 0 9272}; 9273 9274static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { 9275 Opcode_callx0_Slot_inst_encode, 0, 0 9276}; 9277 9278static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { 9279 Opcode_extui_Slot_inst_encode, 0, 0 9280}; 9281 9282static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { 9283 Opcode_ill_Slot_inst_encode, 0, 0 9284}; 9285 9286static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { 9287 Opcode_j_Slot_inst_encode, 0, 0 9288}; 9289 9290static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { 9291 Opcode_jx_Slot_inst_encode, 0, 0 9292}; 9293 9294static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { 9295 Opcode_l16ui_Slot_inst_encode, 0, 0 9296}; 9297 9298static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { 9299 Opcode_l16si_Slot_inst_encode, 0, 0 9300}; 9301 9302static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { 9303 Opcode_l32i_Slot_inst_encode, 0, 0 9304}; 9305 9306static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { 9307 Opcode_l32r_Slot_inst_encode, 0, 0 9308}; 9309 9310static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { 9311 Opcode_l8ui_Slot_inst_encode, 0, 0 9312}; 9313 9314static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { 9315 Opcode_loop_Slot_inst_encode, 0, 0 9316}; 9317 9318static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { 9319 Opcode_loopnez_Slot_inst_encode, 0, 0 9320}; 9321 9322static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { 9323 Opcode_loopgtz_Slot_inst_encode, 0, 0 9324}; 9325 9326static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { 9327 Opcode_movi_Slot_inst_encode, 0, 0 9328}; 9329 9330static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { 9331 Opcode_moveqz_Slot_inst_encode, 0, 0 9332}; 9333 9334static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { 9335 Opcode_movnez_Slot_inst_encode, 0, 0 9336}; 9337 9338static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { 9339 Opcode_movltz_Slot_inst_encode, 0, 0 9340}; 9341 9342static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { 9343 Opcode_movgez_Slot_inst_encode, 0, 0 9344}; 9345 9346static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { 9347 Opcode_neg_Slot_inst_encode, 0, 0 9348}; 9349 9350static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { 9351 Opcode_abs_Slot_inst_encode, 0, 0 9352}; 9353 9354static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { 9355 Opcode_nop_Slot_inst_encode, 0, 0 9356}; 9357 9358static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { 9359 Opcode_ret_Slot_inst_encode, 0, 0 9360}; 9361 9362static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { 9363 Opcode_s16i_Slot_inst_encode, 0, 0 9364}; 9365 9366static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { 9367 Opcode_s32i_Slot_inst_encode, 0, 0 9368}; 9369 9370static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { 9371 Opcode_s8i_Slot_inst_encode, 0, 0 9372}; 9373 9374static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { 9375 Opcode_ssr_Slot_inst_encode, 0, 0 9376}; 9377 9378static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { 9379 Opcode_ssl_Slot_inst_encode, 0, 0 9380}; 9381 9382static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { 9383 Opcode_ssa8l_Slot_inst_encode, 0, 0 9384}; 9385 9386static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { 9387 Opcode_ssa8b_Slot_inst_encode, 0, 0 9388}; 9389 9390static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { 9391 Opcode_ssai_Slot_inst_encode, 0, 0 9392}; 9393 9394static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { 9395 Opcode_sll_Slot_inst_encode, 0, 0 9396}; 9397 9398static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { 9399 Opcode_src_Slot_inst_encode, 0, 0 9400}; 9401 9402static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { 9403 Opcode_srl_Slot_inst_encode, 0, 0 9404}; 9405 9406static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { 9407 Opcode_sra_Slot_inst_encode, 0, 0 9408}; 9409 9410static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { 9411 Opcode_slli_Slot_inst_encode, 0, 0 9412}; 9413 9414static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { 9415 Opcode_srai_Slot_inst_encode, 0, 0 9416}; 9417 9418static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { 9419 Opcode_srli_Slot_inst_encode, 0, 0 9420}; 9421 9422static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { 9423 Opcode_memw_Slot_inst_encode, 0, 0 9424}; 9425 9426static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { 9427 Opcode_extw_Slot_inst_encode, 0, 0 9428}; 9429 9430static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { 9431 Opcode_isync_Slot_inst_encode, 0, 0 9432}; 9433 9434static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { 9435 Opcode_rsync_Slot_inst_encode, 0, 0 9436}; 9437 9438static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { 9439 Opcode_esync_Slot_inst_encode, 0, 0 9440}; 9441 9442static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { 9443 Opcode_dsync_Slot_inst_encode, 0, 0 9444}; 9445 9446static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { 9447 Opcode_rsil_Slot_inst_encode, 0, 0 9448}; 9449 9450static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { 9451 Opcode_rsr_lend_Slot_inst_encode, 0, 0 9452}; 9453 9454static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { 9455 Opcode_wsr_lend_Slot_inst_encode, 0, 0 9456}; 9457 9458static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { 9459 Opcode_xsr_lend_Slot_inst_encode, 0, 0 9460}; 9461 9462static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { 9463 Opcode_rsr_lcount_Slot_inst_encode, 0, 0 9464}; 9465 9466static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { 9467 Opcode_wsr_lcount_Slot_inst_encode, 0, 0 9468}; 9469 9470static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { 9471 Opcode_xsr_lcount_Slot_inst_encode, 0, 0 9472}; 9473 9474static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { 9475 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 9476}; 9477 9478static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { 9479 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 9480}; 9481 9482static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { 9483 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 9484}; 9485 9486static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { 9487 Opcode_rsr_sar_Slot_inst_encode, 0, 0 9488}; 9489 9490static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { 9491 Opcode_wsr_sar_Slot_inst_encode, 0, 0 9492}; 9493 9494static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { 9495 Opcode_xsr_sar_Slot_inst_encode, 0, 0 9496}; 9497 9498static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { 9499 Opcode_rsr_litbase_Slot_inst_encode, 0, 0 9500}; 9501 9502static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { 9503 Opcode_wsr_litbase_Slot_inst_encode, 0, 0 9504}; 9505 9506static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { 9507 Opcode_xsr_litbase_Slot_inst_encode, 0, 0 9508}; 9509 9510static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { 9511 Opcode_rsr_176_Slot_inst_encode, 0, 0 9512}; 9513 9514static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { 9515 Opcode_rsr_208_Slot_inst_encode, 0, 0 9516}; 9517 9518static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { 9519 Opcode_rsr_ps_Slot_inst_encode, 0, 0 9520}; 9521 9522static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { 9523 Opcode_wsr_ps_Slot_inst_encode, 0, 0 9524}; 9525 9526static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { 9527 Opcode_xsr_ps_Slot_inst_encode, 0, 0 9528}; 9529 9530static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { 9531 Opcode_rsr_epc1_Slot_inst_encode, 0, 0 9532}; 9533 9534static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { 9535 Opcode_wsr_epc1_Slot_inst_encode, 0, 0 9536}; 9537 9538static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { 9539 Opcode_xsr_epc1_Slot_inst_encode, 0, 0 9540}; 9541 9542static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { 9543 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 9544}; 9545 9546static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { 9547 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 9548}; 9549 9550static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { 9551 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 9552}; 9553 9554static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { 9555 Opcode_rsr_epc2_Slot_inst_encode, 0, 0 9556}; 9557 9558static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { 9559 Opcode_wsr_epc2_Slot_inst_encode, 0, 0 9560}; 9561 9562static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { 9563 Opcode_xsr_epc2_Slot_inst_encode, 0, 0 9564}; 9565 9566static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { 9567 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 9568}; 9569 9570static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { 9571 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 9572}; 9573 9574static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { 9575 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 9576}; 9577 9578static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { 9579 Opcode_rsr_epc3_Slot_inst_encode, 0, 0 9580}; 9581 9582static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { 9583 Opcode_wsr_epc3_Slot_inst_encode, 0, 0 9584}; 9585 9586static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { 9587 Opcode_xsr_epc3_Slot_inst_encode, 0, 0 9588}; 9589 9590static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { 9591 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 9592}; 9593 9594static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { 9595 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 9596}; 9597 9598static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { 9599 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 9600}; 9601 9602static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { 9603 Opcode_rsr_epc4_Slot_inst_encode, 0, 0 9604}; 9605 9606static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { 9607 Opcode_wsr_epc4_Slot_inst_encode, 0, 0 9608}; 9609 9610static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { 9611 Opcode_xsr_epc4_Slot_inst_encode, 0, 0 9612}; 9613 9614static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { 9615 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 9616}; 9617 9618static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { 9619 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 9620}; 9621 9622static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { 9623 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 9624}; 9625 9626static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { 9627 Opcode_rsr_epc5_Slot_inst_encode, 0, 0 9628}; 9629 9630static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { 9631 Opcode_wsr_epc5_Slot_inst_encode, 0, 0 9632}; 9633 9634static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { 9635 Opcode_xsr_epc5_Slot_inst_encode, 0, 0 9636}; 9637 9638static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { 9639 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 9640}; 9641 9642static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { 9643 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 9644}; 9645 9646static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { 9647 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 9648}; 9649 9650static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { 9651 Opcode_rsr_epc6_Slot_inst_encode, 0, 0 9652}; 9653 9654static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { 9655 Opcode_wsr_epc6_Slot_inst_encode, 0, 0 9656}; 9657 9658static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { 9659 Opcode_xsr_epc6_Slot_inst_encode, 0, 0 9660}; 9661 9662static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { 9663 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 9664}; 9665 9666static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { 9667 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 9668}; 9669 9670static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { 9671 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 9672}; 9673 9674static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { 9675 Opcode_rsr_epc7_Slot_inst_encode, 0, 0 9676}; 9677 9678static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { 9679 Opcode_wsr_epc7_Slot_inst_encode, 0, 0 9680}; 9681 9682static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { 9683 Opcode_xsr_epc7_Slot_inst_encode, 0, 0 9684}; 9685 9686static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { 9687 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 9688}; 9689 9690static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { 9691 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 9692}; 9693 9694static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { 9695 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 9696}; 9697 9698static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { 9699 Opcode_rsr_eps2_Slot_inst_encode, 0, 0 9700}; 9701 9702static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { 9703 Opcode_wsr_eps2_Slot_inst_encode, 0, 0 9704}; 9705 9706static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { 9707 Opcode_xsr_eps2_Slot_inst_encode, 0, 0 9708}; 9709 9710static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { 9711 Opcode_rsr_eps3_Slot_inst_encode, 0, 0 9712}; 9713 9714static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { 9715 Opcode_wsr_eps3_Slot_inst_encode, 0, 0 9716}; 9717 9718static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { 9719 Opcode_xsr_eps3_Slot_inst_encode, 0, 0 9720}; 9721 9722static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { 9723 Opcode_rsr_eps4_Slot_inst_encode, 0, 0 9724}; 9725 9726static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { 9727 Opcode_wsr_eps4_Slot_inst_encode, 0, 0 9728}; 9729 9730static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { 9731 Opcode_xsr_eps4_Slot_inst_encode, 0, 0 9732}; 9733 9734static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { 9735 Opcode_rsr_eps5_Slot_inst_encode, 0, 0 9736}; 9737 9738static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { 9739 Opcode_wsr_eps5_Slot_inst_encode, 0, 0 9740}; 9741 9742static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { 9743 Opcode_xsr_eps5_Slot_inst_encode, 0, 0 9744}; 9745 9746static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { 9747 Opcode_rsr_eps6_Slot_inst_encode, 0, 0 9748}; 9749 9750static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { 9751 Opcode_wsr_eps6_Slot_inst_encode, 0, 0 9752}; 9753 9754static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { 9755 Opcode_xsr_eps6_Slot_inst_encode, 0, 0 9756}; 9757 9758static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { 9759 Opcode_rsr_eps7_Slot_inst_encode, 0, 0 9760}; 9761 9762static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { 9763 Opcode_wsr_eps7_Slot_inst_encode, 0, 0 9764}; 9765 9766static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { 9767 Opcode_xsr_eps7_Slot_inst_encode, 0, 0 9768}; 9769 9770static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { 9771 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 9772}; 9773 9774static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { 9775 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 9776}; 9777 9778static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { 9779 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 9780}; 9781 9782static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { 9783 Opcode_rsr_depc_Slot_inst_encode, 0, 0 9784}; 9785 9786static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { 9787 Opcode_wsr_depc_Slot_inst_encode, 0, 0 9788}; 9789 9790static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { 9791 Opcode_xsr_depc_Slot_inst_encode, 0, 0 9792}; 9793 9794static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { 9795 Opcode_rsr_exccause_Slot_inst_encode, 0, 0 9796}; 9797 9798static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { 9799 Opcode_wsr_exccause_Slot_inst_encode, 0, 0 9800}; 9801 9802static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { 9803 Opcode_xsr_exccause_Slot_inst_encode, 0, 0 9804}; 9805 9806static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { 9807 Opcode_rsr_misc0_Slot_inst_encode, 0, 0 9808}; 9809 9810static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { 9811 Opcode_wsr_misc0_Slot_inst_encode, 0, 0 9812}; 9813 9814static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { 9815 Opcode_xsr_misc0_Slot_inst_encode, 0, 0 9816}; 9817 9818static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { 9819 Opcode_rsr_misc1_Slot_inst_encode, 0, 0 9820}; 9821 9822static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { 9823 Opcode_wsr_misc1_Slot_inst_encode, 0, 0 9824}; 9825 9826static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { 9827 Opcode_xsr_misc1_Slot_inst_encode, 0, 0 9828}; 9829 9830static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { 9831 Opcode_rsr_prid_Slot_inst_encode, 0, 0 9832}; 9833 9834static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { 9835 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 9836}; 9837 9838static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { 9839 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 9840}; 9841 9842static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { 9843 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 9844}; 9845 9846static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { 9847 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 9848}; 9849 9850static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { 9851 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 9852}; 9853 9854static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { 9855 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 9856}; 9857 9858static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { 9859 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 9860}; 9861 9862static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { 9863 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 9864}; 9865 9866static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { 9867 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 9868}; 9869 9870static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { 9871 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 9872}; 9873 9874static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { 9875 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 9876}; 9877 9878static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { 9879 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 9880}; 9881 9882static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { 9883 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 9884}; 9885 9886static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { 9887 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 9888}; 9889 9890static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { 9891 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 9892}; 9893 9894static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { 9895 Opcode_mul_da_ll_Slot_inst_encode, 0, 0 9896}; 9897 9898static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { 9899 Opcode_mul_da_hl_Slot_inst_encode, 0, 0 9900}; 9901 9902static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { 9903 Opcode_mul_da_lh_Slot_inst_encode, 0, 0 9904}; 9905 9906static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { 9907 Opcode_mul_da_hh_Slot_inst_encode, 0, 0 9908}; 9909 9910static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { 9911 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 9912}; 9913 9914static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { 9915 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 9916}; 9917 9918static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { 9919 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 9920}; 9921 9922static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { 9923 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 9924}; 9925 9926static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { 9927 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 9928}; 9929 9930static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { 9931 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 9932}; 9933 9934static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { 9935 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 9936}; 9937 9938static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { 9939 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 9940}; 9941 9942static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { 9943 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 9944}; 9945 9946static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { 9947 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 9948}; 9949 9950static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { 9951 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 9952}; 9953 9954static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { 9955 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 9956}; 9957 9958static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { 9959 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 9960}; 9961 9962static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { 9963 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 9964}; 9965 9966static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { 9967 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 9968}; 9969 9970static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { 9971 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 9972}; 9973 9974static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { 9975 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 9976}; 9977 9978static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { 9979 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 9980}; 9981 9982static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { 9983 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 9984}; 9985 9986static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { 9987 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 9988}; 9989 9990static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { 9991 Opcode_mula_da_ll_Slot_inst_encode, 0, 0 9992}; 9993 9994static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { 9995 Opcode_mula_da_hl_Slot_inst_encode, 0, 0 9996}; 9997 9998static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { 9999 Opcode_mula_da_lh_Slot_inst_encode, 0, 0 10000}; 10001 10002static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { 10003 Opcode_mula_da_hh_Slot_inst_encode, 0, 0 10004}; 10005 10006static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { 10007 Opcode_muls_da_ll_Slot_inst_encode, 0, 0 10008}; 10009 10010static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { 10011 Opcode_muls_da_hl_Slot_inst_encode, 0, 0 10012}; 10013 10014static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { 10015 Opcode_muls_da_lh_Slot_inst_encode, 0, 0 10016}; 10017 10018static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { 10019 Opcode_muls_da_hh_Slot_inst_encode, 0, 0 10020}; 10021 10022static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { 10023 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 10024}; 10025 10026static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { 10027 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 10028}; 10029 10030static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { 10031 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 10032}; 10033 10034static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { 10035 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 10036}; 10037 10038static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { 10039 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 10040}; 10041 10042static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { 10043 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 10044}; 10045 10046static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { 10047 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 10048}; 10049 10050static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { 10051 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 10052}; 10053 10054static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { 10055 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 10056}; 10057 10058static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { 10059 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 10060}; 10061 10062static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { 10063 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 10064}; 10065 10066static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { 10067 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 10068}; 10069 10070static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { 10071 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 10072}; 10073 10074static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { 10075 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 10076}; 10077 10078static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { 10079 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 10080}; 10081 10082static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { 10083 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 10084}; 10085 10086static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { 10087 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 10088}; 10089 10090static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { 10091 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 10092}; 10093 10094static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { 10095 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 10096}; 10097 10098static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { 10099 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 10100}; 10101 10102static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { 10103 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 10104}; 10105 10106static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { 10107 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 10108}; 10109 10110static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { 10111 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 10112}; 10113 10114static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { 10115 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 10116}; 10117 10118static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { 10119 Opcode_lddec_Slot_inst_encode, 0, 0 10120}; 10121 10122static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { 10123 Opcode_ldinc_Slot_inst_encode, 0, 0 10124}; 10125 10126static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { 10127 Opcode_mul16u_Slot_inst_encode, 0, 0 10128}; 10129 10130static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { 10131 Opcode_mul16s_Slot_inst_encode, 0, 0 10132}; 10133 10134static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { 10135 Opcode_rsr_m0_Slot_inst_encode, 0, 0 10136}; 10137 10138static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { 10139 Opcode_wsr_m0_Slot_inst_encode, 0, 0 10140}; 10141 10142static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { 10143 Opcode_xsr_m0_Slot_inst_encode, 0, 0 10144}; 10145 10146static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { 10147 Opcode_rsr_m1_Slot_inst_encode, 0, 0 10148}; 10149 10150static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { 10151 Opcode_wsr_m1_Slot_inst_encode, 0, 0 10152}; 10153 10154static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { 10155 Opcode_xsr_m1_Slot_inst_encode, 0, 0 10156}; 10157 10158static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { 10159 Opcode_rsr_m2_Slot_inst_encode, 0, 0 10160}; 10161 10162static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { 10163 Opcode_wsr_m2_Slot_inst_encode, 0, 0 10164}; 10165 10166static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { 10167 Opcode_xsr_m2_Slot_inst_encode, 0, 0 10168}; 10169 10170static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { 10171 Opcode_rsr_m3_Slot_inst_encode, 0, 0 10172}; 10173 10174static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { 10175 Opcode_wsr_m3_Slot_inst_encode, 0, 0 10176}; 10177 10178static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { 10179 Opcode_xsr_m3_Slot_inst_encode, 0, 0 10180}; 10181 10182static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { 10183 Opcode_rsr_acclo_Slot_inst_encode, 0, 0 10184}; 10185 10186static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { 10187 Opcode_wsr_acclo_Slot_inst_encode, 0, 0 10188}; 10189 10190static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { 10191 Opcode_xsr_acclo_Slot_inst_encode, 0, 0 10192}; 10193 10194static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { 10195 Opcode_rsr_acchi_Slot_inst_encode, 0, 0 10196}; 10197 10198static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { 10199 Opcode_wsr_acchi_Slot_inst_encode, 0, 0 10200}; 10201 10202static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { 10203 Opcode_xsr_acchi_Slot_inst_encode, 0, 0 10204}; 10205 10206static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { 10207 Opcode_rfi_Slot_inst_encode, 0, 0 10208}; 10209 10210static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { 10211 Opcode_waiti_Slot_inst_encode, 0, 0 10212}; 10213 10214static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { 10215 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 10216}; 10217 10218static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { 10219 Opcode_wsr_intset_Slot_inst_encode, 0, 0 10220}; 10221 10222static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { 10223 Opcode_wsr_intclear_Slot_inst_encode, 0, 0 10224}; 10225 10226static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { 10227 Opcode_rsr_intenable_Slot_inst_encode, 0, 0 10228}; 10229 10230static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { 10231 Opcode_wsr_intenable_Slot_inst_encode, 0, 0 10232}; 10233 10234static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { 10235 Opcode_xsr_intenable_Slot_inst_encode, 0, 0 10236}; 10237 10238static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { 10239 Opcode_break_Slot_inst_encode, 0, 0 10240}; 10241 10242static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { 10243 0, 0, Opcode_break_n_Slot_inst16b_encode 10244}; 10245 10246static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { 10247 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 10248}; 10249 10250static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { 10251 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 10252}; 10253 10254static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { 10255 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 10256}; 10257 10258static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { 10259 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 10260}; 10261 10262static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { 10263 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 10264}; 10265 10266static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { 10267 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 10268}; 10269 10270static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { 10271 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 10272}; 10273 10274static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { 10275 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 10276}; 10277 10278static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { 10279 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 10280}; 10281 10282static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { 10283 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 10284}; 10285 10286static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { 10287 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 10288}; 10289 10290static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { 10291 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 10292}; 10293 10294static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { 10295 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 10296}; 10297 10298static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { 10299 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 10300}; 10301 10302static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { 10303 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 10304}; 10305 10306static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { 10307 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 10308}; 10309 10310static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { 10311 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 10312}; 10313 10314static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { 10315 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 10316}; 10317 10318static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { 10319 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 10320}; 10321 10322static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { 10323 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 10324}; 10325 10326static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { 10327 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 10328}; 10329 10330static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { 10331 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 10332}; 10333 10334static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { 10335 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 10336}; 10337 10338static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { 10339 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 10340}; 10341 10342static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { 10343 Opcode_rsr_icount_Slot_inst_encode, 0, 0 10344}; 10345 10346static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { 10347 Opcode_wsr_icount_Slot_inst_encode, 0, 0 10348}; 10349 10350static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { 10351 Opcode_xsr_icount_Slot_inst_encode, 0, 0 10352}; 10353 10354static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { 10355 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 10356}; 10357 10358static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { 10359 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 10360}; 10361 10362static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { 10363 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 10364}; 10365 10366static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { 10367 Opcode_rsr_ddr_Slot_inst_encode, 0, 0 10368}; 10369 10370static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { 10371 Opcode_wsr_ddr_Slot_inst_encode, 0, 0 10372}; 10373 10374static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { 10375 Opcode_xsr_ddr_Slot_inst_encode, 0, 0 10376}; 10377 10378static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { 10379 Opcode_rfdo_Slot_inst_encode, 0, 0 10380}; 10381 10382static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { 10383 Opcode_rfdd_Slot_inst_encode, 0, 0 10384}; 10385 10386static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { 10387 Opcode_wsr_mmid_Slot_inst_encode, 0, 0 10388}; 10389 10390static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { 10391 Opcode_rsr_ccount_Slot_inst_encode, 0, 0 10392}; 10393 10394static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { 10395 Opcode_wsr_ccount_Slot_inst_encode, 0, 0 10396}; 10397 10398static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { 10399 Opcode_xsr_ccount_Slot_inst_encode, 0, 0 10400}; 10401 10402static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { 10403 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 10404}; 10405 10406static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { 10407 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 10408}; 10409 10410static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { 10411 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 10412}; 10413 10414static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { 10415 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 10416}; 10417 10418static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { 10419 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 10420}; 10421 10422static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { 10423 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 10424}; 10425 10426static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { 10427 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 10428}; 10429 10430static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { 10431 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 10432}; 10433 10434static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { 10435 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 10436}; 10437 10438static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { 10439 Opcode_ipf_Slot_inst_encode, 0, 0 10440}; 10441 10442static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { 10443 Opcode_ihi_Slot_inst_encode, 0, 0 10444}; 10445 10446static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { 10447 Opcode_ipfl_Slot_inst_encode, 0, 0 10448}; 10449 10450static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { 10451 Opcode_ihu_Slot_inst_encode, 0, 0 10452}; 10453 10454static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { 10455 Opcode_iiu_Slot_inst_encode, 0, 0 10456}; 10457 10458static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { 10459 Opcode_iii_Slot_inst_encode, 0, 0 10460}; 10461 10462static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { 10463 Opcode_lict_Slot_inst_encode, 0, 0 10464}; 10465 10466static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { 10467 Opcode_licw_Slot_inst_encode, 0, 0 10468}; 10469 10470static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { 10471 Opcode_sict_Slot_inst_encode, 0, 0 10472}; 10473 10474static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { 10475 Opcode_sicw_Slot_inst_encode, 0, 0 10476}; 10477 10478static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { 10479 Opcode_dhwb_Slot_inst_encode, 0, 0 10480}; 10481 10482static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { 10483 Opcode_dhwbi_Slot_inst_encode, 0, 0 10484}; 10485 10486static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { 10487 Opcode_diwb_Slot_inst_encode, 0, 0 10488}; 10489 10490static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { 10491 Opcode_diwbi_Slot_inst_encode, 0, 0 10492}; 10493 10494static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { 10495 Opcode_dhi_Slot_inst_encode, 0, 0 10496}; 10497 10498static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { 10499 Opcode_dii_Slot_inst_encode, 0, 0 10500}; 10501 10502static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { 10503 Opcode_dpfr_Slot_inst_encode, 0, 0 10504}; 10505 10506static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { 10507 Opcode_dpfw_Slot_inst_encode, 0, 0 10508}; 10509 10510static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { 10511 Opcode_dpfro_Slot_inst_encode, 0, 0 10512}; 10513 10514static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { 10515 Opcode_dpfwo_Slot_inst_encode, 0, 0 10516}; 10517 10518static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { 10519 Opcode_dpfl_Slot_inst_encode, 0, 0 10520}; 10521 10522static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { 10523 Opcode_dhu_Slot_inst_encode, 0, 0 10524}; 10525 10526static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { 10527 Opcode_diu_Slot_inst_encode, 0, 0 10528}; 10529 10530static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { 10531 Opcode_sdct_Slot_inst_encode, 0, 0 10532}; 10533 10534static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { 10535 Opcode_ldct_Slot_inst_encode, 0, 0 10536}; 10537 10538static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { 10539 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 10540}; 10541 10542static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { 10543 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 10544}; 10545 10546static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { 10547 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 10548}; 10549 10550static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { 10551 Opcode_rsr_rasid_Slot_inst_encode, 0, 0 10552}; 10553 10554static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { 10555 Opcode_wsr_rasid_Slot_inst_encode, 0, 0 10556}; 10557 10558static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { 10559 Opcode_xsr_rasid_Slot_inst_encode, 0, 0 10560}; 10561 10562static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { 10563 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 10564}; 10565 10566static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { 10567 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 10568}; 10569 10570static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { 10571 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 10572}; 10573 10574static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { 10575 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 10576}; 10577 10578static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { 10579 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 10580}; 10581 10582static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { 10583 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 10584}; 10585 10586static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { 10587 Opcode_idtlb_Slot_inst_encode, 0, 0 10588}; 10589 10590static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { 10591 Opcode_pdtlb_Slot_inst_encode, 0, 0 10592}; 10593 10594static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { 10595 Opcode_rdtlb0_Slot_inst_encode, 0, 0 10596}; 10597 10598static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { 10599 Opcode_rdtlb1_Slot_inst_encode, 0, 0 10600}; 10601 10602static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { 10603 Opcode_wdtlb_Slot_inst_encode, 0, 0 10604}; 10605 10606static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { 10607 Opcode_iitlb_Slot_inst_encode, 0, 0 10608}; 10609 10610static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { 10611 Opcode_pitlb_Slot_inst_encode, 0, 0 10612}; 10613 10614static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { 10615 Opcode_ritlb0_Slot_inst_encode, 0, 0 10616}; 10617 10618static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { 10619 Opcode_ritlb1_Slot_inst_encode, 0, 0 10620}; 10621 10622static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { 10623 Opcode_witlb_Slot_inst_encode, 0, 0 10624}; 10625 10626static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { 10627 Opcode_ldpte_Slot_inst_encode, 0, 0 10628}; 10629 10630static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { 10631 Opcode_hwwitlba_Slot_inst_encode, 0, 0 10632}; 10633 10634static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { 10635 Opcode_hwwdtlba_Slot_inst_encode, 0, 0 10636}; 10637 10638static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { 10639 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 10640}; 10641 10642static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { 10643 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 10644}; 10645 10646static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { 10647 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 10648}; 10649 10650static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { 10651 Opcode_clamps_Slot_inst_encode, 0, 0 10652}; 10653 10654static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { 10655 Opcode_min_Slot_inst_encode, 0, 0 10656}; 10657 10658static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { 10659 Opcode_max_Slot_inst_encode, 0, 0 10660}; 10661 10662static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { 10663 Opcode_minu_Slot_inst_encode, 0, 0 10664}; 10665 10666static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { 10667 Opcode_maxu_Slot_inst_encode, 0, 0 10668}; 10669 10670static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { 10671 Opcode_nsa_Slot_inst_encode, 0, 0 10672}; 10673 10674static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { 10675 Opcode_nsau_Slot_inst_encode, 0, 0 10676}; 10677 10678static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { 10679 Opcode_sext_Slot_inst_encode, 0, 0 10680}; 10681 10682static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { 10683 Opcode_l32ai_Slot_inst_encode, 0, 0 10684}; 10685 10686static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { 10687 Opcode_s32ri_Slot_inst_encode, 0, 0 10688}; 10689 10690static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { 10691 Opcode_s32c1i_Slot_inst_encode, 0, 0 10692}; 10693 10694static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { 10695 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 10696}; 10697 10698static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { 10699 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 10700}; 10701 10702static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { 10703 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 10704}; 10705 10706static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { 10707 Opcode_quou_Slot_inst_encode, 0, 0 10708}; 10709 10710static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { 10711 Opcode_quos_Slot_inst_encode, 0, 0 10712}; 10713 10714static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { 10715 Opcode_remu_Slot_inst_encode, 0, 0 10716}; 10717 10718static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { 10719 Opcode_rems_Slot_inst_encode, 0, 0 10720}; 10721 10722static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { 10723 Opcode_mull_Slot_inst_encode, 0, 0 10724}; 10725 10726static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { 10727 Opcode_rur_expstate_Slot_inst_encode, 0, 0 10728}; 10729 10730static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { 10731 Opcode_wur_expstate_Slot_inst_encode, 0, 0 10732}; 10733 10734static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { 10735 Opcode_read_impwire_Slot_inst_encode, 0, 0 10736}; 10737 10738static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { 10739 Opcode_setb_expstate_Slot_inst_encode, 0, 0 10740}; 10741 10742static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { 10743 Opcode_clrb_expstate_Slot_inst_encode, 0, 0 10744}; 10745 10746static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { 10747 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 10748}; 10749 10750 10751/* Opcode table. */ 10752 10753static xtensa_opcode_internal opcodes[] = { 10754 { "excw", 0 /* xt_iclass_excw */, 10755 0, 10756 Opcode_excw_encode_fns, 0, 0 }, 10757 { "rfe", 1 /* xt_iclass_rfe */, 10758 XTENSA_OPCODE_IS_JUMP, 10759 Opcode_rfe_encode_fns, 0, 0 }, 10760 { "rfde", 2 /* xt_iclass_rfde */, 10761 XTENSA_OPCODE_IS_JUMP, 10762 Opcode_rfde_encode_fns, 0, 0 }, 10763 { "syscall", 3 /* xt_iclass_syscall */, 10764 0, 10765 Opcode_syscall_encode_fns, 0, 0 }, 10766 { "simcall", 4 /* xt_iclass_simcall */, 10767 0, 10768 Opcode_simcall_encode_fns, 0, 0 }, 10769 { "call12", 5 /* xt_iclass_call12 */, 10770 XTENSA_OPCODE_IS_CALL, 10771 Opcode_call12_encode_fns, 0, 0 }, 10772 { "call8", 6 /* xt_iclass_call8 */, 10773 XTENSA_OPCODE_IS_CALL, 10774 Opcode_call8_encode_fns, 0, 0 }, 10775 { "call4", 7 /* xt_iclass_call4 */, 10776 XTENSA_OPCODE_IS_CALL, 10777 Opcode_call4_encode_fns, 0, 0 }, 10778 { "callx12", 8 /* xt_iclass_callx12 */, 10779 XTENSA_OPCODE_IS_CALL, 10780 Opcode_callx12_encode_fns, 0, 0 }, 10781 { "callx8", 9 /* xt_iclass_callx8 */, 10782 XTENSA_OPCODE_IS_CALL, 10783 Opcode_callx8_encode_fns, 0, 0 }, 10784 { "callx4", 10 /* xt_iclass_callx4 */, 10785 XTENSA_OPCODE_IS_CALL, 10786 Opcode_callx4_encode_fns, 0, 0 }, 10787 { "entry", 11 /* xt_iclass_entry */, 10788 0, 10789 Opcode_entry_encode_fns, 0, 0 }, 10790 { "movsp", 12 /* xt_iclass_movsp */, 10791 0, 10792 Opcode_movsp_encode_fns, 0, 0 }, 10793 { "rotw", 13 /* xt_iclass_rotw */, 10794 0, 10795 Opcode_rotw_encode_fns, 0, 0 }, 10796 { "retw", 14 /* xt_iclass_retw */, 10797 XTENSA_OPCODE_IS_JUMP, 10798 Opcode_retw_encode_fns, 0, 0 }, 10799 { "retw.n", 14 /* xt_iclass_retw */, 10800 XTENSA_OPCODE_IS_JUMP, 10801 Opcode_retw_n_encode_fns, 0, 0 }, 10802 { "rfwo", 15 /* xt_iclass_rfwou */, 10803 XTENSA_OPCODE_IS_JUMP, 10804 Opcode_rfwo_encode_fns, 0, 0 }, 10805 { "rfwu", 15 /* xt_iclass_rfwou */, 10806 XTENSA_OPCODE_IS_JUMP, 10807 Opcode_rfwu_encode_fns, 0, 0 }, 10808 { "l32e", 16 /* xt_iclass_l32e */, 10809 0, 10810 Opcode_l32e_encode_fns, 0, 0 }, 10811 { "s32e", 17 /* xt_iclass_s32e */, 10812 0, 10813 Opcode_s32e_encode_fns, 0, 0 }, 10814 { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, 10815 0, 10816 Opcode_rsr_windowbase_encode_fns, 0, 0 }, 10817 { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, 10818 0, 10819 Opcode_wsr_windowbase_encode_fns, 0, 0 }, 10820 { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, 10821 0, 10822 Opcode_xsr_windowbase_encode_fns, 0, 0 }, 10823 { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, 10824 0, 10825 Opcode_rsr_windowstart_encode_fns, 0, 0 }, 10826 { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, 10827 0, 10828 Opcode_wsr_windowstart_encode_fns, 0, 0 }, 10829 { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, 10830 0, 10831 Opcode_xsr_windowstart_encode_fns, 0, 0 }, 10832 { "add.n", 24 /* xt_iclass_add.n */, 10833 0, 10834 Opcode_add_n_encode_fns, 0, 0 }, 10835 { "addi.n", 25 /* xt_iclass_addi.n */, 10836 0, 10837 Opcode_addi_n_encode_fns, 0, 0 }, 10838 { "beqz.n", 26 /* xt_iclass_bz6 */, 10839 XTENSA_OPCODE_IS_BRANCH, 10840 Opcode_beqz_n_encode_fns, 0, 0 }, 10841 { "bnez.n", 26 /* xt_iclass_bz6 */, 10842 XTENSA_OPCODE_IS_BRANCH, 10843 Opcode_bnez_n_encode_fns, 0, 0 }, 10844 { "ill.n", 27 /* xt_iclass_ill.n */, 10845 0, 10846 Opcode_ill_n_encode_fns, 0, 0 }, 10847 { "l32i.n", 28 /* xt_iclass_loadi4 */, 10848 0, 10849 Opcode_l32i_n_encode_fns, 0, 0 }, 10850 { "mov.n", 29 /* xt_iclass_mov.n */, 10851 0, 10852 Opcode_mov_n_encode_fns, 0, 0 }, 10853 { "movi.n", 30 /* xt_iclass_movi.n */, 10854 0, 10855 Opcode_movi_n_encode_fns, 0, 0 }, 10856 { "nop.n", 31 /* xt_iclass_nopn */, 10857 0, 10858 Opcode_nop_n_encode_fns, 0, 0 }, 10859 { "ret.n", 32 /* xt_iclass_retn */, 10860 XTENSA_OPCODE_IS_JUMP, 10861 Opcode_ret_n_encode_fns, 0, 0 }, 10862 { "s32i.n", 33 /* xt_iclass_storei4 */, 10863 0, 10864 Opcode_s32i_n_encode_fns, 0, 0 }, 10865 { "rur.threadptr", 34 /* rur_threadptr */, 10866 0, 10867 Opcode_rur_threadptr_encode_fns, 0, 0 }, 10868 { "wur.threadptr", 35 /* wur_threadptr */, 10869 0, 10870 Opcode_wur_threadptr_encode_fns, 0, 0 }, 10871 { "addi", 36 /* xt_iclass_addi */, 10872 0, 10873 Opcode_addi_encode_fns, 0, 0 }, 10874 { "addmi", 37 /* xt_iclass_addmi */, 10875 0, 10876 Opcode_addmi_encode_fns, 0, 0 }, 10877 { "add", 38 /* xt_iclass_addsub */, 10878 0, 10879 Opcode_add_encode_fns, 0, 0 }, 10880 { "sub", 38 /* xt_iclass_addsub */, 10881 0, 10882 Opcode_sub_encode_fns, 0, 0 }, 10883 { "addx2", 38 /* xt_iclass_addsub */, 10884 0, 10885 Opcode_addx2_encode_fns, 0, 0 }, 10886 { "addx4", 38 /* xt_iclass_addsub */, 10887 0, 10888 Opcode_addx4_encode_fns, 0, 0 }, 10889 { "addx8", 38 /* xt_iclass_addsub */, 10890 0, 10891 Opcode_addx8_encode_fns, 0, 0 }, 10892 { "subx2", 38 /* xt_iclass_addsub */, 10893 0, 10894 Opcode_subx2_encode_fns, 0, 0 }, 10895 { "subx4", 38 /* xt_iclass_addsub */, 10896 0, 10897 Opcode_subx4_encode_fns, 0, 0 }, 10898 { "subx8", 38 /* xt_iclass_addsub */, 10899 0, 10900 Opcode_subx8_encode_fns, 0, 0 }, 10901 { "and", 39 /* xt_iclass_bit */, 10902 0, 10903 Opcode_and_encode_fns, 0, 0 }, 10904 { "or", 39 /* xt_iclass_bit */, 10905 0, 10906 Opcode_or_encode_fns, 0, 0 }, 10907 { "xor", 39 /* xt_iclass_bit */, 10908 0, 10909 Opcode_xor_encode_fns, 0, 0 }, 10910 { "beqi", 40 /* xt_iclass_bsi8 */, 10911 XTENSA_OPCODE_IS_BRANCH, 10912 Opcode_beqi_encode_fns, 0, 0 }, 10913 { "bnei", 40 /* xt_iclass_bsi8 */, 10914 XTENSA_OPCODE_IS_BRANCH, 10915 Opcode_bnei_encode_fns, 0, 0 }, 10916 { "bgei", 40 /* xt_iclass_bsi8 */, 10917 XTENSA_OPCODE_IS_BRANCH, 10918 Opcode_bgei_encode_fns, 0, 0 }, 10919 { "blti", 40 /* xt_iclass_bsi8 */, 10920 XTENSA_OPCODE_IS_BRANCH, 10921 Opcode_blti_encode_fns, 0, 0 }, 10922 { "bbci", 41 /* xt_iclass_bsi8b */, 10923 XTENSA_OPCODE_IS_BRANCH, 10924 Opcode_bbci_encode_fns, 0, 0 }, 10925 { "bbsi", 41 /* xt_iclass_bsi8b */, 10926 XTENSA_OPCODE_IS_BRANCH, 10927 Opcode_bbsi_encode_fns, 0, 0 }, 10928 { "bgeui", 42 /* xt_iclass_bsi8u */, 10929 XTENSA_OPCODE_IS_BRANCH, 10930 Opcode_bgeui_encode_fns, 0, 0 }, 10931 { "bltui", 42 /* xt_iclass_bsi8u */, 10932 XTENSA_OPCODE_IS_BRANCH, 10933 Opcode_bltui_encode_fns, 0, 0 }, 10934 { "beq", 43 /* xt_iclass_bst8 */, 10935 XTENSA_OPCODE_IS_BRANCH, 10936 Opcode_beq_encode_fns, 0, 0 }, 10937 { "bne", 43 /* xt_iclass_bst8 */, 10938 XTENSA_OPCODE_IS_BRANCH, 10939 Opcode_bne_encode_fns, 0, 0 }, 10940 { "bge", 43 /* xt_iclass_bst8 */, 10941 XTENSA_OPCODE_IS_BRANCH, 10942 Opcode_bge_encode_fns, 0, 0 }, 10943 { "blt", 43 /* xt_iclass_bst8 */, 10944 XTENSA_OPCODE_IS_BRANCH, 10945 Opcode_blt_encode_fns, 0, 0 }, 10946 { "bgeu", 43 /* xt_iclass_bst8 */, 10947 XTENSA_OPCODE_IS_BRANCH, 10948 Opcode_bgeu_encode_fns, 0, 0 }, 10949 { "bltu", 43 /* xt_iclass_bst8 */, 10950 XTENSA_OPCODE_IS_BRANCH, 10951 Opcode_bltu_encode_fns, 0, 0 }, 10952 { "bany", 43 /* xt_iclass_bst8 */, 10953 XTENSA_OPCODE_IS_BRANCH, 10954 Opcode_bany_encode_fns, 0, 0 }, 10955 { "bnone", 43 /* xt_iclass_bst8 */, 10956 XTENSA_OPCODE_IS_BRANCH, 10957 Opcode_bnone_encode_fns, 0, 0 }, 10958 { "ball", 43 /* xt_iclass_bst8 */, 10959 XTENSA_OPCODE_IS_BRANCH, 10960 Opcode_ball_encode_fns, 0, 0 }, 10961 { "bnall", 43 /* xt_iclass_bst8 */, 10962 XTENSA_OPCODE_IS_BRANCH, 10963 Opcode_bnall_encode_fns, 0, 0 }, 10964 { "bbc", 43 /* xt_iclass_bst8 */, 10965 XTENSA_OPCODE_IS_BRANCH, 10966 Opcode_bbc_encode_fns, 0, 0 }, 10967 { "bbs", 43 /* xt_iclass_bst8 */, 10968 XTENSA_OPCODE_IS_BRANCH, 10969 Opcode_bbs_encode_fns, 0, 0 }, 10970 { "beqz", 44 /* xt_iclass_bsz12 */, 10971 XTENSA_OPCODE_IS_BRANCH, 10972 Opcode_beqz_encode_fns, 0, 0 }, 10973 { "bnez", 44 /* xt_iclass_bsz12 */, 10974 XTENSA_OPCODE_IS_BRANCH, 10975 Opcode_bnez_encode_fns, 0, 0 }, 10976 { "bgez", 44 /* xt_iclass_bsz12 */, 10977 XTENSA_OPCODE_IS_BRANCH, 10978 Opcode_bgez_encode_fns, 0, 0 }, 10979 { "bltz", 44 /* xt_iclass_bsz12 */, 10980 XTENSA_OPCODE_IS_BRANCH, 10981 Opcode_bltz_encode_fns, 0, 0 }, 10982 { "call0", 45 /* xt_iclass_call0 */, 10983 XTENSA_OPCODE_IS_CALL, 10984 Opcode_call0_encode_fns, 0, 0 }, 10985 { "callx0", 46 /* xt_iclass_callx0 */, 10986 XTENSA_OPCODE_IS_CALL, 10987 Opcode_callx0_encode_fns, 0, 0 }, 10988 { "extui", 47 /* xt_iclass_exti */, 10989 0, 10990 Opcode_extui_encode_fns, 0, 0 }, 10991 { "ill", 48 /* xt_iclass_ill */, 10992 0, 10993 Opcode_ill_encode_fns, 0, 0 }, 10994 { "j", 49 /* xt_iclass_jump */, 10995 XTENSA_OPCODE_IS_JUMP, 10996 Opcode_j_encode_fns, 0, 0 }, 10997 { "jx", 50 /* xt_iclass_jumpx */, 10998 XTENSA_OPCODE_IS_JUMP, 10999 Opcode_jx_encode_fns, 0, 0 }, 11000 { "l16ui", 51 /* xt_iclass_l16ui */, 11001 0, 11002 Opcode_l16ui_encode_fns, 0, 0 }, 11003 { "l16si", 52 /* xt_iclass_l16si */, 11004 0, 11005 Opcode_l16si_encode_fns, 0, 0 }, 11006 { "l32i", 53 /* xt_iclass_l32i */, 11007 0, 11008 Opcode_l32i_encode_fns, 0, 0 }, 11009 { "l32r", 54 /* xt_iclass_l32r */, 11010 0, 11011 Opcode_l32r_encode_fns, 0, 0 }, 11012 { "l8ui", 55 /* xt_iclass_l8i */, 11013 0, 11014 Opcode_l8ui_encode_fns, 0, 0 }, 11015 { "loop", 56 /* xt_iclass_loop */, 11016 XTENSA_OPCODE_IS_LOOP, 11017 Opcode_loop_encode_fns, 0, 0 }, 11018 { "loopnez", 57 /* xt_iclass_loopz */, 11019 XTENSA_OPCODE_IS_LOOP, 11020 Opcode_loopnez_encode_fns, 0, 0 }, 11021 { "loopgtz", 57 /* xt_iclass_loopz */, 11022 XTENSA_OPCODE_IS_LOOP, 11023 Opcode_loopgtz_encode_fns, 0, 0 }, 11024 { "movi", 58 /* xt_iclass_movi */, 11025 0, 11026 Opcode_movi_encode_fns, 0, 0 }, 11027 { "moveqz", 59 /* xt_iclass_movz */, 11028 0, 11029 Opcode_moveqz_encode_fns, 0, 0 }, 11030 { "movnez", 59 /* xt_iclass_movz */, 11031 0, 11032 Opcode_movnez_encode_fns, 0, 0 }, 11033 { "movltz", 59 /* xt_iclass_movz */, 11034 0, 11035 Opcode_movltz_encode_fns, 0, 0 }, 11036 { "movgez", 59 /* xt_iclass_movz */, 11037 0, 11038 Opcode_movgez_encode_fns, 0, 0 }, 11039 { "neg", 60 /* xt_iclass_neg */, 11040 0, 11041 Opcode_neg_encode_fns, 0, 0 }, 11042 { "abs", 60 /* xt_iclass_neg */, 11043 0, 11044 Opcode_abs_encode_fns, 0, 0 }, 11045 { "nop", 61 /* xt_iclass_nop */, 11046 0, 11047 Opcode_nop_encode_fns, 0, 0 }, 11048 { "ret", 62 /* xt_iclass_return */, 11049 XTENSA_OPCODE_IS_JUMP, 11050 Opcode_ret_encode_fns, 0, 0 }, 11051 { "s16i", 63 /* xt_iclass_s16i */, 11052 0, 11053 Opcode_s16i_encode_fns, 0, 0 }, 11054 { "s32i", 64 /* xt_iclass_s32i */, 11055 0, 11056 Opcode_s32i_encode_fns, 0, 0 }, 11057 { "s8i", 65 /* xt_iclass_s8i */, 11058 0, 11059 Opcode_s8i_encode_fns, 0, 0 }, 11060 { "ssr", 66 /* xt_iclass_sar */, 11061 0, 11062 Opcode_ssr_encode_fns, 0, 0 }, 11063 { "ssl", 66 /* xt_iclass_sar */, 11064 0, 11065 Opcode_ssl_encode_fns, 0, 0 }, 11066 { "ssa8l", 66 /* xt_iclass_sar */, 11067 0, 11068 Opcode_ssa8l_encode_fns, 0, 0 }, 11069 { "ssa8b", 66 /* xt_iclass_sar */, 11070 0, 11071 Opcode_ssa8b_encode_fns, 0, 0 }, 11072 { "ssai", 67 /* xt_iclass_sari */, 11073 0, 11074 Opcode_ssai_encode_fns, 0, 0 }, 11075 { "sll", 68 /* xt_iclass_shifts */, 11076 0, 11077 Opcode_sll_encode_fns, 0, 0 }, 11078 { "src", 69 /* xt_iclass_shiftst */, 11079 0, 11080 Opcode_src_encode_fns, 0, 0 }, 11081 { "srl", 70 /* xt_iclass_shiftt */, 11082 0, 11083 Opcode_srl_encode_fns, 0, 0 }, 11084 { "sra", 70 /* xt_iclass_shiftt */, 11085 0, 11086 Opcode_sra_encode_fns, 0, 0 }, 11087 { "slli", 71 /* xt_iclass_slli */, 11088 0, 11089 Opcode_slli_encode_fns, 0, 0 }, 11090 { "srai", 72 /* xt_iclass_srai */, 11091 0, 11092 Opcode_srai_encode_fns, 0, 0 }, 11093 { "srli", 73 /* xt_iclass_srli */, 11094 0, 11095 Opcode_srli_encode_fns, 0, 0 }, 11096 { "memw", 74 /* xt_iclass_memw */, 11097 0, 11098 Opcode_memw_encode_fns, 0, 0 }, 11099 { "extw", 75 /* xt_iclass_extw */, 11100 0, 11101 Opcode_extw_encode_fns, 0, 0 }, 11102 { "isync", 76 /* xt_iclass_isync */, 11103 0, 11104 Opcode_isync_encode_fns, 0, 0 }, 11105 { "rsync", 77 /* xt_iclass_sync */, 11106 0, 11107 Opcode_rsync_encode_fns, 0, 0 }, 11108 { "esync", 77 /* xt_iclass_sync */, 11109 0, 11110 Opcode_esync_encode_fns, 0, 0 }, 11111 { "dsync", 77 /* xt_iclass_sync */, 11112 0, 11113 Opcode_dsync_encode_fns, 0, 0 }, 11114 { "rsil", 78 /* xt_iclass_rsil */, 11115 0, 11116 Opcode_rsil_encode_fns, 0, 0 }, 11117 { "rsr.lend", 79 /* xt_iclass_rsr.lend */, 11118 0, 11119 Opcode_rsr_lend_encode_fns, 0, 0 }, 11120 { "wsr.lend", 80 /* xt_iclass_wsr.lend */, 11121 0, 11122 Opcode_wsr_lend_encode_fns, 0, 0 }, 11123 { "xsr.lend", 81 /* xt_iclass_xsr.lend */, 11124 0, 11125 Opcode_xsr_lend_encode_fns, 0, 0 }, 11126 { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */, 11127 0, 11128 Opcode_rsr_lcount_encode_fns, 0, 0 }, 11129 { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */, 11130 0, 11131 Opcode_wsr_lcount_encode_fns, 0, 0 }, 11132 { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */, 11133 0, 11134 Opcode_xsr_lcount_encode_fns, 0, 0 }, 11135 { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */, 11136 0, 11137 Opcode_rsr_lbeg_encode_fns, 0, 0 }, 11138 { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */, 11139 0, 11140 Opcode_wsr_lbeg_encode_fns, 0, 0 }, 11141 { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */, 11142 0, 11143 Opcode_xsr_lbeg_encode_fns, 0, 0 }, 11144 { "rsr.sar", 88 /* xt_iclass_rsr.sar */, 11145 0, 11146 Opcode_rsr_sar_encode_fns, 0, 0 }, 11147 { "wsr.sar", 89 /* xt_iclass_wsr.sar */, 11148 0, 11149 Opcode_wsr_sar_encode_fns, 0, 0 }, 11150 { "xsr.sar", 90 /* xt_iclass_xsr.sar */, 11151 0, 11152 Opcode_xsr_sar_encode_fns, 0, 0 }, 11153 { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */, 11154 0, 11155 Opcode_rsr_litbase_encode_fns, 0, 0 }, 11156 { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */, 11157 0, 11158 Opcode_wsr_litbase_encode_fns, 0, 0 }, 11159 { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */, 11160 0, 11161 Opcode_xsr_litbase_encode_fns, 0, 0 }, 11162 { "rsr.176", 94 /* xt_iclass_rsr.176 */, 11163 0, 11164 Opcode_rsr_176_encode_fns, 0, 0 }, 11165 { "rsr.208", 95 /* xt_iclass_rsr.208 */, 11166 0, 11167 Opcode_rsr_208_encode_fns, 0, 0 }, 11168 { "rsr.ps", 96 /* xt_iclass_rsr.ps */, 11169 0, 11170 Opcode_rsr_ps_encode_fns, 0, 0 }, 11171 { "wsr.ps", 97 /* xt_iclass_wsr.ps */, 11172 0, 11173 Opcode_wsr_ps_encode_fns, 0, 0 }, 11174 { "xsr.ps", 98 /* xt_iclass_xsr.ps */, 11175 0, 11176 Opcode_xsr_ps_encode_fns, 0, 0 }, 11177 { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */, 11178 0, 11179 Opcode_rsr_epc1_encode_fns, 0, 0 }, 11180 { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */, 11181 0, 11182 Opcode_wsr_epc1_encode_fns, 0, 0 }, 11183 { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */, 11184 0, 11185 Opcode_xsr_epc1_encode_fns, 0, 0 }, 11186 { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */, 11187 0, 11188 Opcode_rsr_excsave1_encode_fns, 0, 0 }, 11189 { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */, 11190 0, 11191 Opcode_wsr_excsave1_encode_fns, 0, 0 }, 11192 { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */, 11193 0, 11194 Opcode_xsr_excsave1_encode_fns, 0, 0 }, 11195 { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */, 11196 0, 11197 Opcode_rsr_epc2_encode_fns, 0, 0 }, 11198 { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */, 11199 0, 11200 Opcode_wsr_epc2_encode_fns, 0, 0 }, 11201 { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */, 11202 0, 11203 Opcode_xsr_epc2_encode_fns, 0, 0 }, 11204 { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */, 11205 0, 11206 Opcode_rsr_excsave2_encode_fns, 0, 0 }, 11207 { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */, 11208 0, 11209 Opcode_wsr_excsave2_encode_fns, 0, 0 }, 11210 { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */, 11211 0, 11212 Opcode_xsr_excsave2_encode_fns, 0, 0 }, 11213 { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */, 11214 0, 11215 Opcode_rsr_epc3_encode_fns, 0, 0 }, 11216 { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */, 11217 0, 11218 Opcode_wsr_epc3_encode_fns, 0, 0 }, 11219 { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */, 11220 0, 11221 Opcode_xsr_epc3_encode_fns, 0, 0 }, 11222 { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */, 11223 0, 11224 Opcode_rsr_excsave3_encode_fns, 0, 0 }, 11225 { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */, 11226 0, 11227 Opcode_wsr_excsave3_encode_fns, 0, 0 }, 11228 { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */, 11229 0, 11230 Opcode_xsr_excsave3_encode_fns, 0, 0 }, 11231 { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */, 11232 0, 11233 Opcode_rsr_epc4_encode_fns, 0, 0 }, 11234 { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */, 11235 0, 11236 Opcode_wsr_epc4_encode_fns, 0, 0 }, 11237 { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */, 11238 0, 11239 Opcode_xsr_epc4_encode_fns, 0, 0 }, 11240 { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */, 11241 0, 11242 Opcode_rsr_excsave4_encode_fns, 0, 0 }, 11243 { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */, 11244 0, 11245 Opcode_wsr_excsave4_encode_fns, 0, 0 }, 11246 { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */, 11247 0, 11248 Opcode_xsr_excsave4_encode_fns, 0, 0 }, 11249 { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */, 11250 0, 11251 Opcode_rsr_epc5_encode_fns, 0, 0 }, 11252 { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */, 11253 0, 11254 Opcode_wsr_epc5_encode_fns, 0, 0 }, 11255 { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */, 11256 0, 11257 Opcode_xsr_epc5_encode_fns, 0, 0 }, 11258 { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */, 11259 0, 11260 Opcode_rsr_excsave5_encode_fns, 0, 0 }, 11261 { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */, 11262 0, 11263 Opcode_wsr_excsave5_encode_fns, 0, 0 }, 11264 { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */, 11265 0, 11266 Opcode_xsr_excsave5_encode_fns, 0, 0 }, 11267 { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */, 11268 0, 11269 Opcode_rsr_epc6_encode_fns, 0, 0 }, 11270 { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */, 11271 0, 11272 Opcode_wsr_epc6_encode_fns, 0, 0 }, 11273 { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */, 11274 0, 11275 Opcode_xsr_epc6_encode_fns, 0, 0 }, 11276 { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */, 11277 0, 11278 Opcode_rsr_excsave6_encode_fns, 0, 0 }, 11279 { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */, 11280 0, 11281 Opcode_wsr_excsave6_encode_fns, 0, 0 }, 11282 { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */, 11283 0, 11284 Opcode_xsr_excsave6_encode_fns, 0, 0 }, 11285 { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */, 11286 0, 11287 Opcode_rsr_epc7_encode_fns, 0, 0 }, 11288 { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */, 11289 0, 11290 Opcode_wsr_epc7_encode_fns, 0, 0 }, 11291 { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */, 11292 0, 11293 Opcode_xsr_epc7_encode_fns, 0, 0 }, 11294 { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */, 11295 0, 11296 Opcode_rsr_excsave7_encode_fns, 0, 0 }, 11297 { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */, 11298 0, 11299 Opcode_wsr_excsave7_encode_fns, 0, 0 }, 11300 { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */, 11301 0, 11302 Opcode_xsr_excsave7_encode_fns, 0, 0 }, 11303 { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */, 11304 0, 11305 Opcode_rsr_eps2_encode_fns, 0, 0 }, 11306 { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */, 11307 0, 11308 Opcode_wsr_eps2_encode_fns, 0, 0 }, 11309 { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */, 11310 0, 11311 Opcode_xsr_eps2_encode_fns, 0, 0 }, 11312 { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */, 11313 0, 11314 Opcode_rsr_eps3_encode_fns, 0, 0 }, 11315 { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */, 11316 0, 11317 Opcode_wsr_eps3_encode_fns, 0, 0 }, 11318 { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */, 11319 0, 11320 Opcode_xsr_eps3_encode_fns, 0, 0 }, 11321 { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */, 11322 0, 11323 Opcode_rsr_eps4_encode_fns, 0, 0 }, 11324 { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */, 11325 0, 11326 Opcode_wsr_eps4_encode_fns, 0, 0 }, 11327 { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */, 11328 0, 11329 Opcode_xsr_eps4_encode_fns, 0, 0 }, 11330 { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */, 11331 0, 11332 Opcode_rsr_eps5_encode_fns, 0, 0 }, 11333 { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */, 11334 0, 11335 Opcode_wsr_eps5_encode_fns, 0, 0 }, 11336 { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */, 11337 0, 11338 Opcode_xsr_eps5_encode_fns, 0, 0 }, 11339 { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */, 11340 0, 11341 Opcode_rsr_eps6_encode_fns, 0, 0 }, 11342 { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */, 11343 0, 11344 Opcode_wsr_eps6_encode_fns, 0, 0 }, 11345 { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */, 11346 0, 11347 Opcode_xsr_eps6_encode_fns, 0, 0 }, 11348 { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */, 11349 0, 11350 Opcode_rsr_eps7_encode_fns, 0, 0 }, 11351 { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */, 11352 0, 11353 Opcode_wsr_eps7_encode_fns, 0, 0 }, 11354 { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */, 11355 0, 11356 Opcode_xsr_eps7_encode_fns, 0, 0 }, 11357 { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */, 11358 0, 11359 Opcode_rsr_excvaddr_encode_fns, 0, 0 }, 11360 { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */, 11361 0, 11362 Opcode_wsr_excvaddr_encode_fns, 0, 0 }, 11363 { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */, 11364 0, 11365 Opcode_xsr_excvaddr_encode_fns, 0, 0 }, 11366 { "rsr.depc", 162 /* xt_iclass_rsr.depc */, 11367 0, 11368 Opcode_rsr_depc_encode_fns, 0, 0 }, 11369 { "wsr.depc", 163 /* xt_iclass_wsr.depc */, 11370 0, 11371 Opcode_wsr_depc_encode_fns, 0, 0 }, 11372 { "xsr.depc", 164 /* xt_iclass_xsr.depc */, 11373 0, 11374 Opcode_xsr_depc_encode_fns, 0, 0 }, 11375 { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */, 11376 0, 11377 Opcode_rsr_exccause_encode_fns, 0, 0 }, 11378 { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */, 11379 0, 11380 Opcode_wsr_exccause_encode_fns, 0, 0 }, 11381 { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */, 11382 0, 11383 Opcode_xsr_exccause_encode_fns, 0, 0 }, 11384 { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */, 11385 0, 11386 Opcode_rsr_misc0_encode_fns, 0, 0 }, 11387 { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */, 11388 0, 11389 Opcode_wsr_misc0_encode_fns, 0, 0 }, 11390 { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */, 11391 0, 11392 Opcode_xsr_misc0_encode_fns, 0, 0 }, 11393 { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */, 11394 0, 11395 Opcode_rsr_misc1_encode_fns, 0, 0 }, 11396 { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */, 11397 0, 11398 Opcode_wsr_misc1_encode_fns, 0, 0 }, 11399 { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */, 11400 0, 11401 Opcode_xsr_misc1_encode_fns, 0, 0 }, 11402 { "rsr.prid", 174 /* xt_iclass_rsr.prid */, 11403 0, 11404 Opcode_rsr_prid_encode_fns, 0, 0 }, 11405 { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */, 11406 0, 11407 Opcode_rsr_vecbase_encode_fns, 0, 0 }, 11408 { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */, 11409 0, 11410 Opcode_wsr_vecbase_encode_fns, 0, 0 }, 11411 { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */, 11412 0, 11413 Opcode_xsr_vecbase_encode_fns, 0, 0 }, 11414 { "mul.aa.ll", 178 /* xt_iclass_mac16_aa */, 11415 0, 11416 Opcode_mul_aa_ll_encode_fns, 0, 0 }, 11417 { "mul.aa.hl", 178 /* xt_iclass_mac16_aa */, 11418 0, 11419 Opcode_mul_aa_hl_encode_fns, 0, 0 }, 11420 { "mul.aa.lh", 178 /* xt_iclass_mac16_aa */, 11421 0, 11422 Opcode_mul_aa_lh_encode_fns, 0, 0 }, 11423 { "mul.aa.hh", 178 /* xt_iclass_mac16_aa */, 11424 0, 11425 Opcode_mul_aa_hh_encode_fns, 0, 0 }, 11426 { "umul.aa.ll", 178 /* xt_iclass_mac16_aa */, 11427 0, 11428 Opcode_umul_aa_ll_encode_fns, 0, 0 }, 11429 { "umul.aa.hl", 178 /* xt_iclass_mac16_aa */, 11430 0, 11431 Opcode_umul_aa_hl_encode_fns, 0, 0 }, 11432 { "umul.aa.lh", 178 /* xt_iclass_mac16_aa */, 11433 0, 11434 Opcode_umul_aa_lh_encode_fns, 0, 0 }, 11435 { "umul.aa.hh", 178 /* xt_iclass_mac16_aa */, 11436 0, 11437 Opcode_umul_aa_hh_encode_fns, 0, 0 }, 11438 { "mul.ad.ll", 179 /* xt_iclass_mac16_ad */, 11439 0, 11440 Opcode_mul_ad_ll_encode_fns, 0, 0 }, 11441 { "mul.ad.hl", 179 /* xt_iclass_mac16_ad */, 11442 0, 11443 Opcode_mul_ad_hl_encode_fns, 0, 0 }, 11444 { "mul.ad.lh", 179 /* xt_iclass_mac16_ad */, 11445 0, 11446 Opcode_mul_ad_lh_encode_fns, 0, 0 }, 11447 { "mul.ad.hh", 179 /* xt_iclass_mac16_ad */, 11448 0, 11449 Opcode_mul_ad_hh_encode_fns, 0, 0 }, 11450 { "mul.da.ll", 180 /* xt_iclass_mac16_da */, 11451 0, 11452 Opcode_mul_da_ll_encode_fns, 0, 0 }, 11453 { "mul.da.hl", 180 /* xt_iclass_mac16_da */, 11454 0, 11455 Opcode_mul_da_hl_encode_fns, 0, 0 }, 11456 { "mul.da.lh", 180 /* xt_iclass_mac16_da */, 11457 0, 11458 Opcode_mul_da_lh_encode_fns, 0, 0 }, 11459 { "mul.da.hh", 180 /* xt_iclass_mac16_da */, 11460 0, 11461 Opcode_mul_da_hh_encode_fns, 0, 0 }, 11462 { "mul.dd.ll", 181 /* xt_iclass_mac16_dd */, 11463 0, 11464 Opcode_mul_dd_ll_encode_fns, 0, 0 }, 11465 { "mul.dd.hl", 181 /* xt_iclass_mac16_dd */, 11466 0, 11467 Opcode_mul_dd_hl_encode_fns, 0, 0 }, 11468 { "mul.dd.lh", 181 /* xt_iclass_mac16_dd */, 11469 0, 11470 Opcode_mul_dd_lh_encode_fns, 0, 0 }, 11471 { "mul.dd.hh", 181 /* xt_iclass_mac16_dd */, 11472 0, 11473 Opcode_mul_dd_hh_encode_fns, 0, 0 }, 11474 { "mula.aa.ll", 182 /* xt_iclass_mac16a_aa */, 11475 0, 11476 Opcode_mula_aa_ll_encode_fns, 0, 0 }, 11477 { "mula.aa.hl", 182 /* xt_iclass_mac16a_aa */, 11478 0, 11479 Opcode_mula_aa_hl_encode_fns, 0, 0 }, 11480 { "mula.aa.lh", 182 /* xt_iclass_mac16a_aa */, 11481 0, 11482 Opcode_mula_aa_lh_encode_fns, 0, 0 }, 11483 { "mula.aa.hh", 182 /* xt_iclass_mac16a_aa */, 11484 0, 11485 Opcode_mula_aa_hh_encode_fns, 0, 0 }, 11486 { "muls.aa.ll", 182 /* xt_iclass_mac16a_aa */, 11487 0, 11488 Opcode_muls_aa_ll_encode_fns, 0, 0 }, 11489 { "muls.aa.hl", 182 /* xt_iclass_mac16a_aa */, 11490 0, 11491 Opcode_muls_aa_hl_encode_fns, 0, 0 }, 11492 { "muls.aa.lh", 182 /* xt_iclass_mac16a_aa */, 11493 0, 11494 Opcode_muls_aa_lh_encode_fns, 0, 0 }, 11495 { "muls.aa.hh", 182 /* xt_iclass_mac16a_aa */, 11496 0, 11497 Opcode_muls_aa_hh_encode_fns, 0, 0 }, 11498 { "mula.ad.ll", 183 /* xt_iclass_mac16a_ad */, 11499 0, 11500 Opcode_mula_ad_ll_encode_fns, 0, 0 }, 11501 { "mula.ad.hl", 183 /* xt_iclass_mac16a_ad */, 11502 0, 11503 Opcode_mula_ad_hl_encode_fns, 0, 0 }, 11504 { "mula.ad.lh", 183 /* xt_iclass_mac16a_ad */, 11505 0, 11506 Opcode_mula_ad_lh_encode_fns, 0, 0 }, 11507 { "mula.ad.hh", 183 /* xt_iclass_mac16a_ad */, 11508 0, 11509 Opcode_mula_ad_hh_encode_fns, 0, 0 }, 11510 { "muls.ad.ll", 183 /* xt_iclass_mac16a_ad */, 11511 0, 11512 Opcode_muls_ad_ll_encode_fns, 0, 0 }, 11513 { "muls.ad.hl", 183 /* xt_iclass_mac16a_ad */, 11514 0, 11515 Opcode_muls_ad_hl_encode_fns, 0, 0 }, 11516 { "muls.ad.lh", 183 /* xt_iclass_mac16a_ad */, 11517 0, 11518 Opcode_muls_ad_lh_encode_fns, 0, 0 }, 11519 { "muls.ad.hh", 183 /* xt_iclass_mac16a_ad */, 11520 0, 11521 Opcode_muls_ad_hh_encode_fns, 0, 0 }, 11522 { "mula.da.ll", 184 /* xt_iclass_mac16a_da */, 11523 0, 11524 Opcode_mula_da_ll_encode_fns, 0, 0 }, 11525 { "mula.da.hl", 184 /* xt_iclass_mac16a_da */, 11526 0, 11527 Opcode_mula_da_hl_encode_fns, 0, 0 }, 11528 { "mula.da.lh", 184 /* xt_iclass_mac16a_da */, 11529 0, 11530 Opcode_mula_da_lh_encode_fns, 0, 0 }, 11531 { "mula.da.hh", 184 /* xt_iclass_mac16a_da */, 11532 0, 11533 Opcode_mula_da_hh_encode_fns, 0, 0 }, 11534 { "muls.da.ll", 184 /* xt_iclass_mac16a_da */, 11535 0, 11536 Opcode_muls_da_ll_encode_fns, 0, 0 }, 11537 { "muls.da.hl", 184 /* xt_iclass_mac16a_da */, 11538 0, 11539 Opcode_muls_da_hl_encode_fns, 0, 0 }, 11540 { "muls.da.lh", 184 /* xt_iclass_mac16a_da */, 11541 0, 11542 Opcode_muls_da_lh_encode_fns, 0, 0 }, 11543 { "muls.da.hh", 184 /* xt_iclass_mac16a_da */, 11544 0, 11545 Opcode_muls_da_hh_encode_fns, 0, 0 }, 11546 { "mula.dd.ll", 185 /* xt_iclass_mac16a_dd */, 11547 0, 11548 Opcode_mula_dd_ll_encode_fns, 0, 0 }, 11549 { "mula.dd.hl", 185 /* xt_iclass_mac16a_dd */, 11550 0, 11551 Opcode_mula_dd_hl_encode_fns, 0, 0 }, 11552 { "mula.dd.lh", 185 /* xt_iclass_mac16a_dd */, 11553 0, 11554 Opcode_mula_dd_lh_encode_fns, 0, 0 }, 11555 { "mula.dd.hh", 185 /* xt_iclass_mac16a_dd */, 11556 0, 11557 Opcode_mula_dd_hh_encode_fns, 0, 0 }, 11558 { "muls.dd.ll", 185 /* xt_iclass_mac16a_dd */, 11559 0, 11560 Opcode_muls_dd_ll_encode_fns, 0, 0 }, 11561 { "muls.dd.hl", 185 /* xt_iclass_mac16a_dd */, 11562 0, 11563 Opcode_muls_dd_hl_encode_fns, 0, 0 }, 11564 { "muls.dd.lh", 185 /* xt_iclass_mac16a_dd */, 11565 0, 11566 Opcode_muls_dd_lh_encode_fns, 0, 0 }, 11567 { "muls.dd.hh", 185 /* xt_iclass_mac16a_dd */, 11568 0, 11569 Opcode_muls_dd_hh_encode_fns, 0, 0 }, 11570 { "mula.da.ll.lddec", 186 /* xt_iclass_mac16al_da */, 11571 0, 11572 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, 11573 { "mula.da.ll.ldinc", 186 /* xt_iclass_mac16al_da */, 11574 0, 11575 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, 11576 { "mula.da.hl.lddec", 186 /* xt_iclass_mac16al_da */, 11577 0, 11578 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, 11579 { "mula.da.hl.ldinc", 186 /* xt_iclass_mac16al_da */, 11580 0, 11581 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, 11582 { "mula.da.lh.lddec", 186 /* xt_iclass_mac16al_da */, 11583 0, 11584 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, 11585 { "mula.da.lh.ldinc", 186 /* xt_iclass_mac16al_da */, 11586 0, 11587 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, 11588 { "mula.da.hh.lddec", 186 /* xt_iclass_mac16al_da */, 11589 0, 11590 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, 11591 { "mula.da.hh.ldinc", 186 /* xt_iclass_mac16al_da */, 11592 0, 11593 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, 11594 { "mula.dd.ll.lddec", 187 /* xt_iclass_mac16al_dd */, 11595 0, 11596 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, 11597 { "mula.dd.ll.ldinc", 187 /* xt_iclass_mac16al_dd */, 11598 0, 11599 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, 11600 { "mula.dd.hl.lddec", 187 /* xt_iclass_mac16al_dd */, 11601 0, 11602 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, 11603 { "mula.dd.hl.ldinc", 187 /* xt_iclass_mac16al_dd */, 11604 0, 11605 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, 11606 { "mula.dd.lh.lddec", 187 /* xt_iclass_mac16al_dd */, 11607 0, 11608 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, 11609 { "mula.dd.lh.ldinc", 187 /* xt_iclass_mac16al_dd */, 11610 0, 11611 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, 11612 { "mula.dd.hh.lddec", 187 /* xt_iclass_mac16al_dd */, 11613 0, 11614 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, 11615 { "mula.dd.hh.ldinc", 187 /* xt_iclass_mac16al_dd */, 11616 0, 11617 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, 11618 { "lddec", 188 /* xt_iclass_mac16_l */, 11619 0, 11620 Opcode_lddec_encode_fns, 0, 0 }, 11621 { "ldinc", 188 /* xt_iclass_mac16_l */, 11622 0, 11623 Opcode_ldinc_encode_fns, 0, 0 }, 11624 { "mul16u", 189 /* xt_iclass_mul16 */, 11625 0, 11626 Opcode_mul16u_encode_fns, 0, 0 }, 11627 { "mul16s", 189 /* xt_iclass_mul16 */, 11628 0, 11629 Opcode_mul16s_encode_fns, 0, 0 }, 11630 { "rsr.m0", 190 /* xt_iclass_rsr.m0 */, 11631 0, 11632 Opcode_rsr_m0_encode_fns, 0, 0 }, 11633 { "wsr.m0", 191 /* xt_iclass_wsr.m0 */, 11634 0, 11635 Opcode_wsr_m0_encode_fns, 0, 0 }, 11636 { "xsr.m0", 192 /* xt_iclass_xsr.m0 */, 11637 0, 11638 Opcode_xsr_m0_encode_fns, 0, 0 }, 11639 { "rsr.m1", 193 /* xt_iclass_rsr.m1 */, 11640 0, 11641 Opcode_rsr_m1_encode_fns, 0, 0 }, 11642 { "wsr.m1", 194 /* xt_iclass_wsr.m1 */, 11643 0, 11644 Opcode_wsr_m1_encode_fns, 0, 0 }, 11645 { "xsr.m1", 195 /* xt_iclass_xsr.m1 */, 11646 0, 11647 Opcode_xsr_m1_encode_fns, 0, 0 }, 11648 { "rsr.m2", 196 /* xt_iclass_rsr.m2 */, 11649 0, 11650 Opcode_rsr_m2_encode_fns, 0, 0 }, 11651 { "wsr.m2", 197 /* xt_iclass_wsr.m2 */, 11652 0, 11653 Opcode_wsr_m2_encode_fns, 0, 0 }, 11654 { "xsr.m2", 198 /* xt_iclass_xsr.m2 */, 11655 0, 11656 Opcode_xsr_m2_encode_fns, 0, 0 }, 11657 { "rsr.m3", 199 /* xt_iclass_rsr.m3 */, 11658 0, 11659 Opcode_rsr_m3_encode_fns, 0, 0 }, 11660 { "wsr.m3", 200 /* xt_iclass_wsr.m3 */, 11661 0, 11662 Opcode_wsr_m3_encode_fns, 0, 0 }, 11663 { "xsr.m3", 201 /* xt_iclass_xsr.m3 */, 11664 0, 11665 Opcode_xsr_m3_encode_fns, 0, 0 }, 11666 { "rsr.acclo", 202 /* xt_iclass_rsr.acclo */, 11667 0, 11668 Opcode_rsr_acclo_encode_fns, 0, 0 }, 11669 { "wsr.acclo", 203 /* xt_iclass_wsr.acclo */, 11670 0, 11671 Opcode_wsr_acclo_encode_fns, 0, 0 }, 11672 { "xsr.acclo", 204 /* xt_iclass_xsr.acclo */, 11673 0, 11674 Opcode_xsr_acclo_encode_fns, 0, 0 }, 11675 { "rsr.acchi", 205 /* xt_iclass_rsr.acchi */, 11676 0, 11677 Opcode_rsr_acchi_encode_fns, 0, 0 }, 11678 { "wsr.acchi", 206 /* xt_iclass_wsr.acchi */, 11679 0, 11680 Opcode_wsr_acchi_encode_fns, 0, 0 }, 11681 { "xsr.acchi", 207 /* xt_iclass_xsr.acchi */, 11682 0, 11683 Opcode_xsr_acchi_encode_fns, 0, 0 }, 11684 { "rfi", 208 /* xt_iclass_rfi */, 11685 XTENSA_OPCODE_IS_JUMP, 11686 Opcode_rfi_encode_fns, 0, 0 }, 11687 { "waiti", 209 /* xt_iclass_wait */, 11688 0, 11689 Opcode_waiti_encode_fns, 0, 0 }, 11690 { "rsr.interrupt", 210 /* xt_iclass_rsr.interrupt */, 11691 0, 11692 Opcode_rsr_interrupt_encode_fns, 0, 0 }, 11693 { "wsr.intset", 211 /* xt_iclass_wsr.intset */, 11694 0, 11695 Opcode_wsr_intset_encode_fns, 0, 0 }, 11696 { "wsr.intclear", 212 /* xt_iclass_wsr.intclear */, 11697 0, 11698 Opcode_wsr_intclear_encode_fns, 0, 0 }, 11699 { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */, 11700 0, 11701 Opcode_rsr_intenable_encode_fns, 0, 0 }, 11702 { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */, 11703 0, 11704 Opcode_wsr_intenable_encode_fns, 0, 0 }, 11705 { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */, 11706 0, 11707 Opcode_xsr_intenable_encode_fns, 0, 0 }, 11708 { "break", 216 /* xt_iclass_break */, 11709 0, 11710 Opcode_break_encode_fns, 0, 0 }, 11711 { "break.n", 217 /* xt_iclass_break.n */, 11712 0, 11713 Opcode_break_n_encode_fns, 0, 0 }, 11714 { "rsr.dbreaka0", 218 /* xt_iclass_rsr.dbreaka0 */, 11715 0, 11716 Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, 11717 { "wsr.dbreaka0", 219 /* xt_iclass_wsr.dbreaka0 */, 11718 0, 11719 Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, 11720 { "xsr.dbreaka0", 220 /* xt_iclass_xsr.dbreaka0 */, 11721 0, 11722 Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, 11723 { "rsr.dbreakc0", 221 /* xt_iclass_rsr.dbreakc0 */, 11724 0, 11725 Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, 11726 { "wsr.dbreakc0", 222 /* xt_iclass_wsr.dbreakc0 */, 11727 0, 11728 Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, 11729 { "xsr.dbreakc0", 223 /* xt_iclass_xsr.dbreakc0 */, 11730 0, 11731 Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, 11732 { "rsr.dbreaka1", 224 /* xt_iclass_rsr.dbreaka1 */, 11733 0, 11734 Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, 11735 { "wsr.dbreaka1", 225 /* xt_iclass_wsr.dbreaka1 */, 11736 0, 11737 Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, 11738 { "xsr.dbreaka1", 226 /* xt_iclass_xsr.dbreaka1 */, 11739 0, 11740 Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, 11741 { "rsr.dbreakc1", 227 /* xt_iclass_rsr.dbreakc1 */, 11742 0, 11743 Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, 11744 { "wsr.dbreakc1", 228 /* xt_iclass_wsr.dbreakc1 */, 11745 0, 11746 Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, 11747 { "xsr.dbreakc1", 229 /* xt_iclass_xsr.dbreakc1 */, 11748 0, 11749 Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, 11750 { "rsr.ibreaka0", 230 /* xt_iclass_rsr.ibreaka0 */, 11751 0, 11752 Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, 11753 { "wsr.ibreaka0", 231 /* xt_iclass_wsr.ibreaka0 */, 11754 0, 11755 Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, 11756 { "xsr.ibreaka0", 232 /* xt_iclass_xsr.ibreaka0 */, 11757 0, 11758 Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, 11759 { "rsr.ibreaka1", 233 /* xt_iclass_rsr.ibreaka1 */, 11760 0, 11761 Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, 11762 { "wsr.ibreaka1", 234 /* xt_iclass_wsr.ibreaka1 */, 11763 0, 11764 Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, 11765 { "xsr.ibreaka1", 235 /* xt_iclass_xsr.ibreaka1 */, 11766 0, 11767 Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, 11768 { "rsr.ibreakenable", 236 /* xt_iclass_rsr.ibreakenable */, 11769 0, 11770 Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, 11771 { "wsr.ibreakenable", 237 /* xt_iclass_wsr.ibreakenable */, 11772 0, 11773 Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, 11774 { "xsr.ibreakenable", 238 /* xt_iclass_xsr.ibreakenable */, 11775 0, 11776 Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, 11777 { "rsr.debugcause", 239 /* xt_iclass_rsr.debugcause */, 11778 0, 11779 Opcode_rsr_debugcause_encode_fns, 0, 0 }, 11780 { "wsr.debugcause", 240 /* xt_iclass_wsr.debugcause */, 11781 0, 11782 Opcode_wsr_debugcause_encode_fns, 0, 0 }, 11783 { "xsr.debugcause", 241 /* xt_iclass_xsr.debugcause */, 11784 0, 11785 Opcode_xsr_debugcause_encode_fns, 0, 0 }, 11786 { "rsr.icount", 242 /* xt_iclass_rsr.icount */, 11787 0, 11788 Opcode_rsr_icount_encode_fns, 0, 0 }, 11789 { "wsr.icount", 243 /* xt_iclass_wsr.icount */, 11790 0, 11791 Opcode_wsr_icount_encode_fns, 0, 0 }, 11792 { "xsr.icount", 244 /* xt_iclass_xsr.icount */, 11793 0, 11794 Opcode_xsr_icount_encode_fns, 0, 0 }, 11795 { "rsr.icountlevel", 245 /* xt_iclass_rsr.icountlevel */, 11796 0, 11797 Opcode_rsr_icountlevel_encode_fns, 0, 0 }, 11798 { "wsr.icountlevel", 246 /* xt_iclass_wsr.icountlevel */, 11799 0, 11800 Opcode_wsr_icountlevel_encode_fns, 0, 0 }, 11801 { "xsr.icountlevel", 247 /* xt_iclass_xsr.icountlevel */, 11802 0, 11803 Opcode_xsr_icountlevel_encode_fns, 0, 0 }, 11804 { "rsr.ddr", 248 /* xt_iclass_rsr.ddr */, 11805 0, 11806 Opcode_rsr_ddr_encode_fns, 0, 0 }, 11807 { "wsr.ddr", 249 /* xt_iclass_wsr.ddr */, 11808 0, 11809 Opcode_wsr_ddr_encode_fns, 0, 0 }, 11810 { "xsr.ddr", 250 /* xt_iclass_xsr.ddr */, 11811 0, 11812 Opcode_xsr_ddr_encode_fns, 0, 0 }, 11813 { "rfdo", 251 /* xt_iclass_rfdo */, 11814 XTENSA_OPCODE_IS_JUMP, 11815 Opcode_rfdo_encode_fns, 0, 0 }, 11816 { "rfdd", 252 /* xt_iclass_rfdd */, 11817 XTENSA_OPCODE_IS_JUMP, 11818 Opcode_rfdd_encode_fns, 0, 0 }, 11819 { "wsr.mmid", 253 /* xt_iclass_wsr.mmid */, 11820 0, 11821 Opcode_wsr_mmid_encode_fns, 0, 0 }, 11822 { "rsr.ccount", 254 /* xt_iclass_rsr.ccount */, 11823 0, 11824 Opcode_rsr_ccount_encode_fns, 0, 0 }, 11825 { "wsr.ccount", 255 /* xt_iclass_wsr.ccount */, 11826 0, 11827 Opcode_wsr_ccount_encode_fns, 0, 0 }, 11828 { "xsr.ccount", 256 /* xt_iclass_xsr.ccount */, 11829 0, 11830 Opcode_xsr_ccount_encode_fns, 0, 0 }, 11831 { "rsr.ccompare0", 257 /* xt_iclass_rsr.ccompare0 */, 11832 0, 11833 Opcode_rsr_ccompare0_encode_fns, 0, 0 }, 11834 { "wsr.ccompare0", 258 /* xt_iclass_wsr.ccompare0 */, 11835 0, 11836 Opcode_wsr_ccompare0_encode_fns, 0, 0 }, 11837 { "xsr.ccompare0", 259 /* xt_iclass_xsr.ccompare0 */, 11838 0, 11839 Opcode_xsr_ccompare0_encode_fns, 0, 0 }, 11840 { "rsr.ccompare1", 260 /* xt_iclass_rsr.ccompare1 */, 11841 0, 11842 Opcode_rsr_ccompare1_encode_fns, 0, 0 }, 11843 { "wsr.ccompare1", 261 /* xt_iclass_wsr.ccompare1 */, 11844 0, 11845 Opcode_wsr_ccompare1_encode_fns, 0, 0 }, 11846 { "xsr.ccompare1", 262 /* xt_iclass_xsr.ccompare1 */, 11847 0, 11848 Opcode_xsr_ccompare1_encode_fns, 0, 0 }, 11849 { "rsr.ccompare2", 263 /* xt_iclass_rsr.ccompare2 */, 11850 0, 11851 Opcode_rsr_ccompare2_encode_fns, 0, 0 }, 11852 { "wsr.ccompare2", 264 /* xt_iclass_wsr.ccompare2 */, 11853 0, 11854 Opcode_wsr_ccompare2_encode_fns, 0, 0 }, 11855 { "xsr.ccompare2", 265 /* xt_iclass_xsr.ccompare2 */, 11856 0, 11857 Opcode_xsr_ccompare2_encode_fns, 0, 0 }, 11858 { "ipf", 266 /* xt_iclass_icache */, 11859 0, 11860 Opcode_ipf_encode_fns, 0, 0 }, 11861 { "ihi", 266 /* xt_iclass_icache */, 11862 0, 11863 Opcode_ihi_encode_fns, 0, 0 }, 11864 { "ipfl", 267 /* xt_iclass_icache_lock */, 11865 0, 11866 Opcode_ipfl_encode_fns, 0, 0 }, 11867 { "ihu", 267 /* xt_iclass_icache_lock */, 11868 0, 11869 Opcode_ihu_encode_fns, 0, 0 }, 11870 { "iiu", 267 /* xt_iclass_icache_lock */, 11871 0, 11872 Opcode_iiu_encode_fns, 0, 0 }, 11873 { "iii", 268 /* xt_iclass_icache_inv */, 11874 0, 11875 Opcode_iii_encode_fns, 0, 0 }, 11876 { "lict", 269 /* xt_iclass_licx */, 11877 0, 11878 Opcode_lict_encode_fns, 0, 0 }, 11879 { "licw", 269 /* xt_iclass_licx */, 11880 0, 11881 Opcode_licw_encode_fns, 0, 0 }, 11882 { "sict", 270 /* xt_iclass_sicx */, 11883 0, 11884 Opcode_sict_encode_fns, 0, 0 }, 11885 { "sicw", 270 /* xt_iclass_sicx */, 11886 0, 11887 Opcode_sicw_encode_fns, 0, 0 }, 11888 { "dhwb", 271 /* xt_iclass_dcache */, 11889 0, 11890 Opcode_dhwb_encode_fns, 0, 0 }, 11891 { "dhwbi", 271 /* xt_iclass_dcache */, 11892 0, 11893 Opcode_dhwbi_encode_fns, 0, 0 }, 11894 { "diwb", 272 /* xt_iclass_dcache_ind */, 11895 0, 11896 Opcode_diwb_encode_fns, 0, 0 }, 11897 { "diwbi", 272 /* xt_iclass_dcache_ind */, 11898 0, 11899 Opcode_diwbi_encode_fns, 0, 0 }, 11900 { "dhi", 273 /* xt_iclass_dcache_inv */, 11901 0, 11902 Opcode_dhi_encode_fns, 0, 0 }, 11903 { "dii", 273 /* xt_iclass_dcache_inv */, 11904 0, 11905 Opcode_dii_encode_fns, 0, 0 }, 11906 { "dpfr", 274 /* xt_iclass_dpf */, 11907 0, 11908 Opcode_dpfr_encode_fns, 0, 0 }, 11909 { "dpfw", 274 /* xt_iclass_dpf */, 11910 0, 11911 Opcode_dpfw_encode_fns, 0, 0 }, 11912 { "dpfro", 274 /* xt_iclass_dpf */, 11913 0, 11914 Opcode_dpfro_encode_fns, 0, 0 }, 11915 { "dpfwo", 274 /* xt_iclass_dpf */, 11916 0, 11917 Opcode_dpfwo_encode_fns, 0, 0 }, 11918 { "dpfl", 275 /* xt_iclass_dcache_lock */, 11919 0, 11920 Opcode_dpfl_encode_fns, 0, 0 }, 11921 { "dhu", 275 /* xt_iclass_dcache_lock */, 11922 0, 11923 Opcode_dhu_encode_fns, 0, 0 }, 11924 { "diu", 275 /* xt_iclass_dcache_lock */, 11925 0, 11926 Opcode_diu_encode_fns, 0, 0 }, 11927 { "sdct", 276 /* xt_iclass_sdct */, 11928 0, 11929 Opcode_sdct_encode_fns, 0, 0 }, 11930 { "ldct", 277 /* xt_iclass_ldct */, 11931 0, 11932 Opcode_ldct_encode_fns, 0, 0 }, 11933 { "wsr.ptevaddr", 278 /* xt_iclass_wsr.ptevaddr */, 11934 0, 11935 Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, 11936 { "rsr.ptevaddr", 279 /* xt_iclass_rsr.ptevaddr */, 11937 0, 11938 Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, 11939 { "xsr.ptevaddr", 280 /* xt_iclass_xsr.ptevaddr */, 11940 0, 11941 Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, 11942 { "rsr.rasid", 281 /* xt_iclass_rsr.rasid */, 11943 0, 11944 Opcode_rsr_rasid_encode_fns, 0, 0 }, 11945 { "wsr.rasid", 282 /* xt_iclass_wsr.rasid */, 11946 0, 11947 Opcode_wsr_rasid_encode_fns, 0, 0 }, 11948 { "xsr.rasid", 283 /* xt_iclass_xsr.rasid */, 11949 0, 11950 Opcode_xsr_rasid_encode_fns, 0, 0 }, 11951 { "rsr.itlbcfg", 284 /* xt_iclass_rsr.itlbcfg */, 11952 0, 11953 Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, 11954 { "wsr.itlbcfg", 285 /* xt_iclass_wsr.itlbcfg */, 11955 0, 11956 Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, 11957 { "xsr.itlbcfg", 286 /* xt_iclass_xsr.itlbcfg */, 11958 0, 11959 Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, 11960 { "rsr.dtlbcfg", 287 /* xt_iclass_rsr.dtlbcfg */, 11961 0, 11962 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, 11963 { "wsr.dtlbcfg", 288 /* xt_iclass_wsr.dtlbcfg */, 11964 0, 11965 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, 11966 { "xsr.dtlbcfg", 289 /* xt_iclass_xsr.dtlbcfg */, 11967 0, 11968 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, 11969 { "idtlb", 290 /* xt_iclass_idtlb */, 11970 0, 11971 Opcode_idtlb_encode_fns, 0, 0 }, 11972 { "pdtlb", 291 /* xt_iclass_rdtlb */, 11973 0, 11974 Opcode_pdtlb_encode_fns, 0, 0 }, 11975 { "rdtlb0", 291 /* xt_iclass_rdtlb */, 11976 0, 11977 Opcode_rdtlb0_encode_fns, 0, 0 }, 11978 { "rdtlb1", 291 /* xt_iclass_rdtlb */, 11979 0, 11980 Opcode_rdtlb1_encode_fns, 0, 0 }, 11981 { "wdtlb", 292 /* xt_iclass_wdtlb */, 11982 0, 11983 Opcode_wdtlb_encode_fns, 0, 0 }, 11984 { "iitlb", 293 /* xt_iclass_iitlb */, 11985 0, 11986 Opcode_iitlb_encode_fns, 0, 0 }, 11987 { "pitlb", 294 /* xt_iclass_ritlb */, 11988 0, 11989 Opcode_pitlb_encode_fns, 0, 0 }, 11990 { "ritlb0", 294 /* xt_iclass_ritlb */, 11991 0, 11992 Opcode_ritlb0_encode_fns, 0, 0 }, 11993 { "ritlb1", 294 /* xt_iclass_ritlb */, 11994 0, 11995 Opcode_ritlb1_encode_fns, 0, 0 }, 11996 { "witlb", 295 /* xt_iclass_witlb */, 11997 0, 11998 Opcode_witlb_encode_fns, 0, 0 }, 11999 { "ldpte", 296 /* xt_iclass_ldpte */, 12000 0, 12001 Opcode_ldpte_encode_fns, 0, 0 }, 12002 { "hwwitlba", 297 /* xt_iclass_hwwitlba */, 12003 XTENSA_OPCODE_IS_BRANCH, 12004 Opcode_hwwitlba_encode_fns, 0, 0 }, 12005 { "hwwdtlba", 298 /* xt_iclass_hwwdtlba */, 12006 0, 12007 Opcode_hwwdtlba_encode_fns, 0, 0 }, 12008 { "rsr.cpenable", 299 /* xt_iclass_rsr.cpenable */, 12009 0, 12010 Opcode_rsr_cpenable_encode_fns, 0, 0 }, 12011 { "wsr.cpenable", 300 /* xt_iclass_wsr.cpenable */, 12012 0, 12013 Opcode_wsr_cpenable_encode_fns, 0, 0 }, 12014 { "xsr.cpenable", 301 /* xt_iclass_xsr.cpenable */, 12015 0, 12016 Opcode_xsr_cpenable_encode_fns, 0, 0 }, 12017 { "clamps", 302 /* xt_iclass_clamp */, 12018 0, 12019 Opcode_clamps_encode_fns, 0, 0 }, 12020 { "min", 303 /* xt_iclass_minmax */, 12021 0, 12022 Opcode_min_encode_fns, 0, 0 }, 12023 { "max", 303 /* xt_iclass_minmax */, 12024 0, 12025 Opcode_max_encode_fns, 0, 0 }, 12026 { "minu", 303 /* xt_iclass_minmax */, 12027 0, 12028 Opcode_minu_encode_fns, 0, 0 }, 12029 { "maxu", 303 /* xt_iclass_minmax */, 12030 0, 12031 Opcode_maxu_encode_fns, 0, 0 }, 12032 { "nsa", 304 /* xt_iclass_nsa */, 12033 0, 12034 Opcode_nsa_encode_fns, 0, 0 }, 12035 { "nsau", 304 /* xt_iclass_nsa */, 12036 0, 12037 Opcode_nsau_encode_fns, 0, 0 }, 12038 { "sext", 305 /* xt_iclass_sx */, 12039 0, 12040 Opcode_sext_encode_fns, 0, 0 }, 12041 { "l32ai", 306 /* xt_iclass_l32ai */, 12042 0, 12043 Opcode_l32ai_encode_fns, 0, 0 }, 12044 { "s32ri", 307 /* xt_iclass_s32ri */, 12045 0, 12046 Opcode_s32ri_encode_fns, 0, 0 }, 12047 { "s32c1i", 308 /* xt_iclass_s32c1i */, 12048 0, 12049 Opcode_s32c1i_encode_fns, 0, 0 }, 12050 { "rsr.scompare1", 309 /* xt_iclass_rsr.scompare1 */, 12051 0, 12052 Opcode_rsr_scompare1_encode_fns, 0, 0 }, 12053 { "wsr.scompare1", 310 /* xt_iclass_wsr.scompare1 */, 12054 0, 12055 Opcode_wsr_scompare1_encode_fns, 0, 0 }, 12056 { "xsr.scompare1", 311 /* xt_iclass_xsr.scompare1 */, 12057 0, 12058 Opcode_xsr_scompare1_encode_fns, 0, 0 }, 12059 { "quou", 312 /* xt_iclass_div */, 12060 0, 12061 Opcode_quou_encode_fns, 0, 0 }, 12062 { "quos", 312 /* xt_iclass_div */, 12063 0, 12064 Opcode_quos_encode_fns, 0, 0 }, 12065 { "remu", 312 /* xt_iclass_div */, 12066 0, 12067 Opcode_remu_encode_fns, 0, 0 }, 12068 { "rems", 312 /* xt_iclass_div */, 12069 0, 12070 Opcode_rems_encode_fns, 0, 0 }, 12071 { "mull", 313 /* xt_mul32 */, 12072 0, 12073 Opcode_mull_encode_fns, 0, 0 }, 12074 { "rur.expstate", 314 /* rur_expstate */, 12075 0, 12076 Opcode_rur_expstate_encode_fns, 0, 0 }, 12077 { "wur.expstate", 315 /* wur_expstate */, 12078 0, 12079 Opcode_wur_expstate_encode_fns, 0, 0 }, 12080 { "read_impwire", 316 /* iclass_READ_IMPWIRE */, 12081 0, 12082 Opcode_read_impwire_encode_fns, 0, 0 }, 12083 { "setb_expstate", 317 /* iclass_SETB_EXPSTATE */, 12084 0, 12085 Opcode_setb_expstate_encode_fns, 0, 0 }, 12086 { "clrb_expstate", 318 /* iclass_CLRB_EXPSTATE */, 12087 0, 12088 Opcode_clrb_expstate_encode_fns, 0, 0 }, 12089 { "wrmsk_expstate", 319 /* iclass_WRMSK_EXPSTATE */, 12090 0, 12091 Opcode_wrmsk_expstate_encode_fns, 0, 0 } 12092}; 12093 12094 12095/* Slot-specific opcode decode functions. */ 12096 12097static int 12098Slot_inst_decode (const xtensa_insnbuf insn) 12099{ 12100 switch (Field_op0_Slot_inst_get (insn)) 12101 { 12102 case 0: 12103 switch (Field_op1_Slot_inst_get (insn)) 12104 { 12105 case 0: 12106 switch (Field_op2_Slot_inst_get (insn)) 12107 { 12108 case 0: 12109 switch (Field_r_Slot_inst_get (insn)) 12110 { 12111 case 0: 12112 switch (Field_m_Slot_inst_get (insn)) 12113 { 12114 case 0: 12115 if (Field_s_Slot_inst_get (insn) == 0 && 12116 Field_n_Slot_inst_get (insn) == 0) 12117 return 79; /* ill */ 12118 break; 12119 case 2: 12120 switch (Field_n_Slot_inst_get (insn)) 12121 { 12122 case 0: 12123 return 98; /* ret */ 12124 case 1: 12125 return 14; /* retw */ 12126 case 2: 12127 return 81; /* jx */ 12128 } 12129 break; 12130 case 3: 12131 switch (Field_n_Slot_inst_get (insn)) 12132 { 12133 case 0: 12134 return 77; /* callx0 */ 12135 case 1: 12136 return 10; /* callx4 */ 12137 case 2: 12138 return 9; /* callx8 */ 12139 case 3: 12140 return 8; /* callx12 */ 12141 } 12142 break; 12143 } 12144 break; 12145 case 1: 12146 return 12; /* movsp */ 12147 case 2: 12148 if (Field_s_Slot_inst_get (insn) == 0) 12149 { 12150 switch (Field_t_Slot_inst_get (insn)) 12151 { 12152 case 0: 12153 return 116; /* isync */ 12154 case 1: 12155 return 117; /* rsync */ 12156 case 2: 12157 return 118; /* esync */ 12158 case 3: 12159 return 119; /* dsync */ 12160 case 8: 12161 return 0; /* excw */ 12162 case 12: 12163 return 114; /* memw */ 12164 case 13: 12165 return 115; /* extw */ 12166 case 15: 12167 return 97; /* nop */ 12168 } 12169 } 12170 break; 12171 case 3: 12172 switch (Field_t_Slot_inst_get (insn)) 12173 { 12174 case 0: 12175 switch (Field_s_Slot_inst_get (insn)) 12176 { 12177 case 0: 12178 return 1; /* rfe */ 12179 case 2: 12180 return 2; /* rfde */ 12181 case 4: 12182 return 16; /* rfwo */ 12183 case 5: 12184 return 17; /* rfwu */ 12185 } 12186 break; 12187 case 1: 12188 return 310; /* rfi */ 12189 } 12190 break; 12191 case 4: 12192 return 318; /* break */ 12193 case 5: 12194 switch (Field_s_Slot_inst_get (insn)) 12195 { 12196 case 0: 12197 if (Field_t_Slot_inst_get (insn) == 0) 12198 return 3; /* syscall */ 12199 break; 12200 case 1: 12201 if (Field_t_Slot_inst_get (insn) == 0) 12202 return 4; /* simcall */ 12203 break; 12204 } 12205 break; 12206 case 6: 12207 return 120; /* rsil */ 12208 case 7: 12209 if (Field_t_Slot_inst_get (insn) == 0) 12210 return 311; /* waiti */ 12211 break; 12212 } 12213 break; 12214 case 1: 12215 return 49; /* and */ 12216 case 2: 12217 return 50; /* or */ 12218 case 3: 12219 return 51; /* xor */ 12220 case 4: 12221 switch (Field_r_Slot_inst_get (insn)) 12222 { 12223 case 0: 12224 if (Field_t_Slot_inst_get (insn) == 0) 12225 return 102; /* ssr */ 12226 break; 12227 case 1: 12228 if (Field_t_Slot_inst_get (insn) == 0) 12229 return 103; /* ssl */ 12230 break; 12231 case 2: 12232 if (Field_t_Slot_inst_get (insn) == 0) 12233 return 104; /* ssa8l */ 12234 break; 12235 case 3: 12236 if (Field_t_Slot_inst_get (insn) == 0) 12237 return 105; /* ssa8b */ 12238 break; 12239 case 4: 12240 if (Field_thi3_Slot_inst_get (insn) == 0) 12241 return 106; /* ssai */ 12242 break; 12243 case 8: 12244 if (Field_s_Slot_inst_get (insn) == 0) 12245 return 13; /* rotw */ 12246 break; 12247 case 14: 12248 return 426; /* nsa */ 12249 case 15: 12250 return 427; /* nsau */ 12251 } 12252 break; 12253 case 5: 12254 switch (Field_r_Slot_inst_get (insn)) 12255 { 12256 case 1: 12257 return 416; /* hwwitlba */ 12258 case 3: 12259 return 412; /* ritlb0 */ 12260 case 4: 12261 if (Field_t_Slot_inst_get (insn) == 0) 12262 return 410; /* iitlb */ 12263 break; 12264 case 5: 12265 return 411; /* pitlb */ 12266 case 6: 12267 return 414; /* witlb */ 12268 case 7: 12269 return 413; /* ritlb1 */ 12270 case 9: 12271 return 417; /* hwwdtlba */ 12272 case 11: 12273 return 407; /* rdtlb0 */ 12274 case 12: 12275 if (Field_t_Slot_inst_get (insn) == 0) 12276 return 405; /* idtlb */ 12277 break; 12278 case 13: 12279 return 406; /* pdtlb */ 12280 case 14: 12281 return 409; /* wdtlb */ 12282 case 15: 12283 return 408; /* rdtlb1 */ 12284 } 12285 break; 12286 case 6: 12287 switch (Field_s_Slot_inst_get (insn)) 12288 { 12289 case 0: 12290 return 95; /* neg */ 12291 case 1: 12292 return 96; /* abs */ 12293 } 12294 break; 12295 case 8: 12296 return 41; /* add */ 12297 case 9: 12298 return 43; /* addx2 */ 12299 case 10: 12300 return 44; /* addx4 */ 12301 case 11: 12302 return 45; /* addx8 */ 12303 case 12: 12304 return 42; /* sub */ 12305 case 13: 12306 return 46; /* subx2 */ 12307 case 14: 12308 return 47; /* subx4 */ 12309 case 15: 12310 return 48; /* subx8 */ 12311 } 12312 break; 12313 case 1: 12314 switch (Field_op2_Slot_inst_get (insn)) 12315 { 12316 case 0: 12317 case 1: 12318 return 111; /* slli */ 12319 case 2: 12320 case 3: 12321 return 112; /* srai */ 12322 case 4: 12323 return 113; /* srli */ 12324 case 6: 12325 switch (Field_sr_Slot_inst_get (insn)) 12326 { 12327 case 0: 12328 return 129; /* xsr.lbeg */ 12329 case 1: 12330 return 123; /* xsr.lend */ 12331 case 2: 12332 return 126; /* xsr.lcount */ 12333 case 3: 12334 return 132; /* xsr.sar */ 12335 case 5: 12336 return 135; /* xsr.litbase */ 12337 case 12: 12338 return 434; /* xsr.scompare1 */ 12339 case 16: 12340 return 306; /* xsr.acclo */ 12341 case 17: 12342 return 309; /* xsr.acchi */ 12343 case 32: 12344 return 294; /* xsr.m0 */ 12345 case 33: 12346 return 297; /* xsr.m1 */ 12347 case 34: 12348 return 300; /* xsr.m2 */ 12349 case 35: 12350 return 303; /* xsr.m3 */ 12351 case 72: 12352 return 22; /* xsr.windowbase */ 12353 case 73: 12354 return 25; /* xsr.windowstart */ 12355 case 83: 12356 return 395; /* xsr.ptevaddr */ 12357 case 90: 12358 return 398; /* xsr.rasid */ 12359 case 91: 12360 return 401; /* xsr.itlbcfg */ 12361 case 92: 12362 return 404; /* xsr.dtlbcfg */ 12363 case 96: 12364 return 340; /* xsr.ibreakenable */ 12365 case 104: 12366 return 352; /* xsr.ddr */ 12367 case 128: 12368 return 334; /* xsr.ibreaka0 */ 12369 case 129: 12370 return 337; /* xsr.ibreaka1 */ 12371 case 144: 12372 return 322; /* xsr.dbreaka0 */ 12373 case 145: 12374 return 328; /* xsr.dbreaka1 */ 12375 case 160: 12376 return 325; /* xsr.dbreakc0 */ 12377 case 161: 12378 return 331; /* xsr.dbreakc1 */ 12379 case 177: 12380 return 143; /* xsr.epc1 */ 12381 case 178: 12382 return 149; /* xsr.epc2 */ 12383 case 179: 12384 return 155; /* xsr.epc3 */ 12385 case 180: 12386 return 161; /* xsr.epc4 */ 12387 case 181: 12388 return 167; /* xsr.epc5 */ 12389 case 182: 12390 return 173; /* xsr.epc6 */ 12391 case 183: 12392 return 179; /* xsr.epc7 */ 12393 case 192: 12394 return 206; /* xsr.depc */ 12395 case 194: 12396 return 185; /* xsr.eps2 */ 12397 case 195: 12398 return 188; /* xsr.eps3 */ 12399 case 196: 12400 return 191; /* xsr.eps4 */ 12401 case 197: 12402 return 194; /* xsr.eps5 */ 12403 case 198: 12404 return 197; /* xsr.eps6 */ 12405 case 199: 12406 return 200; /* xsr.eps7 */ 12407 case 209: 12408 return 146; /* xsr.excsave1 */ 12409 case 210: 12410 return 152; /* xsr.excsave2 */ 12411 case 211: 12412 return 158; /* xsr.excsave3 */ 12413 case 212: 12414 return 164; /* xsr.excsave4 */ 12415 case 213: 12416 return 170; /* xsr.excsave5 */ 12417 case 214: 12418 return 176; /* xsr.excsave6 */ 12419 case 215: 12420 return 182; /* xsr.excsave7 */ 12421 case 224: 12422 return 420; /* xsr.cpenable */ 12423 case 228: 12424 return 317; /* xsr.intenable */ 12425 case 230: 12426 return 140; /* xsr.ps */ 12427 case 231: 12428 return 219; /* xsr.vecbase */ 12429 case 232: 12430 return 209; /* xsr.exccause */ 12431 case 233: 12432 return 343; /* xsr.debugcause */ 12433 case 234: 12434 return 358; /* xsr.ccount */ 12435 case 236: 12436 return 346; /* xsr.icount */ 12437 case 237: 12438 return 349; /* xsr.icountlevel */ 12439 case 238: 12440 return 203; /* xsr.excvaddr */ 12441 case 240: 12442 return 361; /* xsr.ccompare0 */ 12443 case 241: 12444 return 364; /* xsr.ccompare1 */ 12445 case 242: 12446 return 367; /* xsr.ccompare2 */ 12447 case 244: 12448 return 212; /* xsr.misc0 */ 12449 case 245: 12450 return 215; /* xsr.misc1 */ 12451 } 12452 break; 12453 case 8: 12454 return 108; /* src */ 12455 case 9: 12456 if (Field_s_Slot_inst_get (insn) == 0) 12457 return 109; /* srl */ 12458 break; 12459 case 10: 12460 if (Field_t_Slot_inst_get (insn) == 0) 12461 return 107; /* sll */ 12462 break; 12463 case 11: 12464 if (Field_s_Slot_inst_get (insn) == 0) 12465 return 110; /* sra */ 12466 break; 12467 case 12: 12468 return 290; /* mul16u */ 12469 case 13: 12470 return 291; /* mul16s */ 12471 case 15: 12472 switch (Field_r_Slot_inst_get (insn)) 12473 { 12474 case 0: 12475 return 374; /* lict */ 12476 case 1: 12477 return 376; /* sict */ 12478 case 2: 12479 return 375; /* licw */ 12480 case 3: 12481 return 377; /* sicw */ 12482 case 8: 12483 return 392; /* ldct */ 12484 case 9: 12485 return 391; /* sdct */ 12486 case 14: 12487 if (Field_t_Slot_inst_get (insn) == 0) 12488 return 353; /* rfdo */ 12489 if (Field_t_Slot_inst_get (insn) == 1) 12490 return 354; /* rfdd */ 12491 break; 12492 case 15: 12493 return 415; /* ldpte */ 12494 } 12495 break; 12496 } 12497 break; 12498 case 2: 12499 switch (Field_op2_Slot_inst_get (insn)) 12500 { 12501 case 8: 12502 return 439; /* mull */ 12503 case 12: 12504 return 435; /* quou */ 12505 case 13: 12506 return 436; /* quos */ 12507 case 14: 12508 return 437; /* remu */ 12509 case 15: 12510 return 438; /* rems */ 12511 } 12512 break; 12513 case 3: 12514 switch (Field_op2_Slot_inst_get (insn)) 12515 { 12516 case 0: 12517 switch (Field_sr_Slot_inst_get (insn)) 12518 { 12519 case 0: 12520 return 127; /* rsr.lbeg */ 12521 case 1: 12522 return 121; /* rsr.lend */ 12523 case 2: 12524 return 124; /* rsr.lcount */ 12525 case 3: 12526 return 130; /* rsr.sar */ 12527 case 5: 12528 return 133; /* rsr.litbase */ 12529 case 12: 12530 return 432; /* rsr.scompare1 */ 12531 case 16: 12532 return 304; /* rsr.acclo */ 12533 case 17: 12534 return 307; /* rsr.acchi */ 12535 case 32: 12536 return 292; /* rsr.m0 */ 12537 case 33: 12538 return 295; /* rsr.m1 */ 12539 case 34: 12540 return 298; /* rsr.m2 */ 12541 case 35: 12542 return 301; /* rsr.m3 */ 12543 case 72: 12544 return 20; /* rsr.windowbase */ 12545 case 73: 12546 return 23; /* rsr.windowstart */ 12547 case 83: 12548 return 394; /* rsr.ptevaddr */ 12549 case 90: 12550 return 396; /* rsr.rasid */ 12551 case 91: 12552 return 399; /* rsr.itlbcfg */ 12553 case 92: 12554 return 402; /* rsr.dtlbcfg */ 12555 case 96: 12556 return 338; /* rsr.ibreakenable */ 12557 case 104: 12558 return 350; /* rsr.ddr */ 12559 case 128: 12560 return 332; /* rsr.ibreaka0 */ 12561 case 129: 12562 return 335; /* rsr.ibreaka1 */ 12563 case 144: 12564 return 320; /* rsr.dbreaka0 */ 12565 case 145: 12566 return 326; /* rsr.dbreaka1 */ 12567 case 160: 12568 return 323; /* rsr.dbreakc0 */ 12569 case 161: 12570 return 329; /* rsr.dbreakc1 */ 12571 case 176: 12572 return 136; /* rsr.176 */ 12573 case 177: 12574 return 141; /* rsr.epc1 */ 12575 case 178: 12576 return 147; /* rsr.epc2 */ 12577 case 179: 12578 return 153; /* rsr.epc3 */ 12579 case 180: 12580 return 159; /* rsr.epc4 */ 12581 case 181: 12582 return 165; /* rsr.epc5 */ 12583 case 182: 12584 return 171; /* rsr.epc6 */ 12585 case 183: 12586 return 177; /* rsr.epc7 */ 12587 case 192: 12588 return 204; /* rsr.depc */ 12589 case 194: 12590 return 183; /* rsr.eps2 */ 12591 case 195: 12592 return 186; /* rsr.eps3 */ 12593 case 196: 12594 return 189; /* rsr.eps4 */ 12595 case 197: 12596 return 192; /* rsr.eps5 */ 12597 case 198: 12598 return 195; /* rsr.eps6 */ 12599 case 199: 12600 return 198; /* rsr.eps7 */ 12601 case 208: 12602 return 137; /* rsr.208 */ 12603 case 209: 12604 return 144; /* rsr.excsave1 */ 12605 case 210: 12606 return 150; /* rsr.excsave2 */ 12607 case 211: 12608 return 156; /* rsr.excsave3 */ 12609 case 212: 12610 return 162; /* rsr.excsave4 */ 12611 case 213: 12612 return 168; /* rsr.excsave5 */ 12613 case 214: 12614 return 174; /* rsr.excsave6 */ 12615 case 215: 12616 return 180; /* rsr.excsave7 */ 12617 case 224: 12618 return 418; /* rsr.cpenable */ 12619 case 226: 12620 return 312; /* rsr.interrupt */ 12621 case 228: 12622 return 315; /* rsr.intenable */ 12623 case 230: 12624 return 138; /* rsr.ps */ 12625 case 231: 12626 return 217; /* rsr.vecbase */ 12627 case 232: 12628 return 207; /* rsr.exccause */ 12629 case 233: 12630 return 341; /* rsr.debugcause */ 12631 case 234: 12632 return 356; /* rsr.ccount */ 12633 case 235: 12634 return 216; /* rsr.prid */ 12635 case 236: 12636 return 344; /* rsr.icount */ 12637 case 237: 12638 return 347; /* rsr.icountlevel */ 12639 case 238: 12640 return 201; /* rsr.excvaddr */ 12641 case 240: 12642 return 359; /* rsr.ccompare0 */ 12643 case 241: 12644 return 362; /* rsr.ccompare1 */ 12645 case 242: 12646 return 365; /* rsr.ccompare2 */ 12647 case 244: 12648 return 210; /* rsr.misc0 */ 12649 case 245: 12650 return 213; /* rsr.misc1 */ 12651 } 12652 break; 12653 case 1: 12654 switch (Field_sr_Slot_inst_get (insn)) 12655 { 12656 case 0: 12657 return 128; /* wsr.lbeg */ 12658 case 1: 12659 return 122; /* wsr.lend */ 12660 case 2: 12661 return 125; /* wsr.lcount */ 12662 case 3: 12663 return 131; /* wsr.sar */ 12664 case 5: 12665 return 134; /* wsr.litbase */ 12666 case 12: 12667 return 433; /* wsr.scompare1 */ 12668 case 16: 12669 return 305; /* wsr.acclo */ 12670 case 17: 12671 return 308; /* wsr.acchi */ 12672 case 32: 12673 return 293; /* wsr.m0 */ 12674 case 33: 12675 return 296; /* wsr.m1 */ 12676 case 34: 12677 return 299; /* wsr.m2 */ 12678 case 35: 12679 return 302; /* wsr.m3 */ 12680 case 72: 12681 return 21; /* wsr.windowbase */ 12682 case 73: 12683 return 24; /* wsr.windowstart */ 12684 case 83: 12685 return 393; /* wsr.ptevaddr */ 12686 case 89: 12687 return 355; /* wsr.mmid */ 12688 case 90: 12689 return 397; /* wsr.rasid */ 12690 case 91: 12691 return 400; /* wsr.itlbcfg */ 12692 case 92: 12693 return 403; /* wsr.dtlbcfg */ 12694 case 96: 12695 return 339; /* wsr.ibreakenable */ 12696 case 104: 12697 return 351; /* wsr.ddr */ 12698 case 128: 12699 return 333; /* wsr.ibreaka0 */ 12700 case 129: 12701 return 336; /* wsr.ibreaka1 */ 12702 case 144: 12703 return 321; /* wsr.dbreaka0 */ 12704 case 145: 12705 return 327; /* wsr.dbreaka1 */ 12706 case 160: 12707 return 324; /* wsr.dbreakc0 */ 12708 case 161: 12709 return 330; /* wsr.dbreakc1 */ 12710 case 177: 12711 return 142; /* wsr.epc1 */ 12712 case 178: 12713 return 148; /* wsr.epc2 */ 12714 case 179: 12715 return 154; /* wsr.epc3 */ 12716 case 180: 12717 return 160; /* wsr.epc4 */ 12718 case 181: 12719 return 166; /* wsr.epc5 */ 12720 case 182: 12721 return 172; /* wsr.epc6 */ 12722 case 183: 12723 return 178; /* wsr.epc7 */ 12724 case 192: 12725 return 205; /* wsr.depc */ 12726 case 194: 12727 return 184; /* wsr.eps2 */ 12728 case 195: 12729 return 187; /* wsr.eps3 */ 12730 case 196: 12731 return 190; /* wsr.eps4 */ 12732 case 197: 12733 return 193; /* wsr.eps5 */ 12734 case 198: 12735 return 196; /* wsr.eps6 */ 12736 case 199: 12737 return 199; /* wsr.eps7 */ 12738 case 209: 12739 return 145; /* wsr.excsave1 */ 12740 case 210: 12741 return 151; /* wsr.excsave2 */ 12742 case 211: 12743 return 157; /* wsr.excsave3 */ 12744 case 212: 12745 return 163; /* wsr.excsave4 */ 12746 case 213: 12747 return 169; /* wsr.excsave5 */ 12748 case 214: 12749 return 175; /* wsr.excsave6 */ 12750 case 215: 12751 return 181; /* wsr.excsave7 */ 12752 case 224: 12753 return 419; /* wsr.cpenable */ 12754 case 226: 12755 return 313; /* wsr.intset */ 12756 case 227: 12757 return 314; /* wsr.intclear */ 12758 case 228: 12759 return 316; /* wsr.intenable */ 12760 case 230: 12761 return 139; /* wsr.ps */ 12762 case 231: 12763 return 218; /* wsr.vecbase */ 12764 case 232: 12765 return 208; /* wsr.exccause */ 12766 case 233: 12767 return 342; /* wsr.debugcause */ 12768 case 234: 12769 return 357; /* wsr.ccount */ 12770 case 236: 12771 return 345; /* wsr.icount */ 12772 case 237: 12773 return 348; /* wsr.icountlevel */ 12774 case 238: 12775 return 202; /* wsr.excvaddr */ 12776 case 240: 12777 return 360; /* wsr.ccompare0 */ 12778 case 241: 12779 return 363; /* wsr.ccompare1 */ 12780 case 242: 12781 return 366; /* wsr.ccompare2 */ 12782 case 244: 12783 return 211; /* wsr.misc0 */ 12784 case 245: 12785 return 214; /* wsr.misc1 */ 12786 } 12787 break; 12788 case 2: 12789 return 428; /* sext */ 12790 case 3: 12791 return 421; /* clamps */ 12792 case 4: 12793 return 422; /* min */ 12794 case 5: 12795 return 423; /* max */ 12796 case 6: 12797 return 424; /* minu */ 12798 case 7: 12799 return 425; /* maxu */ 12800 case 8: 12801 return 91; /* moveqz */ 12802 case 9: 12803 return 92; /* movnez */ 12804 case 10: 12805 return 93; /* movltz */ 12806 case 11: 12807 return 94; /* movgez */ 12808 case 14: 12809 switch (Field_st_Slot_inst_get (insn)) 12810 { 12811 case 230: 12812 return 440; /* rur.expstate */ 12813 case 231: 12814 return 37; /* rur.threadptr */ 12815 } 12816 break; 12817 case 15: 12818 switch (Field_sr_Slot_inst_get (insn)) 12819 { 12820 case 230: 12821 return 441; /* wur.expstate */ 12822 case 231: 12823 return 38; /* wur.threadptr */ 12824 } 12825 break; 12826 } 12827 break; 12828 case 4: 12829 case 5: 12830 return 78; /* extui */ 12831 case 9: 12832 switch (Field_op2_Slot_inst_get (insn)) 12833 { 12834 case 0: 12835 return 18; /* l32e */ 12836 case 4: 12837 return 19; /* s32e */ 12838 } 12839 break; 12840 } 12841 switch (Field_r_Slot_inst_get (insn)) 12842 { 12843 case 0: 12844 if (Field_s_Slot_inst_get (insn) == 0 && 12845 Field_op2_Slot_inst_get (insn) == 0 && 12846 Field_op1_Slot_inst_get (insn) == 14) 12847 return 442; /* read_impwire */ 12848 break; 12849 case 1: 12850 if (Field_s3to1_Slot_inst_get (insn) == 0 && 12851 Field_op2_Slot_inst_get (insn) == 0 && 12852 Field_op1_Slot_inst_get (insn) == 14) 12853 return 443; /* setb_expstate */ 12854 if (Field_s3to1_Slot_inst_get (insn) == 1 && 12855 Field_op2_Slot_inst_get (insn) == 0 && 12856 Field_op1_Slot_inst_get (insn) == 14) 12857 return 444; /* clrb_expstate */ 12858 break; 12859 case 2: 12860 if (Field_op2_Slot_inst_get (insn) == 0 && 12861 Field_op1_Slot_inst_get (insn) == 14) 12862 return 445; /* wrmsk_expstate */ 12863 break; 12864 } 12865 break; 12866 case 1: 12867 return 85; /* l32r */ 12868 case 2: 12869 switch (Field_r_Slot_inst_get (insn)) 12870 { 12871 case 0: 12872 return 86; /* l8ui */ 12873 case 1: 12874 return 82; /* l16ui */ 12875 case 2: 12876 return 84; /* l32i */ 12877 case 4: 12878 return 101; /* s8i */ 12879 case 5: 12880 return 99; /* s16i */ 12881 case 6: 12882 return 100; /* s32i */ 12883 case 7: 12884 switch (Field_t_Slot_inst_get (insn)) 12885 { 12886 case 0: 12887 return 384; /* dpfr */ 12888 case 1: 12889 return 385; /* dpfw */ 12890 case 2: 12891 return 386; /* dpfro */ 12892 case 3: 12893 return 387; /* dpfwo */ 12894 case 4: 12895 return 378; /* dhwb */ 12896 case 5: 12897 return 379; /* dhwbi */ 12898 case 6: 12899 return 382; /* dhi */ 12900 case 7: 12901 return 383; /* dii */ 12902 case 8: 12903 switch (Field_op1_Slot_inst_get (insn)) 12904 { 12905 case 0: 12906 return 388; /* dpfl */ 12907 case 2: 12908 return 389; /* dhu */ 12909 case 3: 12910 return 390; /* diu */ 12911 case 4: 12912 return 380; /* diwb */ 12913 case 5: 12914 return 381; /* diwbi */ 12915 } 12916 break; 12917 case 12: 12918 return 368; /* ipf */ 12919 case 13: 12920 switch (Field_op1_Slot_inst_get (insn)) 12921 { 12922 case 0: 12923 return 370; /* ipfl */ 12924 case 2: 12925 return 371; /* ihu */ 12926 case 3: 12927 return 372; /* iiu */ 12928 } 12929 break; 12930 case 14: 12931 return 369; /* ihi */ 12932 case 15: 12933 return 373; /* iii */ 12934 } 12935 break; 12936 case 9: 12937 return 83; /* l16si */ 12938 case 10: 12939 return 90; /* movi */ 12940 case 11: 12941 return 429; /* l32ai */ 12942 case 12: 12943 return 39; /* addi */ 12944 case 13: 12945 return 40; /* addmi */ 12946 case 14: 12947 return 431; /* s32c1i */ 12948 case 15: 12949 return 430; /* s32ri */ 12950 } 12951 break; 12952 case 4: 12953 switch (Field_op2_Slot_inst_get (insn)) 12954 { 12955 case 0: 12956 switch (Field_op1_Slot_inst_get (insn)) 12957 { 12958 case 8: 12959 if (Field_t3_Slot_inst_get (insn) == 0 && 12960 Field_tlo_Slot_inst_get (insn) == 0 && 12961 Field_r3_Slot_inst_get (insn) == 0) 12962 return 281; /* mula.dd.ll.ldinc */ 12963 break; 12964 case 9: 12965 if (Field_t3_Slot_inst_get (insn) == 0 && 12966 Field_tlo_Slot_inst_get (insn) == 0 && 12967 Field_r3_Slot_inst_get (insn) == 0) 12968 return 283; /* mula.dd.hl.ldinc */ 12969 break; 12970 case 10: 12971 if (Field_t3_Slot_inst_get (insn) == 0 && 12972 Field_tlo_Slot_inst_get (insn) == 0 && 12973 Field_r3_Slot_inst_get (insn) == 0) 12974 return 285; /* mula.dd.lh.ldinc */ 12975 break; 12976 case 11: 12977 if (Field_t3_Slot_inst_get (insn) == 0 && 12978 Field_tlo_Slot_inst_get (insn) == 0 && 12979 Field_r3_Slot_inst_get (insn) == 0) 12980 return 287; /* mula.dd.hh.ldinc */ 12981 break; 12982 } 12983 break; 12984 case 1: 12985 switch (Field_op1_Slot_inst_get (insn)) 12986 { 12987 case 8: 12988 if (Field_t3_Slot_inst_get (insn) == 0 && 12989 Field_tlo_Slot_inst_get (insn) == 0 && 12990 Field_r3_Slot_inst_get (insn) == 0) 12991 return 280; /* mula.dd.ll.lddec */ 12992 break; 12993 case 9: 12994 if (Field_t3_Slot_inst_get (insn) == 0 && 12995 Field_tlo_Slot_inst_get (insn) == 0 && 12996 Field_r3_Slot_inst_get (insn) == 0) 12997 return 282; /* mula.dd.hl.lddec */ 12998 break; 12999 case 10: 13000 if (Field_t3_Slot_inst_get (insn) == 0 && 13001 Field_tlo_Slot_inst_get (insn) == 0 && 13002 Field_r3_Slot_inst_get (insn) == 0) 13003 return 284; /* mula.dd.lh.lddec */ 13004 break; 13005 case 11: 13006 if (Field_t3_Slot_inst_get (insn) == 0 && 13007 Field_tlo_Slot_inst_get (insn) == 0 && 13008 Field_r3_Slot_inst_get (insn) == 0) 13009 return 286; /* mula.dd.hh.lddec */ 13010 break; 13011 } 13012 break; 13013 case 2: 13014 switch (Field_op1_Slot_inst_get (insn)) 13015 { 13016 case 4: 13017 if (Field_s_Slot_inst_get (insn) == 0 && 13018 Field_w_Slot_inst_get (insn) == 0 && 13019 Field_r3_Slot_inst_get (insn) == 0 && 13020 Field_t3_Slot_inst_get (insn) == 0 && 13021 Field_tlo_Slot_inst_get (insn) == 0) 13022 return 236; /* mul.dd.ll */ 13023 break; 13024 case 5: 13025 if (Field_s_Slot_inst_get (insn) == 0 && 13026 Field_w_Slot_inst_get (insn) == 0 && 13027 Field_r3_Slot_inst_get (insn) == 0 && 13028 Field_t3_Slot_inst_get (insn) == 0 && 13029 Field_tlo_Slot_inst_get (insn) == 0) 13030 return 237; /* mul.dd.hl */ 13031 break; 13032 case 6: 13033 if (Field_s_Slot_inst_get (insn) == 0 && 13034 Field_w_Slot_inst_get (insn) == 0 && 13035 Field_r3_Slot_inst_get (insn) == 0 && 13036 Field_t3_Slot_inst_get (insn) == 0 && 13037 Field_tlo_Slot_inst_get (insn) == 0) 13038 return 238; /* mul.dd.lh */ 13039 break; 13040 case 7: 13041 if (Field_s_Slot_inst_get (insn) == 0 && 13042 Field_w_Slot_inst_get (insn) == 0 && 13043 Field_r3_Slot_inst_get (insn) == 0 && 13044 Field_t3_Slot_inst_get (insn) == 0 && 13045 Field_tlo_Slot_inst_get (insn) == 0) 13046 return 239; /* mul.dd.hh */ 13047 break; 13048 case 8: 13049 if (Field_s_Slot_inst_get (insn) == 0 && 13050 Field_w_Slot_inst_get (insn) == 0 && 13051 Field_r3_Slot_inst_get (insn) == 0 && 13052 Field_t3_Slot_inst_get (insn) == 0 && 13053 Field_tlo_Slot_inst_get (insn) == 0) 13054 return 264; /* mula.dd.ll */ 13055 break; 13056 case 9: 13057 if (Field_s_Slot_inst_get (insn) == 0 && 13058 Field_w_Slot_inst_get (insn) == 0 && 13059 Field_r3_Slot_inst_get (insn) == 0 && 13060 Field_t3_Slot_inst_get (insn) == 0 && 13061 Field_tlo_Slot_inst_get (insn) == 0) 13062 return 265; /* mula.dd.hl */ 13063 break; 13064 case 10: 13065 if (Field_s_Slot_inst_get (insn) == 0 && 13066 Field_w_Slot_inst_get (insn) == 0 && 13067 Field_r3_Slot_inst_get (insn) == 0 && 13068 Field_t3_Slot_inst_get (insn) == 0 && 13069 Field_tlo_Slot_inst_get (insn) == 0) 13070 return 266; /* mula.dd.lh */ 13071 break; 13072 case 11: 13073 if (Field_s_Slot_inst_get (insn) == 0 && 13074 Field_w_Slot_inst_get (insn) == 0 && 13075 Field_r3_Slot_inst_get (insn) == 0 && 13076 Field_t3_Slot_inst_get (insn) == 0 && 13077 Field_tlo_Slot_inst_get (insn) == 0) 13078 return 267; /* mula.dd.hh */ 13079 break; 13080 case 12: 13081 if (Field_s_Slot_inst_get (insn) == 0 && 13082 Field_w_Slot_inst_get (insn) == 0 && 13083 Field_r3_Slot_inst_get (insn) == 0 && 13084 Field_t3_Slot_inst_get (insn) == 0 && 13085 Field_tlo_Slot_inst_get (insn) == 0) 13086 return 268; /* muls.dd.ll */ 13087 break; 13088 case 13: 13089 if (Field_s_Slot_inst_get (insn) == 0 && 13090 Field_w_Slot_inst_get (insn) == 0 && 13091 Field_r3_Slot_inst_get (insn) == 0 && 13092 Field_t3_Slot_inst_get (insn) == 0 && 13093 Field_tlo_Slot_inst_get (insn) == 0) 13094 return 269; /* muls.dd.hl */ 13095 break; 13096 case 14: 13097 if (Field_s_Slot_inst_get (insn) == 0 && 13098 Field_w_Slot_inst_get (insn) == 0 && 13099 Field_r3_Slot_inst_get (insn) == 0 && 13100 Field_t3_Slot_inst_get (insn) == 0 && 13101 Field_tlo_Slot_inst_get (insn) == 0) 13102 return 270; /* muls.dd.lh */ 13103 break; 13104 case 15: 13105 if (Field_s_Slot_inst_get (insn) == 0 && 13106 Field_w_Slot_inst_get (insn) == 0 && 13107 Field_r3_Slot_inst_get (insn) == 0 && 13108 Field_t3_Slot_inst_get (insn) == 0 && 13109 Field_tlo_Slot_inst_get (insn) == 0) 13110 return 271; /* muls.dd.hh */ 13111 break; 13112 } 13113 break; 13114 case 3: 13115 switch (Field_op1_Slot_inst_get (insn)) 13116 { 13117 case 4: 13118 if (Field_r_Slot_inst_get (insn) == 0 && 13119 Field_t3_Slot_inst_get (insn) == 0 && 13120 Field_tlo_Slot_inst_get (insn) == 0) 13121 return 228; /* mul.ad.ll */ 13122 break; 13123 case 5: 13124 if (Field_r_Slot_inst_get (insn) == 0 && 13125 Field_t3_Slot_inst_get (insn) == 0 && 13126 Field_tlo_Slot_inst_get (insn) == 0) 13127 return 229; /* mul.ad.hl */ 13128 break; 13129 case 6: 13130 if (Field_r_Slot_inst_get (insn) == 0 && 13131 Field_t3_Slot_inst_get (insn) == 0 && 13132 Field_tlo_Slot_inst_get (insn) == 0) 13133 return 230; /* mul.ad.lh */ 13134 break; 13135 case 7: 13136 if (Field_r_Slot_inst_get (insn) == 0 && 13137 Field_t3_Slot_inst_get (insn) == 0 && 13138 Field_tlo_Slot_inst_get (insn) == 0) 13139 return 231; /* mul.ad.hh */ 13140 break; 13141 case 8: 13142 if (Field_r_Slot_inst_get (insn) == 0 && 13143 Field_t3_Slot_inst_get (insn) == 0 && 13144 Field_tlo_Slot_inst_get (insn) == 0) 13145 return 248; /* mula.ad.ll */ 13146 break; 13147 case 9: 13148 if (Field_r_Slot_inst_get (insn) == 0 && 13149 Field_t3_Slot_inst_get (insn) == 0 && 13150 Field_tlo_Slot_inst_get (insn) == 0) 13151 return 249; /* mula.ad.hl */ 13152 break; 13153 case 10: 13154 if (Field_r_Slot_inst_get (insn) == 0 && 13155 Field_t3_Slot_inst_get (insn) == 0 && 13156 Field_tlo_Slot_inst_get (insn) == 0) 13157 return 250; /* mula.ad.lh */ 13158 break; 13159 case 11: 13160 if (Field_r_Slot_inst_get (insn) == 0 && 13161 Field_t3_Slot_inst_get (insn) == 0 && 13162 Field_tlo_Slot_inst_get (insn) == 0) 13163 return 251; /* mula.ad.hh */ 13164 break; 13165 case 12: 13166 if (Field_r_Slot_inst_get (insn) == 0 && 13167 Field_t3_Slot_inst_get (insn) == 0 && 13168 Field_tlo_Slot_inst_get (insn) == 0) 13169 return 252; /* muls.ad.ll */ 13170 break; 13171 case 13: 13172 if (Field_r_Slot_inst_get (insn) == 0 && 13173 Field_t3_Slot_inst_get (insn) == 0 && 13174 Field_tlo_Slot_inst_get (insn) == 0) 13175 return 253; /* muls.ad.hl */ 13176 break; 13177 case 14: 13178 if (Field_r_Slot_inst_get (insn) == 0 && 13179 Field_t3_Slot_inst_get (insn) == 0 && 13180 Field_tlo_Slot_inst_get (insn) == 0) 13181 return 254; /* muls.ad.lh */ 13182 break; 13183 case 15: 13184 if (Field_r_Slot_inst_get (insn) == 0 && 13185 Field_t3_Slot_inst_get (insn) == 0 && 13186 Field_tlo_Slot_inst_get (insn) == 0) 13187 return 255; /* muls.ad.hh */ 13188 break; 13189 } 13190 break; 13191 case 4: 13192 switch (Field_op1_Slot_inst_get (insn)) 13193 { 13194 case 8: 13195 if (Field_r3_Slot_inst_get (insn) == 0) 13196 return 273; /* mula.da.ll.ldinc */ 13197 break; 13198 case 9: 13199 if (Field_r3_Slot_inst_get (insn) == 0) 13200 return 275; /* mula.da.hl.ldinc */ 13201 break; 13202 case 10: 13203 if (Field_r3_Slot_inst_get (insn) == 0) 13204 return 277; /* mula.da.lh.ldinc */ 13205 break; 13206 case 11: 13207 if (Field_r3_Slot_inst_get (insn) == 0) 13208 return 279; /* mula.da.hh.ldinc */ 13209 break; 13210 } 13211 break; 13212 case 5: 13213 switch (Field_op1_Slot_inst_get (insn)) 13214 { 13215 case 8: 13216 if (Field_r3_Slot_inst_get (insn) == 0) 13217 return 272; /* mula.da.ll.lddec */ 13218 break; 13219 case 9: 13220 if (Field_r3_Slot_inst_get (insn) == 0) 13221 return 274; /* mula.da.hl.lddec */ 13222 break; 13223 case 10: 13224 if (Field_r3_Slot_inst_get (insn) == 0) 13225 return 276; /* mula.da.lh.lddec */ 13226 break; 13227 case 11: 13228 if (Field_r3_Slot_inst_get (insn) == 0) 13229 return 278; /* mula.da.hh.lddec */ 13230 break; 13231 } 13232 break; 13233 case 6: 13234 switch (Field_op1_Slot_inst_get (insn)) 13235 { 13236 case 4: 13237 if (Field_s_Slot_inst_get (insn) == 0 && 13238 Field_w_Slot_inst_get (insn) == 0 && 13239 Field_r3_Slot_inst_get (insn) == 0) 13240 return 232; /* mul.da.ll */ 13241 break; 13242 case 5: 13243 if (Field_s_Slot_inst_get (insn) == 0 && 13244 Field_w_Slot_inst_get (insn) == 0 && 13245 Field_r3_Slot_inst_get (insn) == 0) 13246 return 233; /* mul.da.hl */ 13247 break; 13248 case 6: 13249 if (Field_s_Slot_inst_get (insn) == 0 && 13250 Field_w_Slot_inst_get (insn) == 0 && 13251 Field_r3_Slot_inst_get (insn) == 0) 13252 return 234; /* mul.da.lh */ 13253 break; 13254 case 7: 13255 if (Field_s_Slot_inst_get (insn) == 0 && 13256 Field_w_Slot_inst_get (insn) == 0 && 13257 Field_r3_Slot_inst_get (insn) == 0) 13258 return 235; /* mul.da.hh */ 13259 break; 13260 case 8: 13261 if (Field_s_Slot_inst_get (insn) == 0 && 13262 Field_w_Slot_inst_get (insn) == 0 && 13263 Field_r3_Slot_inst_get (insn) == 0) 13264 return 256; /* mula.da.ll */ 13265 break; 13266 case 9: 13267 if (Field_s_Slot_inst_get (insn) == 0 && 13268 Field_w_Slot_inst_get (insn) == 0 && 13269 Field_r3_Slot_inst_get (insn) == 0) 13270 return 257; /* mula.da.hl */ 13271 break; 13272 case 10: 13273 if (Field_s_Slot_inst_get (insn) == 0 && 13274 Field_w_Slot_inst_get (insn) == 0 && 13275 Field_r3_Slot_inst_get (insn) == 0) 13276 return 258; /* mula.da.lh */ 13277 break; 13278 case 11: 13279 if (Field_s_Slot_inst_get (insn) == 0 && 13280 Field_w_Slot_inst_get (insn) == 0 && 13281 Field_r3_Slot_inst_get (insn) == 0) 13282 return 259; /* mula.da.hh */ 13283 break; 13284 case 12: 13285 if (Field_s_Slot_inst_get (insn) == 0 && 13286 Field_w_Slot_inst_get (insn) == 0 && 13287 Field_r3_Slot_inst_get (insn) == 0) 13288 return 260; /* muls.da.ll */ 13289 break; 13290 case 13: 13291 if (Field_s_Slot_inst_get (insn) == 0 && 13292 Field_w_Slot_inst_get (insn) == 0 && 13293 Field_r3_Slot_inst_get (insn) == 0) 13294 return 261; /* muls.da.hl */ 13295 break; 13296 case 14: 13297 if (Field_s_Slot_inst_get (insn) == 0 && 13298 Field_w_Slot_inst_get (insn) == 0 && 13299 Field_r3_Slot_inst_get (insn) == 0) 13300 return 262; /* muls.da.lh */ 13301 break; 13302 case 15: 13303 if (Field_s_Slot_inst_get (insn) == 0 && 13304 Field_w_Slot_inst_get (insn) == 0 && 13305 Field_r3_Slot_inst_get (insn) == 0) 13306 return 263; /* muls.da.hh */ 13307 break; 13308 } 13309 break; 13310 case 7: 13311 switch (Field_op1_Slot_inst_get (insn)) 13312 { 13313 case 0: 13314 if (Field_r_Slot_inst_get (insn) == 0) 13315 return 224; /* umul.aa.ll */ 13316 break; 13317 case 1: 13318 if (Field_r_Slot_inst_get (insn) == 0) 13319 return 225; /* umul.aa.hl */ 13320 break; 13321 case 2: 13322 if (Field_r_Slot_inst_get (insn) == 0) 13323 return 226; /* umul.aa.lh */ 13324 break; 13325 case 3: 13326 if (Field_r_Slot_inst_get (insn) == 0) 13327 return 227; /* umul.aa.hh */ 13328 break; 13329 case 4: 13330 if (Field_r_Slot_inst_get (insn) == 0) 13331 return 220; /* mul.aa.ll */ 13332 break; 13333 case 5: 13334 if (Field_r_Slot_inst_get (insn) == 0) 13335 return 221; /* mul.aa.hl */ 13336 break; 13337 case 6: 13338 if (Field_r_Slot_inst_get (insn) == 0) 13339 return 222; /* mul.aa.lh */ 13340 break; 13341 case 7: 13342 if (Field_r_Slot_inst_get (insn) == 0) 13343 return 223; /* mul.aa.hh */ 13344 break; 13345 case 8: 13346 if (Field_r_Slot_inst_get (insn) == 0) 13347 return 240; /* mula.aa.ll */ 13348 break; 13349 case 9: 13350 if (Field_r_Slot_inst_get (insn) == 0) 13351 return 241; /* mula.aa.hl */ 13352 break; 13353 case 10: 13354 if (Field_r_Slot_inst_get (insn) == 0) 13355 return 242; /* mula.aa.lh */ 13356 break; 13357 case 11: 13358 if (Field_r_Slot_inst_get (insn) == 0) 13359 return 243; /* mula.aa.hh */ 13360 break; 13361 case 12: 13362 if (Field_r_Slot_inst_get (insn) == 0) 13363 return 244; /* muls.aa.ll */ 13364 break; 13365 case 13: 13366 if (Field_r_Slot_inst_get (insn) == 0) 13367 return 245; /* muls.aa.hl */ 13368 break; 13369 case 14: 13370 if (Field_r_Slot_inst_get (insn) == 0) 13371 return 246; /* muls.aa.lh */ 13372 break; 13373 case 15: 13374 if (Field_r_Slot_inst_get (insn) == 0) 13375 return 247; /* muls.aa.hh */ 13376 break; 13377 } 13378 break; 13379 case 8: 13380 if (Field_op1_Slot_inst_get (insn) == 0 && 13381 Field_t_Slot_inst_get (insn) == 0 && 13382 Field_rhi_Slot_inst_get (insn) == 0) 13383 return 289; /* ldinc */ 13384 break; 13385 case 9: 13386 if (Field_op1_Slot_inst_get (insn) == 0 && 13387 Field_t_Slot_inst_get (insn) == 0 && 13388 Field_rhi_Slot_inst_get (insn) == 0) 13389 return 288; /* lddec */ 13390 break; 13391 } 13392 break; 13393 case 5: 13394 switch (Field_n_Slot_inst_get (insn)) 13395 { 13396 case 0: 13397 return 76; /* call0 */ 13398 case 1: 13399 return 7; /* call4 */ 13400 case 2: 13401 return 6; /* call8 */ 13402 case 3: 13403 return 5; /* call12 */ 13404 } 13405 break; 13406 case 6: 13407 switch (Field_n_Slot_inst_get (insn)) 13408 { 13409 case 0: 13410 return 80; /* j */ 13411 case 1: 13412 switch (Field_m_Slot_inst_get (insn)) 13413 { 13414 case 0: 13415 return 72; /* beqz */ 13416 case 1: 13417 return 73; /* bnez */ 13418 case 2: 13419 return 75; /* bltz */ 13420 case 3: 13421 return 74; /* bgez */ 13422 } 13423 break; 13424 case 2: 13425 switch (Field_m_Slot_inst_get (insn)) 13426 { 13427 case 0: 13428 return 52; /* beqi */ 13429 case 1: 13430 return 53; /* bnei */ 13431 case 2: 13432 return 55; /* blti */ 13433 case 3: 13434 return 54; /* bgei */ 13435 } 13436 break; 13437 case 3: 13438 switch (Field_m_Slot_inst_get (insn)) 13439 { 13440 case 0: 13441 return 11; /* entry */ 13442 case 1: 13443 switch (Field_r_Slot_inst_get (insn)) 13444 { 13445 case 8: 13446 return 87; /* loop */ 13447 case 9: 13448 return 88; /* loopnez */ 13449 case 10: 13450 return 89; /* loopgtz */ 13451 } 13452 break; 13453 case 2: 13454 return 59; /* bltui */ 13455 case 3: 13456 return 58; /* bgeui */ 13457 } 13458 break; 13459 } 13460 break; 13461 case 7: 13462 switch (Field_r_Slot_inst_get (insn)) 13463 { 13464 case 0: 13465 return 67; /* bnone */ 13466 case 1: 13467 return 60; /* beq */ 13468 case 2: 13469 return 63; /* blt */ 13470 case 3: 13471 return 65; /* bltu */ 13472 case 4: 13473 return 68; /* ball */ 13474 case 5: 13475 return 70; /* bbc */ 13476 case 6: 13477 case 7: 13478 return 56; /* bbci */ 13479 case 8: 13480 return 66; /* bany */ 13481 case 9: 13482 return 61; /* bne */ 13483 case 10: 13484 return 62; /* bge */ 13485 case 11: 13486 return 64; /* bgeu */ 13487 case 12: 13488 return 69; /* bnall */ 13489 case 13: 13490 return 71; /* bbs */ 13491 case 14: 13492 case 15: 13493 return 57; /* bbsi */ 13494 } 13495 break; 13496 } 13497 return XTENSA_UNDEFINED; 13498} 13499 13500static int 13501Slot_inst16b_decode (const xtensa_insnbuf insn) 13502{ 13503 switch (Field_op0_Slot_inst16b_get (insn)) 13504 { 13505 case 12: 13506 switch (Field_i_Slot_inst16b_get (insn)) 13507 { 13508 case 0: 13509 return 33; /* movi.n */ 13510 case 1: 13511 switch (Field_z_Slot_inst16b_get (insn)) 13512 { 13513 case 0: 13514 return 28; /* beqz.n */ 13515 case 1: 13516 return 29; /* bnez.n */ 13517 } 13518 break; 13519 } 13520 break; 13521 case 13: 13522 switch (Field_r_Slot_inst16b_get (insn)) 13523 { 13524 case 0: 13525 return 32; /* mov.n */ 13526 case 15: 13527 switch (Field_t_Slot_inst16b_get (insn)) 13528 { 13529 case 0: 13530 return 35; /* ret.n */ 13531 case 1: 13532 return 15; /* retw.n */ 13533 case 2: 13534 return 319; /* break.n */ 13535 case 3: 13536 if (Field_s_Slot_inst16b_get (insn) == 0) 13537 return 34; /* nop.n */ 13538 break; 13539 case 6: 13540 if (Field_s_Slot_inst16b_get (insn) == 0) 13541 return 30; /* ill.n */ 13542 break; 13543 } 13544 break; 13545 } 13546 break; 13547 } 13548 return XTENSA_UNDEFINED; 13549} 13550 13551static int 13552Slot_inst16a_decode (const xtensa_insnbuf insn) 13553{ 13554 switch (Field_op0_Slot_inst16a_get (insn)) 13555 { 13556 case 8: 13557 return 31; /* l32i.n */ 13558 case 9: 13559 return 36; /* s32i.n */ 13560 case 10: 13561 return 26; /* add.n */ 13562 case 11: 13563 return 27; /* addi.n */ 13564 } 13565 return XTENSA_UNDEFINED; 13566} 13567 13568 13569/* Instruction slots. */ 13570 13571static void 13572Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, 13573 xtensa_insnbuf slotbuf) 13574{ 13575 slotbuf[0] = (insn[0] & 0xffffff); 13576} 13577 13578static void 13579Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, 13580 const xtensa_insnbuf slotbuf) 13581{ 13582 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); 13583} 13584 13585static void 13586Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, 13587 xtensa_insnbuf slotbuf) 13588{ 13589 slotbuf[0] = (insn[0] & 0xffff); 13590} 13591 13592static void 13593Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, 13594 const xtensa_insnbuf slotbuf) 13595{ 13596 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); 13597} 13598 13599static void 13600Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, 13601 xtensa_insnbuf slotbuf) 13602{ 13603 slotbuf[0] = (insn[0] & 0xffff); 13604} 13605 13606static void 13607Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, 13608 const xtensa_insnbuf slotbuf) 13609{ 13610 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); 13611} 13612 13613static xtensa_get_field_fn 13614Slot_inst_get_field_fns[] = { 13615 Field_t_Slot_inst_get, 13616 Field_bbi4_Slot_inst_get, 13617 Field_bbi_Slot_inst_get, 13618 Field_imm12_Slot_inst_get, 13619 Field_imm8_Slot_inst_get, 13620 Field_s_Slot_inst_get, 13621 Field_imm12b_Slot_inst_get, 13622 Field_imm16_Slot_inst_get, 13623 Field_m_Slot_inst_get, 13624 Field_n_Slot_inst_get, 13625 Field_offset_Slot_inst_get, 13626 Field_op0_Slot_inst_get, 13627 Field_op1_Slot_inst_get, 13628 Field_op2_Slot_inst_get, 13629 Field_r_Slot_inst_get, 13630 Field_sa4_Slot_inst_get, 13631 Field_sae4_Slot_inst_get, 13632 Field_sae_Slot_inst_get, 13633 Field_sal_Slot_inst_get, 13634 Field_sargt_Slot_inst_get, 13635 Field_sas4_Slot_inst_get, 13636 Field_sas_Slot_inst_get, 13637 Field_sr_Slot_inst_get, 13638 Field_st_Slot_inst_get, 13639 Field_thi3_Slot_inst_get, 13640 Field_imm4_Slot_inst_get, 13641 Field_mn_Slot_inst_get, 13642 0, 13643 0, 13644 0, 13645 0, 13646 0, 13647 0, 13648 0, 13649 0, 13650 Field_r3_Slot_inst_get, 13651 Field_rbit2_Slot_inst_get, 13652 Field_rhi_Slot_inst_get, 13653 Field_t3_Slot_inst_get, 13654 Field_tbit2_Slot_inst_get, 13655 Field_tlo_Slot_inst_get, 13656 Field_w_Slot_inst_get, 13657 Field_y_Slot_inst_get, 13658 Field_x_Slot_inst_get, 13659 Field_xt_wbr15_imm_Slot_inst_get, 13660 Field_xt_wbr18_imm_Slot_inst_get, 13661 Field_bitindex_Slot_inst_get, 13662 Field_s3to1_Slot_inst_get, 13663 Implicit_Field_ar0_get, 13664 Implicit_Field_ar4_get, 13665 Implicit_Field_ar8_get, 13666 Implicit_Field_ar12_get, 13667 Implicit_Field_mr0_get, 13668 Implicit_Field_mr1_get, 13669 Implicit_Field_mr2_get, 13670 Implicit_Field_mr3_get 13671}; 13672 13673static xtensa_set_field_fn 13674Slot_inst_set_field_fns[] = { 13675 Field_t_Slot_inst_set, 13676 Field_bbi4_Slot_inst_set, 13677 Field_bbi_Slot_inst_set, 13678 Field_imm12_Slot_inst_set, 13679 Field_imm8_Slot_inst_set, 13680 Field_s_Slot_inst_set, 13681 Field_imm12b_Slot_inst_set, 13682 Field_imm16_Slot_inst_set, 13683 Field_m_Slot_inst_set, 13684 Field_n_Slot_inst_set, 13685 Field_offset_Slot_inst_set, 13686 Field_op0_Slot_inst_set, 13687 Field_op1_Slot_inst_set, 13688 Field_op2_Slot_inst_set, 13689 Field_r_Slot_inst_set, 13690 Field_sa4_Slot_inst_set, 13691 Field_sae4_Slot_inst_set, 13692 Field_sae_Slot_inst_set, 13693 Field_sal_Slot_inst_set, 13694 Field_sargt_Slot_inst_set, 13695 Field_sas4_Slot_inst_set, 13696 Field_sas_Slot_inst_set, 13697 Field_sr_Slot_inst_set, 13698 Field_st_Slot_inst_set, 13699 Field_thi3_Slot_inst_set, 13700 Field_imm4_Slot_inst_set, 13701 Field_mn_Slot_inst_set, 13702 0, 13703 0, 13704 0, 13705 0, 13706 0, 13707 0, 13708 0, 13709 0, 13710 Field_r3_Slot_inst_set, 13711 Field_rbit2_Slot_inst_set, 13712 Field_rhi_Slot_inst_set, 13713 Field_t3_Slot_inst_set, 13714 Field_tbit2_Slot_inst_set, 13715 Field_tlo_Slot_inst_set, 13716 Field_w_Slot_inst_set, 13717 Field_y_Slot_inst_set, 13718 Field_x_Slot_inst_set, 13719 Field_xt_wbr15_imm_Slot_inst_set, 13720 Field_xt_wbr18_imm_Slot_inst_set, 13721 Field_bitindex_Slot_inst_set, 13722 Field_s3to1_Slot_inst_set, 13723 Implicit_Field_set, 13724 Implicit_Field_set, 13725 Implicit_Field_set, 13726 Implicit_Field_set, 13727 Implicit_Field_set, 13728 Implicit_Field_set, 13729 Implicit_Field_set, 13730 Implicit_Field_set 13731}; 13732 13733static xtensa_get_field_fn 13734Slot_inst16a_get_field_fns[] = { 13735 Field_t_Slot_inst16a_get, 13736 0, 13737 0, 13738 0, 13739 0, 13740 Field_s_Slot_inst16a_get, 13741 0, 13742 0, 13743 0, 13744 0, 13745 0, 13746 Field_op0_Slot_inst16a_get, 13747 0, 13748 0, 13749 Field_r_Slot_inst16a_get, 13750 0, 13751 0, 13752 0, 13753 0, 13754 0, 13755 0, 13756 0, 13757 Field_sr_Slot_inst16a_get, 13758 Field_st_Slot_inst16a_get, 13759 0, 13760 Field_imm4_Slot_inst16a_get, 13761 0, 13762 Field_i_Slot_inst16a_get, 13763 Field_imm6lo_Slot_inst16a_get, 13764 Field_imm6hi_Slot_inst16a_get, 13765 Field_imm7lo_Slot_inst16a_get, 13766 Field_imm7hi_Slot_inst16a_get, 13767 Field_z_Slot_inst16a_get, 13768 Field_imm6_Slot_inst16a_get, 13769 Field_imm7_Slot_inst16a_get, 13770 0, 13771 0, 13772 0, 13773 0, 13774 0, 13775 0, 13776 0, 13777 0, 13778 0, 13779 0, 13780 0, 13781 Field_bitindex_Slot_inst16a_get, 13782 Field_s3to1_Slot_inst16a_get, 13783 Implicit_Field_ar0_get, 13784 Implicit_Field_ar4_get, 13785 Implicit_Field_ar8_get, 13786 Implicit_Field_ar12_get, 13787 Implicit_Field_mr0_get, 13788 Implicit_Field_mr1_get, 13789 Implicit_Field_mr2_get, 13790 Implicit_Field_mr3_get 13791}; 13792 13793static xtensa_set_field_fn 13794Slot_inst16a_set_field_fns[] = { 13795 Field_t_Slot_inst16a_set, 13796 0, 13797 0, 13798 0, 13799 0, 13800 Field_s_Slot_inst16a_set, 13801 0, 13802 0, 13803 0, 13804 0, 13805 0, 13806 Field_op0_Slot_inst16a_set, 13807 0, 13808 0, 13809 Field_r_Slot_inst16a_set, 13810 0, 13811 0, 13812 0, 13813 0, 13814 0, 13815 0, 13816 0, 13817 Field_sr_Slot_inst16a_set, 13818 Field_st_Slot_inst16a_set, 13819 0, 13820 Field_imm4_Slot_inst16a_set, 13821 0, 13822 Field_i_Slot_inst16a_set, 13823 Field_imm6lo_Slot_inst16a_set, 13824 Field_imm6hi_Slot_inst16a_set, 13825 Field_imm7lo_Slot_inst16a_set, 13826 Field_imm7hi_Slot_inst16a_set, 13827 Field_z_Slot_inst16a_set, 13828 Field_imm6_Slot_inst16a_set, 13829 Field_imm7_Slot_inst16a_set, 13830 0, 13831 0, 13832 0, 13833 0, 13834 0, 13835 0, 13836 0, 13837 0, 13838 0, 13839 0, 13840 0, 13841 Field_bitindex_Slot_inst16a_set, 13842 Field_s3to1_Slot_inst16a_set, 13843 Implicit_Field_set, 13844 Implicit_Field_set, 13845 Implicit_Field_set, 13846 Implicit_Field_set, 13847 Implicit_Field_set, 13848 Implicit_Field_set, 13849 Implicit_Field_set, 13850 Implicit_Field_set 13851}; 13852 13853static xtensa_get_field_fn 13854Slot_inst16b_get_field_fns[] = { 13855 Field_t_Slot_inst16b_get, 13856 0, 13857 0, 13858 0, 13859 0, 13860 Field_s_Slot_inst16b_get, 13861 0, 13862 0, 13863 0, 13864 0, 13865 0, 13866 Field_op0_Slot_inst16b_get, 13867 0, 13868 0, 13869 Field_r_Slot_inst16b_get, 13870 0, 13871 0, 13872 0, 13873 0, 13874 0, 13875 0, 13876 0, 13877 Field_sr_Slot_inst16b_get, 13878 Field_st_Slot_inst16b_get, 13879 0, 13880 Field_imm4_Slot_inst16b_get, 13881 0, 13882 Field_i_Slot_inst16b_get, 13883 Field_imm6lo_Slot_inst16b_get, 13884 Field_imm6hi_Slot_inst16b_get, 13885 Field_imm7lo_Slot_inst16b_get, 13886 Field_imm7hi_Slot_inst16b_get, 13887 Field_z_Slot_inst16b_get, 13888 Field_imm6_Slot_inst16b_get, 13889 Field_imm7_Slot_inst16b_get, 13890 0, 13891 0, 13892 0, 13893 0, 13894 0, 13895 0, 13896 0, 13897 0, 13898 0, 13899 0, 13900 0, 13901 Field_bitindex_Slot_inst16b_get, 13902 Field_s3to1_Slot_inst16b_get, 13903 Implicit_Field_ar0_get, 13904 Implicit_Field_ar4_get, 13905 Implicit_Field_ar8_get, 13906 Implicit_Field_ar12_get, 13907 Implicit_Field_mr0_get, 13908 Implicit_Field_mr1_get, 13909 Implicit_Field_mr2_get, 13910 Implicit_Field_mr3_get 13911}; 13912 13913static xtensa_set_field_fn 13914Slot_inst16b_set_field_fns[] = { 13915 Field_t_Slot_inst16b_set, 13916 0, 13917 0, 13918 0, 13919 0, 13920 Field_s_Slot_inst16b_set, 13921 0, 13922 0, 13923 0, 13924 0, 13925 0, 13926 Field_op0_Slot_inst16b_set, 13927 0, 13928 0, 13929 Field_r_Slot_inst16b_set, 13930 0, 13931 0, 13932 0, 13933 0, 13934 0, 13935 0, 13936 0, 13937 Field_sr_Slot_inst16b_set, 13938 Field_st_Slot_inst16b_set, 13939 0, 13940 Field_imm4_Slot_inst16b_set, 13941 0, 13942 Field_i_Slot_inst16b_set, 13943 Field_imm6lo_Slot_inst16b_set, 13944 Field_imm6hi_Slot_inst16b_set, 13945 Field_imm7lo_Slot_inst16b_set, 13946 Field_imm7hi_Slot_inst16b_set, 13947 Field_z_Slot_inst16b_set, 13948 Field_imm6_Slot_inst16b_set, 13949 Field_imm7_Slot_inst16b_set, 13950 0, 13951 0, 13952 0, 13953 0, 13954 0, 13955 0, 13956 0, 13957 0, 13958 0, 13959 0, 13960 0, 13961 Field_bitindex_Slot_inst16b_set, 13962 Field_s3to1_Slot_inst16b_set, 13963 Implicit_Field_set, 13964 Implicit_Field_set, 13965 Implicit_Field_set, 13966 Implicit_Field_set, 13967 Implicit_Field_set, 13968 Implicit_Field_set, 13969 Implicit_Field_set, 13970 Implicit_Field_set 13971}; 13972 13973static xtensa_slot_internal slots[] = { 13974 { "Inst", "x24", 0, 13975 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, 13976 Slot_inst_get_field_fns, Slot_inst_set_field_fns, 13977 Slot_inst_decode, "nop" }, 13978 { "Inst16a", "x16a", 0, 13979 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, 13980 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, 13981 Slot_inst16a_decode, "" }, 13982 { "Inst16b", "x16b", 0, 13983 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, 13984 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, 13985 Slot_inst16b_decode, "nop.n" } 13986}; 13987 13988 13989/* Instruction formats. */ 13990 13991static void 13992Format_x24_encode (xtensa_insnbuf insn) 13993{ 13994 insn[0] = 0; 13995} 13996 13997static void 13998Format_x16a_encode (xtensa_insnbuf insn) 13999{ 14000 insn[0] = 0x8; 14001} 14002 14003static void 14004Format_x16b_encode (xtensa_insnbuf insn) 14005{ 14006 insn[0] = 0xc; 14007} 14008 14009static int Format_x24_slots[] = { 0 }; 14010 14011static int Format_x16a_slots[] = { 1 }; 14012 14013static int Format_x16b_slots[] = { 2 }; 14014 14015static xtensa_format_internal formats[] = { 14016 { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, 14017 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, 14018 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } 14019}; 14020 14021 14022static int 14023format_decoder (const xtensa_insnbuf insn) 14024{ 14025 if ((insn[0] & 0x8) == 0) 14026 return 0; /* x24 */ 14027 if ((insn[0] & 0xc) == 0x8) 14028 return 1; /* x16a */ 14029 if ((insn[0] & 0xe) == 0xc) 14030 return 2; /* x16b */ 14031 return -1; 14032} 14033 14034static int length_table[16] = { 14035 3, 14036 3, 14037 3, 14038 3, 14039 3, 14040 3, 14041 3, 14042 3, 14043 2, 14044 2, 14045 2, 14046 2, 14047 2, 14048 2, 14049 -1, 14050 -1 14051}; 14052 14053static int 14054length_decoder (const unsigned char *insn) 14055{ 14056 int op0 = insn[0] & 0xf; 14057 return length_table[op0]; 14058} 14059 14060 14061/* Top-level ISA structure. */ 14062 14063xtensa_isa_internal xtensa_modules = { 14064 0 /* little-endian */, 14065 3 /* insn_size */, 0, 14066 3, formats, format_decoder, length_decoder, 14067 3, slots, 14068 56 /* num_fields */, 14069 93, operands, 14070 320, iclasses, 14071 446, opcodes, 0, 14072 2, regfiles, 14073 NUM_STATES, states, 0, 14074 NUM_SYSREGS, sysregs, 0, 14075 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, 14076 1, interfaces, 0, 14077 0, funcUnits, 0 14078}; 14079