1 /* 2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2.1 of the License, or (at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public 15 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 /* 19 * Opcode Masks for Tricore 20 * Format MASK_OP_InstrFormatName_Field 21 */ 22 23 /* This creates a mask with bits start .. end set to 1 and applies it to op */ 24 #define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \ 25 (end) - (start) + 1)) 26 #define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\ 27 (end) - (start) + 1)) 28 29 /* new opcode masks */ 30 31 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7) 32 33 /* 16-Bit Formats */ 34 #define MASK_OP_SB_DISP8(op) MASK_BITS_SHIFT(op, 8, 15) 35 #define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15) 36 37 #define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15) 38 #define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15) 39 #define MASK_OP_SBC_DISP4(op) MASK_BITS_SHIFT(op, 8, 11) 40 41 #define MASK_OP_SBR_S2(op) MASK_BITS_SHIFT(op, 12, 15) 42 #define MASK_OP_SBR_DISP4(op) MASK_BITS_SHIFT(op, 8, 11) 43 44 #define MASK_OP_SBRN_N(op) MASK_BITS_SHIFT(op, 12, 15) 45 #define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11) 46 47 #define MASK_OP_SC_CONST8(op) MASK_BITS_SHIFT(op, 8, 15) 48 49 #define MASK_OP_SLR_S2(op) MASK_BITS_SHIFT(op, 12, 15) 50 #define MASK_OP_SLR_D(op) MASK_BITS_SHIFT(op, 8, 11) 51 52 #define MASK_OP_SLRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15) 53 #define MASK_OP_SLRO_D(op) MASK_BITS_SHIFT(op, 8, 11) 54 55 #define MASK_OP_SR_OP2(op) MASK_BITS_SHIFT(op, 12, 15) 56 #define MASK_OP_SR_S1D(op) MASK_BITS_SHIFT(op, 8, 11) 57 58 #define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15) 59 #define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15) 60 #define MASK_OP_SRC_S1D(op) MASK_BITS_SHIFT(op, 8, 11) 61 62 #define MASK_OP_SRO_S2(op) MASK_BITS_SHIFT(op, 12, 15) 63 #define MASK_OP_SRO_OFF4(op) MASK_BITS_SHIFT(op, 8, 11) 64 65 #define MASK_OP_SRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) 66 #define MASK_OP_SRR_S1D(op) MASK_BITS_SHIFT(op, 8, 11) 67 68 #define MASK_OP_SRRS_S2(op) MASK_BITS_SHIFT(op, 12, 15) 69 #define MASK_OP_SRRS_S1D(op) MASK_BITS_SHIFT(op, 8, 11) 70 #define MASK_OP_SRRS_N(op) MASK_BITS_SHIFT(op, 6, 7) 71 72 #define MASK_OP_SSR_S2(op) MASK_BITS_SHIFT(op, 12, 15) 73 #define MASK_OP_SSR_S1(op) MASK_BITS_SHIFT(op, 8, 11) 74 75 #define MASK_OP_SSRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15) 76 #define MASK_OP_SSRO_S1(op) MASK_BITS_SHIFT(op, 8, 11) 77 78 /* 32-Bit Formats */ 79 80 /* ABS Format */ 81 #define MASK_OP_ABS_OFF18(op) (MASK_BITS_SHIFT(op, 16, 21) + \ 82 (MASK_BITS_SHIFT(op, 28, 31) << 6) + \ 83 (MASK_BITS_SHIFT(op, 22, 25) << 10) +\ 84 (MASK_BITS_SHIFT(op, 12, 15) << 14)) 85 #define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27) 86 #define MASK_OP_ABS_S1D(op) MASK_BITS_SHIFT(op, 8, 11) 87 88 /* ABSB Format */ 89 #define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op) 90 #define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27) 91 #define MASK_OP_ABSB_B(op) MASK_BITS_SHIFT(op, 11, 11) 92 #define MASK_OP_ABSB_BPOS(op) MASK_BITS_SHIFT(op, 8, 10) 93 94 /* B Format */ 95 #define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \ 96 (MASK_BITS_SHIFT(op, 8, 15) << 16)) 97 #define MASK_OP_B_DISP24_SEXT(op) (MASK_BITS_SHIFT(op, 16, 31) + \ 98 (MASK_BITS_SHIFT_SEXT(op, 8, 15) << 16)) 99 /* BIT Format */ 100 #define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31) 101 #define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27) 102 #define MASK_OP_BIT_OP2(op) MASK_BITS_SHIFT(op, 21, 22) 103 #define MASK_OP_BIT_POS1(op) MASK_BITS_SHIFT(op, 16, 20) 104 #define MASK_OP_BIT_S2(op) MASK_BITS_SHIFT(op, 12, 15) 105 #define MASK_OP_BIT_S1(op) MASK_BITS_SHIFT(op, 8, 11) 106 107 /* BO Format */ 108 #define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \ 109 (MASK_BITS_SHIFT(op, 28, 31) << 6)) 110 #define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT(op, 16, 21) + \ 111 (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6)) 112 #define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27) 113 #define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15) 114 #define MASK_OP_BO_S1D(op) MASK_BITS_SHIFT(op, 8, 11) 115 116 /* BOL Format */ 117 #define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \ 118 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \ 119 (MASK_BITS_SHIFT(op, 22, 27) << 10)) 120 #define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \ 121 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \ 122 (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10)) 123 #define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15) 124 #define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11) 125 126 /* BRC Format */ 127 #define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31) 128 #define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30) 129 #define MASK_OP_BRC_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30) 130 #define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15) 131 #define MASK_OP_BRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15) 132 #define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11) 133 134 /* BRN Format */ 135 #define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31) 136 #define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30) 137 #define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30) 138 #define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \ 139 (MASK_BITS_SHIFT(op, 7, 7) << 4)) 140 #define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11) 141 /* BRR Format */ 142 #define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31) 143 #define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30) 144 #define MASK_OP_BRR_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30) 145 #define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) 146 #define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11) 147 148 /* META MASK for similar instr Formats */ 149 #define MASK_OP_META_D(op) MASK_BITS_SHIFT(op, 28, 31) 150 #define MASK_OP_META_S1(op) MASK_BITS_SHIFT(op, 8, 11) 151 152 /* RC Format */ 153 #define MASK_OP_RC_D(op) MASK_OP_META_D(op) 154 #define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27) 155 #define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20) 156 #define MASK_OP_RC_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20) 157 #define MASK_OP_RC_S1(op) MASK_OP_META_S1(op) 158 159 /* RCPW Format */ 160 161 #define MASK_OP_RCPW_D(op) MASK_OP_META_D(op) 162 #define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27) 163 #define MASK_OP_RCPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22) 164 #define MASK_OP_RCPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20) 165 #define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15) 166 #define MASK_OP_RCPW_S1(op) MASK_OP_META_S1(op) 167 168 /* RCR Format */ 169 170 #define MASK_OP_RCR_D(op) MASK_OP_META_D(op) 171 #define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27) 172 #define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23) 173 #define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20) 174 #define MASK_OP_RCR_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20) 175 #define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op) 176 177 /* RCRR Format */ 178 179 #define MASK_OP_RCRR_D(op) MASK_OP_META_D(op) 180 #define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27) 181 #define MASK_OP_RCRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23) 182 #define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15) 183 #define MASK_OP_RCRR_S1(op) MASK_OP_META_S1(op) 184 185 /* RCRW Format */ 186 187 #define MASK_OP_RCRW_D(op) MASK_OP_META_D(op) 188 #define MASK_OP_RCRW_S3(op) MASK_BITS_SHIFT(op, 24, 27) 189 #define MASK_OP_RCRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23) 190 #define MASK_OP_RCRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20) 191 #define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15) 192 #define MASK_OP_RCRW_S1(op) MASK_OP_META_S1(op) 193 194 /* RLC Format */ 195 196 #define MASK_OP_RLC_D(op) MASK_OP_META_D(op) 197 #define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27) 198 #define MASK_OP_RLC_CONST16_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 27) 199 #define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op) 200 201 /* RR Format */ 202 #define MASK_OP_RR_D(op) MASK_OP_META_D(op) 203 #define MASK_OP_RR_OP2(op) MASK_BITS_SHIFT(op, 20, 27) 204 #define MASK_OP_RR_N(op) MASK_BITS_SHIFT(op, 16, 17) 205 #define MASK_OP_RR_S2(op) MASK_BITS_SHIFT(op, 12, 15) 206 #define MASK_OP_RR_S1(op) MASK_OP_META_S1(op) 207 208 /* RR1 Format */ 209 #define MASK_OP_RR1_D(op) MASK_OP_META_D(op) 210 #define MASK_OP_RR1_OP2(op) MASK_BITS_SHIFT(op, 18, 27) 211 #define MASK_OP_RR1_N(op) MASK_BITS_SHIFT(op, 16, 17) 212 #define MASK_OP_RR1_S2(op) MASK_BITS_SHIFT(op, 12, 15) 213 #define MASK_OP_RR1_S1(op) MASK_OP_META_S1(op) 214 215 /* RR2 Format */ 216 #define MASK_OP_RR2_D(op) MASK_OP_META_D(op) 217 #define MASK_OP_RR2_OP2(op) MASK_BITS_SHIFT(op, 16, 27) 218 #define MASK_OP_RR2_S2(op) MASK_BITS_SHIFT(op, 12, 15) 219 #define MASK_OP_RR2_S1(op) MASK_OP_META_S1(op) 220 221 /* RRPW Format */ 222 #define MASK_OP_RRPW_D(op) MASK_OP_META_D(op) 223 #define MASK_OP_RRPW_POS(op) MASK_BITS_SHIFT(op, 23, 27) 224 #define MASK_OP_RRPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22) 225 #define MASK_OP_RRPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20) 226 #define MASK_OP_RRPW_S2(op) MASK_BITS_SHIFT(op, 12, 15) 227 #define MASK_OP_RRPW_S1(op) MASK_OP_META_S1(op) 228 229 /* RRR Format */ 230 #define MASK_OP_RRR_D(op) MASK_OP_META_D(op) 231 #define MASK_OP_RRR_S3(op) MASK_BITS_SHIFT(op, 24, 27) 232 #define MASK_OP_RRR_OP2(op) MASK_BITS_SHIFT(op, 20, 23) 233 #define MASK_OP_RRR_N(op) MASK_BITS_SHIFT(op, 16, 17) 234 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) 235 #define MASK_OP_RRR_S1(op) MASK_OP_META_S1(op) 236 237 /* RRR1 Format */ 238 #define MASK_OP_RRR1_D(op) MASK_OP_META_D(op) 239 #define MASK_OP_RRR1_S3(op) MASK_BITS_SHIFT(op, 24, 27) 240 #define MASK_OP_RRR1_OP2(op) MASK_BITS_SHIFT(op, 18, 23) 241 #define MASK_OP_RRR1_N(op) MASK_BITS_SHIFT(op, 16, 17) 242 #define MASK_OP_RRR1_S2(op) MASK_BITS_SHIFT(op, 12, 15) 243 #define MASK_OP_RRR1_S1(op) MASK_OP_META_S1(op) 244 245 /* RRR2 Format */ 246 #define MASK_OP_RRR2_D(op) MASK_OP_META_D(op) 247 #define MASK_OP_RRR2_S3(op) MASK_BITS_SHIFT(op, 24, 27) 248 #define MASK_OP_RRR2_OP2(op) MASK_BITS_SHIFT(op, 16, 23) 249 #define MASK_OP_RRR2_S2(op) MASK_BITS_SHIFT(op, 12, 15) 250 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op) 251 252 /* RRRR Format */ 253 #define MASK_OP_RRRR_D(op) MASK_OP_META_D(op) 254 #define MASK_OP_RRRR_S3(op) MASK_BITS_SHIFT(op, 24, 27) 255 #define MASK_OP_RRRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23) 256 #define MASK_OP_RRRR_S2(op) MASK_BITS_SHIFT(op, 12, 15) 257 #define MASK_OP_RRRR_S1(op) MASK_OP_META_S1(op) 258 259 /* RRRW Format */ 260 #define MASK_OP_RRRW_D(op) MASK_OP_META_D(op) 261 #define MASK_OP_RRRW_S3(op) MASK_BITS_SHIFT(op, 24, 27) 262 #define MASK_OP_RRRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23) 263 #define MASK_OP_RRRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20) 264 #define MASK_OP_RRRW_S2(op) MASK_BITS_SHIFT(op, 12, 15) 265 #define MASK_OP_RRRW_S1(op) MASK_OP_META_S1(op) 266 267 /* SYS Format */ 268 #define MASK_OP_SYS_OP2(op) MASK_BITS_SHIFT(op, 22, 27) 269 #define MASK_OP_SYS_S1D(op) MASK_OP_META_S1(op) 270 271 272 273 /* 274 * Tricore Opcodes Enums 275 * 276 * Format: OPC(1|2|M)_InstrLen_Name 277 * OPC1 = only op1 field is used 278 * OPC2 = op1 and op2 field used part of OPCM 279 * OPCM = op1 field used to group Instr 280 * InstrLen = 16|32 281 * Name = Name of Instr 282 */ 283 284 /* 16-Bit */ 285 enum { 286 287 OPCM_16_SR_SYSTEM = 0x00, 288 OPCM_16_SR_ACCU = 0x32, 289 290 OPC1_16_SRC_ADD = 0xc2, 291 OPC1_16_SRC_ADD_A15 = 0x92, 292 OPC1_16_SRC_ADD_15A = 0x9a, 293 OPC1_16_SRR_ADD = 0x42, 294 OPC1_16_SRR_ADD_A15 = 0x12, 295 OPC1_16_SRR_ADD_15A = 0x1a, 296 OPC1_16_SRC_ADD_A = 0xb0, 297 OPC1_16_SRR_ADD_A = 0x30, 298 OPC1_16_SRR_ADDS = 0x22, 299 OPC1_16_SRRS_ADDSC_A = 0x10, 300 OPC1_16_SC_AND = 0x16, 301 OPC1_16_SRR_AND = 0x26, 302 OPC1_16_SC_BISR = 0xe0, 303 OPC1_16_SRC_CADD = 0x8a, 304 OPC1_16_SRC_CADDN = 0xca, 305 OPC1_16_SB_CALL = 0x5c, 306 OPC1_16_SRC_CMOV = 0xaa, 307 OPC1_16_SRR_CMOV = 0x2a, 308 OPC1_16_SRC_CMOVN = 0xea, 309 OPC1_16_SRR_CMOVN = 0x6a, 310 OPC1_16_SRC_EQ = 0xba, 311 OPC1_16_SRR_EQ = 0x3a, 312 OPC1_16_SB_J = 0x3c, 313 OPC1_16_SBC_JEQ = 0x1e, 314 OPC1_16_SBC_JEQ2 = 0x9e, 315 OPC1_16_SBR_JEQ = 0x3e, 316 OPC1_16_SBR_JEQ2 = 0xbe, 317 OPC1_16_SBR_JGEZ = 0xce, 318 OPC1_16_SBR_JGTZ = 0x4e, 319 OPC1_16_SR_JI = 0xdc, 320 OPC1_16_SBR_JLEZ = 0x8e, 321 OPC1_16_SBR_JLTZ = 0x0e, 322 OPC1_16_SBC_JNE = 0x5e, 323 OPC1_16_SBC_JNE2 = 0xde, 324 OPC1_16_SBR_JNE = 0x7e, 325 OPC1_16_SBR_JNE2 = 0xfe, 326 OPC1_16_SB_JNZ = 0xee, 327 OPC1_16_SBR_JNZ = 0xf6, 328 OPC1_16_SBR_JNZ_A = 0x7c, 329 OPC1_16_SBRN_JNZ_T = 0xae, 330 OPC1_16_SB_JZ = 0x6e, 331 OPC1_16_SBR_JZ = 0x76, 332 OPC1_16_SBR_JZ_A = 0xbc, 333 OPC1_16_SBRN_JZ_T = 0x2e, 334 OPC1_16_SC_LD_A = 0xd8, 335 OPC1_16_SLR_LD_A = 0xd4, 336 OPC1_16_SLR_LD_A_POSTINC = 0xc4, 337 OPC1_16_SLRO_LD_A = 0xc8, 338 OPC1_16_SRO_LD_A = 0xcc, 339 OPC1_16_SLR_LD_BU = 0x14, 340 OPC1_16_SLR_LD_BU_POSTINC = 0x04, 341 OPC1_16_SLRO_LD_BU = 0x08, 342 OPC1_16_SRO_LD_BU = 0x0c, 343 OPC1_16_SLR_LD_H = 0x94, 344 OPC1_16_SLR_LD_H_POSTINC = 0x84, 345 OPC1_16_SLRO_LD_H = 0x88, 346 OPC1_16_SRO_LD_H = 0x8c, 347 OPC1_16_SC_LD_W = 0x58, 348 OPC1_16_SLR_LD_W = 0x54, 349 OPC1_16_SLR_LD_W_POSTINC = 0x44, 350 OPC1_16_SLRO_LD_W = 0x48, 351 OPC1_16_SRO_LD_W = 0x4c, 352 OPC1_16_SBR_LOOP = 0xfc, 353 OPC1_16_SRC_LT = 0xfa, 354 OPC1_16_SRR_LT = 0x7a, 355 OPC1_16_SC_MOV = 0xda, 356 OPC1_16_SRC_MOV = 0x82, 357 OPC1_16_SRR_MOV = 0x02, 358 OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */ 359 OPC1_16_SRC_MOV_A = 0xa0, 360 OPC1_16_SRR_MOV_A = 0x60, 361 OPC1_16_SRR_MOV_AA = 0x40, 362 OPC1_16_SRR_MOV_D = 0x80, 363 OPC1_16_SRR_MUL = 0xe2, 364 OPC1_16_SR_NOT = 0x46, 365 OPC1_16_SC_OR = 0x96, 366 OPC1_16_SRR_OR = 0xa6, 367 OPC1_16_SRC_SH = 0x06, 368 OPC1_16_SRC_SHA = 0x86, 369 OPC1_16_SC_ST_A = 0xf8, 370 OPC1_16_SRO_ST_A = 0xec, 371 OPC1_16_SSR_ST_A = 0xf4, 372 OPC1_16_SSR_ST_A_POSTINC = 0xe4, 373 OPC1_16_SSRO_ST_A = 0xe8, 374 OPC1_16_SRO_ST_B = 0x2c, 375 OPC1_16_SSR_ST_B = 0x34, 376 OPC1_16_SSR_ST_B_POSTINC = 0x24, 377 OPC1_16_SSRO_ST_B = 0x28, 378 OPC1_16_SRO_ST_H = 0xac, 379 OPC1_16_SSR_ST_H = 0xb4, 380 OPC1_16_SSR_ST_H_POSTINC = 0xa4, 381 OPC1_16_SSRO_ST_H = 0xa8, 382 OPC1_16_SC_ST_W = 0x78, 383 OPC1_16_SRO_ST_W = 0x6c, 384 OPC1_16_SSR_ST_W = 0x74, 385 OPC1_16_SSR_ST_W_POSTINC = 0x64, 386 OPC1_16_SSRO_ST_W = 0x68, 387 OPC1_16_SRR_SUB = 0xa2, 388 OPC1_16_SRR_SUB_A15B = 0x52, 389 OPC1_16_SRR_SUB_15AB = 0x5a, 390 OPC1_16_SC_SUB_A = 0x20, 391 OPC1_16_SRR_SUBS = 0x62, 392 OPC1_16_SRR_XOR = 0xc6, 393 394 }; 395 396 /* 397 * SR Format 398 */ 399 /* OPCM_16_SR_SYSTEM */ 400 enum { 401 402 OPC2_16_SR_NOP = 0x00, 403 OPC2_16_SR_RET = 0x09, 404 OPC2_16_SR_RFE = 0x08, 405 OPC2_16_SR_DEBUG = 0x0a, 406 OPC2_16_SR_FRET = 0x07, 407 }; 408 /* OPCM_16_SR_ACCU */ 409 enum { 410 OPC2_16_SR_RSUB = 0x05, 411 OPC2_16_SR_SAT_B = 0x00, 412 OPC2_16_SR_SAT_BU = 0x01, 413 OPC2_16_SR_SAT_H = 0x02, 414 OPC2_16_SR_SAT_HU = 0x03, 415 416 }; 417 418 /* 32-Bit */ 419 420 enum { 421 /* ABS Format 1, M */ 422 OPCM_32_ABS_LDW = 0x85, 423 OPCM_32_ABS_LDB = 0x05, 424 OPCM_32_ABS_LDMST_SWAP = 0xe5, 425 OPCM_32_ABS_LDST_CONTEXT = 0x15, 426 OPCM_32_ABS_STORE = 0xa5, 427 OPCM_32_ABS_STOREB_H = 0x25, 428 OPC1_32_ABS_STOREQ = 0x65, 429 OPC1_32_ABS_LD_Q = 0x45, 430 OPC1_32_ABS_LEA = 0xc5, 431 /* ABSB Format */ 432 OPC1_32_ABSB_ST_T = 0xd5, 433 /* B Format */ 434 OPC1_32_B_CALL = 0x6d, 435 OPC1_32_B_CALLA = 0xed, 436 OPC1_32_B_FCALL = 0x61, 437 OPC1_32_B_FCALLA = 0xe1, 438 OPC1_32_B_J = 0x1d, 439 OPC1_32_B_JA = 0x9d, 440 OPC1_32_B_JL = 0x5d, 441 OPC1_32_B_JLA = 0xdd, 442 /* Bit Format */ 443 OPCM_32_BIT_ANDACC = 0x47, 444 OPCM_32_BIT_LOGICAL_T1 = 0x87, 445 OPCM_32_BIT_INSERT = 0x67, 446 OPCM_32_BIT_LOGICAL_T2 = 0x07, 447 OPCM_32_BIT_ORAND = 0xc7, 448 OPCM_32_BIT_SH_LOGIC1 = 0x27, 449 OPCM_32_BIT_SH_LOGIC2 = 0xa7, 450 /* BO Format */ 451 OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89, 452 OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9, 453 OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09, 454 OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29, 455 OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49, 456 OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69, 457 /* BOL Format */ 458 OPC1_32_BOL_LD_A_LONGOFF = 0x99, 459 OPC1_32_BOL_LD_W_LONGOFF = 0x19, 460 OPC1_32_BOL_LEA_LONGOFF = 0xd9, 461 OPC1_32_BOL_ST_W_LONGOFF = 0x59, 462 OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */ 463 OPC1_32_BOL_LD_B_LONGOFF = 0x79, /* 1.6 only */ 464 OPC1_32_BOL_LD_BU_LONGOFF = 0x39, /* 1.6 only */ 465 OPC1_32_BOL_LD_H_LONGOFF = 0xc9, /* 1.6 only */ 466 OPC1_32_BOL_LD_HU_LONGOFF = 0xb9, /* 1.6 only */ 467 OPC1_32_BOL_ST_B_LONGOFF = 0xe9, /* 1.6 only */ 468 OPC1_32_BOL_ST_H_LONGOFF = 0xf9, /* 1.6 only */ 469 /* BRC Format */ 470 OPCM_32_BRC_EQ_NEQ = 0xdf, 471 OPCM_32_BRC_GE = 0xff, 472 OPCM_32_BRC_JLT = 0xbf, 473 OPCM_32_BRC_JNE = 0x9f, 474 /* BRN Format */ 475 OPCM_32_BRN_JTT = 0x6f, 476 /* BRR Format */ 477 OPCM_32_BRR_EQ_NEQ = 0x5f, 478 OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d, 479 OPCM_32_BRR_GE = 0x7f, 480 OPCM_32_BRR_JLT = 0x3f, 481 OPCM_32_BRR_JNE = 0x1f, 482 OPCM_32_BRR_JNZ = 0xbd, 483 OPCM_32_BRR_LOOP = 0xfd, 484 /* RC Format */ 485 OPCM_32_RC_LOGICAL_SHIFT = 0x8f, 486 OPCM_32_RC_ACCUMULATOR = 0x8b, 487 OPCM_32_RC_SERVICEROUTINE = 0xad, 488 OPCM_32_RC_MUL = 0x53, 489 /* RCPW Format */ 490 OPCM_32_RCPW_MASK_INSERT = 0xb7, 491 /* RCR Format */ 492 OPCM_32_RCR_COND_SELECT = 0xab, 493 OPCM_32_RCR_MADD = 0x13, 494 OPCM_32_RCR_MSUB = 0x33, 495 /* RCRR Format */ 496 OPC1_32_RCRR_INSERT = 0x97, 497 /* RCRW Format */ 498 OPCM_32_RCRW_MASK_INSERT = 0xd7, 499 /* RLC Format */ 500 OPC1_32_RLC_ADDI = 0x1b, 501 OPC1_32_RLC_ADDIH = 0x9b, 502 OPC1_32_RLC_ADDIH_A = 0x11, 503 OPC1_32_RLC_MFCR = 0x4d, 504 OPC1_32_RLC_MOV = 0x3b, 505 OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */ 506 OPC1_32_RLC_MOV_U = 0xbb, 507 OPC1_32_RLC_MOV_H = 0x7b, 508 OPC1_32_RLC_MOVH_A = 0x91, 509 OPC1_32_RLC_MTCR = 0xcd, 510 /* RR Format */ 511 OPCM_32_RR_LOGICAL_SHIFT = 0x0f, 512 OPCM_32_RR_ACCUMULATOR = 0x0b, 513 OPCM_32_RR_ADDRESS = 0x01, 514 OPCM_32_RR_DIVIDE = 0x4b, 515 OPCM_32_RR_IDIRECT = 0x2d, 516 /* RR1 Format */ 517 OPCM_32_RR1_MUL = 0xb3, 518 OPCM_32_RR1_MULQ = 0x93, 519 /* RR2 Format */ 520 OPCM_32_RR2_MUL = 0x73, 521 /* RRPW Format */ 522 OPCM_32_RRPW_EXTRACT_INSERT = 0x37, 523 OPC1_32_RRPW_DEXTR = 0x77, 524 /* RRR Format */ 525 OPCM_32_RRR_COND_SELECT = 0x2b, 526 OPCM_32_RRR_DIVIDE = 0x6b, 527 /* RRR1 Format */ 528 OPCM_32_RRR1_MADD = 0x83, 529 OPCM_32_RRR1_MADDQ_H = 0x43, 530 OPCM_32_RRR1_MADDSU_H = 0xc3, 531 OPCM_32_RRR1_MSUB_H = 0xa3, 532 OPCM_32_RRR1_MSUB_Q = 0x63, 533 OPCM_32_RRR1_MSUBAD_H = 0xe3, 534 /* RRR2 Format */ 535 OPCM_32_RRR2_MADD = 0x03, 536 OPCM_32_RRR2_MSUB = 0x23, 537 /* RRRR Format */ 538 OPCM_32_RRRR_EXTRACT_INSERT = 0x17, 539 /* RRRW Format */ 540 OPCM_32_RRRW_EXTRACT_INSERT = 0x57, 541 /* SYS Format */ 542 OPCM_32_SYS_INTERRUPTS = 0x0d, 543 OPC1_32_SYS_RSTV = 0x2f, 544 }; 545 546 547 548 /* 549 * ABS Format 550 */ 551 552 /* OPCM_32_ABS_LDW */ 553 enum { 554 555 OPC2_32_ABS_LD_A = 0x02, 556 OPC2_32_ABS_LD_D = 0x01, 557 OPC2_32_ABS_LD_DA = 0x03, 558 OPC2_32_ABS_LD_W = 0x00, 559 }; 560 561 /* OPCM_32_ABS_LDB */ 562 enum { 563 OPC2_32_ABS_LD_B = 0x00, 564 OPC2_32_ABS_LD_BU = 0x01, 565 OPC2_32_ABS_LD_H = 0x02, 566 OPC2_32_ABS_LD_HU = 0x03, 567 }; 568 /* OPCM_32_ABS_LDMST_SWAP */ 569 enum { 570 OPC2_32_ABS_LDMST = 0x01, 571 OPC2_32_ABS_SWAP_W = 0x00, 572 }; 573 /* OPCM_32_ABS_LDST_CONTEXT */ 574 enum { 575 OPC2_32_ABS_LDLCX = 0x02, 576 OPC2_32_ABS_LDUCX = 0x03, 577 OPC2_32_ABS_STLCX = 0x00, 578 OPC2_32_ABS_STUCX = 0x01, 579 }; 580 /* OPCM_32_ABS_STORE */ 581 enum { 582 OPC2_32_ABS_ST_A = 0x02, 583 OPC2_32_ABS_ST_D = 0x01, 584 OPC2_32_ABS_ST_DA = 0x03, 585 OPC2_32_ABS_ST_W = 0x00, 586 }; 587 /* OPCM_32_ABS_STOREB_H */ 588 enum { 589 OPC2_32_ABS_ST_B = 0x00, 590 OPC2_32_ABS_ST_H = 0x02, 591 }; 592 /* 593 * Bit Format 594 */ 595 /* OPCM_32_BIT_ANDACC */ 596 enum { 597 OPC2_32_BIT_AND_AND_T = 0x00, 598 OPC2_32_BIT_AND_ANDN_T = 0x03, 599 OPC2_32_BIT_AND_NOR_T = 0x02, 600 OPC2_32_BIT_AND_OR_T = 0x01, 601 }; 602 /* OPCM_32_BIT_LOGICAL_T */ 603 enum { 604 OPC2_32_BIT_AND_T = 0x00, 605 OPC2_32_BIT_ANDN_T = 0x03, 606 OPC2_32_BIT_NOR_T = 0x02, 607 OPC2_32_BIT_OR_T = 0x01, 608 }; 609 /* OPCM_32_BIT_INSERT */ 610 enum { 611 OPC2_32_BIT_INS_T = 0x00, 612 OPC2_32_BIT_INSN_T = 0x01, 613 }; 614 /* OPCM_32_BIT_LOGICAL_T2 */ 615 enum { 616 OPC2_32_BIT_NAND_T = 0x00, 617 OPC2_32_BIT_ORN_T = 0x01, 618 OPC2_32_BIT_XNOR_T = 0x02, 619 OPC2_32_BIT_XOR_T = 0x03, 620 }; 621 /* OPCM_32_BIT_ORAND */ 622 enum { 623 OPC2_32_BIT_OR_AND_T = 0x00, 624 OPC2_32_BIT_OR_ANDN_T = 0x03, 625 OPC2_32_BIT_OR_NOR_T = 0x02, 626 OPC2_32_BIT_OR_OR_T = 0x01, 627 }; 628 /*OPCM_32_BIT_SH_LOGIC1 */ 629 enum { 630 OPC2_32_BIT_SH_AND_T = 0x00, 631 OPC2_32_BIT_SH_ANDN_T = 0x03, 632 OPC2_32_BIT_SH_NOR_T = 0x02, 633 OPC2_32_BIT_SH_OR_T = 0x01, 634 }; 635 /* OPCM_32_BIT_SH_LOGIC2 */ 636 enum { 637 OPC2_32_BIT_SH_NAND_T = 0x00, 638 OPC2_32_BIT_SH_ORN_T = 0x01, 639 OPC2_32_BIT_SH_XNOR_T = 0x02, 640 OPC2_32_BIT_SH_XOR_T = 0x03, 641 }; 642 /* 643 * BO Format 644 */ 645 /* OPCM_32_BO_ADDRMODE_POST_PRE_BASE */ 646 enum { 647 OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e, 648 OPC2_32_BO_CACHEA_I_POSTINC = 0x0e, 649 OPC2_32_BO_CACHEA_I_PREINC = 0x1e, 650 OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c, 651 OPC2_32_BO_CACHEA_W_POSTINC = 0x0c, 652 OPC2_32_BO_CACHEA_W_PREINC = 0x1c, 653 OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d, 654 OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d, 655 OPC2_32_BO_CACHEA_WI_PREINC = 0x1d, 656 /* 1.3.1 only */ 657 OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b, 658 OPC2_32_BO_CACHEI_W_POSTINC = 0x0b, 659 OPC2_32_BO_CACHEI_W_PREINC = 0x1b, 660 OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f, 661 OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f, 662 OPC2_32_BO_CACHEI_WI_PREINC = 0x1f, 663 /* end 1.3.1 only */ 664 OPC2_32_BO_ST_A_SHORTOFF = 0x26, 665 OPC2_32_BO_ST_A_POSTINC = 0x06, 666 OPC2_32_BO_ST_A_PREINC = 0x16, 667 OPC2_32_BO_ST_B_SHORTOFF = 0x20, 668 OPC2_32_BO_ST_B_POSTINC = 0x00, 669 OPC2_32_BO_ST_B_PREINC = 0x10, 670 OPC2_32_BO_ST_D_SHORTOFF = 0x25, 671 OPC2_32_BO_ST_D_POSTINC = 0x05, 672 OPC2_32_BO_ST_D_PREINC = 0x15, 673 OPC2_32_BO_ST_DA_SHORTOFF = 0x27, 674 OPC2_32_BO_ST_DA_POSTINC = 0x07, 675 OPC2_32_BO_ST_DA_PREINC = 0x17, 676 OPC2_32_BO_ST_H_SHORTOFF = 0x22, 677 OPC2_32_BO_ST_H_POSTINC = 0x02, 678 OPC2_32_BO_ST_H_PREINC = 0x12, 679 OPC2_32_BO_ST_Q_SHORTOFF = 0x28, 680 OPC2_32_BO_ST_Q_POSTINC = 0x08, 681 OPC2_32_BO_ST_Q_PREINC = 0x18, 682 OPC2_32_BO_ST_W_SHORTOFF = 0x24, 683 OPC2_32_BO_ST_W_POSTINC = 0x04, 684 OPC2_32_BO_ST_W_PREINC = 0x14, 685 }; 686 /* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR */ 687 enum { 688 OPC2_32_BO_CACHEA_I_BR = 0x0e, 689 OPC2_32_BO_CACHEA_I_CIRC = 0x1e, 690 OPC2_32_BO_CACHEA_W_BR = 0x0c, 691 OPC2_32_BO_CACHEA_W_CIRC = 0x1c, 692 OPC2_32_BO_CACHEA_WI_BR = 0x0d, 693 OPC2_32_BO_CACHEA_WI_CIRC = 0x1d, 694 OPC2_32_BO_ST_A_BR = 0x06, 695 OPC2_32_BO_ST_A_CIRC = 0x16, 696 OPC2_32_BO_ST_B_BR = 0x00, 697 OPC2_32_BO_ST_B_CIRC = 0x10, 698 OPC2_32_BO_ST_D_BR = 0x05, 699 OPC2_32_BO_ST_D_CIRC = 0x15, 700 OPC2_32_BO_ST_DA_BR = 0x07, 701 OPC2_32_BO_ST_DA_CIRC = 0x17, 702 OPC2_32_BO_ST_H_BR = 0x02, 703 OPC2_32_BO_ST_H_CIRC = 0x12, 704 OPC2_32_BO_ST_Q_BR = 0x08, 705 OPC2_32_BO_ST_Q_CIRC = 0x18, 706 OPC2_32_BO_ST_W_BR = 0x04, 707 OPC2_32_BO_ST_W_CIRC = 0x14, 708 }; 709 /* OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE */ 710 enum { 711 OPC2_32_BO_LD_A_SHORTOFF = 0x26, 712 OPC2_32_BO_LD_A_POSTINC = 0x06, 713 OPC2_32_BO_LD_A_PREINC = 0x16, 714 OPC2_32_BO_LD_B_SHORTOFF = 0x20, 715 OPC2_32_BO_LD_B_POSTINC = 0x00, 716 OPC2_32_BO_LD_B_PREINC = 0x10, 717 OPC2_32_BO_LD_BU_SHORTOFF = 0x21, 718 OPC2_32_BO_LD_BU_POSTINC = 0x01, 719 OPC2_32_BO_LD_BU_PREINC = 0x11, 720 OPC2_32_BO_LD_D_SHORTOFF = 0x25, 721 OPC2_32_BO_LD_D_POSTINC = 0x05, 722 OPC2_32_BO_LD_D_PREINC = 0x15, 723 OPC2_32_BO_LD_DA_SHORTOFF = 0x27, 724 OPC2_32_BO_LD_DA_POSTINC = 0x07, 725 OPC2_32_BO_LD_DA_PREINC = 0x17, 726 OPC2_32_BO_LD_H_SHORTOFF = 0x22, 727 OPC2_32_BO_LD_H_POSTINC = 0x02, 728 OPC2_32_BO_LD_H_PREINC = 0x12, 729 OPC2_32_BO_LD_HU_SHORTOFF = 0x23, 730 OPC2_32_BO_LD_HU_POSTINC = 0x03, 731 OPC2_32_BO_LD_HU_PREINC = 0x13, 732 OPC2_32_BO_LD_Q_SHORTOFF = 0x28, 733 OPC2_32_BO_LD_Q_POSTINC = 0x08, 734 OPC2_32_BO_LD_Q_PREINC = 0x18, 735 OPC2_32_BO_LD_W_SHORTOFF = 0x24, 736 OPC2_32_BO_LD_W_POSTINC = 0x04, 737 OPC2_32_BO_LD_W_PREINC = 0x14, 738 }; 739 /* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR */ 740 enum { 741 OPC2_32_BO_LD_A_BR = 0x06, 742 OPC2_32_BO_LD_A_CIRC = 0x16, 743 OPC2_32_BO_LD_B_BR = 0x00, 744 OPC2_32_BO_LD_B_CIRC = 0x10, 745 OPC2_32_BO_LD_BU_BR = 0x01, 746 OPC2_32_BO_LD_BU_CIRC = 0x11, 747 OPC2_32_BO_LD_D_BR = 0x05, 748 OPC2_32_BO_LD_D_CIRC = 0x15, 749 OPC2_32_BO_LD_DA_BR = 0x07, 750 OPC2_32_BO_LD_DA_CIRC = 0x17, 751 OPC2_32_BO_LD_H_BR = 0x02, 752 OPC2_32_BO_LD_H_CIRC = 0x12, 753 OPC2_32_BO_LD_HU_BR = 0x03, 754 OPC2_32_BO_LD_HU_CIRC = 0x13, 755 OPC2_32_BO_LD_Q_BR = 0x08, 756 OPC2_32_BO_LD_Q_CIRC = 0x18, 757 OPC2_32_BO_LD_W_BR = 0x04, 758 OPC2_32_BO_LD_W_CIRC = 0x14, 759 }; 760 /* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE */ 761 enum { 762 OPC2_32_BO_LDLCX_SHORTOFF = 0x24, 763 OPC2_32_BO_LDMST_SHORTOFF = 0x21, 764 OPC2_32_BO_LDMST_POSTINC = 0x01, 765 OPC2_32_BO_LDMST_PREINC = 0x11, 766 OPC2_32_BO_LDUCX_SHORTOFF = 0x25, 767 OPC2_32_BO_LEA_SHORTOFF = 0x28, 768 OPC2_32_BO_STLCX_SHORTOFF = 0x26, 769 OPC2_32_BO_STUCX_SHORTOFF = 0x27, 770 OPC2_32_BO_SWAP_W_SHORTOFF = 0x20, 771 OPC2_32_BO_SWAP_W_POSTINC = 0x00, 772 OPC2_32_BO_SWAP_W_PREINC = 0x10, 773 OPC2_32_BO_CMPSWAP_W_SHORTOFF = 0x23, 774 OPC2_32_BO_CMPSWAP_W_POSTINC = 0x03, 775 OPC2_32_BO_CMPSWAP_W_PREINC = 0x13, 776 OPC2_32_BO_SWAPMSK_W_SHORTOFF = 0x22, 777 OPC2_32_BO_SWAPMSK_W_POSTINC = 0x02, 778 OPC2_32_BO_SWAPMSK_W_PREINC = 0x12, 779 }; 780 /*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */ 781 enum { 782 OPC2_32_BO_LDMST_BR = 0x01, 783 OPC2_32_BO_LDMST_CIRC = 0x11, 784 OPC2_32_BO_SWAP_W_BR = 0x00, 785 OPC2_32_BO_SWAP_W_CIRC = 0x10, 786 OPC2_32_BO_CMPSWAP_W_BR = 0x03, 787 OPC2_32_BO_CMPSWAP_W_CIRC = 0x13, 788 OPC2_32_BO_SWAPMSK_W_BR = 0x02, 789 OPC2_32_BO_SWAPMSK_W_CIRC = 0x12, 790 }; 791 /* 792 * BRC Format 793 */ 794 /*OPCM_32_BRC_EQ_NEQ */ 795 enum { 796 OPC2_32_BRC_JEQ = 0x00, 797 OPC2_32_BRC_JNE = 0x01, 798 }; 799 /* OPCM_32_BRC_GE */ 800 enum { 801 OP2_32_BRC_JGE = 0x00, 802 OPC_32_BRC_JGE_U = 0x01, 803 }; 804 /* OPCM_32_BRC_JLT */ 805 enum { 806 OPC2_32_BRC_JLT = 0x00, 807 OPC2_32_BRC_JLT_U = 0x01, 808 }; 809 /* OPCM_32_BRC_JNE */ 810 enum { 811 OPC2_32_BRC_JNED = 0x01, 812 OPC2_32_BRC_JNEI = 0x00, 813 }; 814 /* 815 * BRN Format 816 */ 817 /* OPCM_32_BRN_JTT */ 818 enum { 819 OPC2_32_BRN_JNZ_T = 0x01, 820 OPC2_32_BRN_JZ_T = 0x00, 821 }; 822 /* 823 * BRR Format 824 */ 825 /* OPCM_32_BRR_EQ_NEQ */ 826 enum { 827 OPC2_32_BRR_JEQ = 0x00, 828 OPC2_32_BRR_JNE = 0x01, 829 }; 830 /* OPCM_32_BRR_ADDR_EQ_NEQ */ 831 enum { 832 OPC2_32_BRR_JEQ_A = 0x00, 833 OPC2_32_BRR_JNE_A = 0x01, 834 }; 835 /*OPCM_32_BRR_GE */ 836 enum { 837 OPC2_32_BRR_JGE = 0x00, 838 OPC2_32_BRR_JGE_U = 0x01, 839 }; 840 /* OPCM_32_BRR_JLT */ 841 enum { 842 OPC2_32_BRR_JLT = 0x00, 843 OPC2_32_BRR_JLT_U = 0x01, 844 }; 845 /* OPCM_32_BRR_JNE */ 846 enum { 847 OPC2_32_BRR_JNED = 0x01, 848 OPC2_32_BRR_JNEI = 0x00, 849 }; 850 /* OPCM_32_BRR_JNZ */ 851 enum { 852 OPC2_32_BRR_JNZ_A = 0x01, 853 OPC2_32_BRR_JZ_A = 0x00, 854 }; 855 /* OPCM_32_BRR_LOOP */ 856 enum { 857 OPC2_32_BRR_LOOP = 0x00, 858 OPC2_32_BRR_LOOPU = 0x01, 859 }; 860 /* 861 * RC Format 862 */ 863 /* OPCM_32_RC_LOGICAL_SHIFT */ 864 enum { 865 OPC2_32_RC_AND = 0x08, 866 OPC2_32_RC_ANDN = 0x0e, 867 OPC2_32_RC_NAND = 0x09, 868 OPC2_32_RC_NOR = 0x0b, 869 OPC2_32_RC_OR = 0x0a, 870 OPC2_32_RC_ORN = 0x0f, 871 OPC2_32_RC_SH = 0x00, 872 OPC2_32_RC_SH_H = 0x40, 873 OPC2_32_RC_SHA = 0x01, 874 OPC2_32_RC_SHA_H = 0x41, 875 OPC2_32_RC_SHAS = 0x02, 876 OPC2_32_RC_XNOR = 0x0d, 877 OPC2_32_RC_XOR = 0x0c, 878 }; 879 /* OPCM_32_RC_ACCUMULATOR */ 880 enum { 881 OPC2_32_RC_ABSDIF = 0x0e, 882 OPC2_32_RC_ABSDIFS = 0x0f, 883 OPC2_32_RC_ADD = 0x00, 884 OPC2_32_RC_ADDC = 0x05, 885 OPC2_32_RC_ADDS = 0x02, 886 OPC2_32_RC_ADDS_U = 0x03, 887 OPC2_32_RC_ADDX = 0x04, 888 OPC2_32_RC_AND_EQ = 0x20, 889 OPC2_32_RC_AND_GE = 0x24, 890 OPC2_32_RC_AND_GE_U = 0x25, 891 OPC2_32_RC_AND_LT = 0x22, 892 OPC2_32_RC_AND_LT_U = 0x23, 893 OPC2_32_RC_AND_NE = 0x21, 894 OPC2_32_RC_EQ = 0x10, 895 OPC2_32_RC_EQANY_B = 0x56, 896 OPC2_32_RC_EQANY_H = 0x76, 897 OPC2_32_RC_GE = 0x14, 898 OPC2_32_RC_GE_U = 0x15, 899 OPC2_32_RC_LT = 0x12, 900 OPC2_32_RC_LT_U = 0x13, 901 OPC2_32_RC_MAX = 0x1a, 902 OPC2_32_RC_MAX_U = 0x1b, 903 OPC2_32_RC_MIN = 0x18, 904 OPC2_32_RC_MIN_U = 0x19, 905 OPC2_32_RC_NE = 0x11, 906 OPC2_32_RC_OR_EQ = 0x27, 907 OPC2_32_RC_OR_GE = 0x2b, 908 OPC2_32_RC_OR_GE_U = 0x2c, 909 OPC2_32_RC_OR_LT = 0x29, 910 OPC2_32_RC_OR_LT_U = 0x2a, 911 OPC2_32_RC_OR_NE = 0x28, 912 OPC2_32_RC_RSUB = 0x08, 913 OPC2_32_RC_RSUBS = 0x0a, 914 OPC2_32_RC_RSUBS_U = 0x0b, 915 OPC2_32_RC_SH_EQ = 0x37, 916 OPC2_32_RC_SH_GE = 0x3b, 917 OPC2_32_RC_SH_GE_U = 0x3c, 918 OPC2_32_RC_SH_LT = 0x39, 919 OPC2_32_RC_SH_LT_U = 0x3a, 920 OPC2_32_RC_SH_NE = 0x38, 921 OPC2_32_RC_XOR_EQ = 0x2f, 922 OPC2_32_RC_XOR_GE = 0x33, 923 OPC2_32_RC_XOR_GE_U = 0x34, 924 OPC2_32_RC_XOR_LT = 0x31, 925 OPC2_32_RC_XOR_LT_U = 0x32, 926 OPC2_32_RC_XOR_NE = 0x30, 927 }; 928 /* OPCM_32_RC_SERVICEROUTINE */ 929 enum { 930 OPC2_32_RC_BISR = 0x00, 931 OPC2_32_RC_SYSCALL = 0x04, 932 }; 933 /* OPCM_32_RC_MUL */ 934 enum { 935 OPC2_32_RC_MUL_32 = 0x01, 936 OPC2_32_RC_MUL_64 = 0x03, 937 OPC2_32_RC_MULS_32 = 0x05, 938 OPC2_32_RC_MUL_U_64 = 0x02, 939 OPC2_32_RC_MULS_U_32 = 0x04, 940 }; 941 /* 942 * RCPW Format 943 */ 944 /* OPCM_32_RCPW_MASK_INSERT */ 945 enum { 946 OPC2_32_RCPW_IMASK = 0x01, 947 OPC2_32_RCPW_INSERT = 0x00, 948 }; 949 /* 950 * RCR Format 951 */ 952 /* OPCM_32_RCR_COND_SELECT */ 953 enum { 954 OPC2_32_RCR_CADD = 0x00, 955 OPC2_32_RCR_CADDN = 0x01, 956 OPC2_32_RCR_SEL = 0x04, 957 OPC2_32_RCR_SELN = 0x05, 958 }; 959 /* OPCM_32_RCR_MADD */ 960 enum { 961 OPC2_32_RCR_MADD_32 = 0x01, 962 OPC2_32_RCR_MADD_64 = 0x03, 963 OPC2_32_RCR_MADDS_32 = 0x05, 964 OPC2_32_RCR_MADDS_64 = 0x07, 965 OPC2_32_RCR_MADD_U_64 = 0x02, 966 OPC2_32_RCR_MADDS_U_32 = 0x04, 967 OPC2_32_RCR_MADDS_U_64 = 0x06, 968 }; 969 /* OPCM_32_RCR_MSUB */ 970 enum { 971 OPC2_32_RCR_MSUB_32 = 0x01, 972 OPC2_32_RCR_MSUB_64 = 0x03, 973 OPC2_32_RCR_MSUBS_32 = 0x05, 974 OPC2_32_RCR_MSUBS_64 = 0x07, 975 OPC2_32_RCR_MSUB_U_64 = 0x02, 976 OPC2_32_RCR_MSUBS_U_32 = 0x04, 977 OPC2_32_RCR_MSUBS_U_64 = 0x06, 978 }; 979 /* 980 * RCRW Format 981 */ 982 /* OPCM_32_RCRW_MASK_INSERT */ 983 enum { 984 OPC2_32_RCRW_IMASK = 0x01, 985 OPC2_32_RCRW_INSERT = 0x00, 986 }; 987 988 /* 989 * RR Format 990 */ 991 /* OPCM_32_RR_LOGICAL_SHIFT */ 992 enum { 993 OPC2_32_RR_AND = 0x08, 994 OPC2_32_RR_ANDN = 0x0e, 995 OPC2_32_RR_CLO = 0x1c, 996 OPC2_32_RR_CLO_H = 0x7d, 997 OPC2_32_RR_CLS = 0x1d, 998 OPC2_32_RR_CLS_H = 0x7e, 999 OPC2_32_RR_CLZ = 0x1b, 1000 OPC2_32_RR_CLZ_H = 0x7c, 1001 OPC2_32_RR_NAND = 0x09, 1002 OPC2_32_RR_NOR = 0x0b, 1003 OPC2_32_RR_OR = 0x0a, 1004 OPC2_32_RR_ORN = 0x0f, 1005 OPC2_32_RR_SH = 0x00, 1006 OPC2_32_RR_SH_H = 0x40, 1007 OPC2_32_RR_SHA = 0x01, 1008 OPC2_32_RR_SHA_H = 0x41, 1009 OPC2_32_RR_SHAS = 0x02, 1010 OPC2_32_RR_XNOR = 0x0d, 1011 OPC2_32_RR_XOR = 0x0c, 1012 }; 1013 /* OPCM_32_RR_ACCUMULATOR */ 1014 enum { 1015 OPC2_32_RR_ABS = 0x1c, 1016 OPC2_32_RR_ABS_B = 0x5c, 1017 OPC2_32_RR_ABS_H = 0x7c, 1018 OPC2_32_RR_ABSDIF = 0x0e, 1019 OPC2_32_RR_ABSDIF_B = 0x4e, 1020 OPC2_32_RR_ABSDIF_H = 0x6e, 1021 OPC2_32_RR_ABSDIFS = 0x0f, 1022 OPC2_32_RR_ABSDIFS_H = 0x6f, 1023 OPC2_32_RR_ABSS = 0x1d, 1024 OPC2_32_RR_ABSS_H = 0x7d, 1025 OPC2_32_RR_ADD = 0x00, 1026 OPC2_32_RR_ADD_B = 0x40, 1027 OPC2_32_RR_ADD_H = 0x60, 1028 OPC2_32_RR_ADDC = 0x05, 1029 OPC2_32_RR_ADDS = 0x02, 1030 OPC2_32_RR_ADDS_H = 0x62, 1031 OPC2_32_RR_ADDS_HU = 0x63, 1032 OPC2_32_RR_ADDS_U = 0x03, 1033 OPC2_32_RR_ADDX = 0x04, 1034 OPC2_32_RR_AND_EQ = 0x20, 1035 OPC2_32_RR_AND_GE = 0x24, 1036 OPC2_32_RR_AND_GE_U = 0x25, 1037 OPC2_32_RR_AND_LT = 0x22, 1038 OPC2_32_RR_AND_LT_U = 0x23, 1039 OPC2_32_RR_AND_NE = 0x21, 1040 OPC2_32_RR_EQ = 0x10, 1041 OPC2_32_RR_EQ_B = 0x50, 1042 OPC2_32_RR_EQ_H = 0x70, 1043 OPC2_32_RR_EQ_W = 0x90, 1044 OPC2_32_RR_EQANY_B = 0x56, 1045 OPC2_32_RR_EQANY_H = 0x76, 1046 OPC2_32_RR_GE = 0x14, 1047 OPC2_32_RR_GE_U = 0x15, 1048 OPC2_32_RR_LT = 0x12, 1049 OPC2_32_RR_LT_U = 0x13, 1050 OPC2_32_RR_LT_B = 0x52, 1051 OPC2_32_RR_LT_BU = 0x53, 1052 OPC2_32_RR_LT_H = 0x72, 1053 OPC2_32_RR_LT_HU = 0x73, 1054 OPC2_32_RR_LT_W = 0x92, 1055 OPC2_32_RR_LT_WU = 0x93, 1056 OPC2_32_RR_MAX = 0x1a, 1057 OPC2_32_RR_MAX_U = 0x1b, 1058 OPC2_32_RR_MAX_B = 0x5a, 1059 OPC2_32_RR_MAX_BU = 0x5b, 1060 OPC2_32_RR_MAX_H = 0x7a, 1061 OPC2_32_RR_MAX_HU = 0x7b, 1062 OPC2_32_RR_MIN = 0x18, 1063 OPC2_32_RR_MIN_U = 0x19, 1064 OPC2_32_RR_MIN_B = 0x58, 1065 OPC2_32_RR_MIN_BU = 0x59, 1066 OPC2_32_RR_MIN_H = 0x78, 1067 OPC2_32_RR_MIN_HU = 0x79, 1068 OPC2_32_RR_MOV = 0x1f, 1069 OPC2_32_RR_MOVS_64 = 0x80, 1070 OPC2_32_RR_MOV_64 = 0x81, 1071 OPC2_32_RR_NE = 0x11, 1072 OPC2_32_RR_OR_EQ = 0x27, 1073 OPC2_32_RR_OR_GE = 0x2b, 1074 OPC2_32_RR_OR_GE_U = 0x2c, 1075 OPC2_32_RR_OR_LT = 0x29, 1076 OPC2_32_RR_OR_LT_U = 0x2a, 1077 OPC2_32_RR_OR_NE = 0x28, 1078 OPC2_32_RR_SAT_B = 0x5e, 1079 OPC2_32_RR_SAT_BU = 0x5f, 1080 OPC2_32_RR_SAT_H = 0x7e, 1081 OPC2_32_RR_SAT_HU = 0x7f, 1082 OPC2_32_RR_SH_EQ = 0x37, 1083 OPC2_32_RR_SH_GE = 0x3b, 1084 OPC2_32_RR_SH_GE_U = 0x3c, 1085 OPC2_32_RR_SH_LT = 0x39, 1086 OPC2_32_RR_SH_LT_U = 0x3a, 1087 OPC2_32_RR_SH_NE = 0x38, 1088 OPC2_32_RR_SUB = 0x08, 1089 OPC2_32_RR_SUB_B = 0x48, 1090 OPC2_32_RR_SUB_H = 0x68, 1091 OPC2_32_RR_SUBC = 0x0d, 1092 OPC2_32_RR_SUBS = 0x0a, 1093 OPC2_32_RR_SUBS_U = 0x0b, 1094 OPC2_32_RR_SUBS_H = 0x6a, 1095 OPC2_32_RR_SUBS_HU = 0x6b, 1096 OPC2_32_RR_SUBX = 0x0c, 1097 OPC2_32_RR_XOR_EQ = 0x2f, 1098 OPC2_32_RR_XOR_GE = 0x33, 1099 OPC2_32_RR_XOR_GE_U = 0x34, 1100 OPC2_32_RR_XOR_LT = 0x31, 1101 OPC2_32_RR_XOR_LT_U = 0x32, 1102 OPC2_32_RR_XOR_NE = 0x30, 1103 }; 1104 /* OPCM_32_RR_ADDRESS */ 1105 enum { 1106 OPC2_32_RR_ADD_A = 0x01, 1107 OPC2_32_RR_ADDSC_A = 0x60, 1108 OPC2_32_RR_ADDSC_AT = 0x62, 1109 OPC2_32_RR_EQ_A = 0x40, 1110 OPC2_32_RR_EQZ = 0x48, 1111 OPC2_32_RR_GE_A = 0x43, 1112 OPC2_32_RR_LT_A = 0x42, 1113 OPC2_32_RR_MOV_A = 0x63, 1114 OPC2_32_RR_MOV_AA = 0x00, 1115 OPC2_32_RR_MOV_D = 0x4c, 1116 OPC2_32_RR_NE_A = 0x41, 1117 OPC2_32_RR_NEZ_A = 0x49, 1118 OPC2_32_RR_SUB_A = 0x02, 1119 }; 1120 /* OPCM_32_RR_FLOAT */ 1121 enum { 1122 OPC2_32_RR_BMERGE = 0x01, 1123 OPC2_32_RR_BSPLIT = 0x09, 1124 OPC2_32_RR_DVINIT_B = 0x5a, 1125 OPC2_32_RR_DVINIT_BU = 0x4a, 1126 OPC2_32_RR_DVINIT_H = 0x3a, 1127 OPC2_32_RR_DVINIT_HU = 0x2a, 1128 OPC2_32_RR_DVINIT = 0x1a, 1129 OPC2_32_RR_DVINIT_U = 0x0a, 1130 OPC2_32_RR_PARITY = 0x02, 1131 OPC2_32_RR_UNPACK = 0x08, 1132 OPC2_32_RR_CRC32 = 0x03, 1133 OPC2_32_RR_DIV = 0x20, 1134 OPC2_32_RR_DIV_U = 0x21, 1135 OPC2_32_RR_MUL_F = 0x04, 1136 OPC2_32_RR_DIV_F = 0x05, 1137 OPC2_32_RR_FTOI = 0x10, 1138 OPC2_32_RR_ITOF = 0x14, 1139 OPC2_32_RR_CMP_F = 0x00, 1140 OPC2_32_RR_FTOIZ = 0x13, 1141 OPC2_32_RR_FTOQ31 = 0x11, 1142 OPC2_32_RR_FTOQ31Z = 0x18, 1143 OPC2_32_RR_FTOU = 0x12, 1144 OPC2_32_RR_FTOUZ = 0x17, 1145 OPC2_32_RR_Q31TOF = 0x15, 1146 OPC2_32_RR_QSEED_F = 0x19, 1147 OPC2_32_RR_UPDFL = 0x0c, 1148 OPC2_32_RR_UTOF = 0x16, 1149 }; 1150 /* OPCM_32_RR_IDIRECT */ 1151 enum { 1152 OPC2_32_RR_JI = 0x03, 1153 OPC2_32_RR_JLI = 0x02, 1154 OPC2_32_RR_CALLI = 0x00, 1155 OPC2_32_RR_FCALLI = 0x01, 1156 }; 1157 /* 1158 * RR1 Format 1159 */ 1160 /* OPCM_32_RR1_MUL */ 1161 enum { 1162 OPC2_32_RR1_MUL_H_32_LL = 0x1a, 1163 OPC2_32_RR1_MUL_H_32_LU = 0x19, 1164 OPC2_32_RR1_MUL_H_32_UL = 0x18, 1165 OPC2_32_RR1_MUL_H_32_UU = 0x1b, 1166 OPC2_32_RR1_MULM_H_64_LL = 0x1e, 1167 OPC2_32_RR1_MULM_H_64_LU = 0x1d, 1168 OPC2_32_RR1_MULM_H_64_UL = 0x1c, 1169 OPC2_32_RR1_MULM_H_64_UU = 0x1f, 1170 OPC2_32_RR1_MULR_H_16_LL = 0x0e, 1171 OPC2_32_RR1_MULR_H_16_LU = 0x0d, 1172 OPC2_32_RR1_MULR_H_16_UL = 0x0c, 1173 OPC2_32_RR1_MULR_H_16_UU = 0x0f, 1174 }; 1175 /* OPCM_32_RR1_MULQ */ 1176 enum { 1177 OPC2_32_RR1_MUL_Q_32 = 0x02, 1178 OPC2_32_RR1_MUL_Q_64 = 0x1b, 1179 OPC2_32_RR1_MUL_Q_32_L = 0x01, 1180 OPC2_32_RR1_MUL_Q_64_L = 0x19, 1181 OPC2_32_RR1_MUL_Q_32_U = 0x00, 1182 OPC2_32_RR1_MUL_Q_64_U = 0x18, 1183 OPC2_32_RR1_MUL_Q_32_LL = 0x05, 1184 OPC2_32_RR1_MUL_Q_32_UU = 0x04, 1185 OPC2_32_RR1_MULR_Q_32_L = 0x07, 1186 OPC2_32_RR1_MULR_Q_32_U = 0x06, 1187 }; 1188 /* 1189 * RR2 Format 1190 */ 1191 /* OPCM_32_RR2_MUL */ 1192 enum { 1193 OPC2_32_RR2_MUL_32 = 0x0a, 1194 OPC2_32_RR2_MUL_64 = 0x6a, 1195 OPC2_32_RR2_MULS_32 = 0x8a, 1196 OPC2_32_RR2_MUL_U_64 = 0x68, 1197 OPC2_32_RR2_MULS_U_32 = 0x88, 1198 }; 1199 /* 1200 * RRPW Format 1201 */ 1202 /* OPCM_32_RRPW_EXTRACT_INSERT */ 1203 enum { 1204 1205 OPC2_32_RRPW_EXTR = 0x02, 1206 OPC2_32_RRPW_EXTR_U = 0x03, 1207 OPC2_32_RRPW_IMASK = 0x01, 1208 OPC2_32_RRPW_INSERT = 0x00, 1209 }; 1210 /* 1211 * RRR Format 1212 */ 1213 /* OPCM_32_RRR_COND_SELECT */ 1214 enum { 1215 OPC2_32_RRR_CADD = 0x00, 1216 OPC2_32_RRR_CADDN = 0x01, 1217 OPC2_32_RRR_CSUB = 0x02, 1218 OPC2_32_RRR_CSUBN = 0x03, 1219 OPC2_32_RRR_SEL = 0x04, 1220 OPC2_32_RRR_SELN = 0x05, 1221 }; 1222 /* OPCM_32_RRR_FLOAT */ 1223 enum { 1224 OPC2_32_RRR_DVADJ = 0x0d, 1225 OPC2_32_RRR_DVSTEP = 0x0f, 1226 OPC2_32_RRR_DVSTEP_U = 0x0e, 1227 OPC2_32_RRR_IXMAX = 0x0a, 1228 OPC2_32_RRR_IXMAX_U = 0x0b, 1229 OPC2_32_RRR_IXMIN = 0x08, 1230 OPC2_32_RRR_IXMIN_U = 0x09, 1231 OPC2_32_RRR_PACK = 0x00, 1232 OPC2_32_RRR_ADD_F = 0x02, 1233 OPC2_32_RRR_SUB_F = 0x03, 1234 OPC2_32_RRR_MADD_F = 0x06, 1235 OPC2_32_RRR_MSUB_F = 0x07, 1236 }; 1237 /* 1238 * RRR1 Format 1239 */ 1240 /* OPCM_32_RRR1_MADD */ 1241 enum { 1242 OPC2_32_RRR1_MADD_H_LL = 0x1a, 1243 OPC2_32_RRR1_MADD_H_LU = 0x19, 1244 OPC2_32_RRR1_MADD_H_UL = 0x18, 1245 OPC2_32_RRR1_MADD_H_UU = 0x1b, 1246 OPC2_32_RRR1_MADDS_H_LL = 0x3a, 1247 OPC2_32_RRR1_MADDS_H_LU = 0x39, 1248 OPC2_32_RRR1_MADDS_H_UL = 0x38, 1249 OPC2_32_RRR1_MADDS_H_UU = 0x3b, 1250 OPC2_32_RRR1_MADDM_H_LL = 0x1e, 1251 OPC2_32_RRR1_MADDM_H_LU = 0x1d, 1252 OPC2_32_RRR1_MADDM_H_UL = 0x1c, 1253 OPC2_32_RRR1_MADDM_H_UU = 0x1f, 1254 OPC2_32_RRR1_MADDMS_H_LL = 0x3e, 1255 OPC2_32_RRR1_MADDMS_H_LU = 0x3d, 1256 OPC2_32_RRR1_MADDMS_H_UL = 0x3c, 1257 OPC2_32_RRR1_MADDMS_H_UU = 0x3f, 1258 OPC2_32_RRR1_MADDR_H_LL = 0x0e, 1259 OPC2_32_RRR1_MADDR_H_LU = 0x0d, 1260 OPC2_32_RRR1_MADDR_H_UL = 0x0c, 1261 OPC2_32_RRR1_MADDR_H_UU = 0x0f, 1262 OPC2_32_RRR1_MADDRS_H_LL = 0x2e, 1263 OPC2_32_RRR1_MADDRS_H_LU = 0x2d, 1264 OPC2_32_RRR1_MADDRS_H_UL = 0x2c, 1265 OPC2_32_RRR1_MADDRS_H_UU = 0x2f, 1266 }; 1267 /* OPCM_32_RRR1_MADDQ_H */ 1268 enum { 1269 OPC2_32_RRR1_MADD_Q_32 = 0x02, 1270 OPC2_32_RRR1_MADD_Q_64 = 0x1b, 1271 OPC2_32_RRR1_MADD_Q_32_L = 0x01, 1272 OPC2_32_RRR1_MADD_Q_64_L = 0x19, 1273 OPC2_32_RRR1_MADD_Q_32_U = 0x00, 1274 OPC2_32_RRR1_MADD_Q_64_U = 0x18, 1275 OPC2_32_RRR1_MADD_Q_32_LL = 0x05, 1276 OPC2_32_RRR1_MADD_Q_64_LL = 0x1d, 1277 OPC2_32_RRR1_MADD_Q_32_UU = 0x04, 1278 OPC2_32_RRR1_MADD_Q_64_UU = 0x1c, 1279 OPC2_32_RRR1_MADDS_Q_32 = 0x22, 1280 OPC2_32_RRR1_MADDS_Q_64 = 0x3b, 1281 OPC2_32_RRR1_MADDS_Q_32_L = 0x21, 1282 OPC2_32_RRR1_MADDS_Q_64_L = 0x39, 1283 OPC2_32_RRR1_MADDS_Q_32_U = 0x20, 1284 OPC2_32_RRR1_MADDS_Q_64_U = 0x38, 1285 OPC2_32_RRR1_MADDS_Q_32_LL = 0x25, 1286 OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d, 1287 OPC2_32_RRR1_MADDS_Q_32_UU = 0x24, 1288 OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c, 1289 OPC2_32_RRR1_MADDR_H_64_UL = 0x1e, 1290 OPC2_32_RRR1_MADDRS_H_64_UL = 0x3e, 1291 OPC2_32_RRR1_MADDR_Q_32_LL = 0x07, 1292 OPC2_32_RRR1_MADDR_Q_32_UU = 0x06, 1293 OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27, 1294 OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26, 1295 }; 1296 /* OPCM_32_RRR1_MADDSU_H */ 1297 enum { 1298 OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a, 1299 OPC2_32_RRR1_MADDSU_H_32_LU = 0x19, 1300 OPC2_32_RRR1_MADDSU_H_32_UL = 0x18, 1301 OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b, 1302 OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a, 1303 OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39, 1304 OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38, 1305 OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b, 1306 OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e, 1307 OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d, 1308 OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c, 1309 OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f, 1310 OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e, 1311 OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d, 1312 OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c, 1313 OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f, 1314 OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e, 1315 OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d, 1316 OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c, 1317 OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f, 1318 OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e, 1319 OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d, 1320 OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c, 1321 OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f, 1322 }; 1323 /* OPCM_32_RRR1_MSUB_H */ 1324 enum { 1325 OPC2_32_RRR1_MSUB_H_LL = 0x1a, 1326 OPC2_32_RRR1_MSUB_H_LU = 0x19, 1327 OPC2_32_RRR1_MSUB_H_UL = 0x18, 1328 OPC2_32_RRR1_MSUB_H_UU = 0x1b, 1329 OPC2_32_RRR1_MSUBS_H_LL = 0x3a, 1330 OPC2_32_RRR1_MSUBS_H_LU = 0x39, 1331 OPC2_32_RRR1_MSUBS_H_UL = 0x38, 1332 OPC2_32_RRR1_MSUBS_H_UU = 0x3b, 1333 OPC2_32_RRR1_MSUBM_H_LL = 0x1e, 1334 OPC2_32_RRR1_MSUBM_H_LU = 0x1d, 1335 OPC2_32_RRR1_MSUBM_H_UL = 0x1c, 1336 OPC2_32_RRR1_MSUBM_H_UU = 0x1f, 1337 OPC2_32_RRR1_MSUBMS_H_LL = 0x3e, 1338 OPC2_32_RRR1_MSUBMS_H_LU = 0x3d, 1339 OPC2_32_RRR1_MSUBMS_H_UL = 0x3c, 1340 OPC2_32_RRR1_MSUBMS_H_UU = 0x3f, 1341 OPC2_32_RRR1_MSUBR_H_LL = 0x0e, 1342 OPC2_32_RRR1_MSUBR_H_LU = 0x0d, 1343 OPC2_32_RRR1_MSUBR_H_UL = 0x0c, 1344 OPC2_32_RRR1_MSUBR_H_UU = 0x0f, 1345 OPC2_32_RRR1_MSUBRS_H_LL = 0x2e, 1346 OPC2_32_RRR1_MSUBRS_H_LU = 0x2d, 1347 OPC2_32_RRR1_MSUBRS_H_UL = 0x2c, 1348 OPC2_32_RRR1_MSUBRS_H_UU = 0x2f, 1349 }; 1350 /* OPCM_32_RRR1_MSUB_Q */ 1351 enum { 1352 OPC2_32_RRR1_MSUB_Q_32 = 0x02, 1353 OPC2_32_RRR1_MSUB_Q_64 = 0x1b, 1354 OPC2_32_RRR1_MSUB_Q_32_L = 0x01, 1355 OPC2_32_RRR1_MSUB_Q_64_L = 0x19, 1356 OPC2_32_RRR1_MSUB_Q_32_U = 0x00, 1357 OPC2_32_RRR1_MSUB_Q_64_U = 0x18, 1358 OPC2_32_RRR1_MSUB_Q_32_LL = 0x05, 1359 OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d, 1360 OPC2_32_RRR1_MSUB_Q_32_UU = 0x04, 1361 OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c, 1362 OPC2_32_RRR1_MSUBS_Q_32 = 0x22, 1363 OPC2_32_RRR1_MSUBS_Q_64 = 0x3b, 1364 OPC2_32_RRR1_MSUBS_Q_32_L = 0x21, 1365 OPC2_32_RRR1_MSUBS_Q_64_L = 0x39, 1366 OPC2_32_RRR1_MSUBS_Q_32_U = 0x20, 1367 OPC2_32_RRR1_MSUBS_Q_64_U = 0x38, 1368 OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25, 1369 OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d, 1370 OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24, 1371 OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c, 1372 OPC2_32_RRR1_MSUBR_H_64_UL = 0x1e, 1373 OPC2_32_RRR1_MSUBRS_H_64_UL = 0x3e, 1374 OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07, 1375 OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06, 1376 OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27, 1377 OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26, 1378 }; 1379 /* OPCM_32_RRR1_MSUBADS_H */ 1380 enum { 1381 OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a, 1382 OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19, 1383 OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18, 1384 OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b, 1385 OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a, 1386 OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39, 1387 OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38, 1388 OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b, 1389 OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e, 1390 OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d, 1391 OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c, 1392 OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f, 1393 OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e, 1394 OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d, 1395 OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c, 1396 OPC2_32_RRR1_MSUBADMS_H_64_UU = 0x3f, 1397 OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e, 1398 OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d, 1399 OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c, 1400 OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f, 1401 OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e, 1402 OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d, 1403 OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c, 1404 OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f, 1405 }; 1406 /* 1407 * RRR2 Format 1408 */ 1409 /* OPCM_32_RRR2_MADD */ 1410 enum { 1411 OPC2_32_RRR2_MADD_32 = 0x0a, 1412 OPC2_32_RRR2_MADD_64 = 0x6a, 1413 OPC2_32_RRR2_MADDS_32 = 0x8a, 1414 OPC2_32_RRR2_MADDS_64 = 0xea, 1415 OPC2_32_RRR2_MADD_U_64 = 0x68, 1416 OPC2_32_RRR2_MADDS_U_32 = 0x88, 1417 OPC2_32_RRR2_MADDS_U_64 = 0xe8, 1418 }; 1419 /* OPCM_32_RRR2_MSUB */ 1420 enum { 1421 OPC2_32_RRR2_MSUB_32 = 0x0a, 1422 OPC2_32_RRR2_MSUB_64 = 0x6a, 1423 OPC2_32_RRR2_MSUBS_32 = 0x8a, 1424 OPC2_32_RRR2_MSUBS_64 = 0xea, 1425 OPC2_32_RRR2_MSUB_U_64 = 0x68, 1426 OPC2_32_RRR2_MSUBS_U_32 = 0x88, 1427 OPC2_32_RRR2_MSUBS_U_64 = 0xe8, 1428 }; 1429 /* 1430 * RRRR Format 1431 */ 1432 /* OPCM_32_RRRR_EXTRACT_INSERT */ 1433 enum { 1434 OPC2_32_RRRR_DEXTR = 0x04, 1435 OPC2_32_RRRR_EXTR = 0x02, 1436 OPC2_32_RRRR_EXTR_U = 0x03, 1437 OPC2_32_RRRR_INSERT = 0x00, 1438 }; 1439 /* 1440 * RRRW Format 1441 */ 1442 /* OPCM_32_RRRW_EXTRACT_INSERT */ 1443 enum { 1444 OPC2_32_RRRW_EXTR = 0x02, 1445 OPC2_32_RRRW_EXTR_U = 0x03, 1446 OPC2_32_RRRW_IMASK = 0x01, 1447 OPC2_32_RRRW_INSERT = 0x00, 1448 }; 1449 /* 1450 * SYS Format 1451 */ 1452 /* OPCM_32_SYS_INTERRUPTS */ 1453 enum { 1454 OPC2_32_SYS_DEBUG = 0x04, 1455 OPC2_32_SYS_DISABLE = 0x0d, 1456 OPC2_32_SYS_DSYNC = 0x12, 1457 OPC2_32_SYS_ENABLE = 0x0c, 1458 OPC2_32_SYS_ISYNC = 0x13, 1459 OPC2_32_SYS_NOP = 0x00, 1460 OPC2_32_SYS_RET = 0x06, 1461 OPC2_32_SYS_RFE = 0x07, 1462 OPC2_32_SYS_RFM = 0x05, 1463 OPC2_32_SYS_RSLCX = 0x09, 1464 OPC2_32_SYS_SVLCX = 0x08, 1465 OPC2_32_SYS_TRAPSV = 0x15, 1466 OPC2_32_SYS_TRAPV = 0x14, 1467 OPC2_32_SYS_RESTORE = 0x0e, 1468 OPC2_32_SYS_FRET = 0x03, 1469 }; 1470