1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "disas/disas.h" 24 #include "exec/exec-all.h" 25 #include "tcg-op.h" 26 #include "exec/cpu_ldst.h" 27 28 #include "exec/helper-proto.h" 29 #include "exec/helper-gen.h" 30 31 #include "tricore-opcodes.h" 32 #include "exec/log.h" 33 34 /* 35 * TCG registers 36 */ 37 static TCGv cpu_PC; 38 static TCGv cpu_PCXI; 39 static TCGv cpu_PSW; 40 static TCGv cpu_ICR; 41 /* GPR registers */ 42 static TCGv cpu_gpr_a[16]; 43 static TCGv cpu_gpr_d[16]; 44 /* PSW Flag cache */ 45 static TCGv cpu_PSW_C; 46 static TCGv cpu_PSW_V; 47 static TCGv cpu_PSW_SV; 48 static TCGv cpu_PSW_AV; 49 static TCGv cpu_PSW_SAV; 50 /* CPU env */ 51 static TCGv_env cpu_env; 52 53 #include "exec/gen-icount.h" 54 55 static const char *regnames_a[] = { 56 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , 57 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , 58 "a12" , "a13" , "a14" , "a15", 59 }; 60 61 static const char *regnames_d[] = { 62 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , 63 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , 64 "d12" , "d13" , "d14" , "d15", 65 }; 66 67 typedef struct DisasContext { 68 struct TranslationBlock *tb; 69 target_ulong pc, saved_pc, next_pc; 70 uint32_t opcode; 71 int singlestep_enabled; 72 /* Routine used to access memory */ 73 int mem_idx; 74 uint32_t hflags, saved_hflags; 75 int bstate; 76 } DisasContext; 77 78 enum { 79 80 BS_NONE = 0, 81 BS_STOP = 1, 82 BS_BRANCH = 2, 83 BS_EXCP = 3, 84 }; 85 86 enum { 87 MODE_LL = 0, 88 MODE_LU = 1, 89 MODE_UL = 2, 90 MODE_UU = 3, 91 }; 92 93 void tricore_cpu_dump_state(CPUState *cs, FILE *f, 94 fprintf_function cpu_fprintf, int flags) 95 { 96 TriCoreCPU *cpu = TRICORE_CPU(cs); 97 CPUTriCoreState *env = &cpu->env; 98 uint32_t psw; 99 int i; 100 101 psw = psw_read(env); 102 103 cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); 104 cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); 105 cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); 106 cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); 107 cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); 108 cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); 109 110 for (i = 0; i < 16; ++i) { 111 if ((i & 3) == 0) { 112 cpu_fprintf(f, "\nGPR A%02d:", i); 113 } 114 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); 115 } 116 for (i = 0; i < 16; ++i) { 117 if ((i & 3) == 0) { 118 cpu_fprintf(f, "\nGPR D%02d:", i); 119 } 120 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); 121 } 122 cpu_fprintf(f, "\n"); 123 } 124 125 /* 126 * Functions to generate micro-ops 127 */ 128 129 /* Makros for generating helpers */ 130 131 #define gen_helper_1arg(name, arg) do { \ 132 TCGv_i32 helper_tmp = tcg_const_i32(arg); \ 133 gen_helper_##name(cpu_env, helper_tmp); \ 134 tcg_temp_free_i32(helper_tmp); \ 135 } while (0) 136 137 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ 138 TCGv arg00 = tcg_temp_new(); \ 139 TCGv arg01 = tcg_temp_new(); \ 140 TCGv arg11 = tcg_temp_new(); \ 141 tcg_gen_sari_tl(arg00, arg0, 16); \ 142 tcg_gen_ext16s_tl(arg01, arg0); \ 143 tcg_gen_ext16s_tl(arg11, arg1); \ 144 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 145 tcg_temp_free(arg00); \ 146 tcg_temp_free(arg01); \ 147 tcg_temp_free(arg11); \ 148 } while (0) 149 150 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ 151 TCGv arg00 = tcg_temp_new(); \ 152 TCGv arg01 = tcg_temp_new(); \ 153 TCGv arg10 = tcg_temp_new(); \ 154 TCGv arg11 = tcg_temp_new(); \ 155 tcg_gen_sari_tl(arg00, arg0, 16); \ 156 tcg_gen_ext16s_tl(arg01, arg0); \ 157 tcg_gen_sari_tl(arg11, arg1, 16); \ 158 tcg_gen_ext16s_tl(arg10, arg1); \ 159 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 160 tcg_temp_free(arg00); \ 161 tcg_temp_free(arg01); \ 162 tcg_temp_free(arg10); \ 163 tcg_temp_free(arg11); \ 164 } while (0) 165 166 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ 167 TCGv arg00 = tcg_temp_new(); \ 168 TCGv arg01 = tcg_temp_new(); \ 169 TCGv arg10 = tcg_temp_new(); \ 170 TCGv arg11 = tcg_temp_new(); \ 171 tcg_gen_sari_tl(arg00, arg0, 16); \ 172 tcg_gen_ext16s_tl(arg01, arg0); \ 173 tcg_gen_sari_tl(arg10, arg1, 16); \ 174 tcg_gen_ext16s_tl(arg11, arg1); \ 175 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 176 tcg_temp_free(arg00); \ 177 tcg_temp_free(arg01); \ 178 tcg_temp_free(arg10); \ 179 tcg_temp_free(arg11); \ 180 } while (0) 181 182 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ 183 TCGv arg00 = tcg_temp_new(); \ 184 TCGv arg01 = tcg_temp_new(); \ 185 TCGv arg11 = tcg_temp_new(); \ 186 tcg_gen_sari_tl(arg01, arg0, 16); \ 187 tcg_gen_ext16s_tl(arg00, arg0); \ 188 tcg_gen_sari_tl(arg11, arg1, 16); \ 189 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 190 tcg_temp_free(arg00); \ 191 tcg_temp_free(arg01); \ 192 tcg_temp_free(arg11); \ 193 } while (0) 194 195 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ 196 TCGv_i64 ret = tcg_temp_new_i64(); \ 197 TCGv_i64 arg1 = tcg_temp_new_i64(); \ 198 \ 199 tcg_gen_concat_i32_i64(arg1, al1, ah1); \ 200 gen_helper_##name(ret, arg1, arg2); \ 201 tcg_gen_extr_i64_i32(rl, rh, ret); \ 202 \ 203 tcg_temp_free_i64(ret); \ 204 tcg_temp_free_i64(arg1); \ 205 } while (0) 206 207 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ 208 TCGv_i64 ret = tcg_temp_new_i64(); \ 209 \ 210 gen_helper_##name(ret, cpu_env, arg1, arg2); \ 211 tcg_gen_extr_i64_i32(rl, rh, ret); \ 212 \ 213 tcg_temp_free_i64(ret); \ 214 } while (0) 215 216 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) 217 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ 218 ((offset & 0x0fffff) << 1)) 219 220 /* For two 32-bit registers used a 64-bit register, the first 221 registernumber needs to be even. Otherwise we trap. */ 222 static inline void generate_trap(DisasContext *ctx, int class, int tin); 223 #define CHECK_REG_PAIR(reg) do { \ 224 if (reg & 0x1) { \ 225 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ 226 } \ 227 } while (0) 228 229 /* Functions for load/save to/from memory */ 230 231 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, 232 int16_t con, TCGMemOp mop) 233 { 234 TCGv temp = tcg_temp_new(); 235 tcg_gen_addi_tl(temp, r2, con); 236 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 237 tcg_temp_free(temp); 238 } 239 240 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, 241 int16_t con, TCGMemOp mop) 242 { 243 TCGv temp = tcg_temp_new(); 244 tcg_gen_addi_tl(temp, r2, con); 245 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 246 tcg_temp_free(temp); 247 } 248 249 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 250 { 251 TCGv_i64 temp = tcg_temp_new_i64(); 252 253 tcg_gen_concat_i32_i64(temp, rl, rh); 254 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ); 255 256 tcg_temp_free_i64(temp); 257 } 258 259 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 260 DisasContext *ctx) 261 { 262 TCGv temp = tcg_temp_new(); 263 tcg_gen_addi_tl(temp, base, con); 264 gen_st_2regs_64(rh, rl, temp, ctx); 265 tcg_temp_free(temp); 266 } 267 268 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 269 { 270 TCGv_i64 temp = tcg_temp_new_i64(); 271 272 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ); 273 /* write back to two 32 bit regs */ 274 tcg_gen_extr_i64_i32(rl, rh, temp); 275 276 tcg_temp_free_i64(temp); 277 } 278 279 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 280 DisasContext *ctx) 281 { 282 TCGv temp = tcg_temp_new(); 283 tcg_gen_addi_tl(temp, base, con); 284 gen_ld_2regs_64(rh, rl, temp, ctx); 285 tcg_temp_free(temp); 286 } 287 288 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 289 TCGMemOp mop) 290 { 291 TCGv temp = tcg_temp_new(); 292 tcg_gen_addi_tl(temp, r2, off); 293 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 294 tcg_gen_mov_tl(r2, temp); 295 tcg_temp_free(temp); 296 } 297 298 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 299 TCGMemOp mop) 300 { 301 TCGv temp = tcg_temp_new(); 302 tcg_gen_addi_tl(temp, r2, off); 303 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 304 tcg_gen_mov_tl(r2, temp); 305 tcg_temp_free(temp); 306 } 307 308 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ 309 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) 310 { 311 TCGv temp = tcg_temp_new(); 312 TCGv temp2 = tcg_temp_new(); 313 314 CHECK_REG_PAIR(ereg); 315 /* temp = (M(EA, word) */ 316 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 317 /* temp = temp & ~E[a][63:32]) */ 318 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); 319 /* temp2 = (E[a][31:0] & E[a][63:32]); */ 320 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); 321 /* temp = temp | temp2; */ 322 tcg_gen_or_tl(temp, temp, temp2); 323 /* M(EA, word) = temp; */ 324 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); 325 326 tcg_temp_free(temp); 327 tcg_temp_free(temp2); 328 } 329 330 /* tmp = M(EA, word); 331 M(EA, word) = D[a]; 332 D[a] = tmp[31:0];*/ 333 static void gen_swap(DisasContext *ctx, int reg, TCGv ea) 334 { 335 TCGv temp = tcg_temp_new(); 336 337 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 338 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); 339 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 340 341 tcg_temp_free(temp); 342 } 343 344 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) 345 { 346 TCGv temp = tcg_temp_new(); 347 TCGv temp2 = tcg_temp_new(); 348 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 349 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, 350 cpu_gpr_d[reg], temp); 351 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 352 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 353 354 tcg_temp_free(temp); 355 tcg_temp_free(temp2); 356 } 357 358 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) 359 { 360 TCGv temp = tcg_temp_new(); 361 TCGv temp2 = tcg_temp_new(); 362 TCGv temp3 = tcg_temp_new(); 363 364 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 365 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); 366 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); 367 tcg_gen_or_tl(temp2, temp2, temp3); 368 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 369 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 370 371 tcg_temp_free(temp); 372 tcg_temp_free(temp2); 373 tcg_temp_free(temp3); 374 } 375 376 377 /* We generate loads and store to core special function register (csfr) through 378 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 379 makros R, A and E, which allow read-only, all and endinit protected access. 380 These makros also specify in which ISA version the csfr was introduced. */ 381 #define R(ADDRESS, REG, FEATURE) \ 382 case ADDRESS: \ 383 if (tricore_feature(env, FEATURE)) { \ 384 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ 385 } \ 386 break; 387 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 388 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 389 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) 390 { 391 /* since we're caching PSW make this a special case */ 392 if (offset == 0xfe04) { 393 gen_helper_psw_read(ret, cpu_env); 394 } else { 395 switch (offset) { 396 #include "csfr.def" 397 } 398 } 399 } 400 #undef R 401 #undef A 402 #undef E 403 404 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, 405 since no execption occurs */ 406 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ 407 case ADDRESS: \ 408 if (tricore_feature(env, FEATURE)) { \ 409 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ 410 } \ 411 break; 412 /* Endinit protected registers 413 TODO: Since the endinit bit is in a register of a not yet implemented 414 watchdog device, we handle endinit protected registers like 415 all-access registers for now. */ 416 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) 417 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1, 418 int32_t offset) 419 { 420 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 421 /* since we're caching PSW make this a special case */ 422 if (offset == 0xfe04) { 423 gen_helper_psw_write(cpu_env, r1); 424 } else { 425 switch (offset) { 426 #include "csfr.def" 427 } 428 } 429 } else { 430 /* generate privilege trap */ 431 } 432 } 433 434 /* Functions for arithmetic instructions */ 435 436 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) 437 { 438 TCGv t0 = tcg_temp_new_i32(); 439 TCGv result = tcg_temp_new_i32(); 440 /* Addition and set V/SV bits */ 441 tcg_gen_add_tl(result, r1, r2); 442 /* calc V bit */ 443 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 444 tcg_gen_xor_tl(t0, r1, r2); 445 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 446 /* Calc SV bit */ 447 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 448 /* Calc AV/SAV bits */ 449 tcg_gen_add_tl(cpu_PSW_AV, result, result); 450 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 451 /* calc SAV */ 452 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 453 /* write back result */ 454 tcg_gen_mov_tl(ret, result); 455 456 tcg_temp_free(result); 457 tcg_temp_free(t0); 458 } 459 460 static inline void 461 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 462 { 463 TCGv temp = tcg_temp_new(); 464 TCGv_i64 t0 = tcg_temp_new_i64(); 465 TCGv_i64 t1 = tcg_temp_new_i64(); 466 TCGv_i64 result = tcg_temp_new_i64(); 467 468 tcg_gen_add_i64(result, r1, r2); 469 /* calc v bit */ 470 tcg_gen_xor_i64(t1, result, r1); 471 tcg_gen_xor_i64(t0, r1, r2); 472 tcg_gen_andc_i64(t1, t1, t0); 473 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 474 /* calc SV bit */ 475 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 476 /* calc AV/SAV bits */ 477 tcg_gen_extrh_i64_i32(temp, result); 478 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 479 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 480 /* calc SAV */ 481 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 482 /* write back result */ 483 tcg_gen_mov_i64(ret, result); 484 485 tcg_temp_free(temp); 486 tcg_temp_free_i64(result); 487 tcg_temp_free_i64(t0); 488 tcg_temp_free_i64(t1); 489 } 490 491 static inline void 492 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 493 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), 494 void(*op2)(TCGv, TCGv, TCGv)) 495 { 496 TCGv temp = tcg_temp_new(); 497 TCGv temp2 = tcg_temp_new(); 498 TCGv temp3 = tcg_temp_new(); 499 TCGv temp4 = tcg_temp_new(); 500 501 (*op1)(temp, r1_low, r2); 502 /* calc V0 bit */ 503 tcg_gen_xor_tl(temp2, temp, r1_low); 504 tcg_gen_xor_tl(temp3, r1_low, r2); 505 if (op1 == tcg_gen_add_tl) { 506 tcg_gen_andc_tl(temp2, temp2, temp3); 507 } else { 508 tcg_gen_and_tl(temp2, temp2, temp3); 509 } 510 511 (*op2)(temp3, r1_high, r3); 512 /* calc V1 bit */ 513 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); 514 tcg_gen_xor_tl(temp4, r1_high, r3); 515 if (op2 == tcg_gen_add_tl) { 516 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); 517 } else { 518 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); 519 } 520 /* combine V0/V1 bits */ 521 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); 522 /* calc sv bit */ 523 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 524 /* write result */ 525 tcg_gen_mov_tl(ret_low, temp); 526 tcg_gen_mov_tl(ret_high, temp3); 527 /* calc AV bit */ 528 tcg_gen_add_tl(temp, ret_low, ret_low); 529 tcg_gen_xor_tl(temp, temp, ret_low); 530 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 531 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); 532 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 533 /* calc SAV bit */ 534 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 535 536 tcg_temp_free(temp); 537 tcg_temp_free(temp2); 538 tcg_temp_free(temp3); 539 tcg_temp_free(temp4); 540 } 541 542 /* ret = r2 + (r1 * r3); */ 543 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 544 { 545 TCGv_i64 t1 = tcg_temp_new_i64(); 546 TCGv_i64 t2 = tcg_temp_new_i64(); 547 TCGv_i64 t3 = tcg_temp_new_i64(); 548 549 tcg_gen_ext_i32_i64(t1, r1); 550 tcg_gen_ext_i32_i64(t2, r2); 551 tcg_gen_ext_i32_i64(t3, r3); 552 553 tcg_gen_mul_i64(t1, t1, t3); 554 tcg_gen_add_i64(t1, t2, t1); 555 556 tcg_gen_extrl_i64_i32(ret, t1); 557 /* calc V 558 t1 > 0x7fffffff */ 559 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 560 /* t1 < -0x80000000 */ 561 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 562 tcg_gen_or_i64(t2, t2, t3); 563 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 564 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 565 /* Calc SV bit */ 566 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 567 /* Calc AV/SAV bits */ 568 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 569 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 570 /* calc SAV */ 571 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 572 573 tcg_temp_free_i64(t1); 574 tcg_temp_free_i64(t2); 575 tcg_temp_free_i64(t3); 576 } 577 578 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 579 { 580 TCGv temp = tcg_const_i32(con); 581 gen_madd32_d(ret, r1, r2, temp); 582 tcg_temp_free(temp); 583 } 584 585 static inline void 586 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 587 TCGv r3) 588 { 589 TCGv t1 = tcg_temp_new(); 590 TCGv t2 = tcg_temp_new(); 591 TCGv t3 = tcg_temp_new(); 592 TCGv t4 = tcg_temp_new(); 593 594 tcg_gen_muls2_tl(t1, t2, r1, r3); 595 /* only the add can overflow */ 596 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); 597 /* calc V bit */ 598 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 599 tcg_gen_xor_tl(t1, r2_high, t2); 600 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); 601 /* Calc SV bit */ 602 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 603 /* Calc AV/SAV bits */ 604 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 605 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 606 /* calc SAV */ 607 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 608 /* write back the result */ 609 tcg_gen_mov_tl(ret_low, t3); 610 tcg_gen_mov_tl(ret_high, t4); 611 612 tcg_temp_free(t1); 613 tcg_temp_free(t2); 614 tcg_temp_free(t3); 615 tcg_temp_free(t4); 616 } 617 618 static inline void 619 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 620 TCGv r3) 621 { 622 TCGv_i64 t1 = tcg_temp_new_i64(); 623 TCGv_i64 t2 = tcg_temp_new_i64(); 624 TCGv_i64 t3 = tcg_temp_new_i64(); 625 626 tcg_gen_extu_i32_i64(t1, r1); 627 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 628 tcg_gen_extu_i32_i64(t3, r3); 629 630 tcg_gen_mul_i64(t1, t1, t3); 631 tcg_gen_add_i64(t2, t2, t1); 632 /* write back result */ 633 tcg_gen_extr_i64_i32(ret_low, ret_high, t2); 634 /* only the add overflows, if t2 < t1 635 calc V bit */ 636 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); 637 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 638 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 639 /* Calc SV bit */ 640 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 641 /* Calc AV/SAV bits */ 642 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 643 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 644 /* calc SAV */ 645 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 646 647 tcg_temp_free_i64(t1); 648 tcg_temp_free_i64(t2); 649 tcg_temp_free_i64(t3); 650 } 651 652 static inline void 653 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 654 int32_t con) 655 { 656 TCGv temp = tcg_const_i32(con); 657 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 658 tcg_temp_free(temp); 659 } 660 661 static inline void 662 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 663 int32_t con) 664 { 665 TCGv temp = tcg_const_i32(con); 666 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 667 tcg_temp_free(temp); 668 } 669 670 static inline void 671 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 672 TCGv r3, uint32_t n, uint32_t mode) 673 { 674 TCGv temp = tcg_const_i32(n); 675 TCGv temp2 = tcg_temp_new(); 676 TCGv_i64 temp64 = tcg_temp_new_i64(); 677 switch (mode) { 678 case MODE_LL: 679 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 680 break; 681 case MODE_LU: 682 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 683 break; 684 case MODE_UL: 685 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 686 break; 687 case MODE_UU: 688 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 689 break; 690 } 691 tcg_gen_extr_i64_i32(temp, temp2, temp64); 692 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 693 tcg_gen_add_tl, tcg_gen_add_tl); 694 tcg_temp_free(temp); 695 tcg_temp_free(temp2); 696 tcg_temp_free_i64(temp64); 697 } 698 699 static inline void 700 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 701 TCGv r3, uint32_t n, uint32_t mode) 702 { 703 TCGv temp = tcg_const_i32(n); 704 TCGv temp2 = tcg_temp_new(); 705 TCGv_i64 temp64 = tcg_temp_new_i64(); 706 switch (mode) { 707 case MODE_LL: 708 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 709 break; 710 case MODE_LU: 711 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 712 break; 713 case MODE_UL: 714 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 715 break; 716 case MODE_UU: 717 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 718 break; 719 } 720 tcg_gen_extr_i64_i32(temp, temp2, temp64); 721 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 722 tcg_gen_sub_tl, tcg_gen_add_tl); 723 tcg_temp_free(temp); 724 tcg_temp_free(temp2); 725 tcg_temp_free_i64(temp64); 726 } 727 728 static inline void 729 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 730 TCGv r3, uint32_t n, uint32_t mode) 731 { 732 TCGv temp = tcg_const_i32(n); 733 TCGv_i64 temp64 = tcg_temp_new_i64(); 734 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 735 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 736 switch (mode) { 737 case MODE_LL: 738 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 739 break; 740 case MODE_LU: 741 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 742 break; 743 case MODE_UL: 744 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 745 break; 746 case MODE_UU: 747 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 748 break; 749 } 750 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 751 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 752 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 753 tcg_gen_sub_i64(temp64, temp64_2, temp64); 754 tcg_gen_shli_i64(temp64, temp64, 16); 755 756 gen_add64_d(temp64_2, temp64_3, temp64); 757 /* write back result */ 758 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 759 760 tcg_temp_free(temp); 761 tcg_temp_free_i64(temp64); 762 tcg_temp_free_i64(temp64_2); 763 tcg_temp_free_i64(temp64_3); 764 } 765 766 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); 767 768 static inline void 769 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 770 TCGv r3, uint32_t n, uint32_t mode) 771 { 772 TCGv temp = tcg_const_i32(n); 773 TCGv temp2 = tcg_temp_new(); 774 TCGv temp3 = tcg_temp_new(); 775 TCGv_i64 temp64 = tcg_temp_new_i64(); 776 777 switch (mode) { 778 case MODE_LL: 779 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 780 break; 781 case MODE_LU: 782 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 783 break; 784 case MODE_UL: 785 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 786 break; 787 case MODE_UU: 788 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 789 break; 790 } 791 tcg_gen_extr_i64_i32(temp, temp2, temp64); 792 gen_adds(ret_low, r1_low, temp); 793 tcg_gen_mov_tl(temp, cpu_PSW_V); 794 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 795 gen_adds(ret_high, r1_high, temp2); 796 /* combine v bits */ 797 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 798 /* combine av bits */ 799 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 800 801 tcg_temp_free(temp); 802 tcg_temp_free(temp2); 803 tcg_temp_free(temp3); 804 tcg_temp_free_i64(temp64); 805 806 } 807 808 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); 809 810 static inline void 811 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 812 TCGv r3, uint32_t n, uint32_t mode) 813 { 814 TCGv temp = tcg_const_i32(n); 815 TCGv temp2 = tcg_temp_new(); 816 TCGv temp3 = tcg_temp_new(); 817 TCGv_i64 temp64 = tcg_temp_new_i64(); 818 819 switch (mode) { 820 case MODE_LL: 821 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 822 break; 823 case MODE_LU: 824 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 825 break; 826 case MODE_UL: 827 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 828 break; 829 case MODE_UU: 830 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 831 break; 832 } 833 tcg_gen_extr_i64_i32(temp, temp2, temp64); 834 gen_subs(ret_low, r1_low, temp); 835 tcg_gen_mov_tl(temp, cpu_PSW_V); 836 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 837 gen_adds(ret_high, r1_high, temp2); 838 /* combine v bits */ 839 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 840 /* combine av bits */ 841 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 842 843 tcg_temp_free(temp); 844 tcg_temp_free(temp2); 845 tcg_temp_free(temp3); 846 tcg_temp_free_i64(temp64); 847 848 } 849 850 static inline void 851 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 852 TCGv r3, uint32_t n, uint32_t mode) 853 { 854 TCGv temp = tcg_const_i32(n); 855 TCGv_i64 temp64 = tcg_temp_new_i64(); 856 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 857 858 switch (mode) { 859 case MODE_LL: 860 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 861 break; 862 case MODE_LU: 863 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 864 break; 865 case MODE_UL: 866 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 867 break; 868 case MODE_UU: 869 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 870 break; 871 } 872 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 873 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 874 tcg_gen_sub_i64(temp64, temp64_2, temp64); 875 tcg_gen_shli_i64(temp64, temp64, 16); 876 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 877 878 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 879 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 880 881 tcg_temp_free(temp); 882 tcg_temp_free_i64(temp64); 883 tcg_temp_free_i64(temp64_2); 884 } 885 886 887 static inline void 888 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 889 TCGv r3, uint32_t n, uint32_t mode) 890 { 891 TCGv temp = tcg_const_i32(n); 892 TCGv_i64 temp64 = tcg_temp_new_i64(); 893 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 894 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 895 switch (mode) { 896 case MODE_LL: 897 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 898 break; 899 case MODE_LU: 900 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 901 break; 902 case MODE_UL: 903 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 904 break; 905 case MODE_UU: 906 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 907 break; 908 } 909 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 910 gen_add64_d(temp64_3, temp64_2, temp64); 911 /* write back result */ 912 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 913 914 tcg_temp_free(temp); 915 tcg_temp_free_i64(temp64); 916 tcg_temp_free_i64(temp64_2); 917 tcg_temp_free_i64(temp64_3); 918 } 919 920 static inline void 921 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 922 TCGv r3, uint32_t n, uint32_t mode) 923 { 924 TCGv temp = tcg_const_i32(n); 925 TCGv_i64 temp64 = tcg_temp_new_i64(); 926 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 927 switch (mode) { 928 case MODE_LL: 929 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 930 break; 931 case MODE_LU: 932 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 933 break; 934 case MODE_UL: 935 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 936 break; 937 case MODE_UU: 938 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 939 break; 940 } 941 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 942 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 943 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 944 945 tcg_temp_free(temp); 946 tcg_temp_free_i64(temp64); 947 tcg_temp_free_i64(temp64_2); 948 } 949 950 static inline void 951 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 952 uint32_t mode) 953 { 954 TCGv temp = tcg_const_i32(n); 955 TCGv_i64 temp64 = tcg_temp_new_i64(); 956 switch (mode) { 957 case MODE_LL: 958 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 959 break; 960 case MODE_LU: 961 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 962 break; 963 case MODE_UL: 964 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 965 break; 966 case MODE_UU: 967 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 968 break; 969 } 970 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); 971 972 tcg_temp_free(temp); 973 tcg_temp_free_i64(temp64); 974 } 975 976 static inline void 977 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 978 { 979 TCGv temp = tcg_temp_new(); 980 TCGv temp2 = tcg_temp_new(); 981 982 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 983 tcg_gen_shli_tl(temp, r1, 16); 984 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); 985 986 tcg_temp_free(temp); 987 tcg_temp_free(temp2); 988 } 989 990 static inline void 991 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 992 { 993 TCGv temp = tcg_const_i32(n); 994 TCGv temp2 = tcg_temp_new(); 995 TCGv_i64 temp64 = tcg_temp_new_i64(); 996 switch (mode) { 997 case MODE_LL: 998 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 999 break; 1000 case MODE_LU: 1001 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1002 break; 1003 case MODE_UL: 1004 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1005 break; 1006 case MODE_UU: 1007 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1008 break; 1009 } 1010 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1011 tcg_gen_shli_tl(temp, r1, 16); 1012 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); 1013 1014 tcg_temp_free(temp); 1015 tcg_temp_free(temp2); 1016 tcg_temp_free_i64(temp64); 1017 } 1018 1019 1020 static inline void 1021 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1022 uint32_t n, uint32_t mode) 1023 { 1024 TCGv temp = tcg_const_i32(n); 1025 TCGv_i64 temp64 = tcg_temp_new_i64(); 1026 switch (mode) { 1027 case MODE_LL: 1028 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1029 break; 1030 case MODE_LU: 1031 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1032 break; 1033 case MODE_UL: 1034 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1035 break; 1036 case MODE_UU: 1037 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1038 break; 1039 } 1040 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 1041 1042 tcg_temp_free(temp); 1043 tcg_temp_free_i64(temp64); 1044 } 1045 1046 static inline void 1047 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1048 { 1049 TCGv temp = tcg_temp_new(); 1050 TCGv temp2 = tcg_temp_new(); 1051 1052 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1053 tcg_gen_shli_tl(temp, r1, 16); 1054 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); 1055 1056 tcg_temp_free(temp); 1057 tcg_temp_free(temp2); 1058 } 1059 1060 static inline void 1061 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1062 { 1063 TCGv temp = tcg_const_i32(n); 1064 TCGv temp2 = tcg_temp_new(); 1065 TCGv_i64 temp64 = tcg_temp_new_i64(); 1066 switch (mode) { 1067 case MODE_LL: 1068 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1069 break; 1070 case MODE_LU: 1071 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1072 break; 1073 case MODE_UL: 1074 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1075 break; 1076 case MODE_UU: 1077 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1078 break; 1079 } 1080 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1081 tcg_gen_shli_tl(temp, r1, 16); 1082 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); 1083 1084 tcg_temp_free(temp); 1085 tcg_temp_free(temp2); 1086 tcg_temp_free_i64(temp64); 1087 } 1088 1089 static inline void 1090 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1091 { 1092 TCGv temp = tcg_const_i32(n); 1093 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp); 1094 tcg_temp_free(temp); 1095 } 1096 1097 static inline void 1098 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1099 { 1100 TCGv temp = tcg_const_i32(n); 1101 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp); 1102 tcg_temp_free(temp); 1103 } 1104 1105 static inline void 1106 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1107 uint32_t up_shift, CPUTriCoreState *env) 1108 { 1109 TCGv temp = tcg_temp_new(); 1110 TCGv temp2 = tcg_temp_new(); 1111 TCGv temp3 = tcg_temp_new(); 1112 TCGv_i64 t1 = tcg_temp_new_i64(); 1113 TCGv_i64 t2 = tcg_temp_new_i64(); 1114 TCGv_i64 t3 = tcg_temp_new_i64(); 1115 1116 tcg_gen_ext_i32_i64(t2, arg2); 1117 tcg_gen_ext_i32_i64(t3, arg3); 1118 1119 tcg_gen_mul_i64(t2, t2, t3); 1120 tcg_gen_shli_i64(t2, t2, n); 1121 1122 tcg_gen_ext_i32_i64(t1, arg1); 1123 tcg_gen_sari_i64(t2, t2, up_shift); 1124 1125 tcg_gen_add_i64(t3, t1, t2); 1126 tcg_gen_extrl_i64_i32(temp3, t3); 1127 /* calc v bit */ 1128 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1129 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1130 tcg_gen_or_i64(t1, t1, t2); 1131 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1132 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1133 /* We produce an overflow on the host if the mul before was 1134 (0x80000000 * 0x80000000) << 1). If this is the 1135 case, we negate the ovf. */ 1136 if (n == 1) { 1137 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1138 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1139 tcg_gen_and_tl(temp, temp, temp2); 1140 tcg_gen_shli_tl(temp, temp, 31); 1141 /* negate v bit, if special condition */ 1142 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1143 } 1144 /* Calc SV bit */ 1145 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1146 /* Calc AV/SAV bits */ 1147 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1148 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1149 /* calc SAV */ 1150 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1151 /* write back result */ 1152 tcg_gen_mov_tl(ret, temp3); 1153 1154 tcg_temp_free(temp); 1155 tcg_temp_free(temp2); 1156 tcg_temp_free(temp3); 1157 tcg_temp_free_i64(t1); 1158 tcg_temp_free_i64(t2); 1159 tcg_temp_free_i64(t3); 1160 } 1161 1162 static inline void 1163 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1164 { 1165 TCGv temp = tcg_temp_new(); 1166 TCGv temp2 = tcg_temp_new(); 1167 if (n == 0) { 1168 tcg_gen_mul_tl(temp, arg2, arg3); 1169 } else { /* n is expected to be 1 */ 1170 tcg_gen_mul_tl(temp, arg2, arg3); 1171 tcg_gen_shli_tl(temp, temp, 1); 1172 /* catch special case r1 = r2 = 0x8000 */ 1173 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1174 tcg_gen_sub_tl(temp, temp, temp2); 1175 } 1176 gen_add_d(ret, arg1, temp); 1177 1178 tcg_temp_free(temp); 1179 tcg_temp_free(temp2); 1180 } 1181 1182 static inline void 1183 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1184 { 1185 TCGv temp = tcg_temp_new(); 1186 TCGv temp2 = tcg_temp_new(); 1187 if (n == 0) { 1188 tcg_gen_mul_tl(temp, arg2, arg3); 1189 } else { /* n is expected to be 1 */ 1190 tcg_gen_mul_tl(temp, arg2, arg3); 1191 tcg_gen_shli_tl(temp, temp, 1); 1192 /* catch special case r1 = r2 = 0x8000 */ 1193 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1194 tcg_gen_sub_tl(temp, temp, temp2); 1195 } 1196 gen_adds(ret, arg1, temp); 1197 1198 tcg_temp_free(temp); 1199 tcg_temp_free(temp2); 1200 } 1201 1202 static inline void 1203 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1204 TCGv arg3, uint32_t n) 1205 { 1206 TCGv temp = tcg_temp_new(); 1207 TCGv temp2 = tcg_temp_new(); 1208 TCGv_i64 t1 = tcg_temp_new_i64(); 1209 TCGv_i64 t2 = tcg_temp_new_i64(); 1210 TCGv_i64 t3 = tcg_temp_new_i64(); 1211 1212 if (n == 0) { 1213 tcg_gen_mul_tl(temp, arg2, arg3); 1214 } else { /* n is expected to be 1 */ 1215 tcg_gen_mul_tl(temp, arg2, arg3); 1216 tcg_gen_shli_tl(temp, temp, 1); 1217 /* catch special case r1 = r2 = 0x8000 */ 1218 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1219 tcg_gen_sub_tl(temp, temp, temp2); 1220 } 1221 tcg_gen_ext_i32_i64(t2, temp); 1222 tcg_gen_shli_i64(t2, t2, 16); 1223 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1224 gen_add64_d(t3, t1, t2); 1225 /* write back result */ 1226 tcg_gen_extr_i64_i32(rl, rh, t3); 1227 1228 tcg_temp_free_i64(t1); 1229 tcg_temp_free_i64(t2); 1230 tcg_temp_free_i64(t3); 1231 tcg_temp_free(temp); 1232 tcg_temp_free(temp2); 1233 } 1234 1235 static inline void 1236 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1237 TCGv arg3, uint32_t n) 1238 { 1239 TCGv temp = tcg_temp_new(); 1240 TCGv temp2 = tcg_temp_new(); 1241 TCGv_i64 t1 = tcg_temp_new_i64(); 1242 TCGv_i64 t2 = tcg_temp_new_i64(); 1243 1244 if (n == 0) { 1245 tcg_gen_mul_tl(temp, arg2, arg3); 1246 } else { /* n is expected to be 1 */ 1247 tcg_gen_mul_tl(temp, arg2, arg3); 1248 tcg_gen_shli_tl(temp, temp, 1); 1249 /* catch special case r1 = r2 = 0x8000 */ 1250 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1251 tcg_gen_sub_tl(temp, temp, temp2); 1252 } 1253 tcg_gen_ext_i32_i64(t2, temp); 1254 tcg_gen_shli_i64(t2, t2, 16); 1255 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1256 1257 gen_helper_add64_ssov(t1, cpu_env, t1, t2); 1258 tcg_gen_extr_i64_i32(rl, rh, t1); 1259 1260 tcg_temp_free(temp); 1261 tcg_temp_free(temp2); 1262 tcg_temp_free_i64(t1); 1263 tcg_temp_free_i64(t2); 1264 } 1265 1266 static inline void 1267 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1268 TCGv arg3, uint32_t n, CPUTriCoreState *env) 1269 { 1270 TCGv_i64 t1 = tcg_temp_new_i64(); 1271 TCGv_i64 t2 = tcg_temp_new_i64(); 1272 TCGv_i64 t3 = tcg_temp_new_i64(); 1273 TCGv_i64 t4 = tcg_temp_new_i64(); 1274 TCGv temp, temp2; 1275 1276 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1277 tcg_gen_ext_i32_i64(t2, arg2); 1278 tcg_gen_ext_i32_i64(t3, arg3); 1279 1280 tcg_gen_mul_i64(t2, t2, t3); 1281 if (n != 0) { 1282 tcg_gen_shli_i64(t2, t2, 1); 1283 } 1284 tcg_gen_add_i64(t4, t1, t2); 1285 /* calc v bit */ 1286 tcg_gen_xor_i64(t3, t4, t1); 1287 tcg_gen_xor_i64(t2, t1, t2); 1288 tcg_gen_andc_i64(t3, t3, t2); 1289 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1290 /* We produce an overflow on the host if the mul before was 1291 (0x80000000 * 0x80000000) << 1). If this is the 1292 case, we negate the ovf. */ 1293 if (n == 1) { 1294 temp = tcg_temp_new(); 1295 temp2 = tcg_temp_new(); 1296 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1297 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1298 tcg_gen_and_tl(temp, temp, temp2); 1299 tcg_gen_shli_tl(temp, temp, 31); 1300 /* negate v bit, if special condition */ 1301 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1302 1303 tcg_temp_free(temp); 1304 tcg_temp_free(temp2); 1305 } 1306 /* write back result */ 1307 tcg_gen_extr_i64_i32(rl, rh, t4); 1308 /* Calc SV bit */ 1309 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1310 /* Calc AV/SAV bits */ 1311 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1312 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1313 /* calc SAV */ 1314 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1315 1316 tcg_temp_free_i64(t1); 1317 tcg_temp_free_i64(t2); 1318 tcg_temp_free_i64(t3); 1319 tcg_temp_free_i64(t4); 1320 } 1321 1322 static inline void 1323 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1324 uint32_t up_shift) 1325 { 1326 TCGv_i64 t1 = tcg_temp_new_i64(); 1327 TCGv_i64 t2 = tcg_temp_new_i64(); 1328 TCGv_i64 t3 = tcg_temp_new_i64(); 1329 1330 tcg_gen_ext_i32_i64(t1, arg1); 1331 tcg_gen_ext_i32_i64(t2, arg2); 1332 tcg_gen_ext_i32_i64(t3, arg3); 1333 1334 tcg_gen_mul_i64(t2, t2, t3); 1335 tcg_gen_sari_i64(t2, t2, up_shift - n); 1336 1337 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); 1338 1339 tcg_temp_free_i64(t1); 1340 tcg_temp_free_i64(t2); 1341 tcg_temp_free_i64(t3); 1342 } 1343 1344 static inline void 1345 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1346 TCGv arg3, uint32_t n) 1347 { 1348 TCGv_i64 r1 = tcg_temp_new_i64(); 1349 TCGv temp = tcg_const_i32(n); 1350 1351 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1352 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); 1353 tcg_gen_extr_i64_i32(rl, rh, r1); 1354 1355 tcg_temp_free_i64(r1); 1356 tcg_temp_free(temp); 1357 } 1358 /* ret = r2 - (r1 * r3); */ 1359 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 1360 { 1361 TCGv_i64 t1 = tcg_temp_new_i64(); 1362 TCGv_i64 t2 = tcg_temp_new_i64(); 1363 TCGv_i64 t3 = tcg_temp_new_i64(); 1364 1365 tcg_gen_ext_i32_i64(t1, r1); 1366 tcg_gen_ext_i32_i64(t2, r2); 1367 tcg_gen_ext_i32_i64(t3, r3); 1368 1369 tcg_gen_mul_i64(t1, t1, t3); 1370 tcg_gen_sub_i64(t1, t2, t1); 1371 1372 tcg_gen_extrl_i64_i32(ret, t1); 1373 /* calc V 1374 t2 > 0x7fffffff */ 1375 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 1376 /* result < -0x80000000 */ 1377 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 1378 tcg_gen_or_i64(t2, t2, t3); 1379 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 1380 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1381 1382 /* Calc SV bit */ 1383 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1384 /* Calc AV/SAV bits */ 1385 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 1386 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 1387 /* calc SAV */ 1388 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1389 1390 tcg_temp_free_i64(t1); 1391 tcg_temp_free_i64(t2); 1392 tcg_temp_free_i64(t3); 1393 } 1394 1395 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 1396 { 1397 TCGv temp = tcg_const_i32(con); 1398 gen_msub32_d(ret, r1, r2, temp); 1399 tcg_temp_free(temp); 1400 } 1401 1402 static inline void 1403 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1404 TCGv r3) 1405 { 1406 TCGv t1 = tcg_temp_new(); 1407 TCGv t2 = tcg_temp_new(); 1408 TCGv t3 = tcg_temp_new(); 1409 TCGv t4 = tcg_temp_new(); 1410 1411 tcg_gen_muls2_tl(t1, t2, r1, r3); 1412 /* only the sub can overflow */ 1413 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); 1414 /* calc V bit */ 1415 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 1416 tcg_gen_xor_tl(t1, r2_high, t2); 1417 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); 1418 /* Calc SV bit */ 1419 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1420 /* Calc AV/SAV bits */ 1421 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 1422 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 1423 /* calc SAV */ 1424 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1425 /* write back the result */ 1426 tcg_gen_mov_tl(ret_low, t3); 1427 tcg_gen_mov_tl(ret_high, t4); 1428 1429 tcg_temp_free(t1); 1430 tcg_temp_free(t2); 1431 tcg_temp_free(t3); 1432 tcg_temp_free(t4); 1433 } 1434 1435 static inline void 1436 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1437 int32_t con) 1438 { 1439 TCGv temp = tcg_const_i32(con); 1440 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1441 tcg_temp_free(temp); 1442 } 1443 1444 static inline void 1445 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1446 TCGv r3) 1447 { 1448 TCGv_i64 t1 = tcg_temp_new_i64(); 1449 TCGv_i64 t2 = tcg_temp_new_i64(); 1450 TCGv_i64 t3 = tcg_temp_new_i64(); 1451 1452 tcg_gen_extu_i32_i64(t1, r1); 1453 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 1454 tcg_gen_extu_i32_i64(t3, r3); 1455 1456 tcg_gen_mul_i64(t1, t1, t3); 1457 tcg_gen_sub_i64(t3, t2, t1); 1458 tcg_gen_extr_i64_i32(ret_low, ret_high, t3); 1459 /* calc V bit, only the sub can overflow, if t1 > t2 */ 1460 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); 1461 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1462 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1463 /* Calc SV bit */ 1464 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1465 /* Calc AV/SAV bits */ 1466 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 1467 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 1468 /* calc SAV */ 1469 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1470 1471 tcg_temp_free_i64(t1); 1472 tcg_temp_free_i64(t2); 1473 tcg_temp_free_i64(t3); 1474 } 1475 1476 static inline void 1477 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1478 int32_t con) 1479 { 1480 TCGv temp = tcg_const_i32(con); 1481 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1482 tcg_temp_free(temp); 1483 } 1484 1485 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) 1486 { 1487 TCGv temp = tcg_const_i32(r2); 1488 gen_add_d(ret, r1, temp); 1489 tcg_temp_free(temp); 1490 } 1491 /* calculate the carry bit too */ 1492 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) 1493 { 1494 TCGv t0 = tcg_temp_new_i32(); 1495 TCGv result = tcg_temp_new_i32(); 1496 1497 tcg_gen_movi_tl(t0, 0); 1498 /* Addition and set C/V/SV bits */ 1499 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); 1500 /* calc V bit */ 1501 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1502 tcg_gen_xor_tl(t0, r1, r2); 1503 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1504 /* Calc SV bit */ 1505 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1506 /* Calc AV/SAV bits */ 1507 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1508 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1509 /* calc SAV */ 1510 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1511 /* write back result */ 1512 tcg_gen_mov_tl(ret, result); 1513 1514 tcg_temp_free(result); 1515 tcg_temp_free(t0); 1516 } 1517 1518 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) 1519 { 1520 TCGv temp = tcg_const_i32(con); 1521 gen_add_CC(ret, r1, temp); 1522 tcg_temp_free(temp); 1523 } 1524 1525 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) 1526 { 1527 TCGv carry = tcg_temp_new_i32(); 1528 TCGv t0 = tcg_temp_new_i32(); 1529 TCGv result = tcg_temp_new_i32(); 1530 1531 tcg_gen_movi_tl(t0, 0); 1532 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); 1533 /* Addition, carry and set C/V/SV bits */ 1534 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); 1535 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); 1536 /* calc V bit */ 1537 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1538 tcg_gen_xor_tl(t0, r1, r2); 1539 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1540 /* Calc SV bit */ 1541 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1542 /* Calc AV/SAV bits */ 1543 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1544 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1545 /* calc SAV */ 1546 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1547 /* write back result */ 1548 tcg_gen_mov_tl(ret, result); 1549 1550 tcg_temp_free(result); 1551 tcg_temp_free(t0); 1552 tcg_temp_free(carry); 1553 } 1554 1555 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) 1556 { 1557 TCGv temp = tcg_const_i32(con); 1558 gen_addc_CC(ret, r1, temp); 1559 tcg_temp_free(temp); 1560 } 1561 1562 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1563 TCGv r4) 1564 { 1565 TCGv temp = tcg_temp_new(); 1566 TCGv temp2 = tcg_temp_new(); 1567 TCGv result = tcg_temp_new(); 1568 TCGv mask = tcg_temp_new(); 1569 TCGv t0 = tcg_const_i32(0); 1570 1571 /* create mask for sticky bits */ 1572 tcg_gen_setcond_tl(cond, mask, r4, t0); 1573 tcg_gen_shli_tl(mask, mask, 31); 1574 1575 tcg_gen_add_tl(result, r1, r2); 1576 /* Calc PSW_V */ 1577 tcg_gen_xor_tl(temp, result, r1); 1578 tcg_gen_xor_tl(temp2, r1, r2); 1579 tcg_gen_andc_tl(temp, temp, temp2); 1580 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1581 /* Set PSW_SV */ 1582 tcg_gen_and_tl(temp, temp, mask); 1583 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1584 /* calc AV bit */ 1585 tcg_gen_add_tl(temp, result, result); 1586 tcg_gen_xor_tl(temp, temp, result); 1587 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1588 /* calc SAV bit */ 1589 tcg_gen_and_tl(temp, temp, mask); 1590 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1591 /* write back result */ 1592 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1593 1594 tcg_temp_free(t0); 1595 tcg_temp_free(temp); 1596 tcg_temp_free(temp2); 1597 tcg_temp_free(result); 1598 tcg_temp_free(mask); 1599 } 1600 1601 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, 1602 TCGv r3, TCGv r4) 1603 { 1604 TCGv temp = tcg_const_i32(r2); 1605 gen_cond_add(cond, r1, temp, r3, r4); 1606 tcg_temp_free(temp); 1607 } 1608 1609 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) 1610 { 1611 TCGv temp = tcg_temp_new_i32(); 1612 TCGv result = tcg_temp_new_i32(); 1613 1614 tcg_gen_sub_tl(result, r1, r2); 1615 /* calc V bit */ 1616 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1617 tcg_gen_xor_tl(temp, r1, r2); 1618 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1619 /* calc SV bit */ 1620 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1621 /* Calc AV bit */ 1622 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1623 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1624 /* calc SAV bit */ 1625 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1626 /* write back result */ 1627 tcg_gen_mov_tl(ret, result); 1628 1629 tcg_temp_free(temp); 1630 tcg_temp_free(result); 1631 } 1632 1633 static inline void 1634 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 1635 { 1636 TCGv temp = tcg_temp_new(); 1637 TCGv_i64 t0 = tcg_temp_new_i64(); 1638 TCGv_i64 t1 = tcg_temp_new_i64(); 1639 TCGv_i64 result = tcg_temp_new_i64(); 1640 1641 tcg_gen_sub_i64(result, r1, r2); 1642 /* calc v bit */ 1643 tcg_gen_xor_i64(t1, result, r1); 1644 tcg_gen_xor_i64(t0, r1, r2); 1645 tcg_gen_and_i64(t1, t1, t0); 1646 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 1647 /* calc SV bit */ 1648 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1649 /* calc AV/SAV bits */ 1650 tcg_gen_extrh_i64_i32(temp, result); 1651 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 1652 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 1653 /* calc SAV */ 1654 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1655 /* write back result */ 1656 tcg_gen_mov_i64(ret, result); 1657 1658 tcg_temp_free(temp); 1659 tcg_temp_free_i64(result); 1660 tcg_temp_free_i64(t0); 1661 tcg_temp_free_i64(t1); 1662 } 1663 1664 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) 1665 { 1666 TCGv result = tcg_temp_new(); 1667 TCGv temp = tcg_temp_new(); 1668 1669 tcg_gen_sub_tl(result, r1, r2); 1670 /* calc C bit */ 1671 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); 1672 /* calc V bit */ 1673 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1674 tcg_gen_xor_tl(temp, r1, r2); 1675 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1676 /* calc SV bit */ 1677 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1678 /* Calc AV bit */ 1679 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1680 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1681 /* calc SAV bit */ 1682 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1683 /* write back result */ 1684 tcg_gen_mov_tl(ret, result); 1685 1686 tcg_temp_free(result); 1687 tcg_temp_free(temp); 1688 } 1689 1690 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) 1691 { 1692 TCGv temp = tcg_temp_new(); 1693 tcg_gen_not_tl(temp, r2); 1694 gen_addc_CC(ret, r1, temp); 1695 tcg_temp_free(temp); 1696 } 1697 1698 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1699 TCGv r4) 1700 { 1701 TCGv temp = tcg_temp_new(); 1702 TCGv temp2 = tcg_temp_new(); 1703 TCGv result = tcg_temp_new(); 1704 TCGv mask = tcg_temp_new(); 1705 TCGv t0 = tcg_const_i32(0); 1706 1707 /* create mask for sticky bits */ 1708 tcg_gen_setcond_tl(cond, mask, r4, t0); 1709 tcg_gen_shli_tl(mask, mask, 31); 1710 1711 tcg_gen_sub_tl(result, r1, r2); 1712 /* Calc PSW_V */ 1713 tcg_gen_xor_tl(temp, result, r1); 1714 tcg_gen_xor_tl(temp2, r1, r2); 1715 tcg_gen_and_tl(temp, temp, temp2); 1716 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1717 /* Set PSW_SV */ 1718 tcg_gen_and_tl(temp, temp, mask); 1719 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1720 /* calc AV bit */ 1721 tcg_gen_add_tl(temp, result, result); 1722 tcg_gen_xor_tl(temp, temp, result); 1723 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1724 /* calc SAV bit */ 1725 tcg_gen_and_tl(temp, temp, mask); 1726 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1727 /* write back result */ 1728 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1729 1730 tcg_temp_free(t0); 1731 tcg_temp_free(temp); 1732 tcg_temp_free(temp2); 1733 tcg_temp_free(result); 1734 tcg_temp_free(mask); 1735 } 1736 1737 static inline void 1738 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1739 TCGv r3, uint32_t n, uint32_t mode) 1740 { 1741 TCGv temp = tcg_const_i32(n); 1742 TCGv temp2 = tcg_temp_new(); 1743 TCGv_i64 temp64 = tcg_temp_new_i64(); 1744 switch (mode) { 1745 case MODE_LL: 1746 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1747 break; 1748 case MODE_LU: 1749 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1750 break; 1751 case MODE_UL: 1752 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1753 break; 1754 case MODE_UU: 1755 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1756 break; 1757 } 1758 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1759 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1760 tcg_gen_sub_tl, tcg_gen_sub_tl); 1761 tcg_temp_free(temp); 1762 tcg_temp_free(temp2); 1763 tcg_temp_free_i64(temp64); 1764 } 1765 1766 static inline void 1767 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1768 TCGv r3, uint32_t n, uint32_t mode) 1769 { 1770 TCGv temp = tcg_const_i32(n); 1771 TCGv temp2 = tcg_temp_new(); 1772 TCGv temp3 = tcg_temp_new(); 1773 TCGv_i64 temp64 = tcg_temp_new_i64(); 1774 1775 switch (mode) { 1776 case MODE_LL: 1777 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1778 break; 1779 case MODE_LU: 1780 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1781 break; 1782 case MODE_UL: 1783 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1784 break; 1785 case MODE_UU: 1786 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1787 break; 1788 } 1789 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1790 gen_subs(ret_low, r1_low, temp); 1791 tcg_gen_mov_tl(temp, cpu_PSW_V); 1792 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 1793 gen_subs(ret_high, r1_high, temp2); 1794 /* combine v bits */ 1795 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 1796 /* combine av bits */ 1797 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 1798 1799 tcg_temp_free(temp); 1800 tcg_temp_free(temp2); 1801 tcg_temp_free(temp3); 1802 tcg_temp_free_i64(temp64); 1803 } 1804 1805 static inline void 1806 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1807 TCGv r3, uint32_t n, uint32_t mode) 1808 { 1809 TCGv temp = tcg_const_i32(n); 1810 TCGv_i64 temp64 = tcg_temp_new_i64(); 1811 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1812 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1813 switch (mode) { 1814 case MODE_LL: 1815 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 1816 break; 1817 case MODE_LU: 1818 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 1819 break; 1820 case MODE_UL: 1821 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 1822 break; 1823 case MODE_UU: 1824 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 1825 break; 1826 } 1827 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1828 gen_sub64_d(temp64_3, temp64_2, temp64); 1829 /* write back result */ 1830 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 1831 1832 tcg_temp_free(temp); 1833 tcg_temp_free_i64(temp64); 1834 tcg_temp_free_i64(temp64_2); 1835 tcg_temp_free_i64(temp64_3); 1836 } 1837 1838 static inline void 1839 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1840 TCGv r3, uint32_t n, uint32_t mode) 1841 { 1842 TCGv temp = tcg_const_i32(n); 1843 TCGv_i64 temp64 = tcg_temp_new_i64(); 1844 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1845 switch (mode) { 1846 case MODE_LL: 1847 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 1848 break; 1849 case MODE_LU: 1850 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 1851 break; 1852 case MODE_UL: 1853 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 1854 break; 1855 case MODE_UU: 1856 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 1857 break; 1858 } 1859 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1860 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 1861 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 1862 1863 tcg_temp_free(temp); 1864 tcg_temp_free_i64(temp64); 1865 tcg_temp_free_i64(temp64_2); 1866 } 1867 1868 static inline void 1869 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 1870 uint32_t mode) 1871 { 1872 TCGv temp = tcg_const_i32(n); 1873 TCGv_i64 temp64 = tcg_temp_new_i64(); 1874 switch (mode) { 1875 case MODE_LL: 1876 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1877 break; 1878 case MODE_LU: 1879 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1880 break; 1881 case MODE_UL: 1882 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1883 break; 1884 case MODE_UU: 1885 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1886 break; 1887 } 1888 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); 1889 1890 tcg_temp_free(temp); 1891 tcg_temp_free_i64(temp64); 1892 } 1893 1894 static inline void 1895 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1896 { 1897 TCGv temp = tcg_temp_new(); 1898 TCGv temp2 = tcg_temp_new(); 1899 1900 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1901 tcg_gen_shli_tl(temp, r1, 16); 1902 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); 1903 1904 tcg_temp_free(temp); 1905 tcg_temp_free(temp2); 1906 } 1907 1908 static inline void 1909 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1910 uint32_t n, uint32_t mode) 1911 { 1912 TCGv temp = tcg_const_i32(n); 1913 TCGv_i64 temp64 = tcg_temp_new_i64(); 1914 switch (mode) { 1915 case MODE_LL: 1916 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1917 break; 1918 case MODE_LU: 1919 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1920 break; 1921 case MODE_UL: 1922 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1923 break; 1924 case MODE_UU: 1925 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1926 break; 1927 } 1928 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 1929 1930 tcg_temp_free(temp); 1931 tcg_temp_free_i64(temp64); 1932 } 1933 1934 static inline void 1935 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1936 { 1937 TCGv temp = tcg_temp_new(); 1938 TCGv temp2 = tcg_temp_new(); 1939 1940 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1941 tcg_gen_shli_tl(temp, r1, 16); 1942 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); 1943 1944 tcg_temp_free(temp); 1945 tcg_temp_free(temp2); 1946 } 1947 1948 static inline void 1949 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1950 { 1951 TCGv temp = tcg_const_i32(n); 1952 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); 1953 tcg_temp_free(temp); 1954 } 1955 1956 static inline void 1957 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1958 { 1959 TCGv temp = tcg_const_i32(n); 1960 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); 1961 tcg_temp_free(temp); 1962 } 1963 1964 static inline void 1965 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1966 uint32_t up_shift, CPUTriCoreState *env) 1967 { 1968 TCGv temp = tcg_temp_new(); 1969 TCGv temp2 = tcg_temp_new(); 1970 TCGv temp3 = tcg_temp_new(); 1971 TCGv_i64 t1 = tcg_temp_new_i64(); 1972 TCGv_i64 t2 = tcg_temp_new_i64(); 1973 TCGv_i64 t3 = tcg_temp_new_i64(); 1974 TCGv_i64 t4 = tcg_temp_new_i64(); 1975 1976 tcg_gen_ext_i32_i64(t2, arg2); 1977 tcg_gen_ext_i32_i64(t3, arg3); 1978 1979 tcg_gen_mul_i64(t2, t2, t3); 1980 1981 tcg_gen_ext_i32_i64(t1, arg1); 1982 /* if we shift part of the fraction out, we need to round up */ 1983 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1984 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1985 tcg_gen_sari_i64(t2, t2, up_shift - n); 1986 tcg_gen_add_i64(t2, t2, t4); 1987 1988 tcg_gen_sub_i64(t3, t1, t2); 1989 tcg_gen_extrl_i64_i32(temp3, t3); 1990 /* calc v bit */ 1991 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1992 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1993 tcg_gen_or_i64(t1, t1, t2); 1994 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1995 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1996 /* Calc SV bit */ 1997 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1998 /* Calc AV/SAV bits */ 1999 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 2000 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 2001 /* calc SAV */ 2002 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2003 /* write back result */ 2004 tcg_gen_mov_tl(ret, temp3); 2005 2006 tcg_temp_free(temp); 2007 tcg_temp_free(temp2); 2008 tcg_temp_free(temp3); 2009 tcg_temp_free_i64(t1); 2010 tcg_temp_free_i64(t2); 2011 tcg_temp_free_i64(t3); 2012 tcg_temp_free_i64(t4); 2013 } 2014 2015 static inline void 2016 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 2017 { 2018 TCGv temp = tcg_temp_new(); 2019 TCGv temp2 = tcg_temp_new(); 2020 if (n == 0) { 2021 tcg_gen_mul_tl(temp, arg2, arg3); 2022 } else { /* n is expected to be 1 */ 2023 tcg_gen_mul_tl(temp, arg2, arg3); 2024 tcg_gen_shli_tl(temp, temp, 1); 2025 /* catch special case r1 = r2 = 0x8000 */ 2026 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2027 tcg_gen_sub_tl(temp, temp, temp2); 2028 } 2029 gen_sub_d(ret, arg1, temp); 2030 2031 tcg_temp_free(temp); 2032 tcg_temp_free(temp2); 2033 } 2034 2035 static inline void 2036 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 2037 { 2038 TCGv temp = tcg_temp_new(); 2039 TCGv temp2 = tcg_temp_new(); 2040 if (n == 0) { 2041 tcg_gen_mul_tl(temp, arg2, arg3); 2042 } else { /* n is expected to be 1 */ 2043 tcg_gen_mul_tl(temp, arg2, arg3); 2044 tcg_gen_shli_tl(temp, temp, 1); 2045 /* catch special case r1 = r2 = 0x8000 */ 2046 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2047 tcg_gen_sub_tl(temp, temp, temp2); 2048 } 2049 gen_subs(ret, arg1, temp); 2050 2051 tcg_temp_free(temp); 2052 tcg_temp_free(temp2); 2053 } 2054 2055 static inline void 2056 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2057 TCGv arg3, uint32_t n) 2058 { 2059 TCGv temp = tcg_temp_new(); 2060 TCGv temp2 = tcg_temp_new(); 2061 TCGv_i64 t1 = tcg_temp_new_i64(); 2062 TCGv_i64 t2 = tcg_temp_new_i64(); 2063 TCGv_i64 t3 = tcg_temp_new_i64(); 2064 2065 if (n == 0) { 2066 tcg_gen_mul_tl(temp, arg2, arg3); 2067 } else { /* n is expected to be 1 */ 2068 tcg_gen_mul_tl(temp, arg2, arg3); 2069 tcg_gen_shli_tl(temp, temp, 1); 2070 /* catch special case r1 = r2 = 0x8000 */ 2071 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2072 tcg_gen_sub_tl(temp, temp, temp2); 2073 } 2074 tcg_gen_ext_i32_i64(t2, temp); 2075 tcg_gen_shli_i64(t2, t2, 16); 2076 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 2077 gen_sub64_d(t3, t1, t2); 2078 /* write back result */ 2079 tcg_gen_extr_i64_i32(rl, rh, t3); 2080 2081 tcg_temp_free_i64(t1); 2082 tcg_temp_free_i64(t2); 2083 tcg_temp_free_i64(t3); 2084 tcg_temp_free(temp); 2085 tcg_temp_free(temp2); 2086 } 2087 2088 static inline void 2089 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2090 TCGv arg3, uint32_t n) 2091 { 2092 TCGv temp = tcg_temp_new(); 2093 TCGv temp2 = tcg_temp_new(); 2094 TCGv_i64 t1 = tcg_temp_new_i64(); 2095 TCGv_i64 t2 = tcg_temp_new_i64(); 2096 2097 if (n == 0) { 2098 tcg_gen_mul_tl(temp, arg2, arg3); 2099 } else { /* n is expected to be 1 */ 2100 tcg_gen_mul_tl(temp, arg2, arg3); 2101 tcg_gen_shli_tl(temp, temp, 1); 2102 /* catch special case r1 = r2 = 0x8000 */ 2103 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2104 tcg_gen_sub_tl(temp, temp, temp2); 2105 } 2106 tcg_gen_ext_i32_i64(t2, temp); 2107 tcg_gen_shli_i64(t2, t2, 16); 2108 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 2109 2110 gen_helper_sub64_ssov(t1, cpu_env, t1, t2); 2111 tcg_gen_extr_i64_i32(rl, rh, t1); 2112 2113 tcg_temp_free(temp); 2114 tcg_temp_free(temp2); 2115 tcg_temp_free_i64(t1); 2116 tcg_temp_free_i64(t2); 2117 } 2118 2119 static inline void 2120 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2121 TCGv arg3, uint32_t n, CPUTriCoreState *env) 2122 { 2123 TCGv_i64 t1 = tcg_temp_new_i64(); 2124 TCGv_i64 t2 = tcg_temp_new_i64(); 2125 TCGv_i64 t3 = tcg_temp_new_i64(); 2126 TCGv_i64 t4 = tcg_temp_new_i64(); 2127 TCGv temp, temp2; 2128 2129 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 2130 tcg_gen_ext_i32_i64(t2, arg2); 2131 tcg_gen_ext_i32_i64(t3, arg3); 2132 2133 tcg_gen_mul_i64(t2, t2, t3); 2134 if (n != 0) { 2135 tcg_gen_shli_i64(t2, t2, 1); 2136 } 2137 tcg_gen_sub_i64(t4, t1, t2); 2138 /* calc v bit */ 2139 tcg_gen_xor_i64(t3, t4, t1); 2140 tcg_gen_xor_i64(t2, t1, t2); 2141 tcg_gen_and_i64(t3, t3, t2); 2142 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 2143 /* We produce an overflow on the host if the mul before was 2144 (0x80000000 * 0x80000000) << 1). If this is the 2145 case, we negate the ovf. */ 2146 if (n == 1) { 2147 temp = tcg_temp_new(); 2148 temp2 = tcg_temp_new(); 2149 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 2150 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 2151 tcg_gen_and_tl(temp, temp, temp2); 2152 tcg_gen_shli_tl(temp, temp, 31); 2153 /* negate v bit, if special condition */ 2154 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 2155 2156 tcg_temp_free(temp); 2157 tcg_temp_free(temp2); 2158 } 2159 /* write back result */ 2160 tcg_gen_extr_i64_i32(rl, rh, t4); 2161 /* Calc SV bit */ 2162 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2163 /* Calc AV/SAV bits */ 2164 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2165 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2166 /* calc SAV */ 2167 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2168 2169 tcg_temp_free_i64(t1); 2170 tcg_temp_free_i64(t2); 2171 tcg_temp_free_i64(t3); 2172 tcg_temp_free_i64(t4); 2173 } 2174 2175 static inline void 2176 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 2177 uint32_t up_shift) 2178 { 2179 TCGv_i64 t1 = tcg_temp_new_i64(); 2180 TCGv_i64 t2 = tcg_temp_new_i64(); 2181 TCGv_i64 t3 = tcg_temp_new_i64(); 2182 TCGv_i64 t4 = tcg_temp_new_i64(); 2183 2184 tcg_gen_ext_i32_i64(t1, arg1); 2185 tcg_gen_ext_i32_i64(t2, arg2); 2186 tcg_gen_ext_i32_i64(t3, arg3); 2187 2188 tcg_gen_mul_i64(t2, t2, t3); 2189 /* if we shift part of the fraction out, we need to round up */ 2190 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 2191 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 2192 tcg_gen_sari_i64(t3, t2, up_shift - n); 2193 tcg_gen_add_i64(t3, t3, t4); 2194 2195 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); 2196 2197 tcg_temp_free_i64(t1); 2198 tcg_temp_free_i64(t2); 2199 tcg_temp_free_i64(t3); 2200 tcg_temp_free_i64(t4); 2201 } 2202 2203 static inline void 2204 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2205 TCGv arg3, uint32_t n) 2206 { 2207 TCGv_i64 r1 = tcg_temp_new_i64(); 2208 TCGv temp = tcg_const_i32(n); 2209 2210 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 2211 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); 2212 tcg_gen_extr_i64_i32(rl, rh, r1); 2213 2214 tcg_temp_free_i64(r1); 2215 tcg_temp_free(temp); 2216 } 2217 2218 static inline void 2219 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2220 TCGv r3, uint32_t n, uint32_t mode) 2221 { 2222 TCGv temp = tcg_const_i32(n); 2223 TCGv temp2 = tcg_temp_new(); 2224 TCGv_i64 temp64 = tcg_temp_new_i64(); 2225 switch (mode) { 2226 case MODE_LL: 2227 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2228 break; 2229 case MODE_LU: 2230 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2231 break; 2232 case MODE_UL: 2233 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2234 break; 2235 case MODE_UU: 2236 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2237 break; 2238 } 2239 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2240 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 2241 tcg_gen_add_tl, tcg_gen_sub_tl); 2242 tcg_temp_free(temp); 2243 tcg_temp_free(temp2); 2244 tcg_temp_free_i64(temp64); 2245 } 2246 2247 static inline void 2248 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2249 TCGv r3, uint32_t n, uint32_t mode) 2250 { 2251 TCGv temp = tcg_const_i32(n); 2252 TCGv_i64 temp64 = tcg_temp_new_i64(); 2253 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2254 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 2255 switch (mode) { 2256 case MODE_LL: 2257 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2258 break; 2259 case MODE_LU: 2260 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2261 break; 2262 case MODE_UL: 2263 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2264 break; 2265 case MODE_UU: 2266 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2267 break; 2268 } 2269 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 2270 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2271 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2272 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2273 tcg_gen_shli_i64(temp64, temp64, 16); 2274 2275 gen_sub64_d(temp64_2, temp64_3, temp64); 2276 /* write back result */ 2277 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 2278 2279 tcg_temp_free(temp); 2280 tcg_temp_free_i64(temp64); 2281 tcg_temp_free_i64(temp64_2); 2282 tcg_temp_free_i64(temp64_3); 2283 } 2284 2285 static inline void 2286 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2287 { 2288 TCGv temp = tcg_const_i32(n); 2289 TCGv temp2 = tcg_temp_new(); 2290 TCGv_i64 temp64 = tcg_temp_new_i64(); 2291 switch (mode) { 2292 case MODE_LL: 2293 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2294 break; 2295 case MODE_LU: 2296 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2297 break; 2298 case MODE_UL: 2299 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2300 break; 2301 case MODE_UU: 2302 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2303 break; 2304 } 2305 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2306 tcg_gen_shli_tl(temp, r1, 16); 2307 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); 2308 2309 tcg_temp_free(temp); 2310 tcg_temp_free(temp2); 2311 tcg_temp_free_i64(temp64); 2312 } 2313 2314 static inline void 2315 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2316 TCGv r3, uint32_t n, uint32_t mode) 2317 { 2318 TCGv temp = tcg_const_i32(n); 2319 TCGv temp2 = tcg_temp_new(); 2320 TCGv temp3 = tcg_temp_new(); 2321 TCGv_i64 temp64 = tcg_temp_new_i64(); 2322 2323 switch (mode) { 2324 case MODE_LL: 2325 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2326 break; 2327 case MODE_LU: 2328 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2329 break; 2330 case MODE_UL: 2331 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2332 break; 2333 case MODE_UU: 2334 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2335 break; 2336 } 2337 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2338 gen_adds(ret_low, r1_low, temp); 2339 tcg_gen_mov_tl(temp, cpu_PSW_V); 2340 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 2341 gen_subs(ret_high, r1_high, temp2); 2342 /* combine v bits */ 2343 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 2344 /* combine av bits */ 2345 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 2346 2347 tcg_temp_free(temp); 2348 tcg_temp_free(temp2); 2349 tcg_temp_free(temp3); 2350 tcg_temp_free_i64(temp64); 2351 } 2352 2353 static inline void 2354 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2355 TCGv r3, uint32_t n, uint32_t mode) 2356 { 2357 TCGv temp = tcg_const_i32(n); 2358 TCGv_i64 temp64 = tcg_temp_new_i64(); 2359 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2360 2361 switch (mode) { 2362 case MODE_LL: 2363 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2364 break; 2365 case MODE_LU: 2366 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2367 break; 2368 case MODE_UL: 2369 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2370 break; 2371 case MODE_UU: 2372 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2373 break; 2374 } 2375 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2376 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2377 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2378 tcg_gen_shli_i64(temp64, temp64, 16); 2379 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 2380 2381 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 2382 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2383 2384 tcg_temp_free(temp); 2385 tcg_temp_free_i64(temp64); 2386 tcg_temp_free_i64(temp64_2); 2387 } 2388 2389 static inline void 2390 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2391 { 2392 TCGv temp = tcg_const_i32(n); 2393 TCGv temp2 = tcg_temp_new(); 2394 TCGv_i64 temp64 = tcg_temp_new_i64(); 2395 switch (mode) { 2396 case MODE_LL: 2397 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2398 break; 2399 case MODE_LU: 2400 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2401 break; 2402 case MODE_UL: 2403 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2404 break; 2405 case MODE_UU: 2406 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2407 break; 2408 } 2409 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2410 tcg_gen_shli_tl(temp, r1, 16); 2411 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); 2412 2413 tcg_temp_free(temp); 2414 tcg_temp_free(temp2); 2415 tcg_temp_free_i64(temp64); 2416 } 2417 2418 static inline void gen_abs(TCGv ret, TCGv r1) 2419 { 2420 TCGv temp = tcg_temp_new(); 2421 TCGv t0 = tcg_const_i32(0); 2422 2423 tcg_gen_neg_tl(temp, r1); 2424 tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp); 2425 /* overflow can only happen, if r1 = 0x80000000 */ 2426 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); 2427 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2428 /* calc SV bit */ 2429 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2430 /* Calc AV bit */ 2431 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2432 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2433 /* calc SAV bit */ 2434 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2435 2436 tcg_temp_free(temp); 2437 tcg_temp_free(t0); 2438 } 2439 2440 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) 2441 { 2442 TCGv temp = tcg_temp_new_i32(); 2443 TCGv result = tcg_temp_new_i32(); 2444 2445 tcg_gen_sub_tl(result, r1, r2); 2446 tcg_gen_sub_tl(temp, r2, r1); 2447 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); 2448 2449 /* calc V bit */ 2450 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 2451 tcg_gen_xor_tl(temp, result, r2); 2452 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); 2453 tcg_gen_xor_tl(temp, r1, r2); 2454 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 2455 /* calc SV bit */ 2456 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2457 /* Calc AV bit */ 2458 tcg_gen_add_tl(cpu_PSW_AV, result, result); 2459 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 2460 /* calc SAV bit */ 2461 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2462 /* write back result */ 2463 tcg_gen_mov_tl(ret, result); 2464 2465 tcg_temp_free(temp); 2466 tcg_temp_free(result); 2467 } 2468 2469 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) 2470 { 2471 TCGv temp = tcg_const_i32(con); 2472 gen_absdif(ret, r1, temp); 2473 tcg_temp_free(temp); 2474 } 2475 2476 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) 2477 { 2478 TCGv temp = tcg_const_i32(con); 2479 gen_helper_absdif_ssov(ret, cpu_env, r1, temp); 2480 tcg_temp_free(temp); 2481 } 2482 2483 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) 2484 { 2485 TCGv high = tcg_temp_new(); 2486 TCGv low = tcg_temp_new(); 2487 2488 tcg_gen_muls2_tl(low, high, r1, r2); 2489 tcg_gen_mov_tl(ret, low); 2490 /* calc V bit */ 2491 tcg_gen_sari_tl(low, low, 31); 2492 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); 2493 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2494 /* calc SV bit */ 2495 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2496 /* Calc AV bit */ 2497 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2498 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2499 /* calc SAV bit */ 2500 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2501 2502 tcg_temp_free(high); 2503 tcg_temp_free(low); 2504 } 2505 2506 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) 2507 { 2508 TCGv temp = tcg_const_i32(con); 2509 gen_mul_i32s(ret, r1, temp); 2510 tcg_temp_free(temp); 2511 } 2512 2513 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2514 { 2515 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); 2516 /* clear V bit */ 2517 tcg_gen_movi_tl(cpu_PSW_V, 0); 2518 /* calc SV bit */ 2519 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2520 /* Calc AV bit */ 2521 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2522 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2523 /* calc SAV bit */ 2524 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2525 } 2526 2527 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, 2528 int32_t con) 2529 { 2530 TCGv temp = tcg_const_i32(con); 2531 gen_mul_i64s(ret_low, ret_high, r1, temp); 2532 tcg_temp_free(temp); 2533 } 2534 2535 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2536 { 2537 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); 2538 /* clear V bit */ 2539 tcg_gen_movi_tl(cpu_PSW_V, 0); 2540 /* calc SV bit */ 2541 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2542 /* Calc AV bit */ 2543 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2544 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2545 /* calc SAV bit */ 2546 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2547 } 2548 2549 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, 2550 int32_t con) 2551 { 2552 TCGv temp = tcg_const_i32(con); 2553 gen_mul_i64u(ret_low, ret_high, r1, temp); 2554 tcg_temp_free(temp); 2555 } 2556 2557 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) 2558 { 2559 TCGv temp = tcg_const_i32(con); 2560 gen_helper_mul_ssov(ret, cpu_env, r1, temp); 2561 tcg_temp_free(temp); 2562 } 2563 2564 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) 2565 { 2566 TCGv temp = tcg_const_i32(con); 2567 gen_helper_mul_suov(ret, cpu_env, r1, temp); 2568 tcg_temp_free(temp); 2569 } 2570 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ 2571 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2572 { 2573 TCGv temp = tcg_const_i32(con); 2574 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); 2575 tcg_temp_free(temp); 2576 } 2577 2578 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2579 { 2580 TCGv temp = tcg_const_i32(con); 2581 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); 2582 tcg_temp_free(temp); 2583 } 2584 2585 static void 2586 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) 2587 { 2588 TCGv temp = tcg_temp_new(); 2589 TCGv_i64 temp_64 = tcg_temp_new_i64(); 2590 TCGv_i64 temp2_64 = tcg_temp_new_i64(); 2591 2592 if (n == 0) { 2593 if (up_shift == 32) { 2594 tcg_gen_muls2_tl(rh, rl, arg1, arg2); 2595 } else if (up_shift == 16) { 2596 tcg_gen_ext_i32_i64(temp_64, arg1); 2597 tcg_gen_ext_i32_i64(temp2_64, arg2); 2598 2599 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2600 tcg_gen_shri_i64(temp_64, temp_64, up_shift); 2601 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2602 } else { 2603 tcg_gen_muls2_tl(rl, rh, arg1, arg2); 2604 } 2605 /* reset v bit */ 2606 tcg_gen_movi_tl(cpu_PSW_V, 0); 2607 } else { /* n is expected to be 1 */ 2608 tcg_gen_ext_i32_i64(temp_64, arg1); 2609 tcg_gen_ext_i32_i64(temp2_64, arg2); 2610 2611 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2612 2613 if (up_shift == 0) { 2614 tcg_gen_shli_i64(temp_64, temp_64, 1); 2615 } else { 2616 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); 2617 } 2618 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2619 /* overflow only occurs if r1 = r2 = 0x8000 */ 2620 if (up_shift == 0) {/* result is 64 bit */ 2621 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, 2622 0x80000000); 2623 } else { /* result is 32 bit */ 2624 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, 2625 0x80000000); 2626 } 2627 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2628 /* calc sv overflow bit */ 2629 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2630 } 2631 /* calc av overflow bit */ 2632 if (up_shift == 0) { 2633 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2634 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2635 } else { 2636 tcg_gen_add_tl(cpu_PSW_AV, rl, rl); 2637 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); 2638 } 2639 /* calc sav overflow bit */ 2640 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2641 tcg_temp_free(temp); 2642 tcg_temp_free_i64(temp_64); 2643 tcg_temp_free_i64(temp2_64); 2644 } 2645 2646 static void 2647 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2648 { 2649 TCGv temp = tcg_temp_new(); 2650 if (n == 0) { 2651 tcg_gen_mul_tl(ret, arg1, arg2); 2652 } else { /* n is expected to be 1 */ 2653 tcg_gen_mul_tl(ret, arg1, arg2); 2654 tcg_gen_shli_tl(ret, ret, 1); 2655 /* catch special case r1 = r2 = 0x8000 */ 2656 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); 2657 tcg_gen_sub_tl(ret, ret, temp); 2658 } 2659 /* reset v bit */ 2660 tcg_gen_movi_tl(cpu_PSW_V, 0); 2661 /* calc av overflow bit */ 2662 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2663 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2664 /* calc sav overflow bit */ 2665 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2666 2667 tcg_temp_free(temp); 2668 } 2669 2670 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2671 { 2672 TCGv temp = tcg_temp_new(); 2673 if (n == 0) { 2674 tcg_gen_mul_tl(ret, arg1, arg2); 2675 tcg_gen_addi_tl(ret, ret, 0x8000); 2676 } else { 2677 tcg_gen_mul_tl(ret, arg1, arg2); 2678 tcg_gen_shli_tl(ret, ret, 1); 2679 tcg_gen_addi_tl(ret, ret, 0x8000); 2680 /* catch special case r1 = r2 = 0x8000 */ 2681 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); 2682 tcg_gen_muli_tl(temp, temp, 0x8001); 2683 tcg_gen_sub_tl(ret, ret, temp); 2684 } 2685 /* reset v bit */ 2686 tcg_gen_movi_tl(cpu_PSW_V, 0); 2687 /* calc av overflow bit */ 2688 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2689 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2690 /* calc sav overflow bit */ 2691 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2692 /* cut halfword off */ 2693 tcg_gen_andi_tl(ret, ret, 0xffff0000); 2694 2695 tcg_temp_free(temp); 2696 } 2697 2698 static inline void 2699 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2700 TCGv r3) 2701 { 2702 TCGv_i64 temp64 = tcg_temp_new_i64(); 2703 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2704 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); 2705 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2706 tcg_temp_free_i64(temp64); 2707 } 2708 2709 static inline void 2710 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2711 int32_t con) 2712 { 2713 TCGv temp = tcg_const_i32(con); 2714 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2715 tcg_temp_free(temp); 2716 } 2717 2718 static inline void 2719 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2720 TCGv r3) 2721 { 2722 TCGv_i64 temp64 = tcg_temp_new_i64(); 2723 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2724 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); 2725 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2726 tcg_temp_free_i64(temp64); 2727 } 2728 2729 static inline void 2730 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2731 int32_t con) 2732 { 2733 TCGv temp = tcg_const_i32(con); 2734 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2735 tcg_temp_free(temp); 2736 } 2737 2738 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2739 { 2740 TCGv temp = tcg_const_i32(con); 2741 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); 2742 tcg_temp_free(temp); 2743 } 2744 2745 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2746 { 2747 TCGv temp = tcg_const_i32(con); 2748 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); 2749 tcg_temp_free(temp); 2750 } 2751 2752 static inline void 2753 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2754 TCGv r3) 2755 { 2756 TCGv_i64 temp64 = tcg_temp_new_i64(); 2757 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2758 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); 2759 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2760 tcg_temp_free_i64(temp64); 2761 } 2762 2763 static inline void 2764 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2765 int32_t con) 2766 { 2767 TCGv temp = tcg_const_i32(con); 2768 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2769 tcg_temp_free(temp); 2770 } 2771 2772 static inline void 2773 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2774 TCGv r3) 2775 { 2776 TCGv_i64 temp64 = tcg_temp_new_i64(); 2777 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2778 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); 2779 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2780 tcg_temp_free_i64(temp64); 2781 } 2782 2783 static inline void 2784 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2785 int32_t con) 2786 { 2787 TCGv temp = tcg_const_i32(con); 2788 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2789 tcg_temp_free(temp); 2790 } 2791 2792 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) 2793 { 2794 TCGv sat_neg = tcg_const_i32(low); 2795 TCGv temp = tcg_const_i32(up); 2796 2797 /* sat_neg = (arg < low ) ? low : arg; */ 2798 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg); 2799 2800 /* ret = (sat_neg > up ) ? up : sat_neg; */ 2801 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg); 2802 2803 tcg_temp_free(sat_neg); 2804 tcg_temp_free(temp); 2805 } 2806 2807 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) 2808 { 2809 TCGv temp = tcg_const_i32(up); 2810 /* sat_neg = (arg > up ) ? up : arg; */ 2811 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg); 2812 tcg_temp_free(temp); 2813 } 2814 2815 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) 2816 { 2817 if (shift_count == -32) { 2818 tcg_gen_movi_tl(ret, 0); 2819 } else if (shift_count >= 0) { 2820 tcg_gen_shli_tl(ret, r1, shift_count); 2821 } else { 2822 tcg_gen_shri_tl(ret, r1, -shift_count); 2823 } 2824 } 2825 2826 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) 2827 { 2828 TCGv temp_low, temp_high; 2829 2830 if (shiftcount == -16) { 2831 tcg_gen_movi_tl(ret, 0); 2832 } else { 2833 temp_high = tcg_temp_new(); 2834 temp_low = tcg_temp_new(); 2835 2836 tcg_gen_andi_tl(temp_low, r1, 0xffff); 2837 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); 2838 gen_shi(temp_low, temp_low, shiftcount); 2839 gen_shi(ret, temp_high, shiftcount); 2840 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); 2841 2842 tcg_temp_free(temp_low); 2843 tcg_temp_free(temp_high); 2844 } 2845 } 2846 2847 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) 2848 { 2849 uint32_t msk, msk_start; 2850 TCGv temp = tcg_temp_new(); 2851 TCGv temp2 = tcg_temp_new(); 2852 TCGv t_0 = tcg_const_i32(0); 2853 2854 if (shift_count == 0) { 2855 /* Clear PSW.C and PSW.V */ 2856 tcg_gen_movi_tl(cpu_PSW_C, 0); 2857 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); 2858 tcg_gen_mov_tl(ret, r1); 2859 } else if (shift_count == -32) { 2860 /* set PSW.C */ 2861 tcg_gen_mov_tl(cpu_PSW_C, r1); 2862 /* fill ret completely with sign bit */ 2863 tcg_gen_sari_tl(ret, r1, 31); 2864 /* clear PSW.V */ 2865 tcg_gen_movi_tl(cpu_PSW_V, 0); 2866 } else if (shift_count > 0) { 2867 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count); 2868 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count); 2869 2870 /* calc carry */ 2871 msk_start = 32 - shift_count; 2872 msk = ((1 << shift_count) - 1) << msk_start; 2873 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2874 /* calc v/sv bits */ 2875 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); 2876 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); 2877 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 2878 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2879 /* calc sv */ 2880 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); 2881 /* do shift */ 2882 tcg_gen_shli_tl(ret, r1, shift_count); 2883 2884 tcg_temp_free(t_max); 2885 tcg_temp_free(t_min); 2886 } else { 2887 /* clear PSW.V */ 2888 tcg_gen_movi_tl(cpu_PSW_V, 0); 2889 /* calc carry */ 2890 msk = (1 << -shift_count) - 1; 2891 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2892 /* do shift */ 2893 tcg_gen_sari_tl(ret, r1, -shift_count); 2894 } 2895 /* calc av overflow bit */ 2896 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2897 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2898 /* calc sav overflow bit */ 2899 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2900 2901 tcg_temp_free(temp); 2902 tcg_temp_free(temp2); 2903 tcg_temp_free(t_0); 2904 } 2905 2906 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) 2907 { 2908 gen_helper_sha_ssov(ret, cpu_env, r1, r2); 2909 } 2910 2911 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) 2912 { 2913 TCGv temp = tcg_const_i32(con); 2914 gen_shas(ret, r1, temp); 2915 tcg_temp_free(temp); 2916 } 2917 2918 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) 2919 { 2920 TCGv low, high; 2921 2922 if (shift_count == 0) { 2923 tcg_gen_mov_tl(ret, r1); 2924 } else if (shift_count > 0) { 2925 low = tcg_temp_new(); 2926 high = tcg_temp_new(); 2927 2928 tcg_gen_andi_tl(high, r1, 0xffff0000); 2929 tcg_gen_shli_tl(low, r1, shift_count); 2930 tcg_gen_shli_tl(ret, high, shift_count); 2931 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2932 2933 tcg_temp_free(low); 2934 tcg_temp_free(high); 2935 } else { 2936 low = tcg_temp_new(); 2937 high = tcg_temp_new(); 2938 2939 tcg_gen_ext16s_tl(low, r1); 2940 tcg_gen_sari_tl(low, low, -shift_count); 2941 tcg_gen_sari_tl(ret, r1, -shift_count); 2942 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2943 2944 tcg_temp_free(low); 2945 tcg_temp_free(high); 2946 } 2947 2948 } 2949 2950 /* ret = {ret[30:0], (r1 cond r2)}; */ 2951 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) 2952 { 2953 TCGv temp = tcg_temp_new(); 2954 TCGv temp2 = tcg_temp_new(); 2955 2956 tcg_gen_shli_tl(temp, ret, 1); 2957 tcg_gen_setcond_tl(cond, temp2, r1, r2); 2958 tcg_gen_or_tl(ret, temp, temp2); 2959 2960 tcg_temp_free(temp); 2961 tcg_temp_free(temp2); 2962 } 2963 2964 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) 2965 { 2966 TCGv temp = tcg_const_i32(con); 2967 gen_sh_cond(cond, ret, r1, temp); 2968 tcg_temp_free(temp); 2969 } 2970 2971 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) 2972 { 2973 gen_helper_add_ssov(ret, cpu_env, r1, r2); 2974 } 2975 2976 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) 2977 { 2978 TCGv temp = tcg_const_i32(con); 2979 gen_helper_add_ssov(ret, cpu_env, r1, temp); 2980 tcg_temp_free(temp); 2981 } 2982 2983 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) 2984 { 2985 TCGv temp = tcg_const_i32(con); 2986 gen_helper_add_suov(ret, cpu_env, r1, temp); 2987 tcg_temp_free(temp); 2988 } 2989 2990 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) 2991 { 2992 gen_helper_sub_ssov(ret, cpu_env, r1, r2); 2993 } 2994 2995 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) 2996 { 2997 gen_helper_sub_suov(ret, cpu_env, r1, r2); 2998 } 2999 3000 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, 3001 int pos1, int pos2, 3002 void(*op1)(TCGv, TCGv, TCGv), 3003 void(*op2)(TCGv, TCGv, TCGv)) 3004 { 3005 TCGv temp1, temp2; 3006 3007 temp1 = tcg_temp_new(); 3008 temp2 = tcg_temp_new(); 3009 3010 tcg_gen_shri_tl(temp2, r2, pos2); 3011 tcg_gen_shri_tl(temp1, r1, pos1); 3012 3013 (*op1)(temp1, temp1, temp2); 3014 (*op2)(temp1 , ret, temp1); 3015 3016 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); 3017 3018 tcg_temp_free(temp1); 3019 tcg_temp_free(temp2); 3020 } 3021 3022 /* ret = r1[pos1] op1 r2[pos2]; */ 3023 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, 3024 int pos1, int pos2, 3025 void(*op1)(TCGv, TCGv, TCGv)) 3026 { 3027 TCGv temp1, temp2; 3028 3029 temp1 = tcg_temp_new(); 3030 temp2 = tcg_temp_new(); 3031 3032 tcg_gen_shri_tl(temp2, r2, pos2); 3033 tcg_gen_shri_tl(temp1, r1, pos1); 3034 3035 (*op1)(ret, temp1, temp2); 3036 3037 tcg_gen_andi_tl(ret, ret, 0x1); 3038 3039 tcg_temp_free(temp1); 3040 tcg_temp_free(temp2); 3041 } 3042 3043 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, 3044 void(*op)(TCGv, TCGv, TCGv)) 3045 { 3046 TCGv temp = tcg_temp_new(); 3047 TCGv temp2 = tcg_temp_new(); 3048 /* temp = (arg1 cond arg2 )*/ 3049 tcg_gen_setcond_tl(cond, temp, r1, r2); 3050 /* temp2 = ret[0]*/ 3051 tcg_gen_andi_tl(temp2, ret, 0x1); 3052 /* temp = temp insn temp2 */ 3053 (*op)(temp, temp, temp2); 3054 /* ret = {ret[31:1], temp} */ 3055 tcg_gen_deposit_tl(ret, ret, temp, 0, 1); 3056 3057 tcg_temp_free(temp); 3058 tcg_temp_free(temp2); 3059 } 3060 3061 static inline void 3062 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, 3063 void(*op)(TCGv, TCGv, TCGv)) 3064 { 3065 TCGv temp = tcg_const_i32(con); 3066 gen_accumulating_cond(cond, ret, r1, temp, op); 3067 tcg_temp_free(temp); 3068 } 3069 3070 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ 3071 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2) 3072 { 3073 tcg_gen_setcond_tl(cond, ret, r1, r2); 3074 tcg_gen_neg_tl(ret, ret); 3075 } 3076 3077 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) 3078 { 3079 TCGv b0 = tcg_temp_new(); 3080 TCGv b1 = tcg_temp_new(); 3081 TCGv b2 = tcg_temp_new(); 3082 TCGv b3 = tcg_temp_new(); 3083 3084 /* byte 0 */ 3085 tcg_gen_andi_tl(b0, r1, 0xff); 3086 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); 3087 3088 /* byte 1 */ 3089 tcg_gen_andi_tl(b1, r1, 0xff00); 3090 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); 3091 3092 /* byte 2 */ 3093 tcg_gen_andi_tl(b2, r1, 0xff0000); 3094 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); 3095 3096 /* byte 3 */ 3097 tcg_gen_andi_tl(b3, r1, 0xff000000); 3098 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); 3099 3100 /* combine them */ 3101 tcg_gen_or_tl(ret, b0, b1); 3102 tcg_gen_or_tl(ret, ret, b2); 3103 tcg_gen_or_tl(ret, ret, b3); 3104 3105 tcg_temp_free(b0); 3106 tcg_temp_free(b1); 3107 tcg_temp_free(b2); 3108 tcg_temp_free(b3); 3109 } 3110 3111 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) 3112 { 3113 TCGv h0 = tcg_temp_new(); 3114 TCGv h1 = tcg_temp_new(); 3115 3116 /* halfword 0 */ 3117 tcg_gen_andi_tl(h0, r1, 0xffff); 3118 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); 3119 3120 /* halfword 1 */ 3121 tcg_gen_andi_tl(h1, r1, 0xffff0000); 3122 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); 3123 3124 /* combine them */ 3125 tcg_gen_or_tl(ret, h0, h1); 3126 3127 tcg_temp_free(h0); 3128 tcg_temp_free(h1); 3129 } 3130 /* mask = ((1 << width) -1) << pos; 3131 ret = (r1 & ~mask) | (r2 << pos) & mask); */ 3132 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) 3133 { 3134 TCGv mask = tcg_temp_new(); 3135 TCGv temp = tcg_temp_new(); 3136 TCGv temp2 = tcg_temp_new(); 3137 3138 tcg_gen_movi_tl(mask, 1); 3139 tcg_gen_shl_tl(mask, mask, width); 3140 tcg_gen_subi_tl(mask, mask, 1); 3141 tcg_gen_shl_tl(mask, mask, pos); 3142 3143 tcg_gen_shl_tl(temp, r2, pos); 3144 tcg_gen_and_tl(temp, temp, mask); 3145 tcg_gen_andc_tl(temp2, r1, mask); 3146 tcg_gen_or_tl(ret, temp, temp2); 3147 3148 tcg_temp_free(mask); 3149 tcg_temp_free(temp); 3150 tcg_temp_free(temp2); 3151 } 3152 3153 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) 3154 { 3155 TCGv_i64 temp = tcg_temp_new_i64(); 3156 3157 gen_helper_bsplit(temp, r1); 3158 tcg_gen_extr_i64_i32(rl, rh, temp); 3159 3160 tcg_temp_free_i64(temp); 3161 } 3162 3163 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) 3164 { 3165 TCGv_i64 temp = tcg_temp_new_i64(); 3166 3167 gen_helper_unpack(temp, r1); 3168 tcg_gen_extr_i64_i32(rl, rh, temp); 3169 3170 tcg_temp_free_i64(temp); 3171 } 3172 3173 static inline void 3174 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 3175 { 3176 TCGv_i64 ret = tcg_temp_new_i64(); 3177 3178 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 3179 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); 3180 } else { 3181 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); 3182 } 3183 tcg_gen_extr_i64_i32(rl, rh, ret); 3184 3185 tcg_temp_free_i64(ret); 3186 } 3187 3188 static inline void 3189 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 3190 { 3191 TCGv_i64 ret = tcg_temp_new_i64(); 3192 3193 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 3194 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); 3195 } else { 3196 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); 3197 } 3198 tcg_gen_extr_i64_i32(rl, rh, ret); 3199 3200 tcg_temp_free_i64(ret); 3201 } 3202 3203 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) 3204 { 3205 TCGv temp = tcg_temp_new(); 3206 /* calc AV bit */ 3207 tcg_gen_add_tl(temp, arg_low, arg_low); 3208 tcg_gen_xor_tl(temp, temp, arg_low); 3209 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); 3210 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); 3211 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 3212 /* calc SAV bit */ 3213 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3214 tcg_gen_movi_tl(cpu_PSW_V, 0); 3215 tcg_temp_free(temp); 3216 } 3217 3218 static void gen_calc_usb_mulr_h(TCGv arg) 3219 { 3220 TCGv temp = tcg_temp_new(); 3221 /* calc AV bit */ 3222 tcg_gen_add_tl(temp, arg, arg); 3223 tcg_gen_xor_tl(temp, temp, arg); 3224 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); 3225 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 3226 /* calc SAV bit */ 3227 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3228 /* clear V bit */ 3229 tcg_gen_movi_tl(cpu_PSW_V, 0); 3230 tcg_temp_free(temp); 3231 } 3232 3233 /* helpers for generating program flow micro-ops */ 3234 3235 static inline void gen_save_pc(target_ulong pc) 3236 { 3237 tcg_gen_movi_tl(cpu_PC, pc); 3238 } 3239 3240 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3241 { 3242 if (unlikely(ctx->singlestep_enabled)) { 3243 return false; 3244 } 3245 3246 #ifndef CONFIG_USER_ONLY 3247 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3248 #else 3249 return true; 3250 #endif 3251 } 3252 3253 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3254 { 3255 if (use_goto_tb(ctx, dest)) { 3256 tcg_gen_goto_tb(n); 3257 gen_save_pc(dest); 3258 tcg_gen_exit_tb((uintptr_t)ctx->tb + n); 3259 } else { 3260 gen_save_pc(dest); 3261 if (ctx->singlestep_enabled) { 3262 /* raise exception debug */ 3263 } 3264 tcg_gen_exit_tb(0); 3265 } 3266 } 3267 3268 static void generate_trap(DisasContext *ctx, int class, int tin) 3269 { 3270 TCGv_i32 classtemp = tcg_const_i32(class); 3271 TCGv_i32 tintemp = tcg_const_i32(tin); 3272 3273 gen_save_pc(ctx->pc); 3274 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); 3275 ctx->bstate = BS_EXCP; 3276 3277 tcg_temp_free(classtemp); 3278 tcg_temp_free(tintemp); 3279 } 3280 3281 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, 3282 TCGv r2, int16_t address) 3283 { 3284 TCGLabel *jumpLabel = gen_new_label(); 3285 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); 3286 3287 gen_goto_tb(ctx, 1, ctx->next_pc); 3288 3289 gen_set_label(jumpLabel); 3290 gen_goto_tb(ctx, 0, ctx->pc + address * 2); 3291 } 3292 3293 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, 3294 int r2, int16_t address) 3295 { 3296 TCGv temp = tcg_const_i32(r2); 3297 gen_branch_cond(ctx, cond, r1, temp, address); 3298 tcg_temp_free(temp); 3299 } 3300 3301 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) 3302 { 3303 TCGLabel *l1 = gen_new_label(); 3304 3305 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); 3306 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); 3307 gen_goto_tb(ctx, 1, ctx->pc + offset); 3308 gen_set_label(l1); 3309 gen_goto_tb(ctx, 0, ctx->next_pc); 3310 } 3311 3312 static void gen_fcall_save_ctx(DisasContext *ctx) 3313 { 3314 TCGv temp = tcg_temp_new(); 3315 3316 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); 3317 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); 3318 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 3319 tcg_gen_mov_tl(cpu_gpr_a[10], temp); 3320 3321 tcg_temp_free(temp); 3322 } 3323 3324 static void gen_fret(DisasContext *ctx) 3325 { 3326 TCGv temp = tcg_temp_new(); 3327 3328 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); 3329 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); 3330 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); 3331 tcg_gen_mov_tl(cpu_PC, temp); 3332 tcg_gen_exit_tb(0); 3333 ctx->bstate = BS_BRANCH; 3334 3335 tcg_temp_free(temp); 3336 } 3337 3338 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 3339 int r2 , int32_t constant , int32_t offset) 3340 { 3341 TCGv temp, temp2; 3342 int n; 3343 3344 switch (opc) { 3345 /* SB-format jumps */ 3346 case OPC1_16_SB_J: 3347 case OPC1_32_B_J: 3348 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3349 break; 3350 case OPC1_32_B_CALL: 3351 case OPC1_16_SB_CALL: 3352 gen_helper_1arg(call, ctx->next_pc); 3353 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3354 break; 3355 case OPC1_16_SB_JZ: 3356 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); 3357 break; 3358 case OPC1_16_SB_JNZ: 3359 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); 3360 break; 3361 /* SBC-format jumps */ 3362 case OPC1_16_SBC_JEQ: 3363 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); 3364 break; 3365 case OPC1_16_SBC_JNE: 3366 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); 3367 break; 3368 /* SBRN-format jumps */ 3369 case OPC1_16_SBRN_JZ_T: 3370 temp = tcg_temp_new(); 3371 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 3372 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3373 tcg_temp_free(temp); 3374 break; 3375 case OPC1_16_SBRN_JNZ_T: 3376 temp = tcg_temp_new(); 3377 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 3378 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3379 tcg_temp_free(temp); 3380 break; 3381 /* SBR-format jumps */ 3382 case OPC1_16_SBR_JEQ: 3383 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 3384 offset); 3385 break; 3386 case OPC1_16_SBR_JNE: 3387 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 3388 offset); 3389 break; 3390 case OPC1_16_SBR_JNZ: 3391 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); 3392 break; 3393 case OPC1_16_SBR_JNZ_A: 3394 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3395 break; 3396 case OPC1_16_SBR_JGEZ: 3397 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); 3398 break; 3399 case OPC1_16_SBR_JGTZ: 3400 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); 3401 break; 3402 case OPC1_16_SBR_JLEZ: 3403 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); 3404 break; 3405 case OPC1_16_SBR_JLTZ: 3406 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); 3407 break; 3408 case OPC1_16_SBR_JZ: 3409 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); 3410 break; 3411 case OPC1_16_SBR_JZ_A: 3412 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3413 break; 3414 case OPC1_16_SBR_LOOP: 3415 gen_loop(ctx, r1, offset * 2 - 32); 3416 break; 3417 /* SR-format jumps */ 3418 case OPC1_16_SR_JI: 3419 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); 3420 tcg_gen_exit_tb(0); 3421 break; 3422 case OPC2_32_SYS_RET: 3423 case OPC2_16_SR_RET: 3424 gen_helper_ret(cpu_env); 3425 tcg_gen_exit_tb(0); 3426 break; 3427 /* B-format */ 3428 case OPC1_32_B_CALLA: 3429 gen_helper_1arg(call, ctx->next_pc); 3430 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3431 break; 3432 case OPC1_32_B_FCALL: 3433 gen_fcall_save_ctx(ctx); 3434 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3435 break; 3436 case OPC1_32_B_FCALLA: 3437 gen_fcall_save_ctx(ctx); 3438 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3439 break; 3440 case OPC1_32_B_JLA: 3441 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 3442 /* fall through */ 3443 case OPC1_32_B_JA: 3444 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3445 break; 3446 case OPC1_32_B_JL: 3447 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 3448 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3449 break; 3450 /* BOL format */ 3451 case OPCM_32_BRC_EQ_NEQ: 3452 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { 3453 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); 3454 } else { 3455 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); 3456 } 3457 break; 3458 case OPCM_32_BRC_GE: 3459 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { 3460 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); 3461 } else { 3462 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3463 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, 3464 offset); 3465 } 3466 break; 3467 case OPCM_32_BRC_JLT: 3468 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { 3469 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); 3470 } else { 3471 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3472 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, 3473 offset); 3474 } 3475 break; 3476 case OPCM_32_BRC_JNE: 3477 temp = tcg_temp_new(); 3478 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { 3479 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3480 /* subi is unconditional */ 3481 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3482 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3483 } else { 3484 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3485 /* addi is unconditional */ 3486 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3487 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3488 } 3489 tcg_temp_free(temp); 3490 break; 3491 /* BRN format */ 3492 case OPCM_32_BRN_JTT: 3493 n = MASK_OP_BRN_N(ctx->opcode); 3494 3495 temp = tcg_temp_new(); 3496 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); 3497 3498 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { 3499 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3500 } else { 3501 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3502 } 3503 tcg_temp_free(temp); 3504 break; 3505 /* BRR Format */ 3506 case OPCM_32_BRR_EQ_NEQ: 3507 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { 3508 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], 3509 offset); 3510 } else { 3511 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3512 offset); 3513 } 3514 break; 3515 case OPCM_32_BRR_ADDR_EQ_NEQ: 3516 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { 3517 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], 3518 offset); 3519 } else { 3520 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], 3521 offset); 3522 } 3523 break; 3524 case OPCM_32_BRR_GE: 3525 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { 3526 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3527 offset); 3528 } else { 3529 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3530 offset); 3531 } 3532 break; 3533 case OPCM_32_BRR_JLT: 3534 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { 3535 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], 3536 offset); 3537 } else { 3538 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3539 offset); 3540 } 3541 break; 3542 case OPCM_32_BRR_LOOP: 3543 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { 3544 gen_loop(ctx, r2, offset * 2); 3545 } else { 3546 /* OPC2_32_BRR_LOOPU */ 3547 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3548 } 3549 break; 3550 case OPCM_32_BRR_JNE: 3551 temp = tcg_temp_new(); 3552 temp2 = tcg_temp_new(); 3553 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { 3554 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3555 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3556 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3557 /* subi is unconditional */ 3558 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3559 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3560 } else { 3561 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3562 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3563 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3564 /* addi is unconditional */ 3565 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3566 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3567 } 3568 tcg_temp_free(temp); 3569 tcg_temp_free(temp2); 3570 break; 3571 case OPCM_32_BRR_JNZ: 3572 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { 3573 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3574 } else { 3575 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3576 } 3577 break; 3578 default: 3579 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3580 } 3581 ctx->bstate = BS_BRANCH; 3582 } 3583 3584 3585 /* 3586 * Functions for decoding instructions 3587 */ 3588 3589 static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1) 3590 { 3591 int r1; 3592 int32_t const4; 3593 TCGv temp, temp2; 3594 3595 r1 = MASK_OP_SRC_S1D(ctx->opcode); 3596 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); 3597 3598 switch (op1) { 3599 case OPC1_16_SRC_ADD: 3600 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3601 break; 3602 case OPC1_16_SRC_ADD_A15: 3603 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); 3604 break; 3605 case OPC1_16_SRC_ADD_15A: 3606 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); 3607 break; 3608 case OPC1_16_SRC_ADD_A: 3609 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); 3610 break; 3611 case OPC1_16_SRC_CADD: 3612 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3613 cpu_gpr_d[15]); 3614 break; 3615 case OPC1_16_SRC_CADDN: 3616 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3617 cpu_gpr_d[15]); 3618 break; 3619 case OPC1_16_SRC_CMOV: 3620 temp = tcg_const_tl(0); 3621 temp2 = tcg_const_tl(const4); 3622 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3623 temp2, cpu_gpr_d[r1]); 3624 tcg_temp_free(temp); 3625 tcg_temp_free(temp2); 3626 break; 3627 case OPC1_16_SRC_CMOVN: 3628 temp = tcg_const_tl(0); 3629 temp2 = tcg_const_tl(const4); 3630 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3631 temp2, cpu_gpr_d[r1]); 3632 tcg_temp_free(temp); 3633 tcg_temp_free(temp2); 3634 break; 3635 case OPC1_16_SRC_EQ: 3636 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3637 const4); 3638 break; 3639 case OPC1_16_SRC_LT: 3640 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3641 const4); 3642 break; 3643 case OPC1_16_SRC_MOV: 3644 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3645 break; 3646 case OPC1_16_SRC_MOV_A: 3647 const4 = MASK_OP_SRC_CONST4(ctx->opcode); 3648 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); 3649 break; 3650 case OPC1_16_SRC_MOV_E: 3651 if (tricore_feature(env, TRICORE_FEATURE_16)) { 3652 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3653 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); 3654 } else { 3655 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3656 } 3657 break; 3658 case OPC1_16_SRC_SH: 3659 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3660 break; 3661 case OPC1_16_SRC_SHA: 3662 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3663 break; 3664 default: 3665 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3666 } 3667 } 3668 3669 static void decode_srr_opc(DisasContext *ctx, int op1) 3670 { 3671 int r1, r2; 3672 TCGv temp; 3673 3674 r1 = MASK_OP_SRR_S1D(ctx->opcode); 3675 r2 = MASK_OP_SRR_S2(ctx->opcode); 3676 3677 switch (op1) { 3678 case OPC1_16_SRR_ADD: 3679 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3680 break; 3681 case OPC1_16_SRR_ADD_A15: 3682 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3683 break; 3684 case OPC1_16_SRR_ADD_15A: 3685 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3686 break; 3687 case OPC1_16_SRR_ADD_A: 3688 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); 3689 break; 3690 case OPC1_16_SRR_ADDS: 3691 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3692 break; 3693 case OPC1_16_SRR_AND: 3694 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3695 break; 3696 case OPC1_16_SRR_CMOV: 3697 temp = tcg_const_tl(0); 3698 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3699 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3700 tcg_temp_free(temp); 3701 break; 3702 case OPC1_16_SRR_CMOVN: 3703 temp = tcg_const_tl(0); 3704 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3705 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3706 tcg_temp_free(temp); 3707 break; 3708 case OPC1_16_SRR_EQ: 3709 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3710 cpu_gpr_d[r2]); 3711 break; 3712 case OPC1_16_SRR_LT: 3713 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3714 cpu_gpr_d[r2]); 3715 break; 3716 case OPC1_16_SRR_MOV: 3717 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); 3718 break; 3719 case OPC1_16_SRR_MOV_A: 3720 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); 3721 break; 3722 case OPC1_16_SRR_MOV_AA: 3723 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); 3724 break; 3725 case OPC1_16_SRR_MOV_D: 3726 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); 3727 break; 3728 case OPC1_16_SRR_MUL: 3729 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3730 break; 3731 case OPC1_16_SRR_OR: 3732 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3733 break; 3734 case OPC1_16_SRR_SUB: 3735 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3736 break; 3737 case OPC1_16_SRR_SUB_A15B: 3738 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3739 break; 3740 case OPC1_16_SRR_SUB_15AB: 3741 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3742 break; 3743 case OPC1_16_SRR_SUBS: 3744 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3745 break; 3746 case OPC1_16_SRR_XOR: 3747 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3748 break; 3749 default: 3750 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3751 } 3752 } 3753 3754 static void decode_ssr_opc(DisasContext *ctx, int op1) 3755 { 3756 int r1, r2; 3757 3758 r1 = MASK_OP_SSR_S1(ctx->opcode); 3759 r2 = MASK_OP_SSR_S2(ctx->opcode); 3760 3761 switch (op1) { 3762 case OPC1_16_SSR_ST_A: 3763 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3764 break; 3765 case OPC1_16_SSR_ST_A_POSTINC: 3766 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3767 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3768 break; 3769 case OPC1_16_SSR_ST_B: 3770 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3771 break; 3772 case OPC1_16_SSR_ST_B_POSTINC: 3773 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3774 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3775 break; 3776 case OPC1_16_SSR_ST_H: 3777 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3778 break; 3779 case OPC1_16_SSR_ST_H_POSTINC: 3780 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3781 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3782 break; 3783 case OPC1_16_SSR_ST_W: 3784 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3785 break; 3786 case OPC1_16_SSR_ST_W_POSTINC: 3787 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3788 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3789 break; 3790 default: 3791 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3792 } 3793 } 3794 3795 static void decode_sc_opc(DisasContext *ctx, int op1) 3796 { 3797 int32_t const16; 3798 3799 const16 = MASK_OP_SC_CONST8(ctx->opcode); 3800 3801 switch (op1) { 3802 case OPC1_16_SC_AND: 3803 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3804 break; 3805 case OPC1_16_SC_BISR: 3806 gen_helper_1arg(bisr, const16 & 0xff); 3807 break; 3808 case OPC1_16_SC_LD_A: 3809 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3810 break; 3811 case OPC1_16_SC_LD_W: 3812 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3813 break; 3814 case OPC1_16_SC_MOV: 3815 tcg_gen_movi_tl(cpu_gpr_d[15], const16); 3816 break; 3817 case OPC1_16_SC_OR: 3818 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3819 break; 3820 case OPC1_16_SC_ST_A: 3821 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3822 break; 3823 case OPC1_16_SC_ST_W: 3824 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3825 break; 3826 case OPC1_16_SC_SUB_A: 3827 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); 3828 break; 3829 default: 3830 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3831 } 3832 } 3833 3834 static void decode_slr_opc(DisasContext *ctx, int op1) 3835 { 3836 int r1, r2; 3837 3838 r1 = MASK_OP_SLR_D(ctx->opcode); 3839 r2 = MASK_OP_SLR_S2(ctx->opcode); 3840 3841 switch (op1) { 3842 /* SLR-format */ 3843 case OPC1_16_SLR_LD_A: 3844 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3845 break; 3846 case OPC1_16_SLR_LD_A_POSTINC: 3847 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3848 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3849 break; 3850 case OPC1_16_SLR_LD_BU: 3851 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3852 break; 3853 case OPC1_16_SLR_LD_BU_POSTINC: 3854 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3855 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3856 break; 3857 case OPC1_16_SLR_LD_H: 3858 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3859 break; 3860 case OPC1_16_SLR_LD_H_POSTINC: 3861 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3862 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3863 break; 3864 case OPC1_16_SLR_LD_W: 3865 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3866 break; 3867 case OPC1_16_SLR_LD_W_POSTINC: 3868 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3869 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3870 break; 3871 default: 3872 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3873 } 3874 } 3875 3876 static void decode_sro_opc(DisasContext *ctx, int op1) 3877 { 3878 int r2; 3879 int32_t address; 3880 3881 r2 = MASK_OP_SRO_S2(ctx->opcode); 3882 address = MASK_OP_SRO_OFF4(ctx->opcode); 3883 3884 /* SRO-format */ 3885 switch (op1) { 3886 case OPC1_16_SRO_LD_A: 3887 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3888 break; 3889 case OPC1_16_SRO_LD_BU: 3890 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3891 break; 3892 case OPC1_16_SRO_LD_H: 3893 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW); 3894 break; 3895 case OPC1_16_SRO_LD_W: 3896 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3897 break; 3898 case OPC1_16_SRO_ST_A: 3899 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3900 break; 3901 case OPC1_16_SRO_ST_B: 3902 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3903 break; 3904 case OPC1_16_SRO_ST_H: 3905 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3906 break; 3907 case OPC1_16_SRO_ST_W: 3908 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3909 break; 3910 default: 3911 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3912 } 3913 } 3914 3915 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) 3916 { 3917 uint32_t op2; 3918 op2 = MASK_OP_SR_OP2(ctx->opcode); 3919 3920 switch (op2) { 3921 case OPC2_16_SR_NOP: 3922 break; 3923 case OPC2_16_SR_RET: 3924 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 3925 break; 3926 case OPC2_16_SR_RFE: 3927 gen_helper_rfe(cpu_env); 3928 tcg_gen_exit_tb(0); 3929 ctx->bstate = BS_BRANCH; 3930 break; 3931 case OPC2_16_SR_DEBUG: 3932 /* raise EXCP_DEBUG */ 3933 break; 3934 case OPC2_16_SR_FRET: 3935 gen_fret(ctx); 3936 break; 3937 default: 3938 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3939 } 3940 } 3941 3942 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx) 3943 { 3944 uint32_t op2; 3945 uint32_t r1; 3946 TCGv temp; 3947 3948 r1 = MASK_OP_SR_S1D(ctx->opcode); 3949 op2 = MASK_OP_SR_OP2(ctx->opcode); 3950 3951 switch (op2) { 3952 case OPC2_16_SR_RSUB: 3953 /* overflow only if r1 = -0x80000000 */ 3954 temp = tcg_const_i32(-0x80000000); 3955 /* calc V bit */ 3956 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp); 3957 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 3958 /* calc SV bit */ 3959 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 3960 /* sub */ 3961 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3962 /* calc av */ 3963 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); 3964 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); 3965 /* calc sav */ 3966 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3967 tcg_temp_free(temp); 3968 break; 3969 case OPC2_16_SR_SAT_B: 3970 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); 3971 break; 3972 case OPC2_16_SR_SAT_BU: 3973 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); 3974 break; 3975 case OPC2_16_SR_SAT_H: 3976 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); 3977 break; 3978 case OPC2_16_SR_SAT_HU: 3979 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); 3980 break; 3981 default: 3982 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3983 } 3984 } 3985 3986 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) 3987 { 3988 int op1; 3989 int r1, r2; 3990 int32_t const16; 3991 int32_t address; 3992 TCGv temp; 3993 3994 op1 = MASK_OP_MAJOR(ctx->opcode); 3995 3996 /* handle ADDSC.A opcode only being 6 bit long */ 3997 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { 3998 op1 = OPC1_16_SRRS_ADDSC_A; 3999 } 4000 4001 switch (op1) { 4002 case OPC1_16_SRC_ADD: 4003 case OPC1_16_SRC_ADD_A15: 4004 case OPC1_16_SRC_ADD_15A: 4005 case OPC1_16_SRC_ADD_A: 4006 case OPC1_16_SRC_CADD: 4007 case OPC1_16_SRC_CADDN: 4008 case OPC1_16_SRC_CMOV: 4009 case OPC1_16_SRC_CMOVN: 4010 case OPC1_16_SRC_EQ: 4011 case OPC1_16_SRC_LT: 4012 case OPC1_16_SRC_MOV: 4013 case OPC1_16_SRC_MOV_A: 4014 case OPC1_16_SRC_MOV_E: 4015 case OPC1_16_SRC_SH: 4016 case OPC1_16_SRC_SHA: 4017 decode_src_opc(env, ctx, op1); 4018 break; 4019 /* SRR-format */ 4020 case OPC1_16_SRR_ADD: 4021 case OPC1_16_SRR_ADD_A15: 4022 case OPC1_16_SRR_ADD_15A: 4023 case OPC1_16_SRR_ADD_A: 4024 case OPC1_16_SRR_ADDS: 4025 case OPC1_16_SRR_AND: 4026 case OPC1_16_SRR_CMOV: 4027 case OPC1_16_SRR_CMOVN: 4028 case OPC1_16_SRR_EQ: 4029 case OPC1_16_SRR_LT: 4030 case OPC1_16_SRR_MOV: 4031 case OPC1_16_SRR_MOV_A: 4032 case OPC1_16_SRR_MOV_AA: 4033 case OPC1_16_SRR_MOV_D: 4034 case OPC1_16_SRR_MUL: 4035 case OPC1_16_SRR_OR: 4036 case OPC1_16_SRR_SUB: 4037 case OPC1_16_SRR_SUB_A15B: 4038 case OPC1_16_SRR_SUB_15AB: 4039 case OPC1_16_SRR_SUBS: 4040 case OPC1_16_SRR_XOR: 4041 decode_srr_opc(ctx, op1); 4042 break; 4043 /* SSR-format */ 4044 case OPC1_16_SSR_ST_A: 4045 case OPC1_16_SSR_ST_A_POSTINC: 4046 case OPC1_16_SSR_ST_B: 4047 case OPC1_16_SSR_ST_B_POSTINC: 4048 case OPC1_16_SSR_ST_H: 4049 case OPC1_16_SSR_ST_H_POSTINC: 4050 case OPC1_16_SSR_ST_W: 4051 case OPC1_16_SSR_ST_W_POSTINC: 4052 decode_ssr_opc(ctx, op1); 4053 break; 4054 /* SRRS-format */ 4055 case OPC1_16_SRRS_ADDSC_A: 4056 r2 = MASK_OP_SRRS_S2(ctx->opcode); 4057 r1 = MASK_OP_SRRS_S1D(ctx->opcode); 4058 const16 = MASK_OP_SRRS_N(ctx->opcode); 4059 temp = tcg_temp_new(); 4060 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); 4061 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); 4062 tcg_temp_free(temp); 4063 break; 4064 /* SLRO-format */ 4065 case OPC1_16_SLRO_LD_A: 4066 r1 = MASK_OP_SLRO_D(ctx->opcode); 4067 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4068 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4069 break; 4070 case OPC1_16_SLRO_LD_BU: 4071 r1 = MASK_OP_SLRO_D(ctx->opcode); 4072 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4073 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 4074 break; 4075 case OPC1_16_SLRO_LD_H: 4076 r1 = MASK_OP_SLRO_D(ctx->opcode); 4077 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4078 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 4079 break; 4080 case OPC1_16_SLRO_LD_W: 4081 r1 = MASK_OP_SLRO_D(ctx->opcode); 4082 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4083 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4084 break; 4085 /* SB-format */ 4086 case OPC1_16_SB_CALL: 4087 case OPC1_16_SB_J: 4088 case OPC1_16_SB_JNZ: 4089 case OPC1_16_SB_JZ: 4090 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); 4091 gen_compute_branch(ctx, op1, 0, 0, 0, address); 4092 break; 4093 /* SBC-format */ 4094 case OPC1_16_SBC_JEQ: 4095 case OPC1_16_SBC_JNE: 4096 address = MASK_OP_SBC_DISP4(ctx->opcode); 4097 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 4098 gen_compute_branch(ctx, op1, 0, 0, const16, address); 4099 break; 4100 /* SBRN-format */ 4101 case OPC1_16_SBRN_JNZ_T: 4102 case OPC1_16_SBRN_JZ_T: 4103 address = MASK_OP_SBRN_DISP4(ctx->opcode); 4104 const16 = MASK_OP_SBRN_N(ctx->opcode); 4105 gen_compute_branch(ctx, op1, 0, 0, const16, address); 4106 break; 4107 /* SBR-format */ 4108 case OPC1_16_SBR_JEQ: 4109 case OPC1_16_SBR_JGEZ: 4110 case OPC1_16_SBR_JGTZ: 4111 case OPC1_16_SBR_JLEZ: 4112 case OPC1_16_SBR_JLTZ: 4113 case OPC1_16_SBR_JNE: 4114 case OPC1_16_SBR_JNZ: 4115 case OPC1_16_SBR_JNZ_A: 4116 case OPC1_16_SBR_JZ: 4117 case OPC1_16_SBR_JZ_A: 4118 case OPC1_16_SBR_LOOP: 4119 r1 = MASK_OP_SBR_S2(ctx->opcode); 4120 address = MASK_OP_SBR_DISP4(ctx->opcode); 4121 gen_compute_branch(ctx, op1, r1, 0, 0, address); 4122 break; 4123 /* SC-format */ 4124 case OPC1_16_SC_AND: 4125 case OPC1_16_SC_BISR: 4126 case OPC1_16_SC_LD_A: 4127 case OPC1_16_SC_LD_W: 4128 case OPC1_16_SC_MOV: 4129 case OPC1_16_SC_OR: 4130 case OPC1_16_SC_ST_A: 4131 case OPC1_16_SC_ST_W: 4132 case OPC1_16_SC_SUB_A: 4133 decode_sc_opc(ctx, op1); 4134 break; 4135 /* SLR-format */ 4136 case OPC1_16_SLR_LD_A: 4137 case OPC1_16_SLR_LD_A_POSTINC: 4138 case OPC1_16_SLR_LD_BU: 4139 case OPC1_16_SLR_LD_BU_POSTINC: 4140 case OPC1_16_SLR_LD_H: 4141 case OPC1_16_SLR_LD_H_POSTINC: 4142 case OPC1_16_SLR_LD_W: 4143 case OPC1_16_SLR_LD_W_POSTINC: 4144 decode_slr_opc(ctx, op1); 4145 break; 4146 /* SRO-format */ 4147 case OPC1_16_SRO_LD_A: 4148 case OPC1_16_SRO_LD_BU: 4149 case OPC1_16_SRO_LD_H: 4150 case OPC1_16_SRO_LD_W: 4151 case OPC1_16_SRO_ST_A: 4152 case OPC1_16_SRO_ST_B: 4153 case OPC1_16_SRO_ST_H: 4154 case OPC1_16_SRO_ST_W: 4155 decode_sro_opc(ctx, op1); 4156 break; 4157 /* SSRO-format */ 4158 case OPC1_16_SSRO_ST_A: 4159 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4160 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4161 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4162 break; 4163 case OPC1_16_SSRO_ST_B: 4164 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4165 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4166 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 4167 break; 4168 case OPC1_16_SSRO_ST_H: 4169 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4170 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4171 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 4172 break; 4173 case OPC1_16_SSRO_ST_W: 4174 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4175 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4176 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4177 break; 4178 /* SR-format */ 4179 case OPCM_16_SR_SYSTEM: 4180 decode_sr_system(env, ctx); 4181 break; 4182 case OPCM_16_SR_ACCU: 4183 decode_sr_accu(env, ctx); 4184 break; 4185 case OPC1_16_SR_JI: 4186 r1 = MASK_OP_SR_S1D(ctx->opcode); 4187 gen_compute_branch(ctx, op1, r1, 0, 0, 0); 4188 break; 4189 case OPC1_16_SR_NOT: 4190 r1 = MASK_OP_SR_S1D(ctx->opcode); 4191 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 4192 break; 4193 default: 4194 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4195 } 4196 } 4197 4198 /* 4199 * 32 bit instructions 4200 */ 4201 4202 /* ABS-format */ 4203 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx) 4204 { 4205 int32_t op2; 4206 int32_t r1; 4207 uint32_t address; 4208 TCGv temp; 4209 4210 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4211 address = MASK_OP_ABS_OFF18(ctx->opcode); 4212 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4213 4214 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4215 4216 switch (op2) { 4217 case OPC2_32_ABS_LD_A: 4218 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 4219 break; 4220 case OPC2_32_ABS_LD_D: 4221 CHECK_REG_PAIR(r1); 4222 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4223 break; 4224 case OPC2_32_ABS_LD_DA: 4225 CHECK_REG_PAIR(r1); 4226 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4227 break; 4228 case OPC2_32_ABS_LD_W: 4229 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 4230 break; 4231 default: 4232 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4233 } 4234 4235 tcg_temp_free(temp); 4236 } 4237 4238 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx) 4239 { 4240 int32_t op2; 4241 int32_t r1; 4242 uint32_t address; 4243 TCGv temp; 4244 4245 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4246 address = MASK_OP_ABS_OFF18(ctx->opcode); 4247 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4248 4249 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4250 4251 switch (op2) { 4252 case OPC2_32_ABS_LD_B: 4253 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); 4254 break; 4255 case OPC2_32_ABS_LD_BU: 4256 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 4257 break; 4258 case OPC2_32_ABS_LD_H: 4259 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); 4260 break; 4261 case OPC2_32_ABS_LD_HU: 4262 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 4263 break; 4264 default: 4265 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4266 } 4267 4268 tcg_temp_free(temp); 4269 } 4270 4271 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx) 4272 { 4273 int32_t op2; 4274 int32_t r1; 4275 uint32_t address; 4276 TCGv temp; 4277 4278 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4279 address = MASK_OP_ABS_OFF18(ctx->opcode); 4280 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4281 4282 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4283 4284 switch (op2) { 4285 case OPC2_32_ABS_LDMST: 4286 gen_ldmst(ctx, r1, temp); 4287 break; 4288 case OPC2_32_ABS_SWAP_W: 4289 gen_swap(ctx, r1, temp); 4290 break; 4291 default: 4292 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4293 } 4294 4295 tcg_temp_free(temp); 4296 } 4297 4298 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx) 4299 { 4300 uint32_t op2; 4301 int32_t off18; 4302 4303 off18 = MASK_OP_ABS_OFF18(ctx->opcode); 4304 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4305 4306 switch (op2) { 4307 case OPC2_32_ABS_LDLCX: 4308 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); 4309 break; 4310 case OPC2_32_ABS_LDUCX: 4311 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); 4312 break; 4313 case OPC2_32_ABS_STLCX: 4314 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); 4315 break; 4316 case OPC2_32_ABS_STUCX: 4317 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); 4318 break; 4319 default: 4320 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4321 } 4322 } 4323 4324 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx) 4325 { 4326 int32_t op2; 4327 int32_t r1; 4328 uint32_t address; 4329 TCGv temp; 4330 4331 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4332 address = MASK_OP_ABS_OFF18(ctx->opcode); 4333 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4334 4335 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4336 4337 switch (op2) { 4338 case OPC2_32_ABS_ST_A: 4339 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 4340 break; 4341 case OPC2_32_ABS_ST_D: 4342 CHECK_REG_PAIR(r1); 4343 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4344 break; 4345 case OPC2_32_ABS_ST_DA: 4346 CHECK_REG_PAIR(r1); 4347 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4348 break; 4349 case OPC2_32_ABS_ST_W: 4350 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 4351 break; 4352 default: 4353 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4354 } 4355 tcg_temp_free(temp); 4356 } 4357 4358 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx) 4359 { 4360 int32_t op2; 4361 int32_t r1; 4362 uint32_t address; 4363 TCGv temp; 4364 4365 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4366 address = MASK_OP_ABS_OFF18(ctx->opcode); 4367 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4368 4369 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4370 4371 switch (op2) { 4372 case OPC2_32_ABS_ST_B: 4373 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 4374 break; 4375 case OPC2_32_ABS_ST_H: 4376 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 4377 break; 4378 default: 4379 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4380 } 4381 tcg_temp_free(temp); 4382 } 4383 4384 /* Bit-format */ 4385 4386 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx) 4387 { 4388 uint32_t op2; 4389 int r1, r2, r3; 4390 int pos1, pos2; 4391 4392 r1 = MASK_OP_BIT_S1(ctx->opcode); 4393 r2 = MASK_OP_BIT_S2(ctx->opcode); 4394 r3 = MASK_OP_BIT_D(ctx->opcode); 4395 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4396 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4397 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4398 4399 4400 switch (op2) { 4401 case OPC2_32_BIT_AND_AND_T: 4402 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4403 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); 4404 break; 4405 case OPC2_32_BIT_AND_ANDN_T: 4406 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4407 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); 4408 break; 4409 case OPC2_32_BIT_AND_NOR_T: 4410 if (TCG_TARGET_HAS_andc_i32) { 4411 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4412 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); 4413 } else { 4414 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4415 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); 4416 } 4417 break; 4418 case OPC2_32_BIT_AND_OR_T: 4419 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4420 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); 4421 break; 4422 default: 4423 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4424 } 4425 } 4426 4427 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx) 4428 { 4429 uint32_t op2; 4430 int r1, r2, r3; 4431 int pos1, pos2; 4432 r1 = MASK_OP_BIT_S1(ctx->opcode); 4433 r2 = MASK_OP_BIT_S2(ctx->opcode); 4434 r3 = MASK_OP_BIT_D(ctx->opcode); 4435 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4436 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4437 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4438 4439 switch (op2) { 4440 case OPC2_32_BIT_AND_T: 4441 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4442 pos1, pos2, &tcg_gen_and_tl); 4443 break; 4444 case OPC2_32_BIT_ANDN_T: 4445 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4446 pos1, pos2, &tcg_gen_andc_tl); 4447 break; 4448 case OPC2_32_BIT_NOR_T: 4449 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4450 pos1, pos2, &tcg_gen_nor_tl); 4451 break; 4452 case OPC2_32_BIT_OR_T: 4453 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4454 pos1, pos2, &tcg_gen_or_tl); 4455 break; 4456 default: 4457 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4458 } 4459 } 4460 4461 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx) 4462 { 4463 uint32_t op2; 4464 int r1, r2, r3; 4465 int pos1, pos2; 4466 TCGv temp; 4467 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4468 r1 = MASK_OP_BIT_S1(ctx->opcode); 4469 r2 = MASK_OP_BIT_S2(ctx->opcode); 4470 r3 = MASK_OP_BIT_D(ctx->opcode); 4471 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4472 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4473 4474 temp = tcg_temp_new(); 4475 4476 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); 4477 if (op2 == OPC2_32_BIT_INSN_T) { 4478 tcg_gen_not_tl(temp, temp); 4479 } 4480 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); 4481 tcg_temp_free(temp); 4482 } 4483 4484 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx) 4485 { 4486 uint32_t op2; 4487 4488 int r1, r2, r3; 4489 int pos1, pos2; 4490 4491 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4492 r1 = MASK_OP_BIT_S1(ctx->opcode); 4493 r2 = MASK_OP_BIT_S2(ctx->opcode); 4494 r3 = MASK_OP_BIT_D(ctx->opcode); 4495 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4496 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4497 4498 switch (op2) { 4499 case OPC2_32_BIT_NAND_T: 4500 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4501 pos1, pos2, &tcg_gen_nand_tl); 4502 break; 4503 case OPC2_32_BIT_ORN_T: 4504 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4505 pos1, pos2, &tcg_gen_orc_tl); 4506 break; 4507 case OPC2_32_BIT_XNOR_T: 4508 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4509 pos1, pos2, &tcg_gen_eqv_tl); 4510 break; 4511 case OPC2_32_BIT_XOR_T: 4512 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4513 pos1, pos2, &tcg_gen_xor_tl); 4514 break; 4515 default: 4516 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4517 } 4518 } 4519 4520 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx) 4521 { 4522 uint32_t op2; 4523 4524 int r1, r2, r3; 4525 int pos1, pos2; 4526 4527 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4528 r1 = MASK_OP_BIT_S1(ctx->opcode); 4529 r2 = MASK_OP_BIT_S2(ctx->opcode); 4530 r3 = MASK_OP_BIT_D(ctx->opcode); 4531 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4532 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4533 4534 switch (op2) { 4535 case OPC2_32_BIT_OR_AND_T: 4536 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4537 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); 4538 break; 4539 case OPC2_32_BIT_OR_ANDN_T: 4540 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4541 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); 4542 break; 4543 case OPC2_32_BIT_OR_NOR_T: 4544 if (TCG_TARGET_HAS_orc_i32) { 4545 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4546 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); 4547 } else { 4548 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4549 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); 4550 } 4551 break; 4552 case OPC2_32_BIT_OR_OR_T: 4553 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4554 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); 4555 break; 4556 default: 4557 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4558 } 4559 } 4560 4561 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx) 4562 { 4563 uint32_t op2; 4564 int r1, r2, r3; 4565 int pos1, pos2; 4566 TCGv temp; 4567 4568 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4569 r1 = MASK_OP_BIT_S1(ctx->opcode); 4570 r2 = MASK_OP_BIT_S2(ctx->opcode); 4571 r3 = MASK_OP_BIT_D(ctx->opcode); 4572 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4573 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4574 4575 temp = tcg_temp_new(); 4576 4577 switch (op2) { 4578 case OPC2_32_BIT_SH_AND_T: 4579 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4580 pos1, pos2, &tcg_gen_and_tl); 4581 break; 4582 case OPC2_32_BIT_SH_ANDN_T: 4583 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4584 pos1, pos2, &tcg_gen_andc_tl); 4585 break; 4586 case OPC2_32_BIT_SH_NOR_T: 4587 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4588 pos1, pos2, &tcg_gen_nor_tl); 4589 break; 4590 case OPC2_32_BIT_SH_OR_T: 4591 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4592 pos1, pos2, &tcg_gen_or_tl); 4593 break; 4594 default: 4595 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4596 } 4597 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4598 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4599 tcg_temp_free(temp); 4600 } 4601 4602 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx) 4603 { 4604 uint32_t op2; 4605 int r1, r2, r3; 4606 int pos1, pos2; 4607 TCGv temp; 4608 4609 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4610 r1 = MASK_OP_BIT_S1(ctx->opcode); 4611 r2 = MASK_OP_BIT_S2(ctx->opcode); 4612 r3 = MASK_OP_BIT_D(ctx->opcode); 4613 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4614 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4615 4616 temp = tcg_temp_new(); 4617 4618 switch (op2) { 4619 case OPC2_32_BIT_SH_NAND_T: 4620 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , 4621 pos1, pos2, &tcg_gen_nand_tl); 4622 break; 4623 case OPC2_32_BIT_SH_ORN_T: 4624 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4625 pos1, pos2, &tcg_gen_orc_tl); 4626 break; 4627 case OPC2_32_BIT_SH_XNOR_T: 4628 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4629 pos1, pos2, &tcg_gen_eqv_tl); 4630 break; 4631 case OPC2_32_BIT_SH_XOR_T: 4632 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4633 pos1, pos2, &tcg_gen_xor_tl); 4634 break; 4635 default: 4636 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4637 } 4638 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4639 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4640 tcg_temp_free(temp); 4641 } 4642 4643 /* BO-format */ 4644 4645 4646 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, 4647 DisasContext *ctx) 4648 { 4649 uint32_t op2; 4650 uint32_t off10; 4651 int32_t r1, r2; 4652 TCGv temp; 4653 4654 r1 = MASK_OP_BO_S1D(ctx->opcode); 4655 r2 = MASK_OP_BO_S2(ctx->opcode); 4656 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4657 op2 = MASK_OP_BO_OP2(ctx->opcode); 4658 4659 switch (op2) { 4660 case OPC2_32_BO_CACHEA_WI_SHORTOFF: 4661 case OPC2_32_BO_CACHEA_W_SHORTOFF: 4662 case OPC2_32_BO_CACHEA_I_SHORTOFF: 4663 /* instruction to access the cache */ 4664 break; 4665 case OPC2_32_BO_CACHEA_WI_POSTINC: 4666 case OPC2_32_BO_CACHEA_W_POSTINC: 4667 case OPC2_32_BO_CACHEA_I_POSTINC: 4668 /* instruction to access the cache, but we still need to handle 4669 the addressing mode */ 4670 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4671 break; 4672 case OPC2_32_BO_CACHEA_WI_PREINC: 4673 case OPC2_32_BO_CACHEA_W_PREINC: 4674 case OPC2_32_BO_CACHEA_I_PREINC: 4675 /* instruction to access the cache, but we still need to handle 4676 the addressing mode */ 4677 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4678 break; 4679 case OPC2_32_BO_CACHEI_WI_SHORTOFF: 4680 case OPC2_32_BO_CACHEI_W_SHORTOFF: 4681 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 4682 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4683 } 4684 break; 4685 case OPC2_32_BO_CACHEI_W_POSTINC: 4686 case OPC2_32_BO_CACHEI_WI_POSTINC: 4687 if (tricore_feature(env, TRICORE_FEATURE_131)) { 4688 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4689 } else { 4690 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4691 } 4692 break; 4693 case OPC2_32_BO_CACHEI_W_PREINC: 4694 case OPC2_32_BO_CACHEI_WI_PREINC: 4695 if (tricore_feature(env, TRICORE_FEATURE_131)) { 4696 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4697 } else { 4698 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4699 } 4700 break; 4701 case OPC2_32_BO_ST_A_SHORTOFF: 4702 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4703 break; 4704 case OPC2_32_BO_ST_A_POSTINC: 4705 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4706 MO_LESL); 4707 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4708 break; 4709 case OPC2_32_BO_ST_A_PREINC: 4710 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4711 break; 4712 case OPC2_32_BO_ST_B_SHORTOFF: 4713 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4714 break; 4715 case OPC2_32_BO_ST_B_POSTINC: 4716 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4717 MO_UB); 4718 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4719 break; 4720 case OPC2_32_BO_ST_B_PREINC: 4721 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4722 break; 4723 case OPC2_32_BO_ST_D_SHORTOFF: 4724 CHECK_REG_PAIR(r1); 4725 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4726 off10, ctx); 4727 break; 4728 case OPC2_32_BO_ST_D_POSTINC: 4729 CHECK_REG_PAIR(r1); 4730 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4731 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4732 break; 4733 case OPC2_32_BO_ST_D_PREINC: 4734 CHECK_REG_PAIR(r1); 4735 temp = tcg_temp_new(); 4736 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4737 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4738 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4739 tcg_temp_free(temp); 4740 break; 4741 case OPC2_32_BO_ST_DA_SHORTOFF: 4742 CHECK_REG_PAIR(r1); 4743 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4744 off10, ctx); 4745 break; 4746 case OPC2_32_BO_ST_DA_POSTINC: 4747 CHECK_REG_PAIR(r1); 4748 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4749 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4750 break; 4751 case OPC2_32_BO_ST_DA_PREINC: 4752 CHECK_REG_PAIR(r1); 4753 temp = tcg_temp_new(); 4754 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4755 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4756 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4757 tcg_temp_free(temp); 4758 break; 4759 case OPC2_32_BO_ST_H_SHORTOFF: 4760 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4761 break; 4762 case OPC2_32_BO_ST_H_POSTINC: 4763 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4764 MO_LEUW); 4765 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4766 break; 4767 case OPC2_32_BO_ST_H_PREINC: 4768 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4769 break; 4770 case OPC2_32_BO_ST_Q_SHORTOFF: 4771 temp = tcg_temp_new(); 4772 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4773 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4774 tcg_temp_free(temp); 4775 break; 4776 case OPC2_32_BO_ST_Q_POSTINC: 4777 temp = tcg_temp_new(); 4778 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4779 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, 4780 MO_LEUW); 4781 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4782 tcg_temp_free(temp); 4783 break; 4784 case OPC2_32_BO_ST_Q_PREINC: 4785 temp = tcg_temp_new(); 4786 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4787 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4788 tcg_temp_free(temp); 4789 break; 4790 case OPC2_32_BO_ST_W_SHORTOFF: 4791 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4792 break; 4793 case OPC2_32_BO_ST_W_POSTINC: 4794 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4795 MO_LEUL); 4796 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4797 break; 4798 case OPC2_32_BO_ST_W_PREINC: 4799 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4800 break; 4801 default: 4802 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4803 } 4804 } 4805 4806 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env, 4807 DisasContext *ctx) 4808 { 4809 uint32_t op2; 4810 uint32_t off10; 4811 int32_t r1, r2; 4812 TCGv temp, temp2, temp3; 4813 4814 r1 = MASK_OP_BO_S1D(ctx->opcode); 4815 r2 = MASK_OP_BO_S2(ctx->opcode); 4816 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4817 op2 = MASK_OP_BO_OP2(ctx->opcode); 4818 4819 temp = tcg_temp_new(); 4820 temp2 = tcg_temp_new(); 4821 temp3 = tcg_const_i32(off10); 4822 CHECK_REG_PAIR(r2); 4823 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4824 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4825 4826 switch (op2) { 4827 case OPC2_32_BO_CACHEA_WI_BR: 4828 case OPC2_32_BO_CACHEA_W_BR: 4829 case OPC2_32_BO_CACHEA_I_BR: 4830 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4831 break; 4832 case OPC2_32_BO_CACHEA_WI_CIRC: 4833 case OPC2_32_BO_CACHEA_W_CIRC: 4834 case OPC2_32_BO_CACHEA_I_CIRC: 4835 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4836 break; 4837 case OPC2_32_BO_ST_A_BR: 4838 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4839 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4840 break; 4841 case OPC2_32_BO_ST_A_CIRC: 4842 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4843 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4844 break; 4845 case OPC2_32_BO_ST_B_BR: 4846 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4847 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4848 break; 4849 case OPC2_32_BO_ST_B_CIRC: 4850 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4851 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4852 break; 4853 case OPC2_32_BO_ST_D_BR: 4854 CHECK_REG_PAIR(r1); 4855 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4856 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4857 break; 4858 case OPC2_32_BO_ST_D_CIRC: 4859 CHECK_REG_PAIR(r1); 4860 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4861 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4862 tcg_gen_addi_tl(temp, temp, 4); 4863 tcg_gen_rem_tl(temp, temp, temp2); 4864 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4865 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4866 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4867 break; 4868 case OPC2_32_BO_ST_DA_BR: 4869 CHECK_REG_PAIR(r1); 4870 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4871 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4872 break; 4873 case OPC2_32_BO_ST_DA_CIRC: 4874 CHECK_REG_PAIR(r1); 4875 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4876 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4877 tcg_gen_addi_tl(temp, temp, 4); 4878 tcg_gen_rem_tl(temp, temp, temp2); 4879 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4880 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4881 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4882 break; 4883 case OPC2_32_BO_ST_H_BR: 4884 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4885 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4886 break; 4887 case OPC2_32_BO_ST_H_CIRC: 4888 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4889 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4890 break; 4891 case OPC2_32_BO_ST_Q_BR: 4892 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4893 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4894 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4895 break; 4896 case OPC2_32_BO_ST_Q_CIRC: 4897 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4898 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4899 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4900 break; 4901 case OPC2_32_BO_ST_W_BR: 4902 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4903 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4904 break; 4905 case OPC2_32_BO_ST_W_CIRC: 4906 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4907 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4908 break; 4909 default: 4910 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4911 } 4912 tcg_temp_free(temp); 4913 tcg_temp_free(temp2); 4914 tcg_temp_free(temp3); 4915 } 4916 4917 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env, 4918 DisasContext *ctx) 4919 { 4920 uint32_t op2; 4921 uint32_t off10; 4922 int32_t r1, r2; 4923 TCGv temp; 4924 4925 r1 = MASK_OP_BO_S1D(ctx->opcode); 4926 r2 = MASK_OP_BO_S2(ctx->opcode); 4927 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4928 op2 = MASK_OP_BO_OP2(ctx->opcode); 4929 4930 switch (op2) { 4931 case OPC2_32_BO_LD_A_SHORTOFF: 4932 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4933 break; 4934 case OPC2_32_BO_LD_A_POSTINC: 4935 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4936 MO_LEUL); 4937 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4938 break; 4939 case OPC2_32_BO_LD_A_PREINC: 4940 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4941 break; 4942 case OPC2_32_BO_LD_B_SHORTOFF: 4943 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4944 break; 4945 case OPC2_32_BO_LD_B_POSTINC: 4946 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4947 MO_SB); 4948 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4949 break; 4950 case OPC2_32_BO_LD_B_PREINC: 4951 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4952 break; 4953 case OPC2_32_BO_LD_BU_SHORTOFF: 4954 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4955 break; 4956 case OPC2_32_BO_LD_BU_POSTINC: 4957 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4958 MO_UB); 4959 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4960 break; 4961 case OPC2_32_BO_LD_BU_PREINC: 4962 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4963 break; 4964 case OPC2_32_BO_LD_D_SHORTOFF: 4965 CHECK_REG_PAIR(r1); 4966 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4967 off10, ctx); 4968 break; 4969 case OPC2_32_BO_LD_D_POSTINC: 4970 CHECK_REG_PAIR(r1); 4971 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4972 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4973 break; 4974 case OPC2_32_BO_LD_D_PREINC: 4975 CHECK_REG_PAIR(r1); 4976 temp = tcg_temp_new(); 4977 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4978 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4979 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4980 tcg_temp_free(temp); 4981 break; 4982 case OPC2_32_BO_LD_DA_SHORTOFF: 4983 CHECK_REG_PAIR(r1); 4984 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4985 off10, ctx); 4986 break; 4987 case OPC2_32_BO_LD_DA_POSTINC: 4988 CHECK_REG_PAIR(r1); 4989 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4990 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4991 break; 4992 case OPC2_32_BO_LD_DA_PREINC: 4993 CHECK_REG_PAIR(r1); 4994 temp = tcg_temp_new(); 4995 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4996 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4997 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4998 tcg_temp_free(temp); 4999 break; 5000 case OPC2_32_BO_LD_H_SHORTOFF: 5001 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 5002 break; 5003 case OPC2_32_BO_LD_H_POSTINC: 5004 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5005 MO_LESW); 5006 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5007 break; 5008 case OPC2_32_BO_LD_H_PREINC: 5009 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 5010 break; 5011 case OPC2_32_BO_LD_HU_SHORTOFF: 5012 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5013 break; 5014 case OPC2_32_BO_LD_HU_POSTINC: 5015 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5016 MO_LEUW); 5017 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5018 break; 5019 case OPC2_32_BO_LD_HU_PREINC: 5020 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5021 break; 5022 case OPC2_32_BO_LD_Q_SHORTOFF: 5023 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5024 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5025 break; 5026 case OPC2_32_BO_LD_Q_POSTINC: 5027 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5028 MO_LEUW); 5029 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5030 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5031 break; 5032 case OPC2_32_BO_LD_Q_PREINC: 5033 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5034 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5035 break; 5036 case OPC2_32_BO_LD_W_SHORTOFF: 5037 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 5038 break; 5039 case OPC2_32_BO_LD_W_POSTINC: 5040 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5041 MO_LEUL); 5042 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5043 break; 5044 case OPC2_32_BO_LD_W_PREINC: 5045 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 5046 break; 5047 default: 5048 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5049 } 5050 } 5051 5052 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env, 5053 DisasContext *ctx) 5054 { 5055 uint32_t op2; 5056 uint32_t off10; 5057 int r1, r2; 5058 5059 TCGv temp, temp2, temp3; 5060 5061 r1 = MASK_OP_BO_S1D(ctx->opcode); 5062 r2 = MASK_OP_BO_S2(ctx->opcode); 5063 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 5064 op2 = MASK_OP_BO_OP2(ctx->opcode); 5065 5066 temp = tcg_temp_new(); 5067 temp2 = tcg_temp_new(); 5068 temp3 = tcg_const_i32(off10); 5069 CHECK_REG_PAIR(r2); 5070 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 5071 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5072 5073 5074 switch (op2) { 5075 case OPC2_32_BO_LD_A_BR: 5076 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 5077 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5078 break; 5079 case OPC2_32_BO_LD_A_CIRC: 5080 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 5081 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5082 break; 5083 case OPC2_32_BO_LD_B_BR: 5084 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 5085 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5086 break; 5087 case OPC2_32_BO_LD_B_CIRC: 5088 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 5089 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5090 break; 5091 case OPC2_32_BO_LD_BU_BR: 5092 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 5093 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5094 break; 5095 case OPC2_32_BO_LD_BU_CIRC: 5096 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 5097 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5098 break; 5099 case OPC2_32_BO_LD_D_BR: 5100 CHECK_REG_PAIR(r1); 5101 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 5102 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5103 break; 5104 case OPC2_32_BO_LD_D_CIRC: 5105 CHECK_REG_PAIR(r1); 5106 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 5107 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 5108 tcg_gen_addi_tl(temp, temp, 4); 5109 tcg_gen_rem_tl(temp, temp, temp2); 5110 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5111 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 5112 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5113 break; 5114 case OPC2_32_BO_LD_DA_BR: 5115 CHECK_REG_PAIR(r1); 5116 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 5117 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5118 break; 5119 case OPC2_32_BO_LD_DA_CIRC: 5120 CHECK_REG_PAIR(r1); 5121 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 5122 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 5123 tcg_gen_addi_tl(temp, temp, 4); 5124 tcg_gen_rem_tl(temp, temp, temp2); 5125 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5126 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 5127 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5128 break; 5129 case OPC2_32_BO_LD_H_BR: 5130 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 5131 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5132 break; 5133 case OPC2_32_BO_LD_H_CIRC: 5134 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 5135 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5136 break; 5137 case OPC2_32_BO_LD_HU_BR: 5138 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5139 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5140 break; 5141 case OPC2_32_BO_LD_HU_CIRC: 5142 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5143 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5144 break; 5145 case OPC2_32_BO_LD_Q_BR: 5146 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5147 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5148 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5149 break; 5150 case OPC2_32_BO_LD_Q_CIRC: 5151 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5152 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5153 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5154 break; 5155 case OPC2_32_BO_LD_W_BR: 5156 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 5157 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5158 break; 5159 case OPC2_32_BO_LD_W_CIRC: 5160 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 5161 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5162 break; 5163 default: 5164 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5165 } 5166 tcg_temp_free(temp); 5167 tcg_temp_free(temp2); 5168 tcg_temp_free(temp3); 5169 } 5170 5171 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env, 5172 DisasContext *ctx) 5173 { 5174 uint32_t op2; 5175 uint32_t off10; 5176 int r1, r2; 5177 5178 TCGv temp, temp2; 5179 5180 r1 = MASK_OP_BO_S1D(ctx->opcode); 5181 r2 = MASK_OP_BO_S2(ctx->opcode); 5182 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 5183 op2 = MASK_OP_BO_OP2(ctx->opcode); 5184 5185 5186 temp = tcg_temp_new(); 5187 temp2 = tcg_temp_new(); 5188 5189 switch (op2) { 5190 case OPC2_32_BO_LDLCX_SHORTOFF: 5191 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5192 gen_helper_ldlcx(cpu_env, temp); 5193 break; 5194 case OPC2_32_BO_LDMST_SHORTOFF: 5195 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5196 gen_ldmst(ctx, r1, temp); 5197 break; 5198 case OPC2_32_BO_LDMST_POSTINC: 5199 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 5200 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5201 break; 5202 case OPC2_32_BO_LDMST_PREINC: 5203 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5204 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 5205 break; 5206 case OPC2_32_BO_LDUCX_SHORTOFF: 5207 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5208 gen_helper_lducx(cpu_env, temp); 5209 break; 5210 case OPC2_32_BO_LEA_SHORTOFF: 5211 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); 5212 break; 5213 case OPC2_32_BO_STLCX_SHORTOFF: 5214 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5215 gen_helper_stlcx(cpu_env, temp); 5216 break; 5217 case OPC2_32_BO_STUCX_SHORTOFF: 5218 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5219 gen_helper_stucx(cpu_env, temp); 5220 break; 5221 case OPC2_32_BO_SWAP_W_SHORTOFF: 5222 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5223 gen_swap(ctx, r1, temp); 5224 break; 5225 case OPC2_32_BO_SWAP_W_POSTINC: 5226 gen_swap(ctx, r1, cpu_gpr_a[r2]); 5227 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5228 break; 5229 case OPC2_32_BO_SWAP_W_PREINC: 5230 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5231 gen_swap(ctx, r1, cpu_gpr_a[r2]); 5232 break; 5233 case OPC2_32_BO_CMPSWAP_W_SHORTOFF: 5234 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5235 gen_cmpswap(ctx, r1, temp); 5236 break; 5237 case OPC2_32_BO_CMPSWAP_W_POSTINC: 5238 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 5239 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5240 break; 5241 case OPC2_32_BO_CMPSWAP_W_PREINC: 5242 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5243 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 5244 break; 5245 case OPC2_32_BO_SWAPMSK_W_SHORTOFF: 5246 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5247 gen_swapmsk(ctx, r1, temp); 5248 break; 5249 case OPC2_32_BO_SWAPMSK_W_POSTINC: 5250 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 5251 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5252 break; 5253 case OPC2_32_BO_SWAPMSK_W_PREINC: 5254 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5255 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 5256 break; 5257 default: 5258 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5259 } 5260 tcg_temp_free(temp); 5261 tcg_temp_free(temp2); 5262 } 5263 5264 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env, 5265 DisasContext *ctx) 5266 { 5267 uint32_t op2; 5268 uint32_t off10; 5269 int r1, r2; 5270 5271 TCGv temp, temp2, temp3; 5272 5273 r1 = MASK_OP_BO_S1D(ctx->opcode); 5274 r2 = MASK_OP_BO_S2(ctx->opcode); 5275 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 5276 op2 = MASK_OP_BO_OP2(ctx->opcode); 5277 5278 temp = tcg_temp_new(); 5279 temp2 = tcg_temp_new(); 5280 temp3 = tcg_const_i32(off10); 5281 CHECK_REG_PAIR(r2); 5282 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 5283 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5284 5285 switch (op2) { 5286 case OPC2_32_BO_LDMST_BR: 5287 gen_ldmst(ctx, r1, temp2); 5288 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5289 break; 5290 case OPC2_32_BO_LDMST_CIRC: 5291 gen_ldmst(ctx, r1, temp2); 5292 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5293 break; 5294 case OPC2_32_BO_SWAP_W_BR: 5295 gen_swap(ctx, r1, temp2); 5296 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5297 break; 5298 case OPC2_32_BO_SWAP_W_CIRC: 5299 gen_swap(ctx, r1, temp2); 5300 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5301 break; 5302 case OPC2_32_BO_CMPSWAP_W_BR: 5303 gen_cmpswap(ctx, r1, temp2); 5304 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5305 break; 5306 case OPC2_32_BO_CMPSWAP_W_CIRC: 5307 gen_cmpswap(ctx, r1, temp2); 5308 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5309 break; 5310 case OPC2_32_BO_SWAPMSK_W_BR: 5311 gen_swapmsk(ctx, r1, temp2); 5312 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5313 break; 5314 case OPC2_32_BO_SWAPMSK_W_CIRC: 5315 gen_swapmsk(ctx, r1, temp2); 5316 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5317 break; 5318 default: 5319 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5320 } 5321 5322 tcg_temp_free(temp); 5323 tcg_temp_free(temp2); 5324 tcg_temp_free(temp3); 5325 } 5326 5327 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) 5328 { 5329 int r1, r2; 5330 int32_t address; 5331 TCGv temp; 5332 5333 r1 = MASK_OP_BOL_S1D(ctx->opcode); 5334 r2 = MASK_OP_BOL_S2(ctx->opcode); 5335 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); 5336 5337 switch (op1) { 5338 case OPC1_32_BOL_LD_A_LONGOFF: 5339 temp = tcg_temp_new(); 5340 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 5341 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); 5342 tcg_temp_free(temp); 5343 break; 5344 case OPC1_32_BOL_LD_W_LONGOFF: 5345 temp = tcg_temp_new(); 5346 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 5347 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); 5348 tcg_temp_free(temp); 5349 break; 5350 case OPC1_32_BOL_LEA_LONGOFF: 5351 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); 5352 break; 5353 case OPC1_32_BOL_ST_A_LONGOFF: 5354 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5355 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); 5356 } else { 5357 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5358 } 5359 break; 5360 case OPC1_32_BOL_ST_W_LONGOFF: 5361 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); 5362 break; 5363 case OPC1_32_BOL_LD_B_LONGOFF: 5364 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5365 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 5366 } else { 5367 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5368 } 5369 break; 5370 case OPC1_32_BOL_LD_BU_LONGOFF: 5371 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5372 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); 5373 } else { 5374 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5375 } 5376 break; 5377 case OPC1_32_BOL_LD_H_LONGOFF: 5378 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5379 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 5380 } else { 5381 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5382 } 5383 break; 5384 case OPC1_32_BOL_LD_HU_LONGOFF: 5385 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5386 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); 5387 } else { 5388 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5389 } 5390 break; 5391 case OPC1_32_BOL_ST_B_LONGOFF: 5392 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5393 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 5394 } else { 5395 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5396 } 5397 break; 5398 case OPC1_32_BOL_ST_H_LONGOFF: 5399 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5400 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 5401 } else { 5402 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5403 } 5404 break; 5405 default: 5406 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5407 } 5408 } 5409 5410 /* RC format */ 5411 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx) 5412 { 5413 uint32_t op2; 5414 int r1, r2; 5415 int32_t const9; 5416 TCGv temp; 5417 5418 r2 = MASK_OP_RC_D(ctx->opcode); 5419 r1 = MASK_OP_RC_S1(ctx->opcode); 5420 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5421 op2 = MASK_OP_RC_OP2(ctx->opcode); 5422 5423 temp = tcg_temp_new(); 5424 5425 switch (op2) { 5426 case OPC2_32_RC_AND: 5427 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5428 break; 5429 case OPC2_32_RC_ANDN: 5430 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 5431 break; 5432 case OPC2_32_RC_NAND: 5433 tcg_gen_movi_tl(temp, const9); 5434 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5435 break; 5436 case OPC2_32_RC_NOR: 5437 tcg_gen_movi_tl(temp, const9); 5438 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5439 break; 5440 case OPC2_32_RC_OR: 5441 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5442 break; 5443 case OPC2_32_RC_ORN: 5444 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 5445 break; 5446 case OPC2_32_RC_SH: 5447 const9 = sextract32(const9, 0, 6); 5448 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5449 break; 5450 case OPC2_32_RC_SH_H: 5451 const9 = sextract32(const9, 0, 5); 5452 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5453 break; 5454 case OPC2_32_RC_SHA: 5455 const9 = sextract32(const9, 0, 6); 5456 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5457 break; 5458 case OPC2_32_RC_SHA_H: 5459 const9 = sextract32(const9, 0, 5); 5460 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5461 break; 5462 case OPC2_32_RC_SHAS: 5463 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5464 break; 5465 case OPC2_32_RC_XNOR: 5466 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5467 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); 5468 break; 5469 case OPC2_32_RC_XOR: 5470 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5471 break; 5472 default: 5473 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5474 } 5475 tcg_temp_free(temp); 5476 } 5477 5478 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx) 5479 { 5480 uint32_t op2; 5481 int r1, r2; 5482 int16_t const9; 5483 5484 TCGv temp; 5485 5486 r2 = MASK_OP_RC_D(ctx->opcode); 5487 r1 = MASK_OP_RC_S1(ctx->opcode); 5488 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5489 5490 op2 = MASK_OP_RC_OP2(ctx->opcode); 5491 5492 temp = tcg_temp_new(); 5493 5494 switch (op2) { 5495 case OPC2_32_RC_ABSDIF: 5496 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5497 break; 5498 case OPC2_32_RC_ABSDIFS: 5499 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5500 break; 5501 case OPC2_32_RC_ADD: 5502 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5503 break; 5504 case OPC2_32_RC_ADDC: 5505 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5506 break; 5507 case OPC2_32_RC_ADDS: 5508 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5509 break; 5510 case OPC2_32_RC_ADDS_U: 5511 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5512 break; 5513 case OPC2_32_RC_ADDX: 5514 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5515 break; 5516 case OPC2_32_RC_AND_EQ: 5517 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5518 const9, &tcg_gen_and_tl); 5519 break; 5520 case OPC2_32_RC_AND_GE: 5521 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5522 const9, &tcg_gen_and_tl); 5523 break; 5524 case OPC2_32_RC_AND_GE_U: 5525 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5526 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5527 const9, &tcg_gen_and_tl); 5528 break; 5529 case OPC2_32_RC_AND_LT: 5530 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5531 const9, &tcg_gen_and_tl); 5532 break; 5533 case OPC2_32_RC_AND_LT_U: 5534 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5535 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5536 const9, &tcg_gen_and_tl); 5537 break; 5538 case OPC2_32_RC_AND_NE: 5539 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5540 const9, &tcg_gen_and_tl); 5541 break; 5542 case OPC2_32_RC_EQ: 5543 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5544 break; 5545 case OPC2_32_RC_EQANY_B: 5546 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5547 break; 5548 case OPC2_32_RC_EQANY_H: 5549 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5550 break; 5551 case OPC2_32_RC_GE: 5552 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5553 break; 5554 case OPC2_32_RC_GE_U: 5555 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5556 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5557 break; 5558 case OPC2_32_RC_LT: 5559 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5560 break; 5561 case OPC2_32_RC_LT_U: 5562 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5563 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5564 break; 5565 case OPC2_32_RC_MAX: 5566 tcg_gen_movi_tl(temp, const9); 5567 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5568 cpu_gpr_d[r1], temp); 5569 break; 5570 case OPC2_32_RC_MAX_U: 5571 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5572 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5573 cpu_gpr_d[r1], temp); 5574 break; 5575 case OPC2_32_RC_MIN: 5576 tcg_gen_movi_tl(temp, const9); 5577 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5578 cpu_gpr_d[r1], temp); 5579 break; 5580 case OPC2_32_RC_MIN_U: 5581 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5582 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5583 cpu_gpr_d[r1], temp); 5584 break; 5585 case OPC2_32_RC_NE: 5586 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5587 break; 5588 case OPC2_32_RC_OR_EQ: 5589 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5590 const9, &tcg_gen_or_tl); 5591 break; 5592 case OPC2_32_RC_OR_GE: 5593 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5594 const9, &tcg_gen_or_tl); 5595 break; 5596 case OPC2_32_RC_OR_GE_U: 5597 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5598 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5599 const9, &tcg_gen_or_tl); 5600 break; 5601 case OPC2_32_RC_OR_LT: 5602 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5603 const9, &tcg_gen_or_tl); 5604 break; 5605 case OPC2_32_RC_OR_LT_U: 5606 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5607 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5608 const9, &tcg_gen_or_tl); 5609 break; 5610 case OPC2_32_RC_OR_NE: 5611 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5612 const9, &tcg_gen_or_tl); 5613 break; 5614 case OPC2_32_RC_RSUB: 5615 tcg_gen_movi_tl(temp, const9); 5616 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5617 break; 5618 case OPC2_32_RC_RSUBS: 5619 tcg_gen_movi_tl(temp, const9); 5620 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5621 break; 5622 case OPC2_32_RC_RSUBS_U: 5623 tcg_gen_movi_tl(temp, const9); 5624 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5625 break; 5626 case OPC2_32_RC_SH_EQ: 5627 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5628 break; 5629 case OPC2_32_RC_SH_GE: 5630 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5631 break; 5632 case OPC2_32_RC_SH_GE_U: 5633 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5634 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5635 break; 5636 case OPC2_32_RC_SH_LT: 5637 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5638 break; 5639 case OPC2_32_RC_SH_LT_U: 5640 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5641 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5642 break; 5643 case OPC2_32_RC_SH_NE: 5644 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5645 break; 5646 case OPC2_32_RC_XOR_EQ: 5647 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5648 const9, &tcg_gen_xor_tl); 5649 break; 5650 case OPC2_32_RC_XOR_GE: 5651 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5652 const9, &tcg_gen_xor_tl); 5653 break; 5654 case OPC2_32_RC_XOR_GE_U: 5655 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5656 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5657 const9, &tcg_gen_xor_tl); 5658 break; 5659 case OPC2_32_RC_XOR_LT: 5660 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5661 const9, &tcg_gen_xor_tl); 5662 break; 5663 case OPC2_32_RC_XOR_LT_U: 5664 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5665 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5666 const9, &tcg_gen_xor_tl); 5667 break; 5668 case OPC2_32_RC_XOR_NE: 5669 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5670 const9, &tcg_gen_xor_tl); 5671 break; 5672 default: 5673 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5674 } 5675 tcg_temp_free(temp); 5676 } 5677 5678 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx) 5679 { 5680 uint32_t op2; 5681 uint32_t const9; 5682 5683 op2 = MASK_OP_RC_OP2(ctx->opcode); 5684 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5685 5686 switch (op2) { 5687 case OPC2_32_RC_BISR: 5688 gen_helper_1arg(bisr, const9); 5689 break; 5690 case OPC2_32_RC_SYSCALL: 5691 /* TODO: Add exception generation */ 5692 break; 5693 default: 5694 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5695 } 5696 } 5697 5698 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx) 5699 { 5700 uint32_t op2; 5701 int r1, r2; 5702 int16_t const9; 5703 5704 r2 = MASK_OP_RC_D(ctx->opcode); 5705 r1 = MASK_OP_RC_S1(ctx->opcode); 5706 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5707 5708 op2 = MASK_OP_RC_OP2(ctx->opcode); 5709 5710 switch (op2) { 5711 case OPC2_32_RC_MUL_32: 5712 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5713 break; 5714 case OPC2_32_RC_MUL_64: 5715 CHECK_REG_PAIR(r2); 5716 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5717 break; 5718 case OPC2_32_RC_MULS_32: 5719 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5720 break; 5721 case OPC2_32_RC_MUL_U_64: 5722 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5723 CHECK_REG_PAIR(r2); 5724 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5725 break; 5726 case OPC2_32_RC_MULS_U_32: 5727 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5728 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5729 break; 5730 default: 5731 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5732 } 5733 } 5734 5735 /* RCPW format */ 5736 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx) 5737 { 5738 uint32_t op2; 5739 int r1, r2; 5740 int32_t pos, width, const4; 5741 5742 TCGv temp; 5743 5744 op2 = MASK_OP_RCPW_OP2(ctx->opcode); 5745 r1 = MASK_OP_RCPW_S1(ctx->opcode); 5746 r2 = MASK_OP_RCPW_D(ctx->opcode); 5747 const4 = MASK_OP_RCPW_CONST4(ctx->opcode); 5748 width = MASK_OP_RCPW_WIDTH(ctx->opcode); 5749 pos = MASK_OP_RCPW_POS(ctx->opcode); 5750 5751 switch (op2) { 5752 case OPC2_32_RCPW_IMASK: 5753 CHECK_REG_PAIR(r2); 5754 /* if pos + width > 31 undefined result */ 5755 if (pos + width <= 31) { 5756 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); 5757 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); 5758 } 5759 break; 5760 case OPC2_32_RCPW_INSERT: 5761 /* if pos + width > 32 undefined result */ 5762 if (pos + width <= 32) { 5763 temp = tcg_const_i32(const4); 5764 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); 5765 tcg_temp_free(temp); 5766 } 5767 break; 5768 default: 5769 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5770 } 5771 } 5772 5773 /* RCRW format */ 5774 5775 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx) 5776 { 5777 uint32_t op2; 5778 int r1, r3, r4; 5779 int32_t width, const4; 5780 5781 TCGv temp, temp2, temp3; 5782 5783 op2 = MASK_OP_RCRW_OP2(ctx->opcode); 5784 r1 = MASK_OP_RCRW_S1(ctx->opcode); 5785 r3 = MASK_OP_RCRW_S3(ctx->opcode); 5786 r4 = MASK_OP_RCRW_D(ctx->opcode); 5787 width = MASK_OP_RCRW_WIDTH(ctx->opcode); 5788 const4 = MASK_OP_RCRW_CONST4(ctx->opcode); 5789 5790 temp = tcg_temp_new(); 5791 temp2 = tcg_temp_new(); 5792 5793 switch (op2) { 5794 case OPC2_32_RCRW_IMASK: 5795 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); 5796 tcg_gen_movi_tl(temp2, (1 << width) - 1); 5797 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); 5798 tcg_gen_movi_tl(temp2, const4); 5799 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); 5800 break; 5801 case OPC2_32_RCRW_INSERT: 5802 temp3 = tcg_temp_new(); 5803 5804 tcg_gen_movi_tl(temp, width); 5805 tcg_gen_movi_tl(temp2, const4); 5806 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f); 5807 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3); 5808 5809 tcg_temp_free(temp3); 5810 break; 5811 default: 5812 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5813 } 5814 tcg_temp_free(temp); 5815 tcg_temp_free(temp2); 5816 } 5817 5818 /* RCR format */ 5819 5820 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx) 5821 { 5822 uint32_t op2; 5823 int r1, r3, r4; 5824 int32_t const9; 5825 5826 TCGv temp, temp2; 5827 5828 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5829 r1 = MASK_OP_RCR_S1(ctx->opcode); 5830 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5831 r3 = MASK_OP_RCR_S3(ctx->opcode); 5832 r4 = MASK_OP_RCR_D(ctx->opcode); 5833 5834 switch (op2) { 5835 case OPC2_32_RCR_CADD: 5836 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r3], 5837 cpu_gpr_d[r4]); 5838 break; 5839 case OPC2_32_RCR_CADDN: 5840 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r3], 5841 cpu_gpr_d[r4]); 5842 break; 5843 case OPC2_32_RCR_SEL: 5844 temp = tcg_const_i32(0); 5845 temp2 = tcg_const_i32(const9); 5846 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5847 cpu_gpr_d[r1], temp2); 5848 tcg_temp_free(temp); 5849 tcg_temp_free(temp2); 5850 break; 5851 case OPC2_32_RCR_SELN: 5852 temp = tcg_const_i32(0); 5853 temp2 = tcg_const_i32(const9); 5854 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5855 cpu_gpr_d[r1], temp2); 5856 tcg_temp_free(temp); 5857 tcg_temp_free(temp2); 5858 break; 5859 default: 5860 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5861 } 5862 } 5863 5864 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx) 5865 { 5866 uint32_t op2; 5867 int r1, r3, r4; 5868 int32_t const9; 5869 5870 5871 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5872 r1 = MASK_OP_RCR_S1(ctx->opcode); 5873 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5874 r3 = MASK_OP_RCR_S3(ctx->opcode); 5875 r4 = MASK_OP_RCR_D(ctx->opcode); 5876 5877 switch (op2) { 5878 case OPC2_32_RCR_MADD_32: 5879 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5880 break; 5881 case OPC2_32_RCR_MADD_64: 5882 CHECK_REG_PAIR(r4); 5883 CHECK_REG_PAIR(r3); 5884 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5885 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5886 break; 5887 case OPC2_32_RCR_MADDS_32: 5888 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5889 break; 5890 case OPC2_32_RCR_MADDS_64: 5891 CHECK_REG_PAIR(r4); 5892 CHECK_REG_PAIR(r3); 5893 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5894 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5895 break; 5896 case OPC2_32_RCR_MADD_U_64: 5897 CHECK_REG_PAIR(r4); 5898 CHECK_REG_PAIR(r3); 5899 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5900 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5901 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5902 break; 5903 case OPC2_32_RCR_MADDS_U_32: 5904 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5905 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5906 break; 5907 case OPC2_32_RCR_MADDS_U_64: 5908 CHECK_REG_PAIR(r4); 5909 CHECK_REG_PAIR(r3); 5910 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5911 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5912 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5913 break; 5914 default: 5915 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5916 } 5917 } 5918 5919 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx) 5920 { 5921 uint32_t op2; 5922 int r1, r3, r4; 5923 int32_t const9; 5924 5925 5926 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5927 r1 = MASK_OP_RCR_S1(ctx->opcode); 5928 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5929 r3 = MASK_OP_RCR_S3(ctx->opcode); 5930 r4 = MASK_OP_RCR_D(ctx->opcode); 5931 5932 switch (op2) { 5933 case OPC2_32_RCR_MSUB_32: 5934 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5935 break; 5936 case OPC2_32_RCR_MSUB_64: 5937 CHECK_REG_PAIR(r4); 5938 CHECK_REG_PAIR(r3); 5939 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5940 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5941 break; 5942 case OPC2_32_RCR_MSUBS_32: 5943 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5944 break; 5945 case OPC2_32_RCR_MSUBS_64: 5946 CHECK_REG_PAIR(r4); 5947 CHECK_REG_PAIR(r3); 5948 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5949 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5950 break; 5951 case OPC2_32_RCR_MSUB_U_64: 5952 CHECK_REG_PAIR(r4); 5953 CHECK_REG_PAIR(r3); 5954 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5955 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5956 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5957 break; 5958 case OPC2_32_RCR_MSUBS_U_32: 5959 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5960 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5961 break; 5962 case OPC2_32_RCR_MSUBS_U_64: 5963 CHECK_REG_PAIR(r4); 5964 CHECK_REG_PAIR(r3); 5965 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5966 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5967 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5968 break; 5969 default: 5970 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5971 } 5972 } 5973 5974 /* RLC format */ 5975 5976 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, 5977 uint32_t op1) 5978 { 5979 int32_t const16; 5980 int r1, r2; 5981 5982 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); 5983 r1 = MASK_OP_RLC_S1(ctx->opcode); 5984 r2 = MASK_OP_RLC_D(ctx->opcode); 5985 5986 switch (op1) { 5987 case OPC1_32_RLC_ADDI: 5988 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); 5989 break; 5990 case OPC1_32_RLC_ADDIH: 5991 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); 5992 break; 5993 case OPC1_32_RLC_ADDIH_A: 5994 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); 5995 break; 5996 case OPC1_32_RLC_MFCR: 5997 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5998 gen_mfcr(env, cpu_gpr_d[r2], const16); 5999 break; 6000 case OPC1_32_RLC_MOV: 6001 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 6002 break; 6003 case OPC1_32_RLC_MOV_64: 6004 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6005 CHECK_REG_PAIR(r2); 6006 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 6007 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); 6008 } else { 6009 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6010 } 6011 break; 6012 case OPC1_32_RLC_MOV_U: 6013 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 6014 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 6015 break; 6016 case OPC1_32_RLC_MOV_H: 6017 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); 6018 break; 6019 case OPC1_32_RLC_MOVH_A: 6020 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); 6021 break; 6022 case OPC1_32_RLC_MTCR: 6023 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 6024 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16); 6025 break; 6026 default: 6027 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6028 } 6029 } 6030 6031 /* RR format */ 6032 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) 6033 { 6034 uint32_t op2; 6035 int r3, r2, r1; 6036 6037 r3 = MASK_OP_RR_D(ctx->opcode); 6038 r2 = MASK_OP_RR_S2(ctx->opcode); 6039 r1 = MASK_OP_RR_S1(ctx->opcode); 6040 op2 = MASK_OP_RR_OP2(ctx->opcode); 6041 6042 switch (op2) { 6043 case OPC2_32_RR_ABS: 6044 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6045 break; 6046 case OPC2_32_RR_ABS_B: 6047 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6048 break; 6049 case OPC2_32_RR_ABS_H: 6050 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6051 break; 6052 case OPC2_32_RR_ABSDIF: 6053 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6054 break; 6055 case OPC2_32_RR_ABSDIF_B: 6056 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6057 cpu_gpr_d[r2]); 6058 break; 6059 case OPC2_32_RR_ABSDIF_H: 6060 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6061 cpu_gpr_d[r2]); 6062 break; 6063 case OPC2_32_RR_ABSDIFS: 6064 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6065 cpu_gpr_d[r2]); 6066 break; 6067 case OPC2_32_RR_ABSDIFS_H: 6068 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6069 cpu_gpr_d[r2]); 6070 break; 6071 case OPC2_32_RR_ABSS: 6072 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6073 break; 6074 case OPC2_32_RR_ABSS_H: 6075 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6076 break; 6077 case OPC2_32_RR_ADD: 6078 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6079 break; 6080 case OPC2_32_RR_ADD_B: 6081 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6082 break; 6083 case OPC2_32_RR_ADD_H: 6084 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6085 break; 6086 case OPC2_32_RR_ADDC: 6087 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6088 break; 6089 case OPC2_32_RR_ADDS: 6090 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6091 break; 6092 case OPC2_32_RR_ADDS_H: 6093 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6094 cpu_gpr_d[r2]); 6095 break; 6096 case OPC2_32_RR_ADDS_HU: 6097 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6098 cpu_gpr_d[r2]); 6099 break; 6100 case OPC2_32_RR_ADDS_U: 6101 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6102 cpu_gpr_d[r2]); 6103 break; 6104 case OPC2_32_RR_ADDX: 6105 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6106 break; 6107 case OPC2_32_RR_AND_EQ: 6108 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6109 cpu_gpr_d[r2], &tcg_gen_and_tl); 6110 break; 6111 case OPC2_32_RR_AND_GE: 6112 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6113 cpu_gpr_d[r2], &tcg_gen_and_tl); 6114 break; 6115 case OPC2_32_RR_AND_GE_U: 6116 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6117 cpu_gpr_d[r2], &tcg_gen_and_tl); 6118 break; 6119 case OPC2_32_RR_AND_LT: 6120 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6121 cpu_gpr_d[r2], &tcg_gen_and_tl); 6122 break; 6123 case OPC2_32_RR_AND_LT_U: 6124 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6125 cpu_gpr_d[r2], &tcg_gen_and_tl); 6126 break; 6127 case OPC2_32_RR_AND_NE: 6128 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6129 cpu_gpr_d[r2], &tcg_gen_and_tl); 6130 break; 6131 case OPC2_32_RR_EQ: 6132 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6133 cpu_gpr_d[r2]); 6134 break; 6135 case OPC2_32_RR_EQ_B: 6136 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6137 break; 6138 case OPC2_32_RR_EQ_H: 6139 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6140 break; 6141 case OPC2_32_RR_EQ_W: 6142 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6143 break; 6144 case OPC2_32_RR_EQANY_B: 6145 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6146 break; 6147 case OPC2_32_RR_EQANY_H: 6148 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6149 break; 6150 case OPC2_32_RR_GE: 6151 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6152 cpu_gpr_d[r2]); 6153 break; 6154 case OPC2_32_RR_GE_U: 6155 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6156 cpu_gpr_d[r2]); 6157 break; 6158 case OPC2_32_RR_LT: 6159 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6160 cpu_gpr_d[r2]); 6161 break; 6162 case OPC2_32_RR_LT_U: 6163 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6164 cpu_gpr_d[r2]); 6165 break; 6166 case OPC2_32_RR_LT_B: 6167 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6168 break; 6169 case OPC2_32_RR_LT_BU: 6170 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6171 break; 6172 case OPC2_32_RR_LT_H: 6173 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6174 break; 6175 case OPC2_32_RR_LT_HU: 6176 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6177 break; 6178 case OPC2_32_RR_LT_W: 6179 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6180 break; 6181 case OPC2_32_RR_LT_WU: 6182 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6183 break; 6184 case OPC2_32_RR_MAX: 6185 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6186 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6187 break; 6188 case OPC2_32_RR_MAX_U: 6189 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6190 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6191 break; 6192 case OPC2_32_RR_MAX_B: 6193 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6194 break; 6195 case OPC2_32_RR_MAX_BU: 6196 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6197 break; 6198 case OPC2_32_RR_MAX_H: 6199 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6200 break; 6201 case OPC2_32_RR_MAX_HU: 6202 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6203 break; 6204 case OPC2_32_RR_MIN: 6205 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6206 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6207 break; 6208 case OPC2_32_RR_MIN_U: 6209 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6210 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6211 break; 6212 case OPC2_32_RR_MIN_B: 6213 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6214 break; 6215 case OPC2_32_RR_MIN_BU: 6216 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6217 break; 6218 case OPC2_32_RR_MIN_H: 6219 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6220 break; 6221 case OPC2_32_RR_MIN_HU: 6222 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6223 break; 6224 case OPC2_32_RR_MOV: 6225 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6226 break; 6227 case OPC2_32_RR_NE: 6228 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6229 cpu_gpr_d[r2]); 6230 break; 6231 case OPC2_32_RR_OR_EQ: 6232 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6233 cpu_gpr_d[r2], &tcg_gen_or_tl); 6234 break; 6235 case OPC2_32_RR_OR_GE: 6236 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6237 cpu_gpr_d[r2], &tcg_gen_or_tl); 6238 break; 6239 case OPC2_32_RR_OR_GE_U: 6240 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6241 cpu_gpr_d[r2], &tcg_gen_or_tl); 6242 break; 6243 case OPC2_32_RR_OR_LT: 6244 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6245 cpu_gpr_d[r2], &tcg_gen_or_tl); 6246 break; 6247 case OPC2_32_RR_OR_LT_U: 6248 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6249 cpu_gpr_d[r2], &tcg_gen_or_tl); 6250 break; 6251 case OPC2_32_RR_OR_NE: 6252 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6253 cpu_gpr_d[r2], &tcg_gen_or_tl); 6254 break; 6255 case OPC2_32_RR_SAT_B: 6256 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); 6257 break; 6258 case OPC2_32_RR_SAT_BU: 6259 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); 6260 break; 6261 case OPC2_32_RR_SAT_H: 6262 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); 6263 break; 6264 case OPC2_32_RR_SAT_HU: 6265 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); 6266 break; 6267 case OPC2_32_RR_SH_EQ: 6268 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6269 cpu_gpr_d[r2]); 6270 break; 6271 case OPC2_32_RR_SH_GE: 6272 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6273 cpu_gpr_d[r2]); 6274 break; 6275 case OPC2_32_RR_SH_GE_U: 6276 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6277 cpu_gpr_d[r2]); 6278 break; 6279 case OPC2_32_RR_SH_LT: 6280 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6281 cpu_gpr_d[r2]); 6282 break; 6283 case OPC2_32_RR_SH_LT_U: 6284 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6285 cpu_gpr_d[r2]); 6286 break; 6287 case OPC2_32_RR_SH_NE: 6288 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6289 cpu_gpr_d[r2]); 6290 break; 6291 case OPC2_32_RR_SUB: 6292 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6293 break; 6294 case OPC2_32_RR_SUB_B: 6295 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6296 break; 6297 case OPC2_32_RR_SUB_H: 6298 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6299 break; 6300 case OPC2_32_RR_SUBC: 6301 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6302 break; 6303 case OPC2_32_RR_SUBS: 6304 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6305 break; 6306 case OPC2_32_RR_SUBS_U: 6307 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6308 break; 6309 case OPC2_32_RR_SUBS_H: 6310 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6311 cpu_gpr_d[r2]); 6312 break; 6313 case OPC2_32_RR_SUBS_HU: 6314 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6315 cpu_gpr_d[r2]); 6316 break; 6317 case OPC2_32_RR_SUBX: 6318 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6319 break; 6320 case OPC2_32_RR_XOR_EQ: 6321 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6322 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6323 break; 6324 case OPC2_32_RR_XOR_GE: 6325 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6326 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6327 break; 6328 case OPC2_32_RR_XOR_GE_U: 6329 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6330 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6331 break; 6332 case OPC2_32_RR_XOR_LT: 6333 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6334 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6335 break; 6336 case OPC2_32_RR_XOR_LT_U: 6337 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6338 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6339 break; 6340 case OPC2_32_RR_XOR_NE: 6341 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6342 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6343 break; 6344 default: 6345 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6346 } 6347 } 6348 6349 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) 6350 { 6351 uint32_t op2; 6352 int r3, r2, r1; 6353 TCGv temp; 6354 6355 r3 = MASK_OP_RR_D(ctx->opcode); 6356 r2 = MASK_OP_RR_S2(ctx->opcode); 6357 r1 = MASK_OP_RR_S1(ctx->opcode); 6358 6359 temp = tcg_temp_new(); 6360 op2 = MASK_OP_RR_OP2(ctx->opcode); 6361 6362 switch (op2) { 6363 case OPC2_32_RR_AND: 6364 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6365 break; 6366 case OPC2_32_RR_ANDN: 6367 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6368 break; 6369 case OPC2_32_RR_CLO: 6370 gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6371 break; 6372 case OPC2_32_RR_CLO_H: 6373 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6374 break; 6375 case OPC2_32_RR_CLS: 6376 gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6377 break; 6378 case OPC2_32_RR_CLS_H: 6379 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6380 break; 6381 case OPC2_32_RR_CLZ: 6382 gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6383 break; 6384 case OPC2_32_RR_CLZ_H: 6385 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6386 break; 6387 case OPC2_32_RR_NAND: 6388 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6389 break; 6390 case OPC2_32_RR_NOR: 6391 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6392 break; 6393 case OPC2_32_RR_OR: 6394 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6395 break; 6396 case OPC2_32_RR_ORN: 6397 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6398 break; 6399 case OPC2_32_RR_SH: 6400 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6401 break; 6402 case OPC2_32_RR_SH_H: 6403 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6404 break; 6405 case OPC2_32_RR_SHA: 6406 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6407 break; 6408 case OPC2_32_RR_SHA_H: 6409 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6410 break; 6411 case OPC2_32_RR_SHAS: 6412 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6413 break; 6414 case OPC2_32_RR_XNOR: 6415 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6416 break; 6417 case OPC2_32_RR_XOR: 6418 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6419 break; 6420 default: 6421 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6422 } 6423 tcg_temp_free(temp); 6424 } 6425 6426 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx) 6427 { 6428 uint32_t op2, n; 6429 int r1, r2, r3; 6430 TCGv temp; 6431 6432 op2 = MASK_OP_RR_OP2(ctx->opcode); 6433 r3 = MASK_OP_RR_D(ctx->opcode); 6434 r2 = MASK_OP_RR_S2(ctx->opcode); 6435 r1 = MASK_OP_RR_S1(ctx->opcode); 6436 n = MASK_OP_RR_N(ctx->opcode); 6437 6438 switch (op2) { 6439 case OPC2_32_RR_ADD_A: 6440 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6441 break; 6442 case OPC2_32_RR_ADDSC_A: 6443 temp = tcg_temp_new(); 6444 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); 6445 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); 6446 tcg_temp_free(temp); 6447 break; 6448 case OPC2_32_RR_ADDSC_AT: 6449 temp = tcg_temp_new(); 6450 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); 6451 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); 6452 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); 6453 tcg_temp_free(temp); 6454 break; 6455 case OPC2_32_RR_EQ_A: 6456 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 6457 cpu_gpr_a[r2]); 6458 break; 6459 case OPC2_32_RR_EQZ: 6460 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6461 break; 6462 case OPC2_32_RR_GE_A: 6463 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6464 cpu_gpr_a[r2]); 6465 break; 6466 case OPC2_32_RR_LT_A: 6467 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6468 cpu_gpr_a[r2]); 6469 break; 6470 case OPC2_32_RR_MOV_A: 6471 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); 6472 break; 6473 case OPC2_32_RR_MOV_AA: 6474 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); 6475 break; 6476 case OPC2_32_RR_MOV_D: 6477 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); 6478 break; 6479 case OPC2_32_RR_NE_A: 6480 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 6481 cpu_gpr_a[r2]); 6482 break; 6483 case OPC2_32_RR_NEZ_A: 6484 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6485 break; 6486 case OPC2_32_RR_SUB_A: 6487 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6488 break; 6489 default: 6490 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6491 } 6492 } 6493 6494 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) 6495 { 6496 uint32_t op2; 6497 int r1; 6498 6499 op2 = MASK_OP_RR_OP2(ctx->opcode); 6500 r1 = MASK_OP_RR_S1(ctx->opcode); 6501 6502 switch (op2) { 6503 case OPC2_32_RR_JI: 6504 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6505 break; 6506 case OPC2_32_RR_JLI: 6507 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 6508 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6509 break; 6510 case OPC2_32_RR_CALLI: 6511 gen_helper_1arg(call, ctx->next_pc); 6512 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6513 break; 6514 case OPC2_32_RR_FCALLI: 6515 gen_fcall_save_ctx(ctx); 6516 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6517 break; 6518 default: 6519 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6520 } 6521 tcg_gen_exit_tb(0); 6522 ctx->bstate = BS_BRANCH; 6523 } 6524 6525 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) 6526 { 6527 uint32_t op2; 6528 int r1, r2, r3; 6529 6530 TCGv temp, temp2, temp3; 6531 6532 op2 = MASK_OP_RR_OP2(ctx->opcode); 6533 r3 = MASK_OP_RR_D(ctx->opcode); 6534 r2 = MASK_OP_RR_S2(ctx->opcode); 6535 r1 = MASK_OP_RR_S1(ctx->opcode); 6536 6537 switch (op2) { 6538 case OPC2_32_RR_BMERGE: 6539 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6540 break; 6541 case OPC2_32_RR_BSPLIT: 6542 CHECK_REG_PAIR(r3); 6543 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6544 break; 6545 case OPC2_32_RR_DVINIT_B: 6546 CHECK_REG_PAIR(r3); 6547 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6548 cpu_gpr_d[r2]); 6549 break; 6550 case OPC2_32_RR_DVINIT_BU: 6551 temp = tcg_temp_new(); 6552 temp2 = tcg_temp_new(); 6553 temp3 = tcg_temp_new(); 6554 CHECK_REG_PAIR(r3); 6555 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); 6556 /* reset av */ 6557 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6558 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 6559 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6560 tcg_gen_neg_tl(temp, temp3); 6561 /* use cpu_PSW_AV to compare against 0 */ 6562 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV, 6563 temp, temp3); 6564 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); 6565 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV, 6566 temp2, cpu_gpr_d[r2]); 6567 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6568 } else { 6569 /* overflow = (D[b] == 0) */ 6570 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6571 } 6572 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6573 /* sv */ 6574 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6575 /* write result */ 6576 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); 6577 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6578 6579 tcg_temp_free(temp); 6580 tcg_temp_free(temp2); 6581 tcg_temp_free(temp3); 6582 break; 6583 case OPC2_32_RR_DVINIT_H: 6584 CHECK_REG_PAIR(r3); 6585 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6586 cpu_gpr_d[r2]); 6587 break; 6588 case OPC2_32_RR_DVINIT_HU: 6589 temp = tcg_temp_new(); 6590 temp2 = tcg_temp_new(); 6591 temp3 = tcg_temp_new(); 6592 CHECK_REG_PAIR(r3); 6593 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); 6594 /* reset av */ 6595 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6596 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 6597 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6598 tcg_gen_neg_tl(temp, temp3); 6599 /* use cpu_PSW_AV to compare against 0 */ 6600 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV, 6601 temp, temp3); 6602 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); 6603 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV, 6604 temp2, cpu_gpr_d[r2]); 6605 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6606 } else { 6607 /* overflow = (D[b] == 0) */ 6608 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6609 } 6610 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6611 /* sv */ 6612 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6613 /* write result */ 6614 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); 6615 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6616 tcg_temp_free(temp); 6617 tcg_temp_free(temp2); 6618 tcg_temp_free(temp3); 6619 break; 6620 case OPC2_32_RR_DVINIT: 6621 temp = tcg_temp_new(); 6622 temp2 = tcg_temp_new(); 6623 CHECK_REG_PAIR(r3); 6624 /* overflow = ((D[b] == 0) || 6625 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ 6626 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); 6627 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); 6628 tcg_gen_and_tl(temp, temp, temp2); 6629 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); 6630 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 6631 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6632 /* sv */ 6633 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6634 /* reset av */ 6635 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6636 /* write result */ 6637 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6638 /* sign extend to high reg */ 6639 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); 6640 tcg_temp_free(temp); 6641 tcg_temp_free(temp2); 6642 break; 6643 case OPC2_32_RR_DVINIT_U: 6644 /* overflow = (D[b] == 0) */ 6645 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6646 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6647 /* sv */ 6648 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6649 /* reset av */ 6650 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6651 /* write result */ 6652 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6653 /* zero extend to high reg*/ 6654 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); 6655 break; 6656 case OPC2_32_RR_PARITY: 6657 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6658 break; 6659 case OPC2_32_RR_UNPACK: 6660 CHECK_REG_PAIR(r3); 6661 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6662 break; 6663 case OPC2_32_RR_CRC32: 6664 if (tricore_feature(env, TRICORE_FEATURE_161)) { 6665 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6666 } else { 6667 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6668 } 6669 break; 6670 case OPC2_32_RR_DIV: 6671 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6672 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6673 cpu_gpr_d[r2]); 6674 } else { 6675 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6676 } 6677 break; 6678 case OPC2_32_RR_DIV_U: 6679 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6680 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], 6681 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6682 } else { 6683 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6684 } 6685 break; 6686 case OPC2_32_RR_MUL_F: 6687 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6688 break; 6689 case OPC2_32_RR_DIV_F: 6690 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6691 break; 6692 case OPC2_32_RR_CMP_F: 6693 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6694 break; 6695 case OPC2_32_RR_FTOI: 6696 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6697 break; 6698 case OPC2_32_RR_ITOF: 6699 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6700 break; 6701 default: 6702 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6703 } 6704 } 6705 6706 /* RR1 Format */ 6707 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx) 6708 { 6709 uint32_t op2; 6710 6711 int r1, r2, r3; 6712 TCGv n; 6713 TCGv_i64 temp64; 6714 6715 r1 = MASK_OP_RR1_S1(ctx->opcode); 6716 r2 = MASK_OP_RR1_S2(ctx->opcode); 6717 r3 = MASK_OP_RR1_D(ctx->opcode); 6718 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode)); 6719 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6720 6721 switch (op2) { 6722 case OPC2_32_RR1_MUL_H_32_LL: 6723 temp64 = tcg_temp_new_i64(); 6724 CHECK_REG_PAIR(r3); 6725 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6726 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6727 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6728 tcg_temp_free_i64(temp64); 6729 break; 6730 case OPC2_32_RR1_MUL_H_32_LU: 6731 temp64 = tcg_temp_new_i64(); 6732 CHECK_REG_PAIR(r3); 6733 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6734 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6735 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6736 tcg_temp_free_i64(temp64); 6737 break; 6738 case OPC2_32_RR1_MUL_H_32_UL: 6739 temp64 = tcg_temp_new_i64(); 6740 CHECK_REG_PAIR(r3); 6741 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6742 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6743 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6744 tcg_temp_free_i64(temp64); 6745 break; 6746 case OPC2_32_RR1_MUL_H_32_UU: 6747 temp64 = tcg_temp_new_i64(); 6748 CHECK_REG_PAIR(r3); 6749 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6750 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6751 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6752 tcg_temp_free_i64(temp64); 6753 break; 6754 case OPC2_32_RR1_MULM_H_64_LL: 6755 temp64 = tcg_temp_new_i64(); 6756 CHECK_REG_PAIR(r3); 6757 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6758 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6759 /* reset V bit */ 6760 tcg_gen_movi_tl(cpu_PSW_V, 0); 6761 /* reset AV bit */ 6762 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6763 tcg_temp_free_i64(temp64); 6764 break; 6765 case OPC2_32_RR1_MULM_H_64_LU: 6766 temp64 = tcg_temp_new_i64(); 6767 CHECK_REG_PAIR(r3); 6768 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6769 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6770 /* reset V bit */ 6771 tcg_gen_movi_tl(cpu_PSW_V, 0); 6772 /* reset AV bit */ 6773 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6774 tcg_temp_free_i64(temp64); 6775 break; 6776 case OPC2_32_RR1_MULM_H_64_UL: 6777 temp64 = tcg_temp_new_i64(); 6778 CHECK_REG_PAIR(r3); 6779 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6780 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6781 /* reset V bit */ 6782 tcg_gen_movi_tl(cpu_PSW_V, 0); 6783 /* reset AV bit */ 6784 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6785 tcg_temp_free_i64(temp64); 6786 break; 6787 case OPC2_32_RR1_MULM_H_64_UU: 6788 temp64 = tcg_temp_new_i64(); 6789 CHECK_REG_PAIR(r3); 6790 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6791 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6792 /* reset V bit */ 6793 tcg_gen_movi_tl(cpu_PSW_V, 0); 6794 /* reset AV bit */ 6795 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6796 tcg_temp_free_i64(temp64); 6797 6798 break; 6799 case OPC2_32_RR1_MULR_H_16_LL: 6800 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6801 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6802 break; 6803 case OPC2_32_RR1_MULR_H_16_LU: 6804 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6805 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6806 break; 6807 case OPC2_32_RR1_MULR_H_16_UL: 6808 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6809 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6810 break; 6811 case OPC2_32_RR1_MULR_H_16_UU: 6812 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6813 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6814 break; 6815 default: 6816 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6817 } 6818 tcg_temp_free(n); 6819 } 6820 6821 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx) 6822 { 6823 uint32_t op2; 6824 int r1, r2, r3; 6825 uint32_t n; 6826 6827 TCGv temp, temp2; 6828 6829 r1 = MASK_OP_RR1_S1(ctx->opcode); 6830 r2 = MASK_OP_RR1_S2(ctx->opcode); 6831 r3 = MASK_OP_RR1_D(ctx->opcode); 6832 n = MASK_OP_RR1_N(ctx->opcode); 6833 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6834 6835 temp = tcg_temp_new(); 6836 temp2 = tcg_temp_new(); 6837 6838 switch (op2) { 6839 case OPC2_32_RR1_MUL_Q_32: 6840 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); 6841 break; 6842 case OPC2_32_RR1_MUL_Q_64: 6843 CHECK_REG_PAIR(r3); 6844 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6845 n, 0); 6846 break; 6847 case OPC2_32_RR1_MUL_Q_32_L: 6848 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6849 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6850 break; 6851 case OPC2_32_RR1_MUL_Q_64_L: 6852 CHECK_REG_PAIR(r3); 6853 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6854 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6855 break; 6856 case OPC2_32_RR1_MUL_Q_32_U: 6857 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6858 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6859 break; 6860 case OPC2_32_RR1_MUL_Q_64_U: 6861 CHECK_REG_PAIR(r3); 6862 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6863 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6864 break; 6865 case OPC2_32_RR1_MUL_Q_32_LL: 6866 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6867 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6868 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6869 break; 6870 case OPC2_32_RR1_MUL_Q_32_UU: 6871 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6872 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6873 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6874 break; 6875 case OPC2_32_RR1_MULR_Q_32_L: 6876 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6877 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6878 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6879 break; 6880 case OPC2_32_RR1_MULR_Q_32_U: 6881 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6882 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6883 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6884 break; 6885 default: 6886 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6887 } 6888 tcg_temp_free(temp); 6889 tcg_temp_free(temp2); 6890 } 6891 6892 /* RR2 format */ 6893 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx) 6894 { 6895 uint32_t op2; 6896 int r1, r2, r3; 6897 6898 op2 = MASK_OP_RR2_OP2(ctx->opcode); 6899 r1 = MASK_OP_RR2_S1(ctx->opcode); 6900 r2 = MASK_OP_RR2_S2(ctx->opcode); 6901 r3 = MASK_OP_RR2_D(ctx->opcode); 6902 switch (op2) { 6903 case OPC2_32_RR2_MUL_32: 6904 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6905 break; 6906 case OPC2_32_RR2_MUL_64: 6907 CHECK_REG_PAIR(r3); 6908 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6909 cpu_gpr_d[r2]); 6910 break; 6911 case OPC2_32_RR2_MULS_32: 6912 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6913 cpu_gpr_d[r2]); 6914 break; 6915 case OPC2_32_RR2_MUL_U_64: 6916 CHECK_REG_PAIR(r3); 6917 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6918 cpu_gpr_d[r2]); 6919 break; 6920 case OPC2_32_RR2_MULS_U_32: 6921 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6922 cpu_gpr_d[r2]); 6923 break; 6924 default: 6925 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6926 } 6927 } 6928 6929 /* RRPW format */ 6930 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) 6931 { 6932 uint32_t op2; 6933 int r1, r2, r3; 6934 int32_t pos, width; 6935 6936 op2 = MASK_OP_RRPW_OP2(ctx->opcode); 6937 r1 = MASK_OP_RRPW_S1(ctx->opcode); 6938 r2 = MASK_OP_RRPW_S2(ctx->opcode); 6939 r3 = MASK_OP_RRPW_D(ctx->opcode); 6940 pos = MASK_OP_RRPW_POS(ctx->opcode); 6941 width = MASK_OP_RRPW_WIDTH(ctx->opcode); 6942 6943 switch (op2) { 6944 case OPC2_32_RRPW_EXTR: 6945 if (pos + width <= 31) { 6946 /* optimize special cases */ 6947 if ((pos == 0) && (width == 8)) { 6948 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6949 } else if ((pos == 0) && (width == 16)) { 6950 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6951 } else { 6952 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width); 6953 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width); 6954 } 6955 } 6956 break; 6957 case OPC2_32_RRPW_EXTR_U: 6958 if (width == 0) { 6959 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6960 } else { 6961 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); 6962 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width)); 6963 } 6964 break; 6965 case OPC2_32_RRPW_IMASK: 6966 CHECK_REG_PAIR(r3); 6967 if (pos + width <= 31) { 6968 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos); 6969 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); 6970 } 6971 break; 6972 case OPC2_32_RRPW_INSERT: 6973 if (pos + width <= 31) { 6974 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 6975 width, pos); 6976 } 6977 break; 6978 default: 6979 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6980 } 6981 } 6982 6983 /* RRR format */ 6984 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx) 6985 { 6986 uint32_t op2; 6987 int r1, r2, r3, r4; 6988 TCGv temp; 6989 6990 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6991 r1 = MASK_OP_RRR_S1(ctx->opcode); 6992 r2 = MASK_OP_RRR_S2(ctx->opcode); 6993 r3 = MASK_OP_RRR_S3(ctx->opcode); 6994 r4 = MASK_OP_RRR_D(ctx->opcode); 6995 6996 switch (op2) { 6997 case OPC2_32_RRR_CADD: 6998 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 6999 cpu_gpr_d[r4], cpu_gpr_d[r3]); 7000 break; 7001 case OPC2_32_RRR_CADDN: 7002 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 7003 cpu_gpr_d[r3]); 7004 break; 7005 case OPC2_32_RRR_CSUB: 7006 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 7007 cpu_gpr_d[r3]); 7008 break; 7009 case OPC2_32_RRR_CSUBN: 7010 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 7011 cpu_gpr_d[r3]); 7012 break; 7013 case OPC2_32_RRR_SEL: 7014 temp = tcg_const_i32(0); 7015 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 7016 cpu_gpr_d[r1], cpu_gpr_d[r2]); 7017 tcg_temp_free(temp); 7018 break; 7019 case OPC2_32_RRR_SELN: 7020 temp = tcg_const_i32(0); 7021 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 7022 cpu_gpr_d[r1], cpu_gpr_d[r2]); 7023 tcg_temp_free(temp); 7024 break; 7025 default: 7026 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7027 } 7028 } 7029 7030 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) 7031 { 7032 uint32_t op2; 7033 7034 int r1, r2, r3, r4; 7035 7036 op2 = MASK_OP_RRR_OP2(ctx->opcode); 7037 r1 = MASK_OP_RRR_S1(ctx->opcode); 7038 r2 = MASK_OP_RRR_S2(ctx->opcode); 7039 r3 = MASK_OP_RRR_S3(ctx->opcode); 7040 r4 = MASK_OP_RRR_D(ctx->opcode); 7041 7042 switch (op2) { 7043 case OPC2_32_RRR_DVADJ: 7044 CHECK_REG_PAIR(r3); 7045 CHECK_REG_PAIR(r4); 7046 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7047 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7048 break; 7049 case OPC2_32_RRR_DVSTEP: 7050 CHECK_REG_PAIR(r3); 7051 CHECK_REG_PAIR(r4); 7052 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7053 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7054 break; 7055 case OPC2_32_RRR_DVSTEP_U: 7056 CHECK_REG_PAIR(r3); 7057 CHECK_REG_PAIR(r4); 7058 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7059 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7060 break; 7061 case OPC2_32_RRR_IXMAX: 7062 CHECK_REG_PAIR(r3); 7063 CHECK_REG_PAIR(r4); 7064 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7065 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7066 break; 7067 case OPC2_32_RRR_IXMAX_U: 7068 CHECK_REG_PAIR(r3); 7069 CHECK_REG_PAIR(r4); 7070 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7071 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7072 break; 7073 case OPC2_32_RRR_IXMIN: 7074 CHECK_REG_PAIR(r3); 7075 CHECK_REG_PAIR(r4); 7076 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7077 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7078 break; 7079 case OPC2_32_RRR_IXMIN_U: 7080 CHECK_REG_PAIR(r3); 7081 CHECK_REG_PAIR(r4); 7082 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7083 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7084 break; 7085 case OPC2_32_RRR_PACK: 7086 CHECK_REG_PAIR(r3); 7087 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], 7088 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 7089 break; 7090 case OPC2_32_RRR_ADD_F: 7091 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 7092 break; 7093 case OPC2_32_RRR_SUB_F: 7094 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 7095 break; 7096 default: 7097 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7098 } 7099 } 7100 7101 /* RRR2 format */ 7102 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx) 7103 { 7104 uint32_t op2; 7105 uint32_t r1, r2, r3, r4; 7106 7107 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 7108 r1 = MASK_OP_RRR2_S1(ctx->opcode); 7109 r2 = MASK_OP_RRR2_S2(ctx->opcode); 7110 r3 = MASK_OP_RRR2_S3(ctx->opcode); 7111 r4 = MASK_OP_RRR2_D(ctx->opcode); 7112 switch (op2) { 7113 case OPC2_32_RRR2_MADD_32: 7114 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 7115 cpu_gpr_d[r2]); 7116 break; 7117 case OPC2_32_RRR2_MADD_64: 7118 CHECK_REG_PAIR(r4); 7119 CHECK_REG_PAIR(r3); 7120 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7121 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7122 break; 7123 case OPC2_32_RRR2_MADDS_32: 7124 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7125 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7126 break; 7127 case OPC2_32_RRR2_MADDS_64: 7128 CHECK_REG_PAIR(r4); 7129 CHECK_REG_PAIR(r3); 7130 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7131 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7132 break; 7133 case OPC2_32_RRR2_MADD_U_64: 7134 CHECK_REG_PAIR(r4); 7135 CHECK_REG_PAIR(r3); 7136 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7137 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7138 break; 7139 case OPC2_32_RRR2_MADDS_U_32: 7140 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7141 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7142 break; 7143 case OPC2_32_RRR2_MADDS_U_64: 7144 CHECK_REG_PAIR(r4); 7145 CHECK_REG_PAIR(r3); 7146 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7147 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7148 break; 7149 default: 7150 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7151 } 7152 } 7153 7154 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx) 7155 { 7156 uint32_t op2; 7157 uint32_t r1, r2, r3, r4; 7158 7159 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 7160 r1 = MASK_OP_RRR2_S1(ctx->opcode); 7161 r2 = MASK_OP_RRR2_S2(ctx->opcode); 7162 r3 = MASK_OP_RRR2_S3(ctx->opcode); 7163 r4 = MASK_OP_RRR2_D(ctx->opcode); 7164 7165 switch (op2) { 7166 case OPC2_32_RRR2_MSUB_32: 7167 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 7168 cpu_gpr_d[r2]); 7169 break; 7170 case OPC2_32_RRR2_MSUB_64: 7171 CHECK_REG_PAIR(r4); 7172 CHECK_REG_PAIR(r3); 7173 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7174 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7175 break; 7176 case OPC2_32_RRR2_MSUBS_32: 7177 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7178 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7179 break; 7180 case OPC2_32_RRR2_MSUBS_64: 7181 CHECK_REG_PAIR(r4); 7182 CHECK_REG_PAIR(r3); 7183 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7184 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7185 break; 7186 case OPC2_32_RRR2_MSUB_U_64: 7187 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7188 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7189 break; 7190 case OPC2_32_RRR2_MSUBS_U_32: 7191 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7192 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7193 break; 7194 case OPC2_32_RRR2_MSUBS_U_64: 7195 CHECK_REG_PAIR(r4); 7196 CHECK_REG_PAIR(r3); 7197 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7198 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7199 break; 7200 default: 7201 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7202 } 7203 } 7204 7205 /* RRR1 format */ 7206 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx) 7207 { 7208 uint32_t op2; 7209 uint32_t r1, r2, r3, r4, n; 7210 7211 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7212 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7213 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7214 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7215 r4 = MASK_OP_RRR1_D(ctx->opcode); 7216 n = MASK_OP_RRR1_N(ctx->opcode); 7217 7218 switch (op2) { 7219 case OPC2_32_RRR1_MADD_H_LL: 7220 CHECK_REG_PAIR(r4); 7221 CHECK_REG_PAIR(r3); 7222 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7223 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7224 break; 7225 case OPC2_32_RRR1_MADD_H_LU: 7226 CHECK_REG_PAIR(r4); 7227 CHECK_REG_PAIR(r3); 7228 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7229 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7230 break; 7231 case OPC2_32_RRR1_MADD_H_UL: 7232 CHECK_REG_PAIR(r4); 7233 CHECK_REG_PAIR(r3); 7234 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7235 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7236 break; 7237 case OPC2_32_RRR1_MADD_H_UU: 7238 CHECK_REG_PAIR(r4); 7239 CHECK_REG_PAIR(r3); 7240 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7241 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7242 break; 7243 case OPC2_32_RRR1_MADDS_H_LL: 7244 CHECK_REG_PAIR(r4); 7245 CHECK_REG_PAIR(r3); 7246 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7247 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7248 break; 7249 case OPC2_32_RRR1_MADDS_H_LU: 7250 CHECK_REG_PAIR(r4); 7251 CHECK_REG_PAIR(r3); 7252 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7253 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7254 break; 7255 case OPC2_32_RRR1_MADDS_H_UL: 7256 CHECK_REG_PAIR(r4); 7257 CHECK_REG_PAIR(r3); 7258 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7259 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7260 break; 7261 case OPC2_32_RRR1_MADDS_H_UU: 7262 CHECK_REG_PAIR(r4); 7263 CHECK_REG_PAIR(r3); 7264 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7265 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7266 break; 7267 case OPC2_32_RRR1_MADDM_H_LL: 7268 CHECK_REG_PAIR(r4); 7269 CHECK_REG_PAIR(r3); 7270 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7271 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7272 break; 7273 case OPC2_32_RRR1_MADDM_H_LU: 7274 CHECK_REG_PAIR(r4); 7275 CHECK_REG_PAIR(r3); 7276 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7277 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7278 break; 7279 case OPC2_32_RRR1_MADDM_H_UL: 7280 CHECK_REG_PAIR(r4); 7281 CHECK_REG_PAIR(r3); 7282 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7283 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7284 break; 7285 case OPC2_32_RRR1_MADDM_H_UU: 7286 CHECK_REG_PAIR(r4); 7287 CHECK_REG_PAIR(r3); 7288 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7289 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7290 break; 7291 case OPC2_32_RRR1_MADDMS_H_LL: 7292 CHECK_REG_PAIR(r4); 7293 CHECK_REG_PAIR(r3); 7294 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7295 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7296 break; 7297 case OPC2_32_RRR1_MADDMS_H_LU: 7298 CHECK_REG_PAIR(r4); 7299 CHECK_REG_PAIR(r3); 7300 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7301 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7302 break; 7303 case OPC2_32_RRR1_MADDMS_H_UL: 7304 CHECK_REG_PAIR(r4); 7305 CHECK_REG_PAIR(r3); 7306 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7307 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7308 break; 7309 case OPC2_32_RRR1_MADDMS_H_UU: 7310 CHECK_REG_PAIR(r4); 7311 CHECK_REG_PAIR(r3); 7312 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7313 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7314 break; 7315 case OPC2_32_RRR1_MADDR_H_LL: 7316 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7317 cpu_gpr_d[r2], n, MODE_LL); 7318 break; 7319 case OPC2_32_RRR1_MADDR_H_LU: 7320 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7321 cpu_gpr_d[r2], n, MODE_LU); 7322 break; 7323 case OPC2_32_RRR1_MADDR_H_UL: 7324 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7325 cpu_gpr_d[r2], n, MODE_UL); 7326 break; 7327 case OPC2_32_RRR1_MADDR_H_UU: 7328 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7329 cpu_gpr_d[r2], n, MODE_UU); 7330 break; 7331 case OPC2_32_RRR1_MADDRS_H_LL: 7332 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7333 cpu_gpr_d[r2], n, MODE_LL); 7334 break; 7335 case OPC2_32_RRR1_MADDRS_H_LU: 7336 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7337 cpu_gpr_d[r2], n, MODE_LU); 7338 break; 7339 case OPC2_32_RRR1_MADDRS_H_UL: 7340 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7341 cpu_gpr_d[r2], n, MODE_UL); 7342 break; 7343 case OPC2_32_RRR1_MADDRS_H_UU: 7344 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7345 cpu_gpr_d[r2], n, MODE_UU); 7346 break; 7347 default: 7348 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7349 } 7350 } 7351 7352 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) 7353 { 7354 uint32_t op2; 7355 uint32_t r1, r2, r3, r4, n; 7356 TCGv temp, temp2; 7357 7358 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7359 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7360 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7361 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7362 r4 = MASK_OP_RRR1_D(ctx->opcode); 7363 n = MASK_OP_RRR1_N(ctx->opcode); 7364 7365 temp = tcg_const_i32(n); 7366 temp2 = tcg_temp_new(); 7367 7368 switch (op2) { 7369 case OPC2_32_RRR1_MADD_Q_32: 7370 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7371 cpu_gpr_d[r2], n, 32, env); 7372 break; 7373 case OPC2_32_RRR1_MADD_Q_64: 7374 CHECK_REG_PAIR(r4); 7375 CHECK_REG_PAIR(r3); 7376 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7377 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7378 n, env); 7379 break; 7380 case OPC2_32_RRR1_MADD_Q_32_L: 7381 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7382 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7383 temp, n, 16, env); 7384 break; 7385 case OPC2_32_RRR1_MADD_Q_64_L: 7386 CHECK_REG_PAIR(r4); 7387 CHECK_REG_PAIR(r3); 7388 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7389 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7390 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7391 n, env); 7392 break; 7393 case OPC2_32_RRR1_MADD_Q_32_U: 7394 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7395 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7396 temp, n, 16, env); 7397 break; 7398 case OPC2_32_RRR1_MADD_Q_64_U: 7399 CHECK_REG_PAIR(r4); 7400 CHECK_REG_PAIR(r3); 7401 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7402 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7403 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7404 n, env); 7405 break; 7406 case OPC2_32_RRR1_MADD_Q_32_LL: 7407 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7408 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7409 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7410 break; 7411 case OPC2_32_RRR1_MADD_Q_64_LL: 7412 CHECK_REG_PAIR(r4); 7413 CHECK_REG_PAIR(r3); 7414 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7415 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7416 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7417 cpu_gpr_d[r3+1], temp, temp2, n); 7418 break; 7419 case OPC2_32_RRR1_MADD_Q_32_UU: 7420 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7421 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7422 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7423 break; 7424 case OPC2_32_RRR1_MADD_Q_64_UU: 7425 CHECK_REG_PAIR(r4); 7426 CHECK_REG_PAIR(r3); 7427 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7428 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7429 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7430 cpu_gpr_d[r3+1], temp, temp2, n); 7431 break; 7432 case OPC2_32_RRR1_MADDS_Q_32: 7433 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7434 cpu_gpr_d[r2], n, 32); 7435 break; 7436 case OPC2_32_RRR1_MADDS_Q_64: 7437 CHECK_REG_PAIR(r4); 7438 CHECK_REG_PAIR(r3); 7439 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7440 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7441 n); 7442 break; 7443 case OPC2_32_RRR1_MADDS_Q_32_L: 7444 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7445 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7446 temp, n, 16); 7447 break; 7448 case OPC2_32_RRR1_MADDS_Q_64_L: 7449 CHECK_REG_PAIR(r4); 7450 CHECK_REG_PAIR(r3); 7451 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7452 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7453 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7454 n); 7455 break; 7456 case OPC2_32_RRR1_MADDS_Q_32_U: 7457 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7458 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7459 temp, n, 16); 7460 break; 7461 case OPC2_32_RRR1_MADDS_Q_64_U: 7462 CHECK_REG_PAIR(r4); 7463 CHECK_REG_PAIR(r3); 7464 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7465 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7466 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7467 n); 7468 break; 7469 case OPC2_32_RRR1_MADDS_Q_32_LL: 7470 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7471 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7472 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7473 break; 7474 case OPC2_32_RRR1_MADDS_Q_64_LL: 7475 CHECK_REG_PAIR(r4); 7476 CHECK_REG_PAIR(r3); 7477 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7478 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7479 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7480 cpu_gpr_d[r3+1], temp, temp2, n); 7481 break; 7482 case OPC2_32_RRR1_MADDS_Q_32_UU: 7483 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7484 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7485 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7486 break; 7487 case OPC2_32_RRR1_MADDS_Q_64_UU: 7488 CHECK_REG_PAIR(r4); 7489 CHECK_REG_PAIR(r3); 7490 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7491 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7492 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7493 cpu_gpr_d[r3+1], temp, temp2, n); 7494 break; 7495 case OPC2_32_RRR1_MADDR_H_64_UL: 7496 CHECK_REG_PAIR(r3); 7497 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7498 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7499 break; 7500 case OPC2_32_RRR1_MADDRS_H_64_UL: 7501 CHECK_REG_PAIR(r3); 7502 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7503 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7504 break; 7505 case OPC2_32_RRR1_MADDR_Q_32_LL: 7506 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7507 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7508 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7509 break; 7510 case OPC2_32_RRR1_MADDR_Q_32_UU: 7511 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7512 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7513 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7514 break; 7515 case OPC2_32_RRR1_MADDRS_Q_32_LL: 7516 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7517 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7518 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7519 break; 7520 case OPC2_32_RRR1_MADDRS_Q_32_UU: 7521 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7522 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7523 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7524 break; 7525 default: 7526 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7527 } 7528 tcg_temp_free(temp); 7529 tcg_temp_free(temp2); 7530 } 7531 7532 static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx) 7533 { 7534 uint32_t op2; 7535 uint32_t r1, r2, r3, r4, n; 7536 7537 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7538 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7539 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7540 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7541 r4 = MASK_OP_RRR1_D(ctx->opcode); 7542 n = MASK_OP_RRR1_N(ctx->opcode); 7543 7544 switch (op2) { 7545 case OPC2_32_RRR1_MADDSU_H_32_LL: 7546 CHECK_REG_PAIR(r4); 7547 CHECK_REG_PAIR(r3); 7548 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7549 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7550 break; 7551 case OPC2_32_RRR1_MADDSU_H_32_LU: 7552 CHECK_REG_PAIR(r4); 7553 CHECK_REG_PAIR(r3); 7554 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7555 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7556 break; 7557 case OPC2_32_RRR1_MADDSU_H_32_UL: 7558 CHECK_REG_PAIR(r4); 7559 CHECK_REG_PAIR(r3); 7560 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7561 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7562 break; 7563 case OPC2_32_RRR1_MADDSU_H_32_UU: 7564 CHECK_REG_PAIR(r4); 7565 CHECK_REG_PAIR(r3); 7566 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7567 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7568 break; 7569 case OPC2_32_RRR1_MADDSUS_H_32_LL: 7570 CHECK_REG_PAIR(r4); 7571 CHECK_REG_PAIR(r3); 7572 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7573 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7574 n, MODE_LL); 7575 break; 7576 case OPC2_32_RRR1_MADDSUS_H_32_LU: 7577 CHECK_REG_PAIR(r4); 7578 CHECK_REG_PAIR(r3); 7579 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7580 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7581 n, MODE_LU); 7582 break; 7583 case OPC2_32_RRR1_MADDSUS_H_32_UL: 7584 CHECK_REG_PAIR(r4); 7585 CHECK_REG_PAIR(r3); 7586 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7587 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7588 n, MODE_UL); 7589 break; 7590 case OPC2_32_RRR1_MADDSUS_H_32_UU: 7591 CHECK_REG_PAIR(r4); 7592 CHECK_REG_PAIR(r3); 7593 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7594 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7595 n, MODE_UU); 7596 break; 7597 case OPC2_32_RRR1_MADDSUM_H_64_LL: 7598 CHECK_REG_PAIR(r4); 7599 CHECK_REG_PAIR(r3); 7600 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7601 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7602 n, MODE_LL); 7603 break; 7604 case OPC2_32_RRR1_MADDSUM_H_64_LU: 7605 CHECK_REG_PAIR(r4); 7606 CHECK_REG_PAIR(r3); 7607 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7608 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7609 n, MODE_LU); 7610 break; 7611 case OPC2_32_RRR1_MADDSUM_H_64_UL: 7612 CHECK_REG_PAIR(r4); 7613 CHECK_REG_PAIR(r3); 7614 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7615 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7616 n, MODE_UL); 7617 break; 7618 case OPC2_32_RRR1_MADDSUM_H_64_UU: 7619 CHECK_REG_PAIR(r4); 7620 CHECK_REG_PAIR(r3); 7621 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7622 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7623 n, MODE_UU); 7624 break; 7625 case OPC2_32_RRR1_MADDSUMS_H_64_LL: 7626 CHECK_REG_PAIR(r4); 7627 CHECK_REG_PAIR(r3); 7628 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7629 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7630 n, MODE_LL); 7631 break; 7632 case OPC2_32_RRR1_MADDSUMS_H_64_LU: 7633 CHECK_REG_PAIR(r4); 7634 CHECK_REG_PAIR(r3); 7635 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7636 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7637 n, MODE_LU); 7638 break; 7639 case OPC2_32_RRR1_MADDSUMS_H_64_UL: 7640 CHECK_REG_PAIR(r4); 7641 CHECK_REG_PAIR(r3); 7642 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7643 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7644 n, MODE_UL); 7645 break; 7646 case OPC2_32_RRR1_MADDSUMS_H_64_UU: 7647 CHECK_REG_PAIR(r4); 7648 CHECK_REG_PAIR(r3); 7649 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7650 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7651 n, MODE_UU); 7652 break; 7653 case OPC2_32_RRR1_MADDSUR_H_16_LL: 7654 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7655 cpu_gpr_d[r2], n, MODE_LL); 7656 break; 7657 case OPC2_32_RRR1_MADDSUR_H_16_LU: 7658 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7659 cpu_gpr_d[r2], n, MODE_LU); 7660 break; 7661 case OPC2_32_RRR1_MADDSUR_H_16_UL: 7662 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7663 cpu_gpr_d[r2], n, MODE_UL); 7664 break; 7665 case OPC2_32_RRR1_MADDSUR_H_16_UU: 7666 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7667 cpu_gpr_d[r2], n, MODE_UU); 7668 break; 7669 case OPC2_32_RRR1_MADDSURS_H_16_LL: 7670 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7671 cpu_gpr_d[r2], n, MODE_LL); 7672 break; 7673 case OPC2_32_RRR1_MADDSURS_H_16_LU: 7674 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7675 cpu_gpr_d[r2], n, MODE_LU); 7676 break; 7677 case OPC2_32_RRR1_MADDSURS_H_16_UL: 7678 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7679 cpu_gpr_d[r2], n, MODE_UL); 7680 break; 7681 case OPC2_32_RRR1_MADDSURS_H_16_UU: 7682 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7683 cpu_gpr_d[r2], n, MODE_UU); 7684 break; 7685 default: 7686 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7687 } 7688 } 7689 7690 static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx) 7691 { 7692 uint32_t op2; 7693 uint32_t r1, r2, r3, r4, n; 7694 7695 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7696 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7697 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7698 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7699 r4 = MASK_OP_RRR1_D(ctx->opcode); 7700 n = MASK_OP_RRR1_N(ctx->opcode); 7701 7702 switch (op2) { 7703 case OPC2_32_RRR1_MSUB_H_LL: 7704 CHECK_REG_PAIR(r4); 7705 CHECK_REG_PAIR(r3); 7706 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7707 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7708 break; 7709 case OPC2_32_RRR1_MSUB_H_LU: 7710 CHECK_REG_PAIR(r4); 7711 CHECK_REG_PAIR(r3); 7712 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7713 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7714 break; 7715 case OPC2_32_RRR1_MSUB_H_UL: 7716 CHECK_REG_PAIR(r4); 7717 CHECK_REG_PAIR(r3); 7718 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7719 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7720 break; 7721 case OPC2_32_RRR1_MSUB_H_UU: 7722 CHECK_REG_PAIR(r4); 7723 CHECK_REG_PAIR(r3); 7724 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7725 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7726 break; 7727 case OPC2_32_RRR1_MSUBS_H_LL: 7728 CHECK_REG_PAIR(r4); 7729 CHECK_REG_PAIR(r3); 7730 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7731 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7732 break; 7733 case OPC2_32_RRR1_MSUBS_H_LU: 7734 CHECK_REG_PAIR(r4); 7735 CHECK_REG_PAIR(r3); 7736 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7737 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7738 break; 7739 case OPC2_32_RRR1_MSUBS_H_UL: 7740 CHECK_REG_PAIR(r4); 7741 CHECK_REG_PAIR(r3); 7742 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7743 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7744 break; 7745 case OPC2_32_RRR1_MSUBS_H_UU: 7746 CHECK_REG_PAIR(r4); 7747 CHECK_REG_PAIR(r3); 7748 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7749 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7750 break; 7751 case OPC2_32_RRR1_MSUBM_H_LL: 7752 CHECK_REG_PAIR(r4); 7753 CHECK_REG_PAIR(r3); 7754 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7755 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7756 break; 7757 case OPC2_32_RRR1_MSUBM_H_LU: 7758 CHECK_REG_PAIR(r4); 7759 CHECK_REG_PAIR(r3); 7760 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7761 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7762 break; 7763 case OPC2_32_RRR1_MSUBM_H_UL: 7764 CHECK_REG_PAIR(r4); 7765 CHECK_REG_PAIR(r3); 7766 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7767 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7768 break; 7769 case OPC2_32_RRR1_MSUBM_H_UU: 7770 CHECK_REG_PAIR(r4); 7771 CHECK_REG_PAIR(r3); 7772 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7773 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7774 break; 7775 case OPC2_32_RRR1_MSUBMS_H_LL: 7776 CHECK_REG_PAIR(r4); 7777 CHECK_REG_PAIR(r3); 7778 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7779 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7780 break; 7781 case OPC2_32_RRR1_MSUBMS_H_LU: 7782 CHECK_REG_PAIR(r4); 7783 CHECK_REG_PAIR(r3); 7784 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7785 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7786 break; 7787 case OPC2_32_RRR1_MSUBMS_H_UL: 7788 CHECK_REG_PAIR(r4); 7789 CHECK_REG_PAIR(r3); 7790 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7791 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7792 break; 7793 case OPC2_32_RRR1_MSUBMS_H_UU: 7794 CHECK_REG_PAIR(r4); 7795 CHECK_REG_PAIR(r3); 7796 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7797 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7798 break; 7799 case OPC2_32_RRR1_MSUBR_H_LL: 7800 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7801 cpu_gpr_d[r2], n, MODE_LL); 7802 break; 7803 case OPC2_32_RRR1_MSUBR_H_LU: 7804 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7805 cpu_gpr_d[r2], n, MODE_LU); 7806 break; 7807 case OPC2_32_RRR1_MSUBR_H_UL: 7808 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7809 cpu_gpr_d[r2], n, MODE_UL); 7810 break; 7811 case OPC2_32_RRR1_MSUBR_H_UU: 7812 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7813 cpu_gpr_d[r2], n, MODE_UU); 7814 break; 7815 case OPC2_32_RRR1_MSUBRS_H_LL: 7816 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7817 cpu_gpr_d[r2], n, MODE_LL); 7818 break; 7819 case OPC2_32_RRR1_MSUBRS_H_LU: 7820 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7821 cpu_gpr_d[r2], n, MODE_LU); 7822 break; 7823 case OPC2_32_RRR1_MSUBRS_H_UL: 7824 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7825 cpu_gpr_d[r2], n, MODE_UL); 7826 break; 7827 case OPC2_32_RRR1_MSUBRS_H_UU: 7828 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7829 cpu_gpr_d[r2], n, MODE_UU); 7830 break; 7831 default: 7832 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7833 } 7834 } 7835 7836 static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx) 7837 { 7838 uint32_t op2; 7839 uint32_t r1, r2, r3, r4, n; 7840 TCGv temp, temp2; 7841 7842 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7843 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7844 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7845 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7846 r4 = MASK_OP_RRR1_D(ctx->opcode); 7847 n = MASK_OP_RRR1_N(ctx->opcode); 7848 7849 temp = tcg_const_i32(n); 7850 temp2 = tcg_temp_new(); 7851 7852 switch (op2) { 7853 case OPC2_32_RRR1_MSUB_Q_32: 7854 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7855 cpu_gpr_d[r2], n, 32, env); 7856 break; 7857 case OPC2_32_RRR1_MSUB_Q_64: 7858 CHECK_REG_PAIR(r4); 7859 CHECK_REG_PAIR(r3); 7860 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7861 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7862 n, env); 7863 break; 7864 case OPC2_32_RRR1_MSUB_Q_32_L: 7865 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7866 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7867 temp, n, 16, env); 7868 break; 7869 case OPC2_32_RRR1_MSUB_Q_64_L: 7870 CHECK_REG_PAIR(r4); 7871 CHECK_REG_PAIR(r3); 7872 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7873 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7874 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7875 n, env); 7876 break; 7877 case OPC2_32_RRR1_MSUB_Q_32_U: 7878 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7879 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7880 temp, n, 16, env); 7881 break; 7882 case OPC2_32_RRR1_MSUB_Q_64_U: 7883 CHECK_REG_PAIR(r4); 7884 CHECK_REG_PAIR(r3); 7885 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7886 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7887 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7888 n, env); 7889 break; 7890 case OPC2_32_RRR1_MSUB_Q_32_LL: 7891 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7892 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7893 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7894 break; 7895 case OPC2_32_RRR1_MSUB_Q_64_LL: 7896 CHECK_REG_PAIR(r4); 7897 CHECK_REG_PAIR(r3); 7898 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7899 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7900 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7901 cpu_gpr_d[r3+1], temp, temp2, n); 7902 break; 7903 case OPC2_32_RRR1_MSUB_Q_32_UU: 7904 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7905 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7906 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7907 break; 7908 case OPC2_32_RRR1_MSUB_Q_64_UU: 7909 CHECK_REG_PAIR(r4); 7910 CHECK_REG_PAIR(r3); 7911 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7912 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7913 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7914 cpu_gpr_d[r3+1], temp, temp2, n); 7915 break; 7916 case OPC2_32_RRR1_MSUBS_Q_32: 7917 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7918 cpu_gpr_d[r2], n, 32); 7919 break; 7920 case OPC2_32_RRR1_MSUBS_Q_64: 7921 CHECK_REG_PAIR(r4); 7922 CHECK_REG_PAIR(r3); 7923 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7924 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7925 n); 7926 break; 7927 case OPC2_32_RRR1_MSUBS_Q_32_L: 7928 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7929 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7930 temp, n, 16); 7931 break; 7932 case OPC2_32_RRR1_MSUBS_Q_64_L: 7933 CHECK_REG_PAIR(r4); 7934 CHECK_REG_PAIR(r3); 7935 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7936 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7937 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7938 n); 7939 break; 7940 case OPC2_32_RRR1_MSUBS_Q_32_U: 7941 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7942 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7943 temp, n, 16); 7944 break; 7945 case OPC2_32_RRR1_MSUBS_Q_64_U: 7946 CHECK_REG_PAIR(r4); 7947 CHECK_REG_PAIR(r3); 7948 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7949 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7950 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7951 n); 7952 break; 7953 case OPC2_32_RRR1_MSUBS_Q_32_LL: 7954 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7955 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7956 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7957 break; 7958 case OPC2_32_RRR1_MSUBS_Q_64_LL: 7959 CHECK_REG_PAIR(r4); 7960 CHECK_REG_PAIR(r3); 7961 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7962 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7963 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7964 cpu_gpr_d[r3+1], temp, temp2, n); 7965 break; 7966 case OPC2_32_RRR1_MSUBS_Q_32_UU: 7967 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7968 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7969 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7970 break; 7971 case OPC2_32_RRR1_MSUBS_Q_64_UU: 7972 CHECK_REG_PAIR(r4); 7973 CHECK_REG_PAIR(r3); 7974 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7975 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7976 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7977 cpu_gpr_d[r3+1], temp, temp2, n); 7978 break; 7979 case OPC2_32_RRR1_MSUBR_H_64_UL: 7980 CHECK_REG_PAIR(r3); 7981 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7982 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7983 break; 7984 case OPC2_32_RRR1_MSUBRS_H_64_UL: 7985 CHECK_REG_PAIR(r3); 7986 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7987 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7988 break; 7989 case OPC2_32_RRR1_MSUBR_Q_32_LL: 7990 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7991 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7992 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7993 break; 7994 case OPC2_32_RRR1_MSUBR_Q_32_UU: 7995 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7996 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7997 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7998 break; 7999 case OPC2_32_RRR1_MSUBRS_Q_32_LL: 8000 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 8001 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 8002 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8003 break; 8004 case OPC2_32_RRR1_MSUBRS_Q_32_UU: 8005 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 8006 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 8007 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8008 break; 8009 default: 8010 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8011 } 8012 tcg_temp_free(temp); 8013 tcg_temp_free(temp2); 8014 } 8015 8016 static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx) 8017 { 8018 uint32_t op2; 8019 uint32_t r1, r2, r3, r4, n; 8020 8021 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 8022 r1 = MASK_OP_RRR1_S1(ctx->opcode); 8023 r2 = MASK_OP_RRR1_S2(ctx->opcode); 8024 r3 = MASK_OP_RRR1_S3(ctx->opcode); 8025 r4 = MASK_OP_RRR1_D(ctx->opcode); 8026 n = MASK_OP_RRR1_N(ctx->opcode); 8027 8028 switch (op2) { 8029 case OPC2_32_RRR1_MSUBAD_H_32_LL: 8030 CHECK_REG_PAIR(r4); 8031 CHECK_REG_PAIR(r3); 8032 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8033 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 8034 break; 8035 case OPC2_32_RRR1_MSUBAD_H_32_LU: 8036 CHECK_REG_PAIR(r4); 8037 CHECK_REG_PAIR(r3); 8038 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8039 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 8040 break; 8041 case OPC2_32_RRR1_MSUBAD_H_32_UL: 8042 CHECK_REG_PAIR(r4); 8043 CHECK_REG_PAIR(r3); 8044 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8045 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 8046 break; 8047 case OPC2_32_RRR1_MSUBAD_H_32_UU: 8048 CHECK_REG_PAIR(r4); 8049 CHECK_REG_PAIR(r3); 8050 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8051 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 8052 break; 8053 case OPC2_32_RRR1_MSUBADS_H_32_LL: 8054 CHECK_REG_PAIR(r4); 8055 CHECK_REG_PAIR(r3); 8056 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8057 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8058 n, MODE_LL); 8059 break; 8060 case OPC2_32_RRR1_MSUBADS_H_32_LU: 8061 CHECK_REG_PAIR(r4); 8062 CHECK_REG_PAIR(r3); 8063 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8064 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8065 n, MODE_LU); 8066 break; 8067 case OPC2_32_RRR1_MSUBADS_H_32_UL: 8068 CHECK_REG_PAIR(r4); 8069 CHECK_REG_PAIR(r3); 8070 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8071 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8072 n, MODE_UL); 8073 break; 8074 case OPC2_32_RRR1_MSUBADS_H_32_UU: 8075 CHECK_REG_PAIR(r4); 8076 CHECK_REG_PAIR(r3); 8077 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8078 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8079 n, MODE_UU); 8080 break; 8081 case OPC2_32_RRR1_MSUBADM_H_64_LL: 8082 CHECK_REG_PAIR(r4); 8083 CHECK_REG_PAIR(r3); 8084 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8085 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8086 n, MODE_LL); 8087 break; 8088 case OPC2_32_RRR1_MSUBADM_H_64_LU: 8089 CHECK_REG_PAIR(r4); 8090 CHECK_REG_PAIR(r3); 8091 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8092 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8093 n, MODE_LU); 8094 break; 8095 case OPC2_32_RRR1_MSUBADM_H_64_UL: 8096 CHECK_REG_PAIR(r4); 8097 CHECK_REG_PAIR(r3); 8098 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8099 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8100 n, MODE_UL); 8101 break; 8102 case OPC2_32_RRR1_MSUBADM_H_64_UU: 8103 CHECK_REG_PAIR(r4); 8104 CHECK_REG_PAIR(r3); 8105 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8106 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8107 n, MODE_UU); 8108 break; 8109 case OPC2_32_RRR1_MSUBADMS_H_64_LL: 8110 CHECK_REG_PAIR(r4); 8111 CHECK_REG_PAIR(r3); 8112 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8113 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8114 n, MODE_LL); 8115 break; 8116 case OPC2_32_RRR1_MSUBADMS_H_64_LU: 8117 CHECK_REG_PAIR(r4); 8118 CHECK_REG_PAIR(r3); 8119 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8120 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8121 n, MODE_LU); 8122 break; 8123 case OPC2_32_RRR1_MSUBADMS_H_64_UL: 8124 CHECK_REG_PAIR(r4); 8125 CHECK_REG_PAIR(r3); 8126 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8127 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8128 n, MODE_UL); 8129 break; 8130 case OPC2_32_RRR1_MSUBADMS_H_64_UU: 8131 CHECK_REG_PAIR(r4); 8132 CHECK_REG_PAIR(r3); 8133 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8134 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8135 n, MODE_UU); 8136 break; 8137 case OPC2_32_RRR1_MSUBADR_H_16_LL: 8138 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8139 cpu_gpr_d[r2], n, MODE_LL); 8140 break; 8141 case OPC2_32_RRR1_MSUBADR_H_16_LU: 8142 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8143 cpu_gpr_d[r2], n, MODE_LU); 8144 break; 8145 case OPC2_32_RRR1_MSUBADR_H_16_UL: 8146 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8147 cpu_gpr_d[r2], n, MODE_UL); 8148 break; 8149 case OPC2_32_RRR1_MSUBADR_H_16_UU: 8150 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8151 cpu_gpr_d[r2], n, MODE_UU); 8152 break; 8153 case OPC2_32_RRR1_MSUBADRS_H_16_LL: 8154 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8155 cpu_gpr_d[r2], n, MODE_LL); 8156 break; 8157 case OPC2_32_RRR1_MSUBADRS_H_16_LU: 8158 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8159 cpu_gpr_d[r2], n, MODE_LU); 8160 break; 8161 case OPC2_32_RRR1_MSUBADRS_H_16_UL: 8162 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8163 cpu_gpr_d[r2], n, MODE_UL); 8164 break; 8165 case OPC2_32_RRR1_MSUBADRS_H_16_UU: 8166 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8167 cpu_gpr_d[r2], n, MODE_UU); 8168 break; 8169 default: 8170 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8171 } 8172 } 8173 8174 /* RRRR format */ 8175 static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx) 8176 { 8177 uint32_t op2; 8178 int r1, r2, r3, r4; 8179 TCGv tmp_width, tmp_pos; 8180 8181 r1 = MASK_OP_RRRR_S1(ctx->opcode); 8182 r2 = MASK_OP_RRRR_S2(ctx->opcode); 8183 r3 = MASK_OP_RRRR_S3(ctx->opcode); 8184 r4 = MASK_OP_RRRR_D(ctx->opcode); 8185 op2 = MASK_OP_RRRR_OP2(ctx->opcode); 8186 8187 tmp_pos = tcg_temp_new(); 8188 tmp_width = tcg_temp_new(); 8189 8190 switch (op2) { 8191 case OPC2_32_RRRR_DEXTR: 8192 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 8193 if (r1 == r2) { 8194 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 8195 } else { 8196 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); 8197 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 8198 tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos); 8199 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos); 8200 } 8201 break; 8202 case OPC2_32_RRRR_EXTR: 8203 case OPC2_32_RRRR_EXTR_U: 8204 CHECK_REG_PAIR(r3); 8205 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 8206 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 8207 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); 8208 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 8209 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 8210 tcg_gen_subfi_tl(tmp_width, 32, tmp_width); 8211 if (op2 == OPC2_32_RRRR_EXTR) { 8212 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 8213 } else { 8214 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 8215 } 8216 break; 8217 case OPC2_32_RRRR_INSERT: 8218 CHECK_REG_PAIR(r3); 8219 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 8220 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 8221 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, 8222 tmp_pos); 8223 break; 8224 default: 8225 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8226 } 8227 tcg_temp_free(tmp_pos); 8228 tcg_temp_free(tmp_width); 8229 } 8230 8231 /* RRRW format */ 8232 static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) 8233 { 8234 uint32_t op2; 8235 int r1, r2, r3, r4; 8236 int32_t width; 8237 8238 TCGv temp, temp2; 8239 8240 op2 = MASK_OP_RRRW_OP2(ctx->opcode); 8241 r1 = MASK_OP_RRRW_S1(ctx->opcode); 8242 r2 = MASK_OP_RRRW_S2(ctx->opcode); 8243 r3 = MASK_OP_RRRW_S3(ctx->opcode); 8244 r4 = MASK_OP_RRRW_D(ctx->opcode); 8245 width = MASK_OP_RRRW_WIDTH(ctx->opcode); 8246 8247 temp = tcg_temp_new(); 8248 8249 switch (op2) { 8250 case OPC2_32_RRRW_EXTR: 8251 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 8252 tcg_gen_addi_tl(temp, temp, width); 8253 tcg_gen_subfi_tl(temp, 32, temp); 8254 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 8255 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); 8256 break; 8257 case OPC2_32_RRRW_EXTR_U: 8258 if (width == 0) { 8259 tcg_gen_movi_tl(cpu_gpr_d[r4], 0); 8260 } else { 8261 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 8262 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 8263 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); 8264 } 8265 break; 8266 case OPC2_32_RRRW_IMASK: 8267 temp2 = tcg_temp_new(); 8268 8269 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 8270 tcg_gen_movi_tl(temp2, (1 << width) - 1); 8271 tcg_gen_shl_tl(temp2, temp2, temp); 8272 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); 8273 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); 8274 8275 tcg_temp_free(temp2); 8276 break; 8277 case OPC2_32_RRRW_INSERT: 8278 temp2 = tcg_temp_new(); 8279 8280 tcg_gen_movi_tl(temp, width); 8281 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); 8282 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); 8283 8284 tcg_temp_free(temp2); 8285 break; 8286 default: 8287 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8288 } 8289 tcg_temp_free(temp); 8290 } 8291 8292 /* SYS Format*/ 8293 static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) 8294 { 8295 uint32_t op2; 8296 uint32_t r1; 8297 TCGLabel *l1; 8298 TCGv tmp; 8299 8300 op2 = MASK_OP_SYS_OP2(ctx->opcode); 8301 r1 = MASK_OP_SYS_S1D(ctx->opcode); 8302 8303 switch (op2) { 8304 case OPC2_32_SYS_DEBUG: 8305 /* raise EXCP_DEBUG */ 8306 break; 8307 case OPC2_32_SYS_DISABLE: 8308 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE); 8309 break; 8310 case OPC2_32_SYS_DSYNC: 8311 break; 8312 case OPC2_32_SYS_ENABLE: 8313 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE); 8314 break; 8315 case OPC2_32_SYS_ISYNC: 8316 break; 8317 case OPC2_32_SYS_NOP: 8318 break; 8319 case OPC2_32_SYS_RET: 8320 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 8321 break; 8322 case OPC2_32_SYS_FRET: 8323 gen_fret(ctx); 8324 break; 8325 case OPC2_32_SYS_RFE: 8326 gen_helper_rfe(cpu_env); 8327 tcg_gen_exit_tb(0); 8328 ctx->bstate = BS_BRANCH; 8329 break; 8330 case OPC2_32_SYS_RFM: 8331 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 8332 tmp = tcg_temp_new(); 8333 l1 = gen_new_label(); 8334 8335 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR)); 8336 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); 8337 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); 8338 gen_helper_rfm(cpu_env); 8339 gen_set_label(l1); 8340 tcg_gen_exit_tb(0); 8341 ctx->bstate = BS_BRANCH; 8342 tcg_temp_free(tmp); 8343 } else { 8344 /* generate privilege trap */ 8345 } 8346 break; 8347 case OPC2_32_SYS_RSLCX: 8348 gen_helper_rslcx(cpu_env); 8349 break; 8350 case OPC2_32_SYS_SVLCX: 8351 gen_helper_svlcx(cpu_env); 8352 break; 8353 case OPC2_32_SYS_RESTORE: 8354 if (tricore_feature(env, TRICORE_FEATURE_16)) { 8355 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM || 8356 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) { 8357 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); 8358 } /* else raise privilege trap */ 8359 } else { 8360 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8361 } 8362 break; 8363 case OPC2_32_SYS_TRAPSV: 8364 l1 = gen_new_label(); 8365 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); 8366 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); 8367 gen_set_label(l1); 8368 break; 8369 case OPC2_32_SYS_TRAPV: 8370 l1 = gen_new_label(); 8371 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); 8372 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); 8373 gen_set_label(l1); 8374 break; 8375 default: 8376 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8377 } 8378 } 8379 8380 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) 8381 { 8382 int op1; 8383 int32_t r1, r2, r3; 8384 int32_t address, const16; 8385 int8_t b, const4; 8386 int32_t bpos; 8387 TCGv temp, temp2, temp3; 8388 8389 op1 = MASK_OP_MAJOR(ctx->opcode); 8390 8391 /* handle JNZ.T opcode only being 7 bit long */ 8392 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { 8393 op1 = OPCM_32_BRN_JTT; 8394 } 8395 8396 switch (op1) { 8397 /* ABS-format */ 8398 case OPCM_32_ABS_LDW: 8399 decode_abs_ldw(env, ctx); 8400 break; 8401 case OPCM_32_ABS_LDB: 8402 decode_abs_ldb(env, ctx); 8403 break; 8404 case OPCM_32_ABS_LDMST_SWAP: 8405 decode_abs_ldst_swap(env, ctx); 8406 break; 8407 case OPCM_32_ABS_LDST_CONTEXT: 8408 decode_abs_ldst_context(env, ctx); 8409 break; 8410 case OPCM_32_ABS_STORE: 8411 decode_abs_store(env, ctx); 8412 break; 8413 case OPCM_32_ABS_STOREB_H: 8414 decode_abs_storeb_h(env, ctx); 8415 break; 8416 case OPC1_32_ABS_STOREQ: 8417 address = MASK_OP_ABS_OFF18(ctx->opcode); 8418 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8419 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 8420 temp2 = tcg_temp_new(); 8421 8422 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); 8423 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); 8424 8425 tcg_temp_free(temp2); 8426 tcg_temp_free(temp); 8427 break; 8428 case OPC1_32_ABS_LD_Q: 8429 address = MASK_OP_ABS_OFF18(ctx->opcode); 8430 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8431 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 8432 8433 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 8434 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 8435 8436 tcg_temp_free(temp); 8437 break; 8438 case OPC1_32_ABS_LEA: 8439 address = MASK_OP_ABS_OFF18(ctx->opcode); 8440 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8441 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); 8442 break; 8443 /* ABSB-format */ 8444 case OPC1_32_ABSB_ST_T: 8445 address = MASK_OP_ABS_OFF18(ctx->opcode); 8446 b = MASK_OP_ABSB_B(ctx->opcode); 8447 bpos = MASK_OP_ABSB_BPOS(ctx->opcode); 8448 8449 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 8450 temp2 = tcg_temp_new(); 8451 8452 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); 8453 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); 8454 tcg_gen_ori_tl(temp2, temp2, (b << bpos)); 8455 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); 8456 8457 tcg_temp_free(temp); 8458 tcg_temp_free(temp2); 8459 break; 8460 /* B-format */ 8461 case OPC1_32_B_CALL: 8462 case OPC1_32_B_CALLA: 8463 case OPC1_32_B_FCALL: 8464 case OPC1_32_B_FCALLA: 8465 case OPC1_32_B_J: 8466 case OPC1_32_B_JA: 8467 case OPC1_32_B_JL: 8468 case OPC1_32_B_JLA: 8469 address = MASK_OP_B_DISP24_SEXT(ctx->opcode); 8470 gen_compute_branch(ctx, op1, 0, 0, 0, address); 8471 break; 8472 /* Bit-format */ 8473 case OPCM_32_BIT_ANDACC: 8474 decode_bit_andacc(env, ctx); 8475 break; 8476 case OPCM_32_BIT_LOGICAL_T1: 8477 decode_bit_logical_t(env, ctx); 8478 break; 8479 case OPCM_32_BIT_INSERT: 8480 decode_bit_insert(env, ctx); 8481 break; 8482 case OPCM_32_BIT_LOGICAL_T2: 8483 decode_bit_logical_t2(env, ctx); 8484 break; 8485 case OPCM_32_BIT_ORAND: 8486 decode_bit_orand(env, ctx); 8487 break; 8488 case OPCM_32_BIT_SH_LOGIC1: 8489 decode_bit_sh_logic1(env, ctx); 8490 break; 8491 case OPCM_32_BIT_SH_LOGIC2: 8492 decode_bit_sh_logic2(env, ctx); 8493 break; 8494 /* BO Format */ 8495 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: 8496 decode_bo_addrmode_post_pre_base(env, ctx); 8497 break; 8498 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: 8499 decode_bo_addrmode_bitreverse_circular(env, ctx); 8500 break; 8501 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: 8502 decode_bo_addrmode_ld_post_pre_base(env, ctx); 8503 break; 8504 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: 8505 decode_bo_addrmode_ld_bitreverse_circular(env, ctx); 8506 break; 8507 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: 8508 decode_bo_addrmode_stctx_post_pre_base(env, ctx); 8509 break; 8510 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: 8511 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx); 8512 break; 8513 /* BOL-format */ 8514 case OPC1_32_BOL_LD_A_LONGOFF: 8515 case OPC1_32_BOL_LD_W_LONGOFF: 8516 case OPC1_32_BOL_LEA_LONGOFF: 8517 case OPC1_32_BOL_ST_W_LONGOFF: 8518 case OPC1_32_BOL_ST_A_LONGOFF: 8519 case OPC1_32_BOL_LD_B_LONGOFF: 8520 case OPC1_32_BOL_LD_BU_LONGOFF: 8521 case OPC1_32_BOL_LD_H_LONGOFF: 8522 case OPC1_32_BOL_LD_HU_LONGOFF: 8523 case OPC1_32_BOL_ST_B_LONGOFF: 8524 case OPC1_32_BOL_ST_H_LONGOFF: 8525 decode_bol_opc(env, ctx, op1); 8526 break; 8527 /* BRC Format */ 8528 case OPCM_32_BRC_EQ_NEQ: 8529 case OPCM_32_BRC_GE: 8530 case OPCM_32_BRC_JLT: 8531 case OPCM_32_BRC_JNE: 8532 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); 8533 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); 8534 r1 = MASK_OP_BRC_S1(ctx->opcode); 8535 gen_compute_branch(ctx, op1, r1, 0, const4, address); 8536 break; 8537 /* BRN Format */ 8538 case OPCM_32_BRN_JTT: 8539 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); 8540 r1 = MASK_OP_BRN_S1(ctx->opcode); 8541 gen_compute_branch(ctx, op1, r1, 0, 0, address); 8542 break; 8543 /* BRR Format */ 8544 case OPCM_32_BRR_EQ_NEQ: 8545 case OPCM_32_BRR_ADDR_EQ_NEQ: 8546 case OPCM_32_BRR_GE: 8547 case OPCM_32_BRR_JLT: 8548 case OPCM_32_BRR_JNE: 8549 case OPCM_32_BRR_JNZ: 8550 case OPCM_32_BRR_LOOP: 8551 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); 8552 r2 = MASK_OP_BRR_S2(ctx->opcode); 8553 r1 = MASK_OP_BRR_S1(ctx->opcode); 8554 gen_compute_branch(ctx, op1, r1, r2, 0, address); 8555 break; 8556 /* RC Format */ 8557 case OPCM_32_RC_LOGICAL_SHIFT: 8558 decode_rc_logical_shift(env, ctx); 8559 break; 8560 case OPCM_32_RC_ACCUMULATOR: 8561 decode_rc_accumulator(env, ctx); 8562 break; 8563 case OPCM_32_RC_SERVICEROUTINE: 8564 decode_rc_serviceroutine(env, ctx); 8565 break; 8566 case OPCM_32_RC_MUL: 8567 decode_rc_mul(env, ctx); 8568 break; 8569 /* RCPW Format */ 8570 case OPCM_32_RCPW_MASK_INSERT: 8571 decode_rcpw_insert(env, ctx); 8572 break; 8573 /* RCRR Format */ 8574 case OPC1_32_RCRR_INSERT: 8575 r1 = MASK_OP_RCRR_S1(ctx->opcode); 8576 r2 = MASK_OP_RCRR_S3(ctx->opcode); 8577 r3 = MASK_OP_RCRR_D(ctx->opcode); 8578 const16 = MASK_OP_RCRR_CONST4(ctx->opcode); 8579 temp = tcg_const_i32(const16); 8580 temp2 = tcg_temp_new(); /* width*/ 8581 temp3 = tcg_temp_new(); /* pos */ 8582 8583 CHECK_REG_PAIR(r3); 8584 8585 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f); 8586 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 8587 8588 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); 8589 8590 tcg_temp_free(temp); 8591 tcg_temp_free(temp2); 8592 tcg_temp_free(temp3); 8593 break; 8594 /* RCRW Format */ 8595 case OPCM_32_RCRW_MASK_INSERT: 8596 decode_rcrw_insert(env, ctx); 8597 break; 8598 /* RCR Format */ 8599 case OPCM_32_RCR_COND_SELECT: 8600 decode_rcr_cond_select(env, ctx); 8601 break; 8602 case OPCM_32_RCR_MADD: 8603 decode_rcr_madd(env, ctx); 8604 break; 8605 case OPCM_32_RCR_MSUB: 8606 decode_rcr_msub(env, ctx); 8607 break; 8608 /* RLC Format */ 8609 case OPC1_32_RLC_ADDI: 8610 case OPC1_32_RLC_ADDIH: 8611 case OPC1_32_RLC_ADDIH_A: 8612 case OPC1_32_RLC_MFCR: 8613 case OPC1_32_RLC_MOV: 8614 case OPC1_32_RLC_MOV_64: 8615 case OPC1_32_RLC_MOV_U: 8616 case OPC1_32_RLC_MOV_H: 8617 case OPC1_32_RLC_MOVH_A: 8618 case OPC1_32_RLC_MTCR: 8619 decode_rlc_opc(env, ctx, op1); 8620 break; 8621 /* RR Format */ 8622 case OPCM_32_RR_ACCUMULATOR: 8623 decode_rr_accumulator(env, ctx); 8624 break; 8625 case OPCM_32_RR_LOGICAL_SHIFT: 8626 decode_rr_logical_shift(env, ctx); 8627 break; 8628 case OPCM_32_RR_ADDRESS: 8629 decode_rr_address(env, ctx); 8630 break; 8631 case OPCM_32_RR_IDIRECT: 8632 decode_rr_idirect(env, ctx); 8633 break; 8634 case OPCM_32_RR_DIVIDE: 8635 decode_rr_divide(env, ctx); 8636 break; 8637 /* RR1 Format */ 8638 case OPCM_32_RR1_MUL: 8639 decode_rr1_mul(env, ctx); 8640 break; 8641 case OPCM_32_RR1_MULQ: 8642 decode_rr1_mulq(env, ctx); 8643 break; 8644 /* RR2 format */ 8645 case OPCM_32_RR2_MUL: 8646 decode_rr2_mul(env, ctx); 8647 break; 8648 /* RRPW format */ 8649 case OPCM_32_RRPW_EXTRACT_INSERT: 8650 decode_rrpw_extract_insert(env, ctx); 8651 break; 8652 case OPC1_32_RRPW_DEXTR: 8653 r1 = MASK_OP_RRPW_S1(ctx->opcode); 8654 r2 = MASK_OP_RRPW_S2(ctx->opcode); 8655 r3 = MASK_OP_RRPW_D(ctx->opcode); 8656 const16 = MASK_OP_RRPW_POS(ctx->opcode); 8657 if (r1 == r2) { 8658 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16); 8659 } else { 8660 temp = tcg_temp_new(); 8661 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16); 8662 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16); 8663 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 8664 tcg_temp_free(temp); 8665 } 8666 break; 8667 /* RRR Format */ 8668 case OPCM_32_RRR_COND_SELECT: 8669 decode_rrr_cond_select(env, ctx); 8670 break; 8671 case OPCM_32_RRR_DIVIDE: 8672 decode_rrr_divide(env, ctx); 8673 break; 8674 /* RRR2 Format */ 8675 case OPCM_32_RRR2_MADD: 8676 decode_rrr2_madd(env, ctx); 8677 break; 8678 case OPCM_32_RRR2_MSUB: 8679 decode_rrr2_msub(env, ctx); 8680 break; 8681 /* RRR1 format */ 8682 case OPCM_32_RRR1_MADD: 8683 decode_rrr1_madd(env, ctx); 8684 break; 8685 case OPCM_32_RRR1_MADDQ_H: 8686 decode_rrr1_maddq_h(env, ctx); 8687 break; 8688 case OPCM_32_RRR1_MADDSU_H: 8689 decode_rrr1_maddsu_h(env, ctx); 8690 break; 8691 case OPCM_32_RRR1_MSUB_H: 8692 decode_rrr1_msub(env, ctx); 8693 break; 8694 case OPCM_32_RRR1_MSUB_Q: 8695 decode_rrr1_msubq_h(env, ctx); 8696 break; 8697 case OPCM_32_RRR1_MSUBAD_H: 8698 decode_rrr1_msubad_h(env, ctx); 8699 break; 8700 /* RRRR format */ 8701 case OPCM_32_RRRR_EXTRACT_INSERT: 8702 decode_rrrr_extract_insert(env, ctx); 8703 break; 8704 /* RRRW format */ 8705 case OPCM_32_RRRW_EXTRACT_INSERT: 8706 decode_rrrw_extract_insert(env, ctx); 8707 break; 8708 /* SYS format */ 8709 case OPCM_32_SYS_INTERRUPTS: 8710 decode_sys_interrupts(env, ctx); 8711 break; 8712 case OPC1_32_SYS_RSTV: 8713 tcg_gen_movi_tl(cpu_PSW_V, 0); 8714 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); 8715 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 8716 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); 8717 break; 8718 default: 8719 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8720 } 8721 } 8722 8723 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch) 8724 { 8725 /* 16-Bit Instruction */ 8726 if ((ctx->opcode & 0x1) == 0) { 8727 ctx->next_pc = ctx->pc + 2; 8728 decode_16Bit_opc(env, ctx); 8729 /* 32-Bit Instruction */ 8730 } else { 8731 ctx->next_pc = ctx->pc + 4; 8732 decode_32Bit_opc(env, ctx); 8733 } 8734 } 8735 8736 void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb) 8737 { 8738 TriCoreCPU *cpu = tricore_env_get_cpu(env); 8739 CPUState *cs = CPU(cpu); 8740 DisasContext ctx; 8741 target_ulong pc_start; 8742 int num_insns, max_insns; 8743 8744 num_insns = 0; 8745 max_insns = tb->cflags & CF_COUNT_MASK; 8746 if (max_insns == 0) { 8747 max_insns = CF_COUNT_MASK; 8748 } 8749 if (singlestep) { 8750 max_insns = 1; 8751 } 8752 if (max_insns > TCG_MAX_INSNS) { 8753 max_insns = TCG_MAX_INSNS; 8754 } 8755 8756 pc_start = tb->pc; 8757 ctx.pc = pc_start; 8758 ctx.saved_pc = -1; 8759 ctx.tb = tb; 8760 ctx.singlestep_enabled = cs->singlestep_enabled; 8761 ctx.bstate = BS_NONE; 8762 ctx.mem_idx = cpu_mmu_index(env, false); 8763 8764 tcg_clear_temp_count(); 8765 gen_tb_start(tb); 8766 while (ctx.bstate == BS_NONE) { 8767 tcg_gen_insn_start(ctx.pc); 8768 num_insns++; 8769 8770 ctx.opcode = cpu_ldl_code(env, ctx.pc); 8771 decode_opc(env, &ctx, 0); 8772 8773 if (num_insns >= max_insns || tcg_op_buf_full()) { 8774 gen_save_pc(ctx.next_pc); 8775 tcg_gen_exit_tb(0); 8776 break; 8777 } 8778 ctx.pc = ctx.next_pc; 8779 } 8780 8781 gen_tb_end(tb, num_insns); 8782 tb->size = ctx.pc - pc_start; 8783 tb->icount = num_insns; 8784 8785 if (tcg_check_temp_count()) { 8786 printf("LEAK at %08x\n", env->PC); 8787 } 8788 8789 #ifdef DEBUG_DISAS 8790 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 8791 && qemu_log_in_addr_range(pc_start)) { 8792 qemu_log_lock(); 8793 qemu_log("IN: %s\n", lookup_symbol(pc_start)); 8794 log_target_disas(cs, pc_start, ctx.pc - pc_start, 0); 8795 qemu_log("\n"); 8796 qemu_log_unlock(); 8797 } 8798 #endif 8799 } 8800 8801 void 8802 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, 8803 target_ulong *data) 8804 { 8805 env->PC = data[0]; 8806 } 8807 /* 8808 * 8809 * Initialization 8810 * 8811 */ 8812 8813 void cpu_state_reset(CPUTriCoreState *env) 8814 { 8815 /* Reset Regs to Default Value */ 8816 env->PSW = 0xb80; 8817 fpu_set_state(env); 8818 } 8819 8820 static void tricore_tcg_init_csfr(void) 8821 { 8822 cpu_PCXI = tcg_global_mem_new(cpu_env, 8823 offsetof(CPUTriCoreState, PCXI), "PCXI"); 8824 cpu_PSW = tcg_global_mem_new(cpu_env, 8825 offsetof(CPUTriCoreState, PSW), "PSW"); 8826 cpu_PC = tcg_global_mem_new(cpu_env, 8827 offsetof(CPUTriCoreState, PC), "PC"); 8828 cpu_ICR = tcg_global_mem_new(cpu_env, 8829 offsetof(CPUTriCoreState, ICR), "ICR"); 8830 } 8831 8832 void tricore_tcg_init(void) 8833 { 8834 int i; 8835 static int inited; 8836 if (inited) { 8837 return; 8838 } 8839 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 8840 tcg_ctx.tcg_env = cpu_env; 8841 /* reg init */ 8842 for (i = 0 ; i < 16 ; i++) { 8843 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, 8844 offsetof(CPUTriCoreState, gpr_a[i]), 8845 regnames_a[i]); 8846 } 8847 for (i = 0 ; i < 16 ; i++) { 8848 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env, 8849 offsetof(CPUTriCoreState, gpr_d[i]), 8850 regnames_d[i]); 8851 } 8852 tricore_tcg_init_csfr(); 8853 /* init PSW flag cache */ 8854 cpu_PSW_C = tcg_global_mem_new(cpu_env, 8855 offsetof(CPUTriCoreState, PSW_USB_C), 8856 "PSW_C"); 8857 cpu_PSW_V = tcg_global_mem_new(cpu_env, 8858 offsetof(CPUTriCoreState, PSW_USB_V), 8859 "PSW_V"); 8860 cpu_PSW_SV = tcg_global_mem_new(cpu_env, 8861 offsetof(CPUTriCoreState, PSW_USB_SV), 8862 "PSW_SV"); 8863 cpu_PSW_AV = tcg_global_mem_new(cpu_env, 8864 offsetof(CPUTriCoreState, PSW_USB_AV), 8865 "PSW_AV"); 8866 cpu_PSW_SAV = tcg_global_mem_new(cpu_env, 8867 offsetof(CPUTriCoreState, PSW_USB_SAV), 8868 "PSW_SAV"); 8869 } 8870