1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "disas/disas.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "exec/cpu_ldst.h" 27 #include "qemu/qemu-print.h" 28 29 #include "exec/helper-proto.h" 30 #include "exec/helper-gen.h" 31 32 #include "tricore-opcodes.h" 33 #include "exec/translator.h" 34 #include "exec/log.h" 35 36 #define HELPER_H "helper.h" 37 #include "exec/helper-info.c.inc" 38 #undef HELPER_H 39 40 #define DISAS_EXIT DISAS_TARGET_0 41 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 42 #define DISAS_JUMP DISAS_TARGET_2 43 44 /* 45 * TCG registers 46 */ 47 static TCGv cpu_PC; 48 static TCGv cpu_PCXI; 49 static TCGv cpu_PSW; 50 static TCGv cpu_ICR; 51 /* GPR registers */ 52 static TCGv cpu_gpr_a[16]; 53 static TCGv cpu_gpr_d[16]; 54 /* PSW Flag cache */ 55 static TCGv cpu_PSW_C; 56 static TCGv cpu_PSW_V; 57 static TCGv cpu_PSW_SV; 58 static TCGv cpu_PSW_AV; 59 static TCGv cpu_PSW_SAV; 60 61 static const char *regnames_a[] = { 62 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , 63 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , 64 "a12" , "a13" , "a14" , "a15", 65 }; 66 67 static const char *regnames_d[] = { 68 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , 69 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , 70 "d12" , "d13" , "d14" , "d15", 71 }; 72 73 typedef struct DisasContext { 74 DisasContextBase base; 75 target_ulong pc_succ_insn; 76 uint32_t opcode; 77 /* Routine used to access memory */ 78 int mem_idx; 79 int priv; 80 uint64_t features; 81 uint32_t icr_ie_mask, icr_ie_offset; 82 } DisasContext; 83 84 static int has_feature(DisasContext *ctx, int feature) 85 { 86 return (ctx->features & (1ULL << feature)) != 0; 87 } 88 89 enum { 90 MODE_LL = 0, 91 MODE_LU = 1, 92 MODE_UL = 2, 93 MODE_UU = 3, 94 }; 95 96 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) 97 { 98 TriCoreCPU *cpu = TRICORE_CPU(cs); 99 CPUTriCoreState *env = &cpu->env; 100 uint32_t psw; 101 int i; 102 103 psw = psw_read(env); 104 105 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); 106 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); 107 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); 108 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); 109 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); 110 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); 111 112 for (i = 0; i < 16; ++i) { 113 if ((i & 3) == 0) { 114 qemu_fprintf(f, "\nGPR A%02d:", i); 115 } 116 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); 117 } 118 for (i = 0; i < 16; ++i) { 119 if ((i & 3) == 0) { 120 qemu_fprintf(f, "\nGPR D%02d:", i); 121 } 122 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); 123 } 124 qemu_fprintf(f, "\n"); 125 } 126 127 /* 128 * Functions to generate micro-ops 129 */ 130 131 /* Macros for generating helpers */ 132 133 #define gen_helper_1arg(name, arg) do { \ 134 TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ 135 gen_helper_##name(cpu_env, helper_tmp); \ 136 } while (0) 137 138 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ 139 TCGv arg00 = tcg_temp_new(); \ 140 TCGv arg01 = tcg_temp_new(); \ 141 TCGv arg11 = tcg_temp_new(); \ 142 tcg_gen_sari_tl(arg00, arg0, 16); \ 143 tcg_gen_ext16s_tl(arg01, arg0); \ 144 tcg_gen_ext16s_tl(arg11, arg1); \ 145 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 146 } while (0) 147 148 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ 149 TCGv arg00 = tcg_temp_new(); \ 150 TCGv arg01 = tcg_temp_new(); \ 151 TCGv arg10 = tcg_temp_new(); \ 152 TCGv arg11 = tcg_temp_new(); \ 153 tcg_gen_sari_tl(arg00, arg0, 16); \ 154 tcg_gen_ext16s_tl(arg01, arg0); \ 155 tcg_gen_sari_tl(arg11, arg1, 16); \ 156 tcg_gen_ext16s_tl(arg10, arg1); \ 157 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 158 } while (0) 159 160 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ 161 TCGv arg00 = tcg_temp_new(); \ 162 TCGv arg01 = tcg_temp_new(); \ 163 TCGv arg10 = tcg_temp_new(); \ 164 TCGv arg11 = tcg_temp_new(); \ 165 tcg_gen_sari_tl(arg00, arg0, 16); \ 166 tcg_gen_ext16s_tl(arg01, arg0); \ 167 tcg_gen_sari_tl(arg10, arg1, 16); \ 168 tcg_gen_ext16s_tl(arg11, arg1); \ 169 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 170 } while (0) 171 172 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ 173 TCGv arg00 = tcg_temp_new(); \ 174 TCGv arg01 = tcg_temp_new(); \ 175 TCGv arg11 = tcg_temp_new(); \ 176 tcg_gen_sari_tl(arg01, arg0, 16); \ 177 tcg_gen_ext16s_tl(arg00, arg0); \ 178 tcg_gen_sari_tl(arg11, arg1, 16); \ 179 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 180 } while (0) 181 182 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ 183 TCGv_i64 ret = tcg_temp_new_i64(); \ 184 TCGv_i64 arg1 = tcg_temp_new_i64(); \ 185 \ 186 tcg_gen_concat_i32_i64(arg1, al1, ah1); \ 187 gen_helper_##name(ret, arg1, arg2); \ 188 tcg_gen_extr_i64_i32(rl, rh, ret); \ 189 } while (0) 190 191 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ 192 TCGv_i64 ret = tcg_temp_new_i64(); \ 193 \ 194 gen_helper_##name(ret, cpu_env, arg1, arg2); \ 195 tcg_gen_extr_i64_i32(rl, rh, ret); \ 196 } while (0) 197 198 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) 199 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ 200 ((offset & 0x0fffff) << 1)) 201 202 /* For two 32-bit registers used a 64-bit register, the first 203 registernumber needs to be even. Otherwise we trap. */ 204 static inline void generate_trap(DisasContext *ctx, int class, int tin); 205 #define CHECK_REG_PAIR(reg) do { \ 206 if (reg & 0x1) { \ 207 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ 208 } \ 209 } while (0) 210 211 /* Functions for load/save to/from memory */ 212 213 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, 214 int16_t con, MemOp mop) 215 { 216 TCGv temp = tcg_temp_new(); 217 tcg_gen_addi_tl(temp, r2, con); 218 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 219 } 220 221 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, 222 int16_t con, MemOp mop) 223 { 224 TCGv temp = tcg_temp_new(); 225 tcg_gen_addi_tl(temp, r2, con); 226 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 227 } 228 229 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 230 { 231 TCGv_i64 temp = tcg_temp_new_i64(); 232 233 tcg_gen_concat_i32_i64(temp, rl, rh); 234 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); 235 } 236 237 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 238 DisasContext *ctx) 239 { 240 TCGv temp = tcg_temp_new(); 241 tcg_gen_addi_tl(temp, base, con); 242 gen_st_2regs_64(rh, rl, temp, ctx); 243 } 244 245 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 246 { 247 TCGv_i64 temp = tcg_temp_new_i64(); 248 249 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ); 250 /* write back to two 32 bit regs */ 251 tcg_gen_extr_i64_i32(rl, rh, temp); 252 } 253 254 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 255 DisasContext *ctx) 256 { 257 TCGv temp = tcg_temp_new(); 258 tcg_gen_addi_tl(temp, base, con); 259 gen_ld_2regs_64(rh, rl, temp, ctx); 260 } 261 262 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 263 MemOp mop) 264 { 265 TCGv temp = tcg_temp_new(); 266 tcg_gen_addi_tl(temp, r2, off); 267 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 268 tcg_gen_mov_tl(r2, temp); 269 } 270 271 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 272 MemOp mop) 273 { 274 TCGv temp = tcg_temp_new(); 275 tcg_gen_addi_tl(temp, r2, off); 276 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 277 tcg_gen_mov_tl(r2, temp); 278 } 279 280 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ 281 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) 282 { 283 TCGv temp = tcg_temp_new(); 284 TCGv temp2 = tcg_temp_new(); 285 286 CHECK_REG_PAIR(ereg); 287 /* temp = (M(EA, word) */ 288 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 289 /* temp = temp & ~E[a][63:32]) */ 290 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); 291 /* temp2 = (E[a][31:0] & E[a][63:32]); */ 292 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); 293 /* temp = temp | temp2; */ 294 tcg_gen_or_tl(temp, temp, temp2); 295 /* M(EA, word) = temp; */ 296 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); 297 } 298 299 /* tmp = M(EA, word); 300 M(EA, word) = D[a]; 301 D[a] = tmp[31:0];*/ 302 static void gen_swap(DisasContext *ctx, int reg, TCGv ea) 303 { 304 TCGv temp = tcg_temp_new(); 305 306 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 307 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); 308 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 309 } 310 311 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) 312 { 313 TCGv temp = tcg_temp_new(); 314 TCGv temp2 = tcg_temp_new(); 315 CHECK_REG_PAIR(reg); 316 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 317 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, 318 cpu_gpr_d[reg], temp); 319 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 320 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 321 } 322 323 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) 324 { 325 TCGv temp = tcg_temp_new(); 326 TCGv temp2 = tcg_temp_new(); 327 TCGv temp3 = tcg_temp_new(); 328 CHECK_REG_PAIR(reg); 329 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 330 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); 331 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); 332 tcg_gen_or_tl(temp2, temp2, temp3); 333 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 334 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 335 } 336 337 /* We generate loads and store to core special function register (csfr) through 338 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 339 macros R, A and E, which allow read-only, all and endinit protected access. 340 These macros also specify in which ISA version the csfr was introduced. */ 341 #define R(ADDRESS, REG, FEATURE) \ 342 case ADDRESS: \ 343 if (has_feature(ctx, FEATURE)) { \ 344 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ 345 } \ 346 break; 347 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 348 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 349 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) 350 { 351 /* since we're caching PSW make this a special case */ 352 if (offset == 0xfe04) { 353 gen_helper_psw_read(ret, cpu_env); 354 } else { 355 switch (offset) { 356 #include "csfr.h.inc" 357 } 358 } 359 } 360 #undef R 361 #undef A 362 #undef E 363 364 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, 365 since no exception occurs */ 366 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ 367 case ADDRESS: \ 368 if (has_feature(ctx, FEATURE)) { \ 369 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ 370 } \ 371 break; 372 /* Endinit protected registers 373 TODO: Since the endinit bit is in a register of a not yet implemented 374 watchdog device, we handle endinit protected registers like 375 all-access registers for now. */ 376 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) 377 static inline void gen_mtcr(DisasContext *ctx, TCGv r1, 378 int32_t offset) 379 { 380 if (ctx->priv == TRICORE_PRIV_SM) { 381 /* since we're caching PSW make this a special case */ 382 if (offset == 0xfe04) { 383 gen_helper_psw_write(cpu_env, r1); 384 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 385 } else { 386 switch (offset) { 387 #include "csfr.h.inc" 388 } 389 } 390 } else { 391 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 392 } 393 } 394 395 /* Functions for arithmetic instructions */ 396 397 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) 398 { 399 TCGv t0 = tcg_temp_new_i32(); 400 TCGv result = tcg_temp_new_i32(); 401 /* Addition and set V/SV bits */ 402 tcg_gen_add_tl(result, r1, r2); 403 /* calc V bit */ 404 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 405 tcg_gen_xor_tl(t0, r1, r2); 406 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 407 /* Calc SV bit */ 408 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 409 /* Calc AV/SAV bits */ 410 tcg_gen_add_tl(cpu_PSW_AV, result, result); 411 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 412 /* calc SAV */ 413 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 414 /* write back result */ 415 tcg_gen_mov_tl(ret, result); 416 } 417 418 static inline void 419 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 420 { 421 TCGv temp = tcg_temp_new(); 422 TCGv_i64 t0 = tcg_temp_new_i64(); 423 TCGv_i64 t1 = tcg_temp_new_i64(); 424 TCGv_i64 result = tcg_temp_new_i64(); 425 426 tcg_gen_add_i64(result, r1, r2); 427 /* calc v bit */ 428 tcg_gen_xor_i64(t1, result, r1); 429 tcg_gen_xor_i64(t0, r1, r2); 430 tcg_gen_andc_i64(t1, t1, t0); 431 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 432 /* calc SV bit */ 433 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 434 /* calc AV/SAV bits */ 435 tcg_gen_extrh_i64_i32(temp, result); 436 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 437 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 438 /* calc SAV */ 439 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 440 /* write back result */ 441 tcg_gen_mov_i64(ret, result); 442 } 443 444 static inline void 445 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 446 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), 447 void(*op2)(TCGv, TCGv, TCGv)) 448 { 449 TCGv temp = tcg_temp_new(); 450 TCGv temp2 = tcg_temp_new(); 451 TCGv temp3 = tcg_temp_new(); 452 TCGv temp4 = tcg_temp_new(); 453 454 (*op1)(temp, r1_low, r2); 455 /* calc V0 bit */ 456 tcg_gen_xor_tl(temp2, temp, r1_low); 457 tcg_gen_xor_tl(temp3, r1_low, r2); 458 if (op1 == tcg_gen_add_tl) { 459 tcg_gen_andc_tl(temp2, temp2, temp3); 460 } else { 461 tcg_gen_and_tl(temp2, temp2, temp3); 462 } 463 464 (*op2)(temp3, r1_high, r3); 465 /* calc V1 bit */ 466 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); 467 tcg_gen_xor_tl(temp4, r1_high, r3); 468 if (op2 == tcg_gen_add_tl) { 469 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); 470 } else { 471 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); 472 } 473 /* combine V0/V1 bits */ 474 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); 475 /* calc sv bit */ 476 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 477 /* write result */ 478 tcg_gen_mov_tl(ret_low, temp); 479 tcg_gen_mov_tl(ret_high, temp3); 480 /* calc AV bit */ 481 tcg_gen_add_tl(temp, ret_low, ret_low); 482 tcg_gen_xor_tl(temp, temp, ret_low); 483 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 484 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); 485 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 486 /* calc SAV bit */ 487 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 488 } 489 490 /* ret = r2 + (r1 * r3); */ 491 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 492 { 493 TCGv_i64 t1 = tcg_temp_new_i64(); 494 TCGv_i64 t2 = tcg_temp_new_i64(); 495 TCGv_i64 t3 = tcg_temp_new_i64(); 496 497 tcg_gen_ext_i32_i64(t1, r1); 498 tcg_gen_ext_i32_i64(t2, r2); 499 tcg_gen_ext_i32_i64(t3, r3); 500 501 tcg_gen_mul_i64(t1, t1, t3); 502 tcg_gen_add_i64(t1, t2, t1); 503 504 tcg_gen_extrl_i64_i32(ret, t1); 505 /* calc V 506 t1 > 0x7fffffff */ 507 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 508 /* t1 < -0x80000000 */ 509 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 510 tcg_gen_or_i64(t2, t2, t3); 511 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 512 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 513 /* Calc SV bit */ 514 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 515 /* Calc AV/SAV bits */ 516 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 517 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 518 /* calc SAV */ 519 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 520 } 521 522 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 523 { 524 TCGv temp = tcg_constant_i32(con); 525 gen_madd32_d(ret, r1, r2, temp); 526 } 527 528 static inline void 529 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 530 TCGv r3) 531 { 532 TCGv t1 = tcg_temp_new(); 533 TCGv t2 = tcg_temp_new(); 534 TCGv t3 = tcg_temp_new(); 535 TCGv t4 = tcg_temp_new(); 536 537 tcg_gen_muls2_tl(t1, t2, r1, r3); 538 /* only the add can overflow */ 539 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); 540 /* calc V bit */ 541 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 542 tcg_gen_xor_tl(t1, r2_high, t2); 543 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); 544 /* Calc SV bit */ 545 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 546 /* Calc AV/SAV bits */ 547 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 548 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 549 /* calc SAV */ 550 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 551 /* write back the result */ 552 tcg_gen_mov_tl(ret_low, t3); 553 tcg_gen_mov_tl(ret_high, t4); 554 } 555 556 static inline void 557 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 558 TCGv r3) 559 { 560 TCGv_i64 t1 = tcg_temp_new_i64(); 561 TCGv_i64 t2 = tcg_temp_new_i64(); 562 TCGv_i64 t3 = tcg_temp_new_i64(); 563 564 tcg_gen_extu_i32_i64(t1, r1); 565 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 566 tcg_gen_extu_i32_i64(t3, r3); 567 568 tcg_gen_mul_i64(t1, t1, t3); 569 tcg_gen_add_i64(t2, t2, t1); 570 /* write back result */ 571 tcg_gen_extr_i64_i32(ret_low, ret_high, t2); 572 /* only the add overflows, if t2 < t1 573 calc V bit */ 574 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); 575 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 576 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 577 /* Calc SV bit */ 578 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 579 /* Calc AV/SAV bits */ 580 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 581 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 582 /* calc SAV */ 583 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 584 } 585 586 static inline void 587 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 588 int32_t con) 589 { 590 TCGv temp = tcg_constant_i32(con); 591 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 592 } 593 594 static inline void 595 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 596 int32_t con) 597 { 598 TCGv temp = tcg_constant_i32(con); 599 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 600 } 601 602 static inline void 603 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 604 TCGv r3, uint32_t n, uint32_t mode) 605 { 606 TCGv t_n = tcg_constant_i32(n); 607 TCGv temp = tcg_temp_new(); 608 TCGv temp2 = tcg_temp_new(); 609 TCGv_i64 temp64 = tcg_temp_new_i64(); 610 switch (mode) { 611 case MODE_LL: 612 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 613 break; 614 case MODE_LU: 615 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 616 break; 617 case MODE_UL: 618 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 619 break; 620 case MODE_UU: 621 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 622 break; 623 } 624 tcg_gen_extr_i64_i32(temp, temp2, temp64); 625 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 626 tcg_gen_add_tl, tcg_gen_add_tl); 627 } 628 629 static inline void 630 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 631 TCGv r3, uint32_t n, uint32_t mode) 632 { 633 TCGv t_n = tcg_constant_i32(n); 634 TCGv temp = tcg_temp_new(); 635 TCGv temp2 = tcg_temp_new(); 636 TCGv_i64 temp64 = tcg_temp_new_i64(); 637 switch (mode) { 638 case MODE_LL: 639 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 640 break; 641 case MODE_LU: 642 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 643 break; 644 case MODE_UL: 645 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 646 break; 647 case MODE_UU: 648 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 649 break; 650 } 651 tcg_gen_extr_i64_i32(temp, temp2, temp64); 652 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 653 tcg_gen_sub_tl, tcg_gen_add_tl); 654 } 655 656 static inline void 657 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 658 TCGv r3, uint32_t n, uint32_t mode) 659 { 660 TCGv t_n = tcg_constant_i32(n); 661 TCGv_i64 temp64 = tcg_temp_new_i64(); 662 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 663 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 664 switch (mode) { 665 case MODE_LL: 666 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 667 break; 668 case MODE_LU: 669 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 670 break; 671 case MODE_UL: 672 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 673 break; 674 case MODE_UU: 675 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 676 break; 677 } 678 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 679 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 680 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 681 tcg_gen_sub_i64(temp64, temp64_2, temp64); 682 tcg_gen_shli_i64(temp64, temp64, 16); 683 684 gen_add64_d(temp64_2, temp64_3, temp64); 685 /* write back result */ 686 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 687 } 688 689 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); 690 691 static inline void 692 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 693 TCGv r3, uint32_t n, uint32_t mode) 694 { 695 TCGv t_n = tcg_constant_i32(n); 696 TCGv temp = tcg_temp_new(); 697 TCGv temp2 = tcg_temp_new(); 698 TCGv temp3 = tcg_temp_new(); 699 TCGv_i64 temp64 = tcg_temp_new_i64(); 700 701 switch (mode) { 702 case MODE_LL: 703 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 704 break; 705 case MODE_LU: 706 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 707 break; 708 case MODE_UL: 709 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 710 break; 711 case MODE_UU: 712 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 713 break; 714 } 715 tcg_gen_extr_i64_i32(temp, temp2, temp64); 716 gen_adds(ret_low, r1_low, temp); 717 tcg_gen_mov_tl(temp, cpu_PSW_V); 718 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 719 gen_adds(ret_high, r1_high, temp2); 720 /* combine v bits */ 721 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 722 /* combine av bits */ 723 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 724 } 725 726 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); 727 728 static inline void 729 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 730 TCGv r3, uint32_t n, uint32_t mode) 731 { 732 TCGv t_n = tcg_constant_i32(n); 733 TCGv temp = tcg_temp_new(); 734 TCGv temp2 = tcg_temp_new(); 735 TCGv temp3 = tcg_temp_new(); 736 TCGv_i64 temp64 = tcg_temp_new_i64(); 737 738 switch (mode) { 739 case MODE_LL: 740 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 741 break; 742 case MODE_LU: 743 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 744 break; 745 case MODE_UL: 746 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 747 break; 748 case MODE_UU: 749 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 750 break; 751 } 752 tcg_gen_extr_i64_i32(temp, temp2, temp64); 753 gen_subs(ret_low, r1_low, temp); 754 tcg_gen_mov_tl(temp, cpu_PSW_V); 755 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 756 gen_adds(ret_high, r1_high, temp2); 757 /* combine v bits */ 758 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 759 /* combine av bits */ 760 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 761 } 762 763 static inline void 764 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 765 TCGv r3, uint32_t n, uint32_t mode) 766 { 767 TCGv t_n = tcg_constant_i32(n); 768 TCGv_i64 temp64 = tcg_temp_new_i64(); 769 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 770 771 switch (mode) { 772 case MODE_LL: 773 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 774 break; 775 case MODE_LU: 776 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 777 break; 778 case MODE_UL: 779 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 780 break; 781 case MODE_UU: 782 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 783 break; 784 } 785 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 786 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 787 tcg_gen_sub_i64(temp64, temp64_2, temp64); 788 tcg_gen_shli_i64(temp64, temp64, 16); 789 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 790 791 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 792 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 793 } 794 795 796 static inline void 797 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 798 TCGv r3, uint32_t n, uint32_t mode) 799 { 800 TCGv t_n = tcg_constant_i32(n); 801 TCGv_i64 temp64 = tcg_temp_new_i64(); 802 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 803 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 804 switch (mode) { 805 case MODE_LL: 806 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 807 break; 808 case MODE_LU: 809 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 810 break; 811 case MODE_UL: 812 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 813 break; 814 case MODE_UU: 815 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 816 break; 817 } 818 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 819 gen_add64_d(temp64_3, temp64_2, temp64); 820 /* write back result */ 821 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 822 } 823 824 static inline void 825 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 826 TCGv r3, uint32_t n, uint32_t mode) 827 { 828 TCGv t_n = tcg_constant_i32(n); 829 TCGv_i64 temp64 = tcg_temp_new_i64(); 830 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 831 switch (mode) { 832 case MODE_LL: 833 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 834 break; 835 case MODE_LU: 836 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 837 break; 838 case MODE_UL: 839 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 840 break; 841 case MODE_UU: 842 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 843 break; 844 } 845 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 846 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 847 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 848 } 849 850 static inline void 851 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 852 uint32_t mode) 853 { 854 TCGv t_n = tcg_constant_i32(n); 855 TCGv_i64 temp64 = tcg_temp_new_i64(); 856 switch (mode) { 857 case MODE_LL: 858 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 859 break; 860 case MODE_LU: 861 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 862 break; 863 case MODE_UL: 864 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 865 break; 866 case MODE_UU: 867 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 868 break; 869 } 870 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); 871 } 872 873 static inline void 874 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 875 { 876 TCGv temp = tcg_temp_new(); 877 TCGv temp2 = tcg_temp_new(); 878 879 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 880 tcg_gen_shli_tl(temp, r1, 16); 881 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); 882 } 883 884 static inline void 885 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 886 { 887 TCGv t_n = tcg_constant_i32(n); 888 TCGv temp = tcg_temp_new(); 889 TCGv temp2 = tcg_temp_new(); 890 TCGv_i64 temp64 = tcg_temp_new_i64(); 891 switch (mode) { 892 case MODE_LL: 893 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 894 break; 895 case MODE_LU: 896 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 897 break; 898 case MODE_UL: 899 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 900 break; 901 case MODE_UU: 902 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 903 break; 904 } 905 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 906 tcg_gen_shli_tl(temp, r1, 16); 907 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); 908 } 909 910 911 static inline void 912 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 913 uint32_t n, uint32_t mode) 914 { 915 TCGv t_n = tcg_constant_i32(n); 916 TCGv_i64 temp64 = tcg_temp_new_i64(); 917 switch (mode) { 918 case MODE_LL: 919 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 920 break; 921 case MODE_LU: 922 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 923 break; 924 case MODE_UL: 925 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 926 break; 927 case MODE_UU: 928 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 929 break; 930 } 931 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 932 } 933 934 static inline void 935 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 936 { 937 TCGv temp = tcg_temp_new(); 938 TCGv temp2 = tcg_temp_new(); 939 940 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 941 tcg_gen_shli_tl(temp, r1, 16); 942 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); 943 } 944 945 static inline void 946 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 947 { 948 TCGv t_n = tcg_constant_i32(n); 949 TCGv temp = tcg_temp_new(); 950 TCGv temp2 = tcg_temp_new(); 951 TCGv_i64 temp64 = tcg_temp_new_i64(); 952 switch (mode) { 953 case MODE_LL: 954 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 955 break; 956 case MODE_LU: 957 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 958 break; 959 case MODE_UL: 960 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 961 break; 962 case MODE_UU: 963 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 964 break; 965 } 966 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 967 tcg_gen_shli_tl(temp, r1, 16); 968 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); 969 } 970 971 static inline void 972 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 973 { 974 TCGv t_n = tcg_constant_i32(n); 975 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n); 976 } 977 978 static inline void 979 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 980 { 981 TCGv t_n = tcg_constant_i32(n); 982 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n); 983 } 984 985 static inline void 986 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 987 uint32_t up_shift) 988 { 989 TCGv temp = tcg_temp_new(); 990 TCGv temp2 = tcg_temp_new(); 991 TCGv temp3 = tcg_temp_new(); 992 TCGv_i64 t1 = tcg_temp_new_i64(); 993 TCGv_i64 t2 = tcg_temp_new_i64(); 994 TCGv_i64 t3 = tcg_temp_new_i64(); 995 996 tcg_gen_ext_i32_i64(t2, arg2); 997 tcg_gen_ext_i32_i64(t3, arg3); 998 999 tcg_gen_mul_i64(t2, t2, t3); 1000 tcg_gen_shli_i64(t2, t2, n); 1001 1002 tcg_gen_ext_i32_i64(t1, arg1); 1003 tcg_gen_sari_i64(t2, t2, up_shift); 1004 1005 tcg_gen_add_i64(t3, t1, t2); 1006 tcg_gen_extrl_i64_i32(temp3, t3); 1007 /* calc v bit */ 1008 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1009 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1010 tcg_gen_or_i64(t1, t1, t2); 1011 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1012 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1013 /* We produce an overflow on the host if the mul before was 1014 (0x80000000 * 0x80000000) << 1). If this is the 1015 case, we negate the ovf. */ 1016 if (n == 1) { 1017 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1018 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1019 tcg_gen_and_tl(temp, temp, temp2); 1020 tcg_gen_shli_tl(temp, temp, 31); 1021 /* negate v bit, if special condition */ 1022 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1023 } 1024 /* Calc SV bit */ 1025 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1026 /* Calc AV/SAV bits */ 1027 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1028 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1029 /* calc SAV */ 1030 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1031 /* write back result */ 1032 tcg_gen_mov_tl(ret, temp3); 1033 } 1034 1035 static inline void 1036 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1037 { 1038 TCGv temp = tcg_temp_new(); 1039 TCGv temp2 = tcg_temp_new(); 1040 if (n == 0) { 1041 tcg_gen_mul_tl(temp, arg2, arg3); 1042 } else { /* n is expected to be 1 */ 1043 tcg_gen_mul_tl(temp, arg2, arg3); 1044 tcg_gen_shli_tl(temp, temp, 1); 1045 /* catch special case r1 = r2 = 0x8000 */ 1046 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1047 tcg_gen_sub_tl(temp, temp, temp2); 1048 } 1049 gen_add_d(ret, arg1, temp); 1050 } 1051 1052 static inline void 1053 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1054 { 1055 TCGv temp = tcg_temp_new(); 1056 TCGv temp2 = tcg_temp_new(); 1057 if (n == 0) { 1058 tcg_gen_mul_tl(temp, arg2, arg3); 1059 } else { /* n is expected to be 1 */ 1060 tcg_gen_mul_tl(temp, arg2, arg3); 1061 tcg_gen_shli_tl(temp, temp, 1); 1062 /* catch special case r1 = r2 = 0x8000 */ 1063 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1064 tcg_gen_sub_tl(temp, temp, temp2); 1065 } 1066 gen_adds(ret, arg1, temp); 1067 } 1068 1069 static inline void 1070 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1071 TCGv arg3, uint32_t n) 1072 { 1073 TCGv temp = tcg_temp_new(); 1074 TCGv temp2 = tcg_temp_new(); 1075 TCGv_i64 t1 = tcg_temp_new_i64(); 1076 TCGv_i64 t2 = tcg_temp_new_i64(); 1077 TCGv_i64 t3 = tcg_temp_new_i64(); 1078 1079 if (n == 0) { 1080 tcg_gen_mul_tl(temp, arg2, arg3); 1081 } else { /* n is expected to be 1 */ 1082 tcg_gen_mul_tl(temp, arg2, arg3); 1083 tcg_gen_shli_tl(temp, temp, 1); 1084 /* catch special case r1 = r2 = 0x8000 */ 1085 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1086 tcg_gen_sub_tl(temp, temp, temp2); 1087 } 1088 tcg_gen_ext_i32_i64(t2, temp); 1089 tcg_gen_shli_i64(t2, t2, 16); 1090 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1091 gen_add64_d(t3, t1, t2); 1092 /* write back result */ 1093 tcg_gen_extr_i64_i32(rl, rh, t3); 1094 } 1095 1096 static inline void 1097 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1098 TCGv arg3, uint32_t n) 1099 { 1100 TCGv temp = tcg_temp_new(); 1101 TCGv temp2 = tcg_temp_new(); 1102 TCGv_i64 t1 = tcg_temp_new_i64(); 1103 TCGv_i64 t2 = tcg_temp_new_i64(); 1104 1105 if (n == 0) { 1106 tcg_gen_mul_tl(temp, arg2, arg3); 1107 } else { /* n is expected to be 1 */ 1108 tcg_gen_mul_tl(temp, arg2, arg3); 1109 tcg_gen_shli_tl(temp, temp, 1); 1110 /* catch special case r1 = r2 = 0x8000 */ 1111 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1112 tcg_gen_sub_tl(temp, temp, temp2); 1113 } 1114 tcg_gen_ext_i32_i64(t2, temp); 1115 tcg_gen_shli_i64(t2, t2, 16); 1116 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1117 1118 gen_helper_add64_ssov(t1, cpu_env, t1, t2); 1119 tcg_gen_extr_i64_i32(rl, rh, t1); 1120 } 1121 1122 static inline void 1123 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1124 TCGv arg3, uint32_t n) 1125 { 1126 TCGv_i64 t1 = tcg_temp_new_i64(); 1127 TCGv_i64 t2 = tcg_temp_new_i64(); 1128 TCGv_i64 t3 = tcg_temp_new_i64(); 1129 TCGv_i64 t4 = tcg_temp_new_i64(); 1130 TCGv temp, temp2; 1131 1132 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1133 tcg_gen_ext_i32_i64(t2, arg2); 1134 tcg_gen_ext_i32_i64(t3, arg3); 1135 1136 tcg_gen_mul_i64(t2, t2, t3); 1137 if (n != 0) { 1138 tcg_gen_shli_i64(t2, t2, 1); 1139 } 1140 tcg_gen_add_i64(t4, t1, t2); 1141 /* calc v bit */ 1142 tcg_gen_xor_i64(t3, t4, t1); 1143 tcg_gen_xor_i64(t2, t1, t2); 1144 tcg_gen_andc_i64(t3, t3, t2); 1145 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1146 /* We produce an overflow on the host if the mul before was 1147 (0x80000000 * 0x80000000) << 1). If this is the 1148 case, we negate the ovf. */ 1149 if (n == 1) { 1150 temp = tcg_temp_new(); 1151 temp2 = tcg_temp_new(); 1152 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1153 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1154 tcg_gen_and_tl(temp, temp, temp2); 1155 tcg_gen_shli_tl(temp, temp, 31); 1156 /* negate v bit, if special condition */ 1157 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1158 } 1159 /* write back result */ 1160 tcg_gen_extr_i64_i32(rl, rh, t4); 1161 /* Calc SV bit */ 1162 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1163 /* Calc AV/SAV bits */ 1164 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1165 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1166 /* calc SAV */ 1167 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1168 } 1169 1170 static inline void 1171 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1172 uint32_t up_shift) 1173 { 1174 TCGv_i64 t1 = tcg_temp_new_i64(); 1175 TCGv_i64 t2 = tcg_temp_new_i64(); 1176 TCGv_i64 t3 = tcg_temp_new_i64(); 1177 1178 tcg_gen_ext_i32_i64(t1, arg1); 1179 tcg_gen_ext_i32_i64(t2, arg2); 1180 tcg_gen_ext_i32_i64(t3, arg3); 1181 1182 tcg_gen_mul_i64(t2, t2, t3); 1183 tcg_gen_sari_i64(t2, t2, up_shift - n); 1184 1185 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); 1186 } 1187 1188 static inline void 1189 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1190 TCGv arg3, uint32_t n) 1191 { 1192 TCGv_i64 r1 = tcg_temp_new_i64(); 1193 TCGv t_n = tcg_constant_i32(n); 1194 1195 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1196 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); 1197 tcg_gen_extr_i64_i32(rl, rh, r1); 1198 } 1199 1200 /* ret = r2 - (r1 * r3); */ 1201 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 1202 { 1203 TCGv_i64 t1 = tcg_temp_new_i64(); 1204 TCGv_i64 t2 = tcg_temp_new_i64(); 1205 TCGv_i64 t3 = tcg_temp_new_i64(); 1206 1207 tcg_gen_ext_i32_i64(t1, r1); 1208 tcg_gen_ext_i32_i64(t2, r2); 1209 tcg_gen_ext_i32_i64(t3, r3); 1210 1211 tcg_gen_mul_i64(t1, t1, t3); 1212 tcg_gen_sub_i64(t1, t2, t1); 1213 1214 tcg_gen_extrl_i64_i32(ret, t1); 1215 /* calc V 1216 t2 > 0x7fffffff */ 1217 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 1218 /* result < -0x80000000 */ 1219 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 1220 tcg_gen_or_i64(t2, t2, t3); 1221 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 1222 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1223 1224 /* Calc SV bit */ 1225 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1226 /* Calc AV/SAV bits */ 1227 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 1228 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 1229 /* calc SAV */ 1230 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1231 } 1232 1233 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 1234 { 1235 TCGv temp = tcg_constant_i32(con); 1236 gen_msub32_d(ret, r1, r2, temp); 1237 } 1238 1239 static inline void 1240 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1241 TCGv r3) 1242 { 1243 TCGv t1 = tcg_temp_new(); 1244 TCGv t2 = tcg_temp_new(); 1245 TCGv t3 = tcg_temp_new(); 1246 TCGv t4 = tcg_temp_new(); 1247 1248 tcg_gen_muls2_tl(t1, t2, r1, r3); 1249 /* only the sub can overflow */ 1250 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); 1251 /* calc V bit */ 1252 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 1253 tcg_gen_xor_tl(t1, r2_high, t2); 1254 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); 1255 /* Calc SV bit */ 1256 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1257 /* Calc AV/SAV bits */ 1258 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 1259 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 1260 /* calc SAV */ 1261 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1262 /* write back the result */ 1263 tcg_gen_mov_tl(ret_low, t3); 1264 tcg_gen_mov_tl(ret_high, t4); 1265 } 1266 1267 static inline void 1268 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1269 int32_t con) 1270 { 1271 TCGv temp = tcg_constant_i32(con); 1272 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1273 } 1274 1275 static inline void 1276 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1277 TCGv r3) 1278 { 1279 TCGv_i64 t1 = tcg_temp_new_i64(); 1280 TCGv_i64 t2 = tcg_temp_new_i64(); 1281 TCGv_i64 t3 = tcg_temp_new_i64(); 1282 1283 tcg_gen_extu_i32_i64(t1, r1); 1284 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 1285 tcg_gen_extu_i32_i64(t3, r3); 1286 1287 tcg_gen_mul_i64(t1, t1, t3); 1288 tcg_gen_sub_i64(t3, t2, t1); 1289 tcg_gen_extr_i64_i32(ret_low, ret_high, t3); 1290 /* calc V bit, only the sub can overflow, if t1 > t2 */ 1291 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); 1292 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1293 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1294 /* Calc SV bit */ 1295 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1296 /* Calc AV/SAV bits */ 1297 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 1298 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 1299 /* calc SAV */ 1300 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1301 } 1302 1303 static inline void 1304 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1305 int32_t con) 1306 { 1307 TCGv temp = tcg_constant_i32(con); 1308 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1309 } 1310 1311 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) 1312 { 1313 TCGv temp = tcg_constant_i32(r2); 1314 gen_add_d(ret, r1, temp); 1315 } 1316 1317 /* calculate the carry bit too */ 1318 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) 1319 { 1320 TCGv t0 = tcg_temp_new_i32(); 1321 TCGv result = tcg_temp_new_i32(); 1322 1323 tcg_gen_movi_tl(t0, 0); 1324 /* Addition and set C/V/SV bits */ 1325 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); 1326 /* calc V bit */ 1327 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1328 tcg_gen_xor_tl(t0, r1, r2); 1329 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1330 /* Calc SV bit */ 1331 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1332 /* Calc AV/SAV bits */ 1333 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1334 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1335 /* calc SAV */ 1336 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1337 /* write back result */ 1338 tcg_gen_mov_tl(ret, result); 1339 } 1340 1341 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) 1342 { 1343 TCGv temp = tcg_constant_i32(con); 1344 gen_add_CC(ret, r1, temp); 1345 } 1346 1347 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) 1348 { 1349 TCGv carry = tcg_temp_new_i32(); 1350 TCGv t0 = tcg_temp_new_i32(); 1351 TCGv result = tcg_temp_new_i32(); 1352 1353 tcg_gen_movi_tl(t0, 0); 1354 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); 1355 /* Addition, carry and set C/V/SV bits */ 1356 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); 1357 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); 1358 /* calc V bit */ 1359 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1360 tcg_gen_xor_tl(t0, r1, r2); 1361 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1362 /* Calc SV bit */ 1363 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1364 /* Calc AV/SAV bits */ 1365 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1366 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1367 /* calc SAV */ 1368 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1369 /* write back result */ 1370 tcg_gen_mov_tl(ret, result); 1371 } 1372 1373 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) 1374 { 1375 TCGv temp = tcg_constant_i32(con); 1376 gen_addc_CC(ret, r1, temp); 1377 } 1378 1379 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1380 TCGv r4) 1381 { 1382 TCGv temp = tcg_temp_new(); 1383 TCGv temp2 = tcg_temp_new(); 1384 TCGv result = tcg_temp_new(); 1385 TCGv mask = tcg_temp_new(); 1386 TCGv t0 = tcg_constant_i32(0); 1387 1388 /* create mask for sticky bits */ 1389 tcg_gen_setcond_tl(cond, mask, r4, t0); 1390 tcg_gen_shli_tl(mask, mask, 31); 1391 1392 tcg_gen_add_tl(result, r1, r2); 1393 /* Calc PSW_V */ 1394 tcg_gen_xor_tl(temp, result, r1); 1395 tcg_gen_xor_tl(temp2, r1, r2); 1396 tcg_gen_andc_tl(temp, temp, temp2); 1397 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1398 /* Set PSW_SV */ 1399 tcg_gen_and_tl(temp, temp, mask); 1400 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1401 /* calc AV bit */ 1402 tcg_gen_add_tl(temp, result, result); 1403 tcg_gen_xor_tl(temp, temp, result); 1404 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1405 /* calc SAV bit */ 1406 tcg_gen_and_tl(temp, temp, mask); 1407 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1408 /* write back result */ 1409 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1410 } 1411 1412 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, 1413 TCGv r3, TCGv r4) 1414 { 1415 TCGv temp = tcg_constant_i32(r2); 1416 gen_cond_add(cond, r1, temp, r3, r4); 1417 } 1418 1419 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) 1420 { 1421 TCGv temp = tcg_temp_new_i32(); 1422 TCGv result = tcg_temp_new_i32(); 1423 1424 tcg_gen_sub_tl(result, r1, r2); 1425 /* calc V bit */ 1426 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1427 tcg_gen_xor_tl(temp, r1, r2); 1428 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1429 /* calc SV bit */ 1430 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1431 /* Calc AV bit */ 1432 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1433 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1434 /* calc SAV bit */ 1435 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1436 /* write back result */ 1437 tcg_gen_mov_tl(ret, result); 1438 } 1439 1440 static inline void 1441 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 1442 { 1443 TCGv temp = tcg_temp_new(); 1444 TCGv_i64 t0 = tcg_temp_new_i64(); 1445 TCGv_i64 t1 = tcg_temp_new_i64(); 1446 TCGv_i64 result = tcg_temp_new_i64(); 1447 1448 tcg_gen_sub_i64(result, r1, r2); 1449 /* calc v bit */ 1450 tcg_gen_xor_i64(t1, result, r1); 1451 tcg_gen_xor_i64(t0, r1, r2); 1452 tcg_gen_and_i64(t1, t1, t0); 1453 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 1454 /* calc SV bit */ 1455 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1456 /* calc AV/SAV bits */ 1457 tcg_gen_extrh_i64_i32(temp, result); 1458 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 1459 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 1460 /* calc SAV */ 1461 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1462 /* write back result */ 1463 tcg_gen_mov_i64(ret, result); 1464 } 1465 1466 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) 1467 { 1468 TCGv result = tcg_temp_new(); 1469 TCGv temp = tcg_temp_new(); 1470 1471 tcg_gen_sub_tl(result, r1, r2); 1472 /* calc C bit */ 1473 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); 1474 /* calc V bit */ 1475 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1476 tcg_gen_xor_tl(temp, r1, r2); 1477 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1478 /* calc SV bit */ 1479 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1480 /* Calc AV bit */ 1481 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1482 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1483 /* calc SAV bit */ 1484 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1485 /* write back result */ 1486 tcg_gen_mov_tl(ret, result); 1487 } 1488 1489 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) 1490 { 1491 TCGv temp = tcg_temp_new(); 1492 tcg_gen_not_tl(temp, r2); 1493 gen_addc_CC(ret, r1, temp); 1494 } 1495 1496 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1497 TCGv r4) 1498 { 1499 TCGv temp = tcg_temp_new(); 1500 TCGv temp2 = tcg_temp_new(); 1501 TCGv result = tcg_temp_new(); 1502 TCGv mask = tcg_temp_new(); 1503 TCGv t0 = tcg_constant_i32(0); 1504 1505 /* create mask for sticky bits */ 1506 tcg_gen_setcond_tl(cond, mask, r4, t0); 1507 tcg_gen_shli_tl(mask, mask, 31); 1508 1509 tcg_gen_sub_tl(result, r1, r2); 1510 /* Calc PSW_V */ 1511 tcg_gen_xor_tl(temp, result, r1); 1512 tcg_gen_xor_tl(temp2, r1, r2); 1513 tcg_gen_and_tl(temp, temp, temp2); 1514 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1515 /* Set PSW_SV */ 1516 tcg_gen_and_tl(temp, temp, mask); 1517 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1518 /* calc AV bit */ 1519 tcg_gen_add_tl(temp, result, result); 1520 tcg_gen_xor_tl(temp, temp, result); 1521 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1522 /* calc SAV bit */ 1523 tcg_gen_and_tl(temp, temp, mask); 1524 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1525 /* write back result */ 1526 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1527 } 1528 1529 static inline void 1530 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1531 TCGv r3, uint32_t n, uint32_t mode) 1532 { 1533 TCGv t_n = tcg_constant_i32(n); 1534 TCGv temp = tcg_temp_new(); 1535 TCGv temp2 = tcg_temp_new(); 1536 TCGv_i64 temp64 = tcg_temp_new_i64(); 1537 switch (mode) { 1538 case MODE_LL: 1539 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1540 break; 1541 case MODE_LU: 1542 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1543 break; 1544 case MODE_UL: 1545 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1546 break; 1547 case MODE_UU: 1548 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1549 break; 1550 } 1551 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1552 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1553 tcg_gen_sub_tl, tcg_gen_sub_tl); 1554 } 1555 1556 static inline void 1557 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1558 TCGv r3, uint32_t n, uint32_t mode) 1559 { 1560 TCGv t_n = tcg_constant_i32(n); 1561 TCGv temp = tcg_temp_new(); 1562 TCGv temp2 = tcg_temp_new(); 1563 TCGv temp3 = tcg_temp_new(); 1564 TCGv_i64 temp64 = tcg_temp_new_i64(); 1565 1566 switch (mode) { 1567 case MODE_LL: 1568 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1569 break; 1570 case MODE_LU: 1571 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1572 break; 1573 case MODE_UL: 1574 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1575 break; 1576 case MODE_UU: 1577 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1578 break; 1579 } 1580 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1581 gen_subs(ret_low, r1_low, temp); 1582 tcg_gen_mov_tl(temp, cpu_PSW_V); 1583 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 1584 gen_subs(ret_high, r1_high, temp2); 1585 /* combine v bits */ 1586 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 1587 /* combine av bits */ 1588 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 1589 } 1590 1591 static inline void 1592 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1593 TCGv r3, uint32_t n, uint32_t mode) 1594 { 1595 TCGv t_n = tcg_constant_i32(n); 1596 TCGv_i64 temp64 = tcg_temp_new_i64(); 1597 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1598 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1599 switch (mode) { 1600 case MODE_LL: 1601 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1602 break; 1603 case MODE_LU: 1604 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1605 break; 1606 case MODE_UL: 1607 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1608 break; 1609 case MODE_UU: 1610 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1611 break; 1612 } 1613 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1614 gen_sub64_d(temp64_3, temp64_2, temp64); 1615 /* write back result */ 1616 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 1617 } 1618 1619 static inline void 1620 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1621 TCGv r3, uint32_t n, uint32_t mode) 1622 { 1623 TCGv t_n = tcg_constant_i32(n); 1624 TCGv_i64 temp64 = tcg_temp_new_i64(); 1625 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1626 switch (mode) { 1627 case MODE_LL: 1628 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1629 break; 1630 case MODE_LU: 1631 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1632 break; 1633 case MODE_UL: 1634 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1635 break; 1636 case MODE_UU: 1637 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1638 break; 1639 } 1640 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1641 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 1642 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 1643 } 1644 1645 static inline void 1646 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 1647 uint32_t mode) 1648 { 1649 TCGv t_n = tcg_constant_i32(n); 1650 TCGv_i64 temp64 = tcg_temp_new_i64(); 1651 switch (mode) { 1652 case MODE_LL: 1653 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1654 break; 1655 case MODE_LU: 1656 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1657 break; 1658 case MODE_UL: 1659 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1660 break; 1661 case MODE_UU: 1662 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1663 break; 1664 } 1665 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); 1666 } 1667 1668 static inline void 1669 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1670 { 1671 TCGv temp = tcg_temp_new(); 1672 TCGv temp2 = tcg_temp_new(); 1673 1674 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1675 tcg_gen_shli_tl(temp, r1, 16); 1676 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); 1677 } 1678 1679 static inline void 1680 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1681 uint32_t n, uint32_t mode) 1682 { 1683 TCGv t_n = tcg_constant_i32(n); 1684 TCGv_i64 temp64 = tcg_temp_new_i64(); 1685 switch (mode) { 1686 case MODE_LL: 1687 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1688 break; 1689 case MODE_LU: 1690 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1691 break; 1692 case MODE_UL: 1693 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1694 break; 1695 case MODE_UU: 1696 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1697 break; 1698 } 1699 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 1700 } 1701 1702 static inline void 1703 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1704 { 1705 TCGv temp = tcg_temp_new(); 1706 TCGv temp2 = tcg_temp_new(); 1707 1708 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1709 tcg_gen_shli_tl(temp, r1, 16); 1710 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); 1711 } 1712 1713 static inline void 1714 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1715 { 1716 TCGv temp = tcg_constant_i32(n); 1717 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); 1718 } 1719 1720 static inline void 1721 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1722 { 1723 TCGv temp = tcg_constant_i32(n); 1724 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); 1725 } 1726 1727 static inline void 1728 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1729 uint32_t up_shift) 1730 { 1731 TCGv temp3 = tcg_temp_new(); 1732 TCGv_i64 t1 = tcg_temp_new_i64(); 1733 TCGv_i64 t2 = tcg_temp_new_i64(); 1734 TCGv_i64 t3 = tcg_temp_new_i64(); 1735 TCGv_i64 t4 = tcg_temp_new_i64(); 1736 1737 tcg_gen_ext_i32_i64(t2, arg2); 1738 tcg_gen_ext_i32_i64(t3, arg3); 1739 1740 tcg_gen_mul_i64(t2, t2, t3); 1741 1742 tcg_gen_ext_i32_i64(t1, arg1); 1743 /* if we shift part of the fraction out, we need to round up */ 1744 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1745 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1746 tcg_gen_sari_i64(t2, t2, up_shift - n); 1747 tcg_gen_add_i64(t2, t2, t4); 1748 1749 tcg_gen_sub_i64(t3, t1, t2); 1750 tcg_gen_extrl_i64_i32(temp3, t3); 1751 /* calc v bit */ 1752 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1753 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1754 tcg_gen_or_i64(t1, t1, t2); 1755 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1756 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1757 /* Calc SV bit */ 1758 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1759 /* Calc AV/SAV bits */ 1760 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1761 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1762 /* calc SAV */ 1763 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1764 /* write back result */ 1765 tcg_gen_mov_tl(ret, temp3); 1766 } 1767 1768 static inline void 1769 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1770 { 1771 TCGv temp = tcg_temp_new(); 1772 TCGv temp2 = tcg_temp_new(); 1773 if (n == 0) { 1774 tcg_gen_mul_tl(temp, arg2, arg3); 1775 } else { /* n is expected to be 1 */ 1776 tcg_gen_mul_tl(temp, arg2, arg3); 1777 tcg_gen_shli_tl(temp, temp, 1); 1778 /* catch special case r1 = r2 = 0x8000 */ 1779 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1780 tcg_gen_sub_tl(temp, temp, temp2); 1781 } 1782 gen_sub_d(ret, arg1, temp); 1783 } 1784 1785 static inline void 1786 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1787 { 1788 TCGv temp = tcg_temp_new(); 1789 TCGv temp2 = tcg_temp_new(); 1790 if (n == 0) { 1791 tcg_gen_mul_tl(temp, arg2, arg3); 1792 } else { /* n is expected to be 1 */ 1793 tcg_gen_mul_tl(temp, arg2, arg3); 1794 tcg_gen_shli_tl(temp, temp, 1); 1795 /* catch special case r1 = r2 = 0x8000 */ 1796 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1797 tcg_gen_sub_tl(temp, temp, temp2); 1798 } 1799 gen_subs(ret, arg1, temp); 1800 } 1801 1802 static inline void 1803 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1804 TCGv arg3, uint32_t n) 1805 { 1806 TCGv temp = tcg_temp_new(); 1807 TCGv temp2 = tcg_temp_new(); 1808 TCGv_i64 t1 = tcg_temp_new_i64(); 1809 TCGv_i64 t2 = tcg_temp_new_i64(); 1810 TCGv_i64 t3 = tcg_temp_new_i64(); 1811 1812 if (n == 0) { 1813 tcg_gen_mul_tl(temp, arg2, arg3); 1814 } else { /* n is expected to be 1 */ 1815 tcg_gen_mul_tl(temp, arg2, arg3); 1816 tcg_gen_shli_tl(temp, temp, 1); 1817 /* catch special case r1 = r2 = 0x8000 */ 1818 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1819 tcg_gen_sub_tl(temp, temp, temp2); 1820 } 1821 tcg_gen_ext_i32_i64(t2, temp); 1822 tcg_gen_shli_i64(t2, t2, 16); 1823 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1824 gen_sub64_d(t3, t1, t2); 1825 /* write back result */ 1826 tcg_gen_extr_i64_i32(rl, rh, t3); 1827 } 1828 1829 static inline void 1830 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1831 TCGv arg3, uint32_t n) 1832 { 1833 TCGv temp = tcg_temp_new(); 1834 TCGv temp2 = tcg_temp_new(); 1835 TCGv_i64 t1 = tcg_temp_new_i64(); 1836 TCGv_i64 t2 = tcg_temp_new_i64(); 1837 1838 if (n == 0) { 1839 tcg_gen_mul_tl(temp, arg2, arg3); 1840 } else { /* n is expected to be 1 */ 1841 tcg_gen_mul_tl(temp, arg2, arg3); 1842 tcg_gen_shli_tl(temp, temp, 1); 1843 /* catch special case r1 = r2 = 0x8000 */ 1844 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1845 tcg_gen_sub_tl(temp, temp, temp2); 1846 } 1847 tcg_gen_ext_i32_i64(t2, temp); 1848 tcg_gen_shli_i64(t2, t2, 16); 1849 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1850 1851 gen_helper_sub64_ssov(t1, cpu_env, t1, t2); 1852 tcg_gen_extr_i64_i32(rl, rh, t1); 1853 } 1854 1855 static inline void 1856 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1857 TCGv arg3, uint32_t n) 1858 { 1859 TCGv_i64 t1 = tcg_temp_new_i64(); 1860 TCGv_i64 t2 = tcg_temp_new_i64(); 1861 TCGv_i64 t3 = tcg_temp_new_i64(); 1862 TCGv_i64 t4 = tcg_temp_new_i64(); 1863 TCGv temp, temp2; 1864 1865 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1866 tcg_gen_ext_i32_i64(t2, arg2); 1867 tcg_gen_ext_i32_i64(t3, arg3); 1868 1869 tcg_gen_mul_i64(t2, t2, t3); 1870 if (n != 0) { 1871 tcg_gen_shli_i64(t2, t2, 1); 1872 } 1873 tcg_gen_sub_i64(t4, t1, t2); 1874 /* calc v bit */ 1875 tcg_gen_xor_i64(t3, t4, t1); 1876 tcg_gen_xor_i64(t2, t1, t2); 1877 tcg_gen_and_i64(t3, t3, t2); 1878 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1879 /* We produce an overflow on the host if the mul before was 1880 (0x80000000 * 0x80000000) << 1). If this is the 1881 case, we negate the ovf. */ 1882 if (n == 1) { 1883 temp = tcg_temp_new(); 1884 temp2 = tcg_temp_new(); 1885 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1886 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1887 tcg_gen_and_tl(temp, temp, temp2); 1888 tcg_gen_shli_tl(temp, temp, 31); 1889 /* negate v bit, if special condition */ 1890 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1891 } 1892 /* write back result */ 1893 tcg_gen_extr_i64_i32(rl, rh, t4); 1894 /* Calc SV bit */ 1895 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1896 /* Calc AV/SAV bits */ 1897 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1898 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1899 /* calc SAV */ 1900 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1901 } 1902 1903 static inline void 1904 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1905 uint32_t up_shift) 1906 { 1907 TCGv_i64 t1 = tcg_temp_new_i64(); 1908 TCGv_i64 t2 = tcg_temp_new_i64(); 1909 TCGv_i64 t3 = tcg_temp_new_i64(); 1910 TCGv_i64 t4 = tcg_temp_new_i64(); 1911 1912 tcg_gen_ext_i32_i64(t1, arg1); 1913 tcg_gen_ext_i32_i64(t2, arg2); 1914 tcg_gen_ext_i32_i64(t3, arg3); 1915 1916 tcg_gen_mul_i64(t2, t2, t3); 1917 /* if we shift part of the fraction out, we need to round up */ 1918 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1919 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1920 tcg_gen_sari_i64(t3, t2, up_shift - n); 1921 tcg_gen_add_i64(t3, t3, t4); 1922 1923 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); 1924 } 1925 1926 static inline void 1927 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1928 TCGv arg3, uint32_t n) 1929 { 1930 TCGv_i64 r1 = tcg_temp_new_i64(); 1931 TCGv t_n = tcg_constant_i32(n); 1932 1933 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1934 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); 1935 tcg_gen_extr_i64_i32(rl, rh, r1); 1936 } 1937 1938 static inline void 1939 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1940 TCGv r3, uint32_t n, uint32_t mode) 1941 { 1942 TCGv t_n = tcg_constant_i32(n); 1943 TCGv temp = tcg_temp_new(); 1944 TCGv temp2 = tcg_temp_new(); 1945 TCGv_i64 temp64 = tcg_temp_new_i64(); 1946 switch (mode) { 1947 case MODE_LL: 1948 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1949 break; 1950 case MODE_LU: 1951 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1952 break; 1953 case MODE_UL: 1954 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1955 break; 1956 case MODE_UU: 1957 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1958 break; 1959 } 1960 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1961 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1962 tcg_gen_add_tl, tcg_gen_sub_tl); 1963 } 1964 1965 static inline void 1966 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1967 TCGv r3, uint32_t n, uint32_t mode) 1968 { 1969 TCGv t_n = tcg_constant_i32(n); 1970 TCGv_i64 temp64 = tcg_temp_new_i64(); 1971 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1972 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1973 switch (mode) { 1974 case MODE_LL: 1975 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1976 break; 1977 case MODE_LU: 1978 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1979 break; 1980 case MODE_UL: 1981 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1982 break; 1983 case MODE_UU: 1984 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1985 break; 1986 } 1987 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 1988 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 1989 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 1990 tcg_gen_sub_i64(temp64, temp64_2, temp64); 1991 tcg_gen_shli_i64(temp64, temp64, 16); 1992 1993 gen_sub64_d(temp64_2, temp64_3, temp64); 1994 /* write back result */ 1995 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 1996 } 1997 1998 static inline void 1999 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2000 { 2001 TCGv t_n = tcg_constant_i32(n); 2002 TCGv temp = tcg_temp_new(); 2003 TCGv temp2 = tcg_temp_new(); 2004 TCGv_i64 temp64 = tcg_temp_new_i64(); 2005 switch (mode) { 2006 case MODE_LL: 2007 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2008 break; 2009 case MODE_LU: 2010 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2011 break; 2012 case MODE_UL: 2013 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2014 break; 2015 case MODE_UU: 2016 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2017 break; 2018 } 2019 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2020 tcg_gen_shli_tl(temp, r1, 16); 2021 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); 2022 } 2023 2024 static inline void 2025 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2026 TCGv r3, uint32_t n, uint32_t mode) 2027 { 2028 TCGv t_n = tcg_constant_i32(n); 2029 TCGv temp = tcg_temp_new(); 2030 TCGv temp2 = tcg_temp_new(); 2031 TCGv temp3 = tcg_temp_new(); 2032 TCGv_i64 temp64 = tcg_temp_new_i64(); 2033 2034 switch (mode) { 2035 case MODE_LL: 2036 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2037 break; 2038 case MODE_LU: 2039 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2040 break; 2041 case MODE_UL: 2042 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2043 break; 2044 case MODE_UU: 2045 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2046 break; 2047 } 2048 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2049 gen_adds(ret_low, r1_low, temp); 2050 tcg_gen_mov_tl(temp, cpu_PSW_V); 2051 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 2052 gen_subs(ret_high, r1_high, temp2); 2053 /* combine v bits */ 2054 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 2055 /* combine av bits */ 2056 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 2057 } 2058 2059 static inline void 2060 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2061 TCGv r3, uint32_t n, uint32_t mode) 2062 { 2063 TCGv t_n = tcg_constant_i32(n); 2064 TCGv_i64 temp64 = tcg_temp_new_i64(); 2065 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2066 2067 switch (mode) { 2068 case MODE_LL: 2069 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2070 break; 2071 case MODE_LU: 2072 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2073 break; 2074 case MODE_UL: 2075 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2076 break; 2077 case MODE_UU: 2078 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2079 break; 2080 } 2081 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2082 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2083 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2084 tcg_gen_shli_i64(temp64, temp64, 16); 2085 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 2086 2087 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 2088 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2089 } 2090 2091 static inline void 2092 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2093 { 2094 TCGv t_n = tcg_constant_i32(n); 2095 TCGv temp = tcg_temp_new(); 2096 TCGv temp2 = tcg_temp_new(); 2097 TCGv_i64 temp64 = tcg_temp_new_i64(); 2098 switch (mode) { 2099 case MODE_LL: 2100 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2101 break; 2102 case MODE_LU: 2103 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2104 break; 2105 case MODE_UL: 2106 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2107 break; 2108 case MODE_UU: 2109 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2110 break; 2111 } 2112 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2113 tcg_gen_shli_tl(temp, r1, 16); 2114 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); 2115 } 2116 2117 static inline void gen_abs(TCGv ret, TCGv r1) 2118 { 2119 tcg_gen_abs_tl(ret, r1); 2120 /* overflow can only happen, if r1 = 0x80000000 */ 2121 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); 2122 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2123 /* calc SV bit */ 2124 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2125 /* Calc AV bit */ 2126 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2127 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2128 /* calc SAV bit */ 2129 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2130 } 2131 2132 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) 2133 { 2134 TCGv temp = tcg_temp_new_i32(); 2135 TCGv result = tcg_temp_new_i32(); 2136 2137 tcg_gen_sub_tl(result, r1, r2); 2138 tcg_gen_sub_tl(temp, r2, r1); 2139 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); 2140 2141 /* calc V bit */ 2142 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 2143 tcg_gen_xor_tl(temp, result, r2); 2144 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); 2145 tcg_gen_xor_tl(temp, r1, r2); 2146 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 2147 /* calc SV bit */ 2148 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2149 /* Calc AV bit */ 2150 tcg_gen_add_tl(cpu_PSW_AV, result, result); 2151 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 2152 /* calc SAV bit */ 2153 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2154 /* write back result */ 2155 tcg_gen_mov_tl(ret, result); 2156 } 2157 2158 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) 2159 { 2160 TCGv temp = tcg_constant_i32(con); 2161 gen_absdif(ret, r1, temp); 2162 } 2163 2164 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) 2165 { 2166 TCGv temp = tcg_constant_i32(con); 2167 gen_helper_absdif_ssov(ret, cpu_env, r1, temp); 2168 } 2169 2170 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) 2171 { 2172 TCGv high = tcg_temp_new(); 2173 TCGv low = tcg_temp_new(); 2174 2175 tcg_gen_muls2_tl(low, high, r1, r2); 2176 tcg_gen_mov_tl(ret, low); 2177 /* calc V bit */ 2178 tcg_gen_sari_tl(low, low, 31); 2179 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); 2180 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2181 /* calc SV bit */ 2182 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2183 /* Calc AV bit */ 2184 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2185 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2186 /* calc SAV bit */ 2187 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2188 } 2189 2190 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) 2191 { 2192 TCGv temp = tcg_constant_i32(con); 2193 gen_mul_i32s(ret, r1, temp); 2194 } 2195 2196 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2197 { 2198 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); 2199 /* clear V bit */ 2200 tcg_gen_movi_tl(cpu_PSW_V, 0); 2201 /* calc SV bit */ 2202 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2203 /* Calc AV bit */ 2204 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2205 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2206 /* calc SAV bit */ 2207 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2208 } 2209 2210 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, 2211 int32_t con) 2212 { 2213 TCGv temp = tcg_constant_i32(con); 2214 gen_mul_i64s(ret_low, ret_high, r1, temp); 2215 } 2216 2217 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2218 { 2219 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); 2220 /* clear V bit */ 2221 tcg_gen_movi_tl(cpu_PSW_V, 0); 2222 /* calc SV bit */ 2223 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2224 /* Calc AV bit */ 2225 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2226 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2227 /* calc SAV bit */ 2228 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2229 } 2230 2231 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, 2232 int32_t con) 2233 { 2234 TCGv temp = tcg_constant_i32(con); 2235 gen_mul_i64u(ret_low, ret_high, r1, temp); 2236 } 2237 2238 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) 2239 { 2240 TCGv temp = tcg_constant_i32(con); 2241 gen_helper_mul_ssov(ret, cpu_env, r1, temp); 2242 } 2243 2244 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) 2245 { 2246 TCGv temp = tcg_constant_i32(con); 2247 gen_helper_mul_suov(ret, cpu_env, r1, temp); 2248 } 2249 2250 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ 2251 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2252 { 2253 TCGv temp = tcg_constant_i32(con); 2254 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); 2255 } 2256 2257 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2258 { 2259 TCGv temp = tcg_constant_i32(con); 2260 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); 2261 } 2262 2263 static void 2264 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) 2265 { 2266 TCGv_i64 temp_64 = tcg_temp_new_i64(); 2267 TCGv_i64 temp2_64 = tcg_temp_new_i64(); 2268 2269 if (n == 0) { 2270 if (up_shift == 32) { 2271 tcg_gen_muls2_tl(rh, rl, arg1, arg2); 2272 } else if (up_shift == 16) { 2273 tcg_gen_ext_i32_i64(temp_64, arg1); 2274 tcg_gen_ext_i32_i64(temp2_64, arg2); 2275 2276 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2277 tcg_gen_shri_i64(temp_64, temp_64, up_shift); 2278 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2279 } else { 2280 tcg_gen_muls2_tl(rl, rh, arg1, arg2); 2281 } 2282 /* reset v bit */ 2283 tcg_gen_movi_tl(cpu_PSW_V, 0); 2284 } else { /* n is expected to be 1 */ 2285 tcg_gen_ext_i32_i64(temp_64, arg1); 2286 tcg_gen_ext_i32_i64(temp2_64, arg2); 2287 2288 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2289 2290 if (up_shift == 0) { 2291 tcg_gen_shli_i64(temp_64, temp_64, 1); 2292 } else { 2293 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); 2294 } 2295 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2296 /* overflow only occurs if r1 = r2 = 0x8000 */ 2297 if (up_shift == 0) {/* result is 64 bit */ 2298 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, 2299 0x80000000); 2300 } else { /* result is 32 bit */ 2301 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, 2302 0x80000000); 2303 } 2304 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2305 /* calc sv overflow bit */ 2306 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2307 } 2308 /* calc av overflow bit */ 2309 if (up_shift == 0) { 2310 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2311 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2312 } else { 2313 tcg_gen_add_tl(cpu_PSW_AV, rl, rl); 2314 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); 2315 } 2316 /* calc sav overflow bit */ 2317 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2318 } 2319 2320 static void 2321 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2322 { 2323 TCGv temp = tcg_temp_new(); 2324 if (n == 0) { 2325 tcg_gen_mul_tl(ret, arg1, arg2); 2326 } else { /* n is expected to be 1 */ 2327 tcg_gen_mul_tl(ret, arg1, arg2); 2328 tcg_gen_shli_tl(ret, ret, 1); 2329 /* catch special case r1 = r2 = 0x8000 */ 2330 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); 2331 tcg_gen_sub_tl(ret, ret, temp); 2332 } 2333 /* reset v bit */ 2334 tcg_gen_movi_tl(cpu_PSW_V, 0); 2335 /* calc av overflow bit */ 2336 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2337 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2338 /* calc sav overflow bit */ 2339 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2340 } 2341 2342 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2343 { 2344 TCGv temp = tcg_temp_new(); 2345 if (n == 0) { 2346 tcg_gen_mul_tl(ret, arg1, arg2); 2347 tcg_gen_addi_tl(ret, ret, 0x8000); 2348 } else { 2349 tcg_gen_mul_tl(ret, arg1, arg2); 2350 tcg_gen_shli_tl(ret, ret, 1); 2351 tcg_gen_addi_tl(ret, ret, 0x8000); 2352 /* catch special case r1 = r2 = 0x8000 */ 2353 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); 2354 tcg_gen_muli_tl(temp, temp, 0x8001); 2355 tcg_gen_sub_tl(ret, ret, temp); 2356 } 2357 /* reset v bit */ 2358 tcg_gen_movi_tl(cpu_PSW_V, 0); 2359 /* calc av overflow bit */ 2360 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2361 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2362 /* calc sav overflow bit */ 2363 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2364 /* cut halfword off */ 2365 tcg_gen_andi_tl(ret, ret, 0xffff0000); 2366 } 2367 2368 static inline void 2369 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2370 TCGv r3) 2371 { 2372 TCGv_i64 temp64 = tcg_temp_new_i64(); 2373 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2374 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); 2375 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2376 } 2377 2378 static inline void 2379 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2380 int32_t con) 2381 { 2382 TCGv temp = tcg_constant_i32(con); 2383 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2384 } 2385 2386 static inline void 2387 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2388 TCGv r3) 2389 { 2390 TCGv_i64 temp64 = tcg_temp_new_i64(); 2391 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2392 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); 2393 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2394 } 2395 2396 static inline void 2397 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2398 int32_t con) 2399 { 2400 TCGv temp = tcg_constant_i32(con); 2401 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2402 } 2403 2404 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2405 { 2406 TCGv temp = tcg_constant_i32(con); 2407 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); 2408 } 2409 2410 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2411 { 2412 TCGv temp = tcg_constant_i32(con); 2413 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); 2414 } 2415 2416 static inline void 2417 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2418 TCGv r3) 2419 { 2420 TCGv_i64 temp64 = tcg_temp_new_i64(); 2421 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2422 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); 2423 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2424 } 2425 2426 static inline void 2427 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2428 int32_t con) 2429 { 2430 TCGv temp = tcg_constant_i32(con); 2431 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2432 } 2433 2434 static inline void 2435 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2436 TCGv r3) 2437 { 2438 TCGv_i64 temp64 = tcg_temp_new_i64(); 2439 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2440 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); 2441 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2442 } 2443 2444 static inline void 2445 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2446 int32_t con) 2447 { 2448 TCGv temp = tcg_constant_i32(con); 2449 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2450 } 2451 2452 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) 2453 { 2454 tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low)); 2455 tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up)); 2456 } 2457 2458 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) 2459 { 2460 tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up)); 2461 } 2462 2463 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) 2464 { 2465 if (shift_count == -32) { 2466 tcg_gen_movi_tl(ret, 0); 2467 } else if (shift_count >= 0) { 2468 tcg_gen_shli_tl(ret, r1, shift_count); 2469 } else { 2470 tcg_gen_shri_tl(ret, r1, -shift_count); 2471 } 2472 } 2473 2474 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) 2475 { 2476 TCGv temp_low, temp_high; 2477 2478 if (shiftcount == -16) { 2479 tcg_gen_movi_tl(ret, 0); 2480 } else { 2481 temp_high = tcg_temp_new(); 2482 temp_low = tcg_temp_new(); 2483 2484 tcg_gen_andi_tl(temp_low, r1, 0xffff); 2485 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); 2486 gen_shi(temp_low, temp_low, shiftcount); 2487 gen_shi(ret, temp_high, shiftcount); 2488 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); 2489 } 2490 } 2491 2492 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) 2493 { 2494 uint32_t msk, msk_start; 2495 TCGv temp = tcg_temp_new(); 2496 TCGv temp2 = tcg_temp_new(); 2497 2498 if (shift_count == 0) { 2499 /* Clear PSW.C and PSW.V */ 2500 tcg_gen_movi_tl(cpu_PSW_C, 0); 2501 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); 2502 tcg_gen_mov_tl(ret, r1); 2503 } else if (shift_count == -32) { 2504 /* set PSW.C */ 2505 tcg_gen_mov_tl(cpu_PSW_C, r1); 2506 /* fill ret completely with sign bit */ 2507 tcg_gen_sari_tl(ret, r1, 31); 2508 /* clear PSW.V */ 2509 tcg_gen_movi_tl(cpu_PSW_V, 0); 2510 } else if (shift_count > 0) { 2511 TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count); 2512 TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count); 2513 2514 /* calc carry */ 2515 msk_start = 32 - shift_count; 2516 msk = ((1 << shift_count) - 1) << msk_start; 2517 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2518 /* calc v/sv bits */ 2519 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); 2520 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); 2521 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 2522 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2523 /* calc sv */ 2524 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); 2525 /* do shift */ 2526 tcg_gen_shli_tl(ret, r1, shift_count); 2527 } else { 2528 /* clear PSW.V */ 2529 tcg_gen_movi_tl(cpu_PSW_V, 0); 2530 /* calc carry */ 2531 msk = (1 << -shift_count) - 1; 2532 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2533 /* do shift */ 2534 tcg_gen_sari_tl(ret, r1, -shift_count); 2535 } 2536 /* calc av overflow bit */ 2537 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2538 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2539 /* calc sav overflow bit */ 2540 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2541 } 2542 2543 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) 2544 { 2545 gen_helper_sha_ssov(ret, cpu_env, r1, r2); 2546 } 2547 2548 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) 2549 { 2550 TCGv temp = tcg_constant_i32(con); 2551 gen_shas(ret, r1, temp); 2552 } 2553 2554 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) 2555 { 2556 TCGv low, high; 2557 2558 if (shift_count == 0) { 2559 tcg_gen_mov_tl(ret, r1); 2560 } else if (shift_count > 0) { 2561 low = tcg_temp_new(); 2562 high = tcg_temp_new(); 2563 2564 tcg_gen_andi_tl(high, r1, 0xffff0000); 2565 tcg_gen_shli_tl(low, r1, shift_count); 2566 tcg_gen_shli_tl(ret, high, shift_count); 2567 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2568 } else { 2569 low = tcg_temp_new(); 2570 high = tcg_temp_new(); 2571 2572 tcg_gen_ext16s_tl(low, r1); 2573 tcg_gen_sari_tl(low, low, -shift_count); 2574 tcg_gen_sari_tl(ret, r1, -shift_count); 2575 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2576 } 2577 } 2578 2579 /* ret = {ret[30:0], (r1 cond r2)}; */ 2580 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) 2581 { 2582 TCGv temp = tcg_temp_new(); 2583 TCGv temp2 = tcg_temp_new(); 2584 2585 tcg_gen_shli_tl(temp, ret, 1); 2586 tcg_gen_setcond_tl(cond, temp2, r1, r2); 2587 tcg_gen_or_tl(ret, temp, temp2); 2588 } 2589 2590 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) 2591 { 2592 TCGv temp = tcg_constant_i32(con); 2593 gen_sh_cond(cond, ret, r1, temp); 2594 } 2595 2596 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) 2597 { 2598 gen_helper_add_ssov(ret, cpu_env, r1, r2); 2599 } 2600 2601 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) 2602 { 2603 TCGv temp = tcg_constant_i32(con); 2604 gen_helper_add_ssov(ret, cpu_env, r1, temp); 2605 } 2606 2607 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) 2608 { 2609 TCGv temp = tcg_constant_i32(con); 2610 gen_helper_add_suov(ret, cpu_env, r1, temp); 2611 } 2612 2613 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) 2614 { 2615 gen_helper_sub_ssov(ret, cpu_env, r1, r2); 2616 } 2617 2618 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) 2619 { 2620 gen_helper_sub_suov(ret, cpu_env, r1, r2); 2621 } 2622 2623 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, 2624 int pos1, int pos2, 2625 void(*op1)(TCGv, TCGv, TCGv), 2626 void(*op2)(TCGv, TCGv, TCGv)) 2627 { 2628 TCGv temp1, temp2; 2629 2630 temp1 = tcg_temp_new(); 2631 temp2 = tcg_temp_new(); 2632 2633 tcg_gen_shri_tl(temp2, r2, pos2); 2634 tcg_gen_shri_tl(temp1, r1, pos1); 2635 2636 (*op1)(temp1, temp1, temp2); 2637 (*op2)(temp1 , ret, temp1); 2638 2639 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); 2640 } 2641 2642 /* ret = r1[pos1] op1 r2[pos2]; */ 2643 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, 2644 int pos1, int pos2, 2645 void(*op1)(TCGv, TCGv, TCGv)) 2646 { 2647 TCGv temp1, temp2; 2648 2649 temp1 = tcg_temp_new(); 2650 temp2 = tcg_temp_new(); 2651 2652 tcg_gen_shri_tl(temp2, r2, pos2); 2653 tcg_gen_shri_tl(temp1, r1, pos1); 2654 2655 (*op1)(ret, temp1, temp2); 2656 2657 tcg_gen_andi_tl(ret, ret, 0x1); 2658 } 2659 2660 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, 2661 void(*op)(TCGv, TCGv, TCGv)) 2662 { 2663 TCGv temp = tcg_temp_new(); 2664 TCGv temp2 = tcg_temp_new(); 2665 /* temp = (arg1 cond arg2 )*/ 2666 tcg_gen_setcond_tl(cond, temp, r1, r2); 2667 /* temp2 = ret[0]*/ 2668 tcg_gen_andi_tl(temp2, ret, 0x1); 2669 /* temp = temp insn temp2 */ 2670 (*op)(temp, temp, temp2); 2671 /* ret = {ret[31:1], temp} */ 2672 tcg_gen_deposit_tl(ret, ret, temp, 0, 1); 2673 } 2674 2675 static inline void 2676 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, 2677 void(*op)(TCGv, TCGv, TCGv)) 2678 { 2679 TCGv temp = tcg_constant_i32(con); 2680 gen_accumulating_cond(cond, ret, r1, temp, op); 2681 } 2682 2683 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ 2684 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2) 2685 { 2686 tcg_gen_setcond_tl(cond, ret, r1, r2); 2687 tcg_gen_neg_tl(ret, ret); 2688 } 2689 2690 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) 2691 { 2692 TCGv b0 = tcg_temp_new(); 2693 TCGv b1 = tcg_temp_new(); 2694 TCGv b2 = tcg_temp_new(); 2695 TCGv b3 = tcg_temp_new(); 2696 2697 /* byte 0 */ 2698 tcg_gen_andi_tl(b0, r1, 0xff); 2699 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); 2700 2701 /* byte 1 */ 2702 tcg_gen_andi_tl(b1, r1, 0xff00); 2703 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); 2704 2705 /* byte 2 */ 2706 tcg_gen_andi_tl(b2, r1, 0xff0000); 2707 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); 2708 2709 /* byte 3 */ 2710 tcg_gen_andi_tl(b3, r1, 0xff000000); 2711 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); 2712 2713 /* combine them */ 2714 tcg_gen_or_tl(ret, b0, b1); 2715 tcg_gen_or_tl(ret, ret, b2); 2716 tcg_gen_or_tl(ret, ret, b3); 2717 } 2718 2719 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) 2720 { 2721 TCGv h0 = tcg_temp_new(); 2722 TCGv h1 = tcg_temp_new(); 2723 2724 /* halfword 0 */ 2725 tcg_gen_andi_tl(h0, r1, 0xffff); 2726 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); 2727 2728 /* halfword 1 */ 2729 tcg_gen_andi_tl(h1, r1, 0xffff0000); 2730 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); 2731 2732 /* combine them */ 2733 tcg_gen_or_tl(ret, h0, h1); 2734 } 2735 2736 /* mask = ((1 << width) -1) << pos; 2737 ret = (r1 & ~mask) | (r2 << pos) & mask); */ 2738 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) 2739 { 2740 TCGv mask = tcg_temp_new(); 2741 TCGv temp = tcg_temp_new(); 2742 TCGv temp2 = tcg_temp_new(); 2743 2744 tcg_gen_movi_tl(mask, 1); 2745 tcg_gen_shl_tl(mask, mask, width); 2746 tcg_gen_subi_tl(mask, mask, 1); 2747 tcg_gen_shl_tl(mask, mask, pos); 2748 2749 tcg_gen_shl_tl(temp, r2, pos); 2750 tcg_gen_and_tl(temp, temp, mask); 2751 tcg_gen_andc_tl(temp2, r1, mask); 2752 tcg_gen_or_tl(ret, temp, temp2); 2753 } 2754 2755 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) 2756 { 2757 TCGv_i64 temp = tcg_temp_new_i64(); 2758 2759 gen_helper_bsplit(temp, r1); 2760 tcg_gen_extr_i64_i32(rl, rh, temp); 2761 } 2762 2763 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) 2764 { 2765 TCGv_i64 temp = tcg_temp_new_i64(); 2766 2767 gen_helper_unpack(temp, r1); 2768 tcg_gen_extr_i64_i32(rl, rh, temp); 2769 } 2770 2771 static inline void 2772 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2773 { 2774 TCGv_i64 ret = tcg_temp_new_i64(); 2775 2776 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2777 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); 2778 } else { 2779 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); 2780 } 2781 tcg_gen_extr_i64_i32(rl, rh, ret); 2782 } 2783 2784 static inline void 2785 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2786 { 2787 TCGv_i64 ret = tcg_temp_new_i64(); 2788 2789 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2790 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); 2791 } else { 2792 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); 2793 } 2794 tcg_gen_extr_i64_i32(rl, rh, ret); 2795 } 2796 2797 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) 2798 { 2799 TCGv temp = tcg_temp_new(); 2800 /* calc AV bit */ 2801 tcg_gen_add_tl(temp, arg_low, arg_low); 2802 tcg_gen_xor_tl(temp, temp, arg_low); 2803 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); 2804 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); 2805 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2806 /* calc SAV bit */ 2807 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2808 tcg_gen_movi_tl(cpu_PSW_V, 0); 2809 } 2810 2811 static void gen_calc_usb_mulr_h(TCGv arg) 2812 { 2813 TCGv temp = tcg_temp_new(); 2814 /* calc AV bit */ 2815 tcg_gen_add_tl(temp, arg, arg); 2816 tcg_gen_xor_tl(temp, temp, arg); 2817 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); 2818 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2819 /* calc SAV bit */ 2820 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2821 /* clear V bit */ 2822 tcg_gen_movi_tl(cpu_PSW_V, 0); 2823 } 2824 2825 /* helpers for generating program flow micro-ops */ 2826 2827 static inline void gen_save_pc(target_ulong pc) 2828 { 2829 tcg_gen_movi_tl(cpu_PC, pc); 2830 } 2831 2832 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 2833 { 2834 if (translator_use_goto_tb(&ctx->base, dest)) { 2835 tcg_gen_goto_tb(n); 2836 gen_save_pc(dest); 2837 tcg_gen_exit_tb(ctx->base.tb, n); 2838 } else { 2839 gen_save_pc(dest); 2840 tcg_gen_lookup_and_goto_ptr(); 2841 } 2842 ctx->base.is_jmp = DISAS_NORETURN; 2843 } 2844 2845 static void generate_trap(DisasContext *ctx, int class, int tin) 2846 { 2847 TCGv_i32 classtemp = tcg_constant_i32(class); 2848 TCGv_i32 tintemp = tcg_constant_i32(tin); 2849 2850 gen_save_pc(ctx->base.pc_next); 2851 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); 2852 ctx->base.is_jmp = DISAS_NORETURN; 2853 } 2854 2855 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, 2856 TCGv r2, int16_t address) 2857 { 2858 TCGLabel *jumpLabel = gen_new_label(); 2859 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); 2860 2861 gen_goto_tb(ctx, 1, ctx->pc_succ_insn); 2862 2863 gen_set_label(jumpLabel); 2864 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); 2865 } 2866 2867 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, 2868 int r2, int16_t address) 2869 { 2870 TCGv temp = tcg_constant_i32(r2); 2871 gen_branch_cond(ctx, cond, r1, temp, address); 2872 } 2873 2874 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) 2875 { 2876 TCGLabel *l1 = gen_new_label(); 2877 2878 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); 2879 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); 2880 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); 2881 gen_set_label(l1); 2882 gen_goto_tb(ctx, 0, ctx->pc_succ_insn); 2883 } 2884 2885 static void gen_fcall_save_ctx(DisasContext *ctx) 2886 { 2887 TCGv temp = tcg_temp_new(); 2888 2889 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); 2890 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); 2891 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 2892 tcg_gen_mov_tl(cpu_gpr_a[10], temp); 2893 } 2894 2895 static void gen_fret(DisasContext *ctx) 2896 { 2897 TCGv temp = tcg_temp_new(); 2898 2899 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); 2900 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); 2901 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); 2902 tcg_gen_mov_tl(cpu_PC, temp); 2903 ctx->base.is_jmp = DISAS_EXIT; 2904 } 2905 2906 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 2907 int r2 , int32_t constant , int32_t offset) 2908 { 2909 TCGv temp, temp2; 2910 int n; 2911 2912 switch (opc) { 2913 /* SB-format jumps */ 2914 case OPC1_16_SB_J: 2915 case OPC1_32_B_J: 2916 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2917 break; 2918 case OPC1_32_B_CALL: 2919 case OPC1_16_SB_CALL: 2920 gen_helper_1arg(call, ctx->pc_succ_insn); 2921 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2922 break; 2923 case OPC1_16_SB_JZ: 2924 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); 2925 break; 2926 case OPC1_16_SB_JNZ: 2927 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); 2928 break; 2929 /* SBC-format jumps */ 2930 case OPC1_16_SBC_JEQ: 2931 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); 2932 break; 2933 case OPC1_16_SBC_JEQ2: 2934 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, 2935 offset + 16); 2936 break; 2937 case OPC1_16_SBC_JNE: 2938 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); 2939 break; 2940 case OPC1_16_SBC_JNE2: 2941 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 2942 constant, offset + 16); 2943 break; 2944 /* SBRN-format jumps */ 2945 case OPC1_16_SBRN_JZ_T: 2946 temp = tcg_temp_new(); 2947 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2948 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 2949 break; 2950 case OPC1_16_SBRN_JNZ_T: 2951 temp = tcg_temp_new(); 2952 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2953 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 2954 break; 2955 /* SBR-format jumps */ 2956 case OPC1_16_SBR_JEQ: 2957 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2958 offset); 2959 break; 2960 case OPC1_16_SBR_JEQ2: 2961 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2962 offset + 16); 2963 break; 2964 case OPC1_16_SBR_JNE: 2965 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2966 offset); 2967 break; 2968 case OPC1_16_SBR_JNE2: 2969 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2970 offset + 16); 2971 break; 2972 case OPC1_16_SBR_JNZ: 2973 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); 2974 break; 2975 case OPC1_16_SBR_JNZ_A: 2976 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 2977 break; 2978 case OPC1_16_SBR_JGEZ: 2979 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); 2980 break; 2981 case OPC1_16_SBR_JGTZ: 2982 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); 2983 break; 2984 case OPC1_16_SBR_JLEZ: 2985 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); 2986 break; 2987 case OPC1_16_SBR_JLTZ: 2988 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); 2989 break; 2990 case OPC1_16_SBR_JZ: 2991 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); 2992 break; 2993 case OPC1_16_SBR_JZ_A: 2994 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 2995 break; 2996 case OPC1_16_SBR_LOOP: 2997 gen_loop(ctx, r1, offset * 2 - 32); 2998 break; 2999 /* SR-format jumps */ 3000 case OPC1_16_SR_JI: 3001 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); 3002 ctx->base.is_jmp = DISAS_EXIT; 3003 break; 3004 case OPC2_32_SYS_RET: 3005 case OPC2_16_SR_RET: 3006 gen_helper_ret(cpu_env); 3007 ctx->base.is_jmp = DISAS_EXIT; 3008 break; 3009 /* B-format */ 3010 case OPC1_32_B_CALLA: 3011 gen_helper_1arg(call, ctx->pc_succ_insn); 3012 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3013 break; 3014 case OPC1_32_B_FCALL: 3015 gen_fcall_save_ctx(ctx); 3016 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3017 break; 3018 case OPC1_32_B_FCALLA: 3019 gen_fcall_save_ctx(ctx); 3020 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3021 break; 3022 case OPC1_32_B_JLA: 3023 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3024 /* fall through */ 3025 case OPC1_32_B_JA: 3026 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3027 break; 3028 case OPC1_32_B_JL: 3029 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3030 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3031 break; 3032 /* BOL format */ 3033 case OPCM_32_BRC_EQ_NEQ: 3034 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { 3035 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); 3036 } else { 3037 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); 3038 } 3039 break; 3040 case OPCM_32_BRC_GE: 3041 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { 3042 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); 3043 } else { 3044 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3045 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, 3046 offset); 3047 } 3048 break; 3049 case OPCM_32_BRC_JLT: 3050 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { 3051 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); 3052 } else { 3053 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3054 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, 3055 offset); 3056 } 3057 break; 3058 case OPCM_32_BRC_JNE: 3059 temp = tcg_temp_new(); 3060 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { 3061 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3062 /* subi is unconditional */ 3063 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3064 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3065 } else { 3066 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3067 /* addi is unconditional */ 3068 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3069 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3070 } 3071 break; 3072 /* BRN format */ 3073 case OPCM_32_BRN_JTT: 3074 n = MASK_OP_BRN_N(ctx->opcode); 3075 3076 temp = tcg_temp_new(); 3077 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); 3078 3079 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { 3080 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3081 } else { 3082 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3083 } 3084 break; 3085 /* BRR Format */ 3086 case OPCM_32_BRR_EQ_NEQ: 3087 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { 3088 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], 3089 offset); 3090 } else { 3091 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3092 offset); 3093 } 3094 break; 3095 case OPCM_32_BRR_ADDR_EQ_NEQ: 3096 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { 3097 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], 3098 offset); 3099 } else { 3100 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], 3101 offset); 3102 } 3103 break; 3104 case OPCM_32_BRR_GE: 3105 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { 3106 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3107 offset); 3108 } else { 3109 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3110 offset); 3111 } 3112 break; 3113 case OPCM_32_BRR_JLT: 3114 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { 3115 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], 3116 offset); 3117 } else { 3118 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3119 offset); 3120 } 3121 break; 3122 case OPCM_32_BRR_LOOP: 3123 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { 3124 gen_loop(ctx, r2, offset * 2); 3125 } else { 3126 /* OPC2_32_BRR_LOOPU */ 3127 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3128 } 3129 break; 3130 case OPCM_32_BRR_JNE: 3131 temp = tcg_temp_new(); 3132 temp2 = tcg_temp_new(); 3133 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { 3134 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3135 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3136 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3137 /* subi is unconditional */ 3138 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3139 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3140 } else { 3141 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3142 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3143 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3144 /* addi is unconditional */ 3145 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3146 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3147 } 3148 break; 3149 case OPCM_32_BRR_JNZ: 3150 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { 3151 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3152 } else { 3153 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3154 } 3155 break; 3156 default: 3157 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3158 } 3159 } 3160 3161 3162 /* 3163 * Functions for decoding instructions 3164 */ 3165 3166 static void decode_src_opc(DisasContext *ctx, int op1) 3167 { 3168 int r1; 3169 int32_t const4; 3170 TCGv temp, temp2; 3171 3172 r1 = MASK_OP_SRC_S1D(ctx->opcode); 3173 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); 3174 3175 switch (op1) { 3176 case OPC1_16_SRC_ADD: 3177 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3178 break; 3179 case OPC1_16_SRC_ADD_A15: 3180 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); 3181 break; 3182 case OPC1_16_SRC_ADD_15A: 3183 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); 3184 break; 3185 case OPC1_16_SRC_ADD_A: 3186 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); 3187 break; 3188 case OPC1_16_SRC_CADD: 3189 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3190 cpu_gpr_d[15]); 3191 break; 3192 case OPC1_16_SRC_CADDN: 3193 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3194 cpu_gpr_d[15]); 3195 break; 3196 case OPC1_16_SRC_CMOV: 3197 temp = tcg_constant_tl(0); 3198 temp2 = tcg_constant_tl(const4); 3199 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3200 temp2, cpu_gpr_d[r1]); 3201 break; 3202 case OPC1_16_SRC_CMOVN: 3203 temp = tcg_constant_tl(0); 3204 temp2 = tcg_constant_tl(const4); 3205 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3206 temp2, cpu_gpr_d[r1]); 3207 break; 3208 case OPC1_16_SRC_EQ: 3209 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3210 const4); 3211 break; 3212 case OPC1_16_SRC_LT: 3213 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3214 const4); 3215 break; 3216 case OPC1_16_SRC_MOV: 3217 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3218 break; 3219 case OPC1_16_SRC_MOV_A: 3220 const4 = MASK_OP_SRC_CONST4(ctx->opcode); 3221 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); 3222 break; 3223 case OPC1_16_SRC_MOV_E: 3224 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3225 CHECK_REG_PAIR(r1); 3226 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3227 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); 3228 } else { 3229 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3230 } 3231 break; 3232 case OPC1_16_SRC_SH: 3233 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3234 break; 3235 case OPC1_16_SRC_SHA: 3236 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3237 break; 3238 default: 3239 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3240 } 3241 } 3242 3243 static void decode_srr_opc(DisasContext *ctx, int op1) 3244 { 3245 int r1, r2; 3246 TCGv temp; 3247 3248 r1 = MASK_OP_SRR_S1D(ctx->opcode); 3249 r2 = MASK_OP_SRR_S2(ctx->opcode); 3250 3251 switch (op1) { 3252 case OPC1_16_SRR_ADD: 3253 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3254 break; 3255 case OPC1_16_SRR_ADD_A15: 3256 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3257 break; 3258 case OPC1_16_SRR_ADD_15A: 3259 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3260 break; 3261 case OPC1_16_SRR_ADD_A: 3262 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); 3263 break; 3264 case OPC1_16_SRR_ADDS: 3265 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3266 break; 3267 case OPC1_16_SRR_AND: 3268 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3269 break; 3270 case OPC1_16_SRR_CMOV: 3271 temp = tcg_constant_tl(0); 3272 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3273 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3274 break; 3275 case OPC1_16_SRR_CMOVN: 3276 temp = tcg_constant_tl(0); 3277 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3278 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3279 break; 3280 case OPC1_16_SRR_EQ: 3281 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3282 cpu_gpr_d[r2]); 3283 break; 3284 case OPC1_16_SRR_LT: 3285 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3286 cpu_gpr_d[r2]); 3287 break; 3288 case OPC1_16_SRR_MOV: 3289 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); 3290 break; 3291 case OPC1_16_SRR_MOV_A: 3292 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); 3293 break; 3294 case OPC1_16_SRR_MOV_AA: 3295 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); 3296 break; 3297 case OPC1_16_SRR_MOV_D: 3298 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); 3299 break; 3300 case OPC1_16_SRR_MUL: 3301 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3302 break; 3303 case OPC1_16_SRR_OR: 3304 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3305 break; 3306 case OPC1_16_SRR_SUB: 3307 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3308 break; 3309 case OPC1_16_SRR_SUB_A15B: 3310 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3311 break; 3312 case OPC1_16_SRR_SUB_15AB: 3313 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3314 break; 3315 case OPC1_16_SRR_SUBS: 3316 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3317 break; 3318 case OPC1_16_SRR_XOR: 3319 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3320 break; 3321 default: 3322 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3323 } 3324 } 3325 3326 static void decode_ssr_opc(DisasContext *ctx, int op1) 3327 { 3328 int r1, r2; 3329 3330 r1 = MASK_OP_SSR_S1(ctx->opcode); 3331 r2 = MASK_OP_SSR_S2(ctx->opcode); 3332 3333 switch (op1) { 3334 case OPC1_16_SSR_ST_A: 3335 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3336 break; 3337 case OPC1_16_SSR_ST_A_POSTINC: 3338 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3339 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3340 break; 3341 case OPC1_16_SSR_ST_B: 3342 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3343 break; 3344 case OPC1_16_SSR_ST_B_POSTINC: 3345 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3346 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3347 break; 3348 case OPC1_16_SSR_ST_H: 3349 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3350 break; 3351 case OPC1_16_SSR_ST_H_POSTINC: 3352 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3353 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3354 break; 3355 case OPC1_16_SSR_ST_W: 3356 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3357 break; 3358 case OPC1_16_SSR_ST_W_POSTINC: 3359 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3360 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3361 break; 3362 default: 3363 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3364 } 3365 } 3366 3367 static void decode_sc_opc(DisasContext *ctx, int op1) 3368 { 3369 int32_t const16; 3370 3371 const16 = MASK_OP_SC_CONST8(ctx->opcode); 3372 3373 switch (op1) { 3374 case OPC1_16_SC_AND: 3375 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3376 break; 3377 case OPC1_16_SC_BISR: 3378 if (ctx->priv == TRICORE_PRIV_SM) { 3379 gen_helper_1arg(bisr, const16 & 0xff); 3380 } else { 3381 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 3382 } 3383 break; 3384 case OPC1_16_SC_LD_A: 3385 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3386 break; 3387 case OPC1_16_SC_LD_W: 3388 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3389 break; 3390 case OPC1_16_SC_MOV: 3391 tcg_gen_movi_tl(cpu_gpr_d[15], const16); 3392 break; 3393 case OPC1_16_SC_OR: 3394 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3395 break; 3396 case OPC1_16_SC_ST_A: 3397 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3398 break; 3399 case OPC1_16_SC_ST_W: 3400 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3401 break; 3402 case OPC1_16_SC_SUB_A: 3403 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); 3404 break; 3405 default: 3406 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3407 } 3408 } 3409 3410 static void decode_slr_opc(DisasContext *ctx, int op1) 3411 { 3412 int r1, r2; 3413 3414 r1 = MASK_OP_SLR_D(ctx->opcode); 3415 r2 = MASK_OP_SLR_S2(ctx->opcode); 3416 3417 switch (op1) { 3418 /* SLR-format */ 3419 case OPC1_16_SLR_LD_A: 3420 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3421 break; 3422 case OPC1_16_SLR_LD_A_POSTINC: 3423 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3424 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3425 break; 3426 case OPC1_16_SLR_LD_BU: 3427 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3428 break; 3429 case OPC1_16_SLR_LD_BU_POSTINC: 3430 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3431 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3432 break; 3433 case OPC1_16_SLR_LD_H: 3434 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3435 break; 3436 case OPC1_16_SLR_LD_H_POSTINC: 3437 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3438 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3439 break; 3440 case OPC1_16_SLR_LD_W: 3441 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3442 break; 3443 case OPC1_16_SLR_LD_W_POSTINC: 3444 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3445 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3446 break; 3447 default: 3448 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3449 } 3450 } 3451 3452 static void decode_sro_opc(DisasContext *ctx, int op1) 3453 { 3454 int r2; 3455 int32_t address; 3456 3457 r2 = MASK_OP_SRO_S2(ctx->opcode); 3458 address = MASK_OP_SRO_OFF4(ctx->opcode); 3459 3460 /* SRO-format */ 3461 switch (op1) { 3462 case OPC1_16_SRO_LD_A: 3463 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3464 break; 3465 case OPC1_16_SRO_LD_BU: 3466 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3467 break; 3468 case OPC1_16_SRO_LD_H: 3469 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3470 break; 3471 case OPC1_16_SRO_LD_W: 3472 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3473 break; 3474 case OPC1_16_SRO_ST_A: 3475 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3476 break; 3477 case OPC1_16_SRO_ST_B: 3478 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3479 break; 3480 case OPC1_16_SRO_ST_H: 3481 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3482 break; 3483 case OPC1_16_SRO_ST_W: 3484 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3485 break; 3486 default: 3487 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3488 } 3489 } 3490 3491 static void decode_sr_system(DisasContext *ctx) 3492 { 3493 uint32_t op2; 3494 op2 = MASK_OP_SR_OP2(ctx->opcode); 3495 3496 switch (op2) { 3497 case OPC2_16_SR_NOP: 3498 break; 3499 case OPC2_16_SR_RET: 3500 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 3501 break; 3502 case OPC2_16_SR_RFE: 3503 gen_helper_rfe(cpu_env); 3504 ctx->base.is_jmp = DISAS_EXIT; 3505 break; 3506 case OPC2_16_SR_DEBUG: 3507 /* raise EXCP_DEBUG */ 3508 break; 3509 case OPC2_16_SR_FRET: 3510 gen_fret(ctx); 3511 break; 3512 default: 3513 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3514 } 3515 } 3516 3517 static void decode_sr_accu(DisasContext *ctx) 3518 { 3519 uint32_t op2; 3520 uint32_t r1; 3521 3522 r1 = MASK_OP_SR_S1D(ctx->opcode); 3523 op2 = MASK_OP_SR_OP2(ctx->opcode); 3524 3525 switch (op2) { 3526 case OPC2_16_SR_RSUB: 3527 /* calc V bit -- overflow only if r1 = -0x80000000 */ 3528 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000); 3529 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 3530 /* calc SV bit */ 3531 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 3532 /* sub */ 3533 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3534 /* calc av */ 3535 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); 3536 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); 3537 /* calc sav */ 3538 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3539 break; 3540 case OPC2_16_SR_SAT_B: 3541 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); 3542 break; 3543 case OPC2_16_SR_SAT_BU: 3544 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); 3545 break; 3546 case OPC2_16_SR_SAT_H: 3547 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); 3548 break; 3549 case OPC2_16_SR_SAT_HU: 3550 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); 3551 break; 3552 default: 3553 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3554 } 3555 } 3556 3557 static void decode_16Bit_opc(DisasContext *ctx) 3558 { 3559 int op1; 3560 int r1, r2; 3561 int32_t const16; 3562 int32_t address; 3563 TCGv temp; 3564 3565 op1 = MASK_OP_MAJOR(ctx->opcode); 3566 3567 /* handle ADDSC.A opcode only being 6 bit long */ 3568 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { 3569 op1 = OPC1_16_SRRS_ADDSC_A; 3570 } 3571 3572 switch (op1) { 3573 case OPC1_16_SRC_ADD: 3574 case OPC1_16_SRC_ADD_A15: 3575 case OPC1_16_SRC_ADD_15A: 3576 case OPC1_16_SRC_ADD_A: 3577 case OPC1_16_SRC_CADD: 3578 case OPC1_16_SRC_CADDN: 3579 case OPC1_16_SRC_CMOV: 3580 case OPC1_16_SRC_CMOVN: 3581 case OPC1_16_SRC_EQ: 3582 case OPC1_16_SRC_LT: 3583 case OPC1_16_SRC_MOV: 3584 case OPC1_16_SRC_MOV_A: 3585 case OPC1_16_SRC_MOV_E: 3586 case OPC1_16_SRC_SH: 3587 case OPC1_16_SRC_SHA: 3588 decode_src_opc(ctx, op1); 3589 break; 3590 /* SRR-format */ 3591 case OPC1_16_SRR_ADD: 3592 case OPC1_16_SRR_ADD_A15: 3593 case OPC1_16_SRR_ADD_15A: 3594 case OPC1_16_SRR_ADD_A: 3595 case OPC1_16_SRR_ADDS: 3596 case OPC1_16_SRR_AND: 3597 case OPC1_16_SRR_CMOV: 3598 case OPC1_16_SRR_CMOVN: 3599 case OPC1_16_SRR_EQ: 3600 case OPC1_16_SRR_LT: 3601 case OPC1_16_SRR_MOV: 3602 case OPC1_16_SRR_MOV_A: 3603 case OPC1_16_SRR_MOV_AA: 3604 case OPC1_16_SRR_MOV_D: 3605 case OPC1_16_SRR_MUL: 3606 case OPC1_16_SRR_OR: 3607 case OPC1_16_SRR_SUB: 3608 case OPC1_16_SRR_SUB_A15B: 3609 case OPC1_16_SRR_SUB_15AB: 3610 case OPC1_16_SRR_SUBS: 3611 case OPC1_16_SRR_XOR: 3612 decode_srr_opc(ctx, op1); 3613 break; 3614 /* SSR-format */ 3615 case OPC1_16_SSR_ST_A: 3616 case OPC1_16_SSR_ST_A_POSTINC: 3617 case OPC1_16_SSR_ST_B: 3618 case OPC1_16_SSR_ST_B_POSTINC: 3619 case OPC1_16_SSR_ST_H: 3620 case OPC1_16_SSR_ST_H_POSTINC: 3621 case OPC1_16_SSR_ST_W: 3622 case OPC1_16_SSR_ST_W_POSTINC: 3623 decode_ssr_opc(ctx, op1); 3624 break; 3625 /* SRRS-format */ 3626 case OPC1_16_SRRS_ADDSC_A: 3627 r2 = MASK_OP_SRRS_S2(ctx->opcode); 3628 r1 = MASK_OP_SRRS_S1D(ctx->opcode); 3629 const16 = MASK_OP_SRRS_N(ctx->opcode); 3630 temp = tcg_temp_new(); 3631 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); 3632 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); 3633 break; 3634 /* SLRO-format */ 3635 case OPC1_16_SLRO_LD_A: 3636 r1 = MASK_OP_SLRO_D(ctx->opcode); 3637 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3638 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3639 break; 3640 case OPC1_16_SLRO_LD_BU: 3641 r1 = MASK_OP_SLRO_D(ctx->opcode); 3642 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3643 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3644 break; 3645 case OPC1_16_SLRO_LD_H: 3646 r1 = MASK_OP_SLRO_D(ctx->opcode); 3647 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3648 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3649 break; 3650 case OPC1_16_SLRO_LD_W: 3651 r1 = MASK_OP_SLRO_D(ctx->opcode); 3652 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3653 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3654 break; 3655 /* SB-format */ 3656 case OPC1_16_SB_CALL: 3657 case OPC1_16_SB_J: 3658 case OPC1_16_SB_JNZ: 3659 case OPC1_16_SB_JZ: 3660 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); 3661 gen_compute_branch(ctx, op1, 0, 0, 0, address); 3662 break; 3663 /* SBC-format */ 3664 case OPC1_16_SBC_JEQ: 3665 case OPC1_16_SBC_JNE: 3666 address = MASK_OP_SBC_DISP4(ctx->opcode); 3667 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3668 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3669 break; 3670 case OPC1_16_SBC_JEQ2: 3671 case OPC1_16_SBC_JNE2: 3672 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3673 address = MASK_OP_SBC_DISP4(ctx->opcode); 3674 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3675 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3676 } else { 3677 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3678 } 3679 break; 3680 /* SBRN-format */ 3681 case OPC1_16_SBRN_JNZ_T: 3682 case OPC1_16_SBRN_JZ_T: 3683 address = MASK_OP_SBRN_DISP4(ctx->opcode); 3684 const16 = MASK_OP_SBRN_N(ctx->opcode); 3685 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3686 break; 3687 /* SBR-format */ 3688 case OPC1_16_SBR_JEQ2: 3689 case OPC1_16_SBR_JNE2: 3690 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3691 r1 = MASK_OP_SBR_S2(ctx->opcode); 3692 address = MASK_OP_SBR_DISP4(ctx->opcode); 3693 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3694 } else { 3695 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3696 } 3697 break; 3698 case OPC1_16_SBR_JEQ: 3699 case OPC1_16_SBR_JGEZ: 3700 case OPC1_16_SBR_JGTZ: 3701 case OPC1_16_SBR_JLEZ: 3702 case OPC1_16_SBR_JLTZ: 3703 case OPC1_16_SBR_JNE: 3704 case OPC1_16_SBR_JNZ: 3705 case OPC1_16_SBR_JNZ_A: 3706 case OPC1_16_SBR_JZ: 3707 case OPC1_16_SBR_JZ_A: 3708 case OPC1_16_SBR_LOOP: 3709 r1 = MASK_OP_SBR_S2(ctx->opcode); 3710 address = MASK_OP_SBR_DISP4(ctx->opcode); 3711 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3712 break; 3713 /* SC-format */ 3714 case OPC1_16_SC_AND: 3715 case OPC1_16_SC_BISR: 3716 case OPC1_16_SC_LD_A: 3717 case OPC1_16_SC_LD_W: 3718 case OPC1_16_SC_MOV: 3719 case OPC1_16_SC_OR: 3720 case OPC1_16_SC_ST_A: 3721 case OPC1_16_SC_ST_W: 3722 case OPC1_16_SC_SUB_A: 3723 decode_sc_opc(ctx, op1); 3724 break; 3725 /* SLR-format */ 3726 case OPC1_16_SLR_LD_A: 3727 case OPC1_16_SLR_LD_A_POSTINC: 3728 case OPC1_16_SLR_LD_BU: 3729 case OPC1_16_SLR_LD_BU_POSTINC: 3730 case OPC1_16_SLR_LD_H: 3731 case OPC1_16_SLR_LD_H_POSTINC: 3732 case OPC1_16_SLR_LD_W: 3733 case OPC1_16_SLR_LD_W_POSTINC: 3734 decode_slr_opc(ctx, op1); 3735 break; 3736 /* SRO-format */ 3737 case OPC1_16_SRO_LD_A: 3738 case OPC1_16_SRO_LD_BU: 3739 case OPC1_16_SRO_LD_H: 3740 case OPC1_16_SRO_LD_W: 3741 case OPC1_16_SRO_ST_A: 3742 case OPC1_16_SRO_ST_B: 3743 case OPC1_16_SRO_ST_H: 3744 case OPC1_16_SRO_ST_W: 3745 decode_sro_opc(ctx, op1); 3746 break; 3747 /* SSRO-format */ 3748 case OPC1_16_SSRO_ST_A: 3749 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3750 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3751 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3752 break; 3753 case OPC1_16_SSRO_ST_B: 3754 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3755 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3756 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3757 break; 3758 case OPC1_16_SSRO_ST_H: 3759 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3760 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3761 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3762 break; 3763 case OPC1_16_SSRO_ST_W: 3764 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3765 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3766 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3767 break; 3768 /* SR-format */ 3769 case OPCM_16_SR_SYSTEM: 3770 decode_sr_system(ctx); 3771 break; 3772 case OPCM_16_SR_ACCU: 3773 decode_sr_accu(ctx); 3774 break; 3775 case OPC1_16_SR_JI: 3776 r1 = MASK_OP_SR_S1D(ctx->opcode); 3777 gen_compute_branch(ctx, op1, r1, 0, 0, 0); 3778 break; 3779 case OPC1_16_SR_NOT: 3780 r1 = MASK_OP_SR_S1D(ctx->opcode); 3781 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3782 break; 3783 default: 3784 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3785 } 3786 } 3787 3788 /* 3789 * 32 bit instructions 3790 */ 3791 3792 /* ABS-format */ 3793 static void decode_abs_ldw(DisasContext *ctx) 3794 { 3795 int32_t op2; 3796 int32_t r1; 3797 uint32_t address; 3798 TCGv temp; 3799 3800 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3801 address = MASK_OP_ABS_OFF18(ctx->opcode); 3802 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3803 3804 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3805 3806 switch (op2) { 3807 case OPC2_32_ABS_LD_A: 3808 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3809 break; 3810 case OPC2_32_ABS_LD_D: 3811 CHECK_REG_PAIR(r1); 3812 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3813 break; 3814 case OPC2_32_ABS_LD_DA: 3815 CHECK_REG_PAIR(r1); 3816 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3817 break; 3818 case OPC2_32_ABS_LD_W: 3819 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3820 break; 3821 default: 3822 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3823 } 3824 } 3825 3826 static void decode_abs_ldb(DisasContext *ctx) 3827 { 3828 int32_t op2; 3829 int32_t r1; 3830 uint32_t address; 3831 TCGv temp; 3832 3833 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3834 address = MASK_OP_ABS_OFF18(ctx->opcode); 3835 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3836 3837 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3838 3839 switch (op2) { 3840 case OPC2_32_ABS_LD_B: 3841 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); 3842 break; 3843 case OPC2_32_ABS_LD_BU: 3844 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3845 break; 3846 case OPC2_32_ABS_LD_H: 3847 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); 3848 break; 3849 case OPC2_32_ABS_LD_HU: 3850 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3851 break; 3852 default: 3853 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3854 } 3855 } 3856 3857 static void decode_abs_ldst_swap(DisasContext *ctx) 3858 { 3859 int32_t op2; 3860 int32_t r1; 3861 uint32_t address; 3862 TCGv temp; 3863 3864 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3865 address = MASK_OP_ABS_OFF18(ctx->opcode); 3866 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3867 3868 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3869 3870 switch (op2) { 3871 case OPC2_32_ABS_LDMST: 3872 gen_ldmst(ctx, r1, temp); 3873 break; 3874 case OPC2_32_ABS_SWAP_W: 3875 gen_swap(ctx, r1, temp); 3876 break; 3877 default: 3878 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3879 } 3880 } 3881 3882 static void decode_abs_ldst_context(DisasContext *ctx) 3883 { 3884 uint32_t op2; 3885 int32_t off18; 3886 3887 off18 = MASK_OP_ABS_OFF18(ctx->opcode); 3888 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3889 3890 switch (op2) { 3891 case OPC2_32_ABS_LDLCX: 3892 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); 3893 break; 3894 case OPC2_32_ABS_LDUCX: 3895 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); 3896 break; 3897 case OPC2_32_ABS_STLCX: 3898 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); 3899 break; 3900 case OPC2_32_ABS_STUCX: 3901 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); 3902 break; 3903 default: 3904 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3905 } 3906 } 3907 3908 static void decode_abs_store(DisasContext *ctx) 3909 { 3910 int32_t op2; 3911 int32_t r1; 3912 uint32_t address; 3913 TCGv temp; 3914 3915 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3916 address = MASK_OP_ABS_OFF18(ctx->opcode); 3917 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3918 3919 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3920 3921 switch (op2) { 3922 case OPC2_32_ABS_ST_A: 3923 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3924 break; 3925 case OPC2_32_ABS_ST_D: 3926 CHECK_REG_PAIR(r1); 3927 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3928 break; 3929 case OPC2_32_ABS_ST_DA: 3930 CHECK_REG_PAIR(r1); 3931 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3932 break; 3933 case OPC2_32_ABS_ST_W: 3934 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3935 break; 3936 default: 3937 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3938 } 3939 } 3940 3941 static void decode_abs_storeb_h(DisasContext *ctx) 3942 { 3943 int32_t op2; 3944 int32_t r1; 3945 uint32_t address; 3946 TCGv temp; 3947 3948 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3949 address = MASK_OP_ABS_OFF18(ctx->opcode); 3950 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3951 3952 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3953 3954 switch (op2) { 3955 case OPC2_32_ABS_ST_B: 3956 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3957 break; 3958 case OPC2_32_ABS_ST_H: 3959 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3960 break; 3961 default: 3962 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3963 } 3964 } 3965 3966 /* Bit-format */ 3967 3968 static void decode_bit_andacc(DisasContext *ctx) 3969 { 3970 uint32_t op2; 3971 int r1, r2, r3; 3972 int pos1, pos2; 3973 3974 r1 = MASK_OP_BIT_S1(ctx->opcode); 3975 r2 = MASK_OP_BIT_S2(ctx->opcode); 3976 r3 = MASK_OP_BIT_D(ctx->opcode); 3977 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 3978 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 3979 op2 = MASK_OP_BIT_OP2(ctx->opcode); 3980 3981 3982 switch (op2) { 3983 case OPC2_32_BIT_AND_AND_T: 3984 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3985 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); 3986 break; 3987 case OPC2_32_BIT_AND_ANDN_T: 3988 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3989 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); 3990 break; 3991 case OPC2_32_BIT_AND_NOR_T: 3992 if (TCG_TARGET_HAS_andc_i32) { 3993 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3994 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); 3995 } else { 3996 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3997 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); 3998 } 3999 break; 4000 case OPC2_32_BIT_AND_OR_T: 4001 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4002 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); 4003 break; 4004 default: 4005 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4006 } 4007 } 4008 4009 static void decode_bit_logical_t(DisasContext *ctx) 4010 { 4011 uint32_t op2; 4012 int r1, r2, r3; 4013 int pos1, pos2; 4014 r1 = MASK_OP_BIT_S1(ctx->opcode); 4015 r2 = MASK_OP_BIT_S2(ctx->opcode); 4016 r3 = MASK_OP_BIT_D(ctx->opcode); 4017 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4018 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4019 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4020 4021 switch (op2) { 4022 case OPC2_32_BIT_AND_T: 4023 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4024 pos1, pos2, &tcg_gen_and_tl); 4025 break; 4026 case OPC2_32_BIT_ANDN_T: 4027 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4028 pos1, pos2, &tcg_gen_andc_tl); 4029 break; 4030 case OPC2_32_BIT_NOR_T: 4031 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4032 pos1, pos2, &tcg_gen_nor_tl); 4033 break; 4034 case OPC2_32_BIT_OR_T: 4035 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4036 pos1, pos2, &tcg_gen_or_tl); 4037 break; 4038 default: 4039 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4040 } 4041 } 4042 4043 static void decode_bit_insert(DisasContext *ctx) 4044 { 4045 uint32_t op2; 4046 int r1, r2, r3; 4047 int pos1, pos2; 4048 TCGv temp; 4049 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4050 r1 = MASK_OP_BIT_S1(ctx->opcode); 4051 r2 = MASK_OP_BIT_S2(ctx->opcode); 4052 r3 = MASK_OP_BIT_D(ctx->opcode); 4053 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4054 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4055 4056 temp = tcg_temp_new(); 4057 4058 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); 4059 if (op2 == OPC2_32_BIT_INSN_T) { 4060 tcg_gen_not_tl(temp, temp); 4061 } 4062 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); 4063 } 4064 4065 static void decode_bit_logical_t2(DisasContext *ctx) 4066 { 4067 uint32_t op2; 4068 4069 int r1, r2, r3; 4070 int pos1, pos2; 4071 4072 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4073 r1 = MASK_OP_BIT_S1(ctx->opcode); 4074 r2 = MASK_OP_BIT_S2(ctx->opcode); 4075 r3 = MASK_OP_BIT_D(ctx->opcode); 4076 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4077 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4078 4079 switch (op2) { 4080 case OPC2_32_BIT_NAND_T: 4081 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4082 pos1, pos2, &tcg_gen_nand_tl); 4083 break; 4084 case OPC2_32_BIT_ORN_T: 4085 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4086 pos1, pos2, &tcg_gen_orc_tl); 4087 break; 4088 case OPC2_32_BIT_XNOR_T: 4089 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4090 pos1, pos2, &tcg_gen_eqv_tl); 4091 break; 4092 case OPC2_32_BIT_XOR_T: 4093 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4094 pos1, pos2, &tcg_gen_xor_tl); 4095 break; 4096 default: 4097 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4098 } 4099 } 4100 4101 static void decode_bit_orand(DisasContext *ctx) 4102 { 4103 uint32_t op2; 4104 4105 int r1, r2, r3; 4106 int pos1, pos2; 4107 4108 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4109 r1 = MASK_OP_BIT_S1(ctx->opcode); 4110 r2 = MASK_OP_BIT_S2(ctx->opcode); 4111 r3 = MASK_OP_BIT_D(ctx->opcode); 4112 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4113 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4114 4115 switch (op2) { 4116 case OPC2_32_BIT_OR_AND_T: 4117 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4118 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); 4119 break; 4120 case OPC2_32_BIT_OR_ANDN_T: 4121 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4122 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); 4123 break; 4124 case OPC2_32_BIT_OR_NOR_T: 4125 if (TCG_TARGET_HAS_orc_i32) { 4126 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4127 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); 4128 } else { 4129 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4130 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); 4131 } 4132 break; 4133 case OPC2_32_BIT_OR_OR_T: 4134 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4135 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); 4136 break; 4137 default: 4138 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4139 } 4140 } 4141 4142 static void decode_bit_sh_logic1(DisasContext *ctx) 4143 { 4144 uint32_t op2; 4145 int r1, r2, r3; 4146 int pos1, pos2; 4147 TCGv temp; 4148 4149 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4150 r1 = MASK_OP_BIT_S1(ctx->opcode); 4151 r2 = MASK_OP_BIT_S2(ctx->opcode); 4152 r3 = MASK_OP_BIT_D(ctx->opcode); 4153 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4154 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4155 4156 temp = tcg_temp_new(); 4157 4158 switch (op2) { 4159 case OPC2_32_BIT_SH_AND_T: 4160 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4161 pos1, pos2, &tcg_gen_and_tl); 4162 break; 4163 case OPC2_32_BIT_SH_ANDN_T: 4164 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4165 pos1, pos2, &tcg_gen_andc_tl); 4166 break; 4167 case OPC2_32_BIT_SH_NOR_T: 4168 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4169 pos1, pos2, &tcg_gen_nor_tl); 4170 break; 4171 case OPC2_32_BIT_SH_OR_T: 4172 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4173 pos1, pos2, &tcg_gen_or_tl); 4174 break; 4175 default: 4176 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4177 } 4178 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4179 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4180 } 4181 4182 static void decode_bit_sh_logic2(DisasContext *ctx) 4183 { 4184 uint32_t op2; 4185 int r1, r2, r3; 4186 int pos1, pos2; 4187 TCGv temp; 4188 4189 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4190 r1 = MASK_OP_BIT_S1(ctx->opcode); 4191 r2 = MASK_OP_BIT_S2(ctx->opcode); 4192 r3 = MASK_OP_BIT_D(ctx->opcode); 4193 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4194 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4195 4196 temp = tcg_temp_new(); 4197 4198 switch (op2) { 4199 case OPC2_32_BIT_SH_NAND_T: 4200 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , 4201 pos1, pos2, &tcg_gen_nand_tl); 4202 break; 4203 case OPC2_32_BIT_SH_ORN_T: 4204 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4205 pos1, pos2, &tcg_gen_orc_tl); 4206 break; 4207 case OPC2_32_BIT_SH_XNOR_T: 4208 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4209 pos1, pos2, &tcg_gen_eqv_tl); 4210 break; 4211 case OPC2_32_BIT_SH_XOR_T: 4212 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4213 pos1, pos2, &tcg_gen_xor_tl); 4214 break; 4215 default: 4216 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4217 } 4218 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4219 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4220 } 4221 4222 /* BO-format */ 4223 4224 4225 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) 4226 { 4227 uint32_t op2; 4228 uint32_t off10; 4229 int32_t r1, r2; 4230 TCGv temp; 4231 4232 r1 = MASK_OP_BO_S1D(ctx->opcode); 4233 r2 = MASK_OP_BO_S2(ctx->opcode); 4234 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4235 op2 = MASK_OP_BO_OP2(ctx->opcode); 4236 4237 switch (op2) { 4238 case OPC2_32_BO_CACHEA_WI_SHORTOFF: 4239 case OPC2_32_BO_CACHEA_W_SHORTOFF: 4240 case OPC2_32_BO_CACHEA_I_SHORTOFF: 4241 /* instruction to access the cache */ 4242 break; 4243 case OPC2_32_BO_CACHEA_WI_POSTINC: 4244 case OPC2_32_BO_CACHEA_W_POSTINC: 4245 case OPC2_32_BO_CACHEA_I_POSTINC: 4246 /* instruction to access the cache, but we still need to handle 4247 the addressing mode */ 4248 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4249 break; 4250 case OPC2_32_BO_CACHEA_WI_PREINC: 4251 case OPC2_32_BO_CACHEA_W_PREINC: 4252 case OPC2_32_BO_CACHEA_I_PREINC: 4253 /* instruction to access the cache, but we still need to handle 4254 the addressing mode */ 4255 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4256 break; 4257 case OPC2_32_BO_CACHEI_WI_SHORTOFF: 4258 case OPC2_32_BO_CACHEI_W_SHORTOFF: 4259 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 4260 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4261 } 4262 break; 4263 case OPC2_32_BO_CACHEI_W_POSTINC: 4264 case OPC2_32_BO_CACHEI_WI_POSTINC: 4265 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4266 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4267 } else { 4268 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4269 } 4270 break; 4271 case OPC2_32_BO_CACHEI_W_PREINC: 4272 case OPC2_32_BO_CACHEI_WI_PREINC: 4273 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4274 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4275 } else { 4276 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4277 } 4278 break; 4279 case OPC2_32_BO_ST_A_SHORTOFF: 4280 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4281 break; 4282 case OPC2_32_BO_ST_A_POSTINC: 4283 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4284 MO_LESL); 4285 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4286 break; 4287 case OPC2_32_BO_ST_A_PREINC: 4288 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4289 break; 4290 case OPC2_32_BO_ST_B_SHORTOFF: 4291 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4292 break; 4293 case OPC2_32_BO_ST_B_POSTINC: 4294 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4295 MO_UB); 4296 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4297 break; 4298 case OPC2_32_BO_ST_B_PREINC: 4299 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4300 break; 4301 case OPC2_32_BO_ST_D_SHORTOFF: 4302 CHECK_REG_PAIR(r1); 4303 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4304 off10, ctx); 4305 break; 4306 case OPC2_32_BO_ST_D_POSTINC: 4307 CHECK_REG_PAIR(r1); 4308 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4309 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4310 break; 4311 case OPC2_32_BO_ST_D_PREINC: 4312 CHECK_REG_PAIR(r1); 4313 temp = tcg_temp_new(); 4314 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4315 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4316 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4317 break; 4318 case OPC2_32_BO_ST_DA_SHORTOFF: 4319 CHECK_REG_PAIR(r1); 4320 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4321 off10, ctx); 4322 break; 4323 case OPC2_32_BO_ST_DA_POSTINC: 4324 CHECK_REG_PAIR(r1); 4325 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4326 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4327 break; 4328 case OPC2_32_BO_ST_DA_PREINC: 4329 CHECK_REG_PAIR(r1); 4330 temp = tcg_temp_new(); 4331 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4332 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4333 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4334 break; 4335 case OPC2_32_BO_ST_H_SHORTOFF: 4336 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4337 break; 4338 case OPC2_32_BO_ST_H_POSTINC: 4339 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4340 MO_LEUW); 4341 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4342 break; 4343 case OPC2_32_BO_ST_H_PREINC: 4344 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4345 break; 4346 case OPC2_32_BO_ST_Q_SHORTOFF: 4347 temp = tcg_temp_new(); 4348 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4349 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4350 break; 4351 case OPC2_32_BO_ST_Q_POSTINC: 4352 temp = tcg_temp_new(); 4353 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4354 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, 4355 MO_LEUW); 4356 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4357 break; 4358 case OPC2_32_BO_ST_Q_PREINC: 4359 temp = tcg_temp_new(); 4360 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4361 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4362 break; 4363 case OPC2_32_BO_ST_W_SHORTOFF: 4364 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4365 break; 4366 case OPC2_32_BO_ST_W_POSTINC: 4367 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4368 MO_LEUL); 4369 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4370 break; 4371 case OPC2_32_BO_ST_W_PREINC: 4372 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4373 break; 4374 default: 4375 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4376 } 4377 } 4378 4379 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) 4380 { 4381 uint32_t op2; 4382 uint32_t off10; 4383 int32_t r1, r2; 4384 TCGv temp, temp2, t_off10; 4385 4386 r1 = MASK_OP_BO_S1D(ctx->opcode); 4387 r2 = MASK_OP_BO_S2(ctx->opcode); 4388 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4389 op2 = MASK_OP_BO_OP2(ctx->opcode); 4390 4391 temp = tcg_temp_new(); 4392 temp2 = tcg_temp_new(); 4393 t_off10 = tcg_constant_i32(off10); 4394 CHECK_REG_PAIR(r2); 4395 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4396 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4397 4398 switch (op2) { 4399 case OPC2_32_BO_CACHEA_WI_BR: 4400 case OPC2_32_BO_CACHEA_W_BR: 4401 case OPC2_32_BO_CACHEA_I_BR: 4402 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4403 break; 4404 case OPC2_32_BO_CACHEA_WI_CIRC: 4405 case OPC2_32_BO_CACHEA_W_CIRC: 4406 case OPC2_32_BO_CACHEA_I_CIRC: 4407 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4408 break; 4409 case OPC2_32_BO_ST_A_BR: 4410 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4411 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4412 break; 4413 case OPC2_32_BO_ST_A_CIRC: 4414 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4415 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4416 break; 4417 case OPC2_32_BO_ST_B_BR: 4418 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4419 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4420 break; 4421 case OPC2_32_BO_ST_B_CIRC: 4422 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4423 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4424 break; 4425 case OPC2_32_BO_ST_D_BR: 4426 CHECK_REG_PAIR(r1); 4427 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4428 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4429 break; 4430 case OPC2_32_BO_ST_D_CIRC: 4431 CHECK_REG_PAIR(r1); 4432 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4433 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4434 tcg_gen_addi_tl(temp, temp, 4); 4435 tcg_gen_rem_tl(temp, temp, temp2); 4436 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4437 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4438 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4439 break; 4440 case OPC2_32_BO_ST_DA_BR: 4441 CHECK_REG_PAIR(r1); 4442 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4443 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4444 break; 4445 case OPC2_32_BO_ST_DA_CIRC: 4446 CHECK_REG_PAIR(r1); 4447 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4448 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4449 tcg_gen_addi_tl(temp, temp, 4); 4450 tcg_gen_rem_tl(temp, temp, temp2); 4451 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4452 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4453 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4454 break; 4455 case OPC2_32_BO_ST_H_BR: 4456 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4457 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4458 break; 4459 case OPC2_32_BO_ST_H_CIRC: 4460 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4461 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4462 break; 4463 case OPC2_32_BO_ST_Q_BR: 4464 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4465 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4466 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4467 break; 4468 case OPC2_32_BO_ST_Q_CIRC: 4469 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4470 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4471 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4472 break; 4473 case OPC2_32_BO_ST_W_BR: 4474 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4475 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4476 break; 4477 case OPC2_32_BO_ST_W_CIRC: 4478 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4479 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4480 break; 4481 default: 4482 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4483 } 4484 } 4485 4486 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) 4487 { 4488 uint32_t op2; 4489 uint32_t off10; 4490 int32_t r1, r2; 4491 TCGv temp; 4492 4493 r1 = MASK_OP_BO_S1D(ctx->opcode); 4494 r2 = MASK_OP_BO_S2(ctx->opcode); 4495 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4496 op2 = MASK_OP_BO_OP2(ctx->opcode); 4497 4498 switch (op2) { 4499 case OPC2_32_BO_LD_A_SHORTOFF: 4500 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4501 break; 4502 case OPC2_32_BO_LD_A_POSTINC: 4503 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4504 MO_LEUL); 4505 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4506 break; 4507 case OPC2_32_BO_LD_A_PREINC: 4508 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4509 break; 4510 case OPC2_32_BO_LD_B_SHORTOFF: 4511 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4512 break; 4513 case OPC2_32_BO_LD_B_POSTINC: 4514 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4515 MO_SB); 4516 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4517 break; 4518 case OPC2_32_BO_LD_B_PREINC: 4519 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4520 break; 4521 case OPC2_32_BO_LD_BU_SHORTOFF: 4522 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4523 break; 4524 case OPC2_32_BO_LD_BU_POSTINC: 4525 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4526 MO_UB); 4527 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4528 break; 4529 case OPC2_32_BO_LD_BU_PREINC: 4530 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4531 break; 4532 case OPC2_32_BO_LD_D_SHORTOFF: 4533 CHECK_REG_PAIR(r1); 4534 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4535 off10, ctx); 4536 break; 4537 case OPC2_32_BO_LD_D_POSTINC: 4538 CHECK_REG_PAIR(r1); 4539 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4540 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4541 break; 4542 case OPC2_32_BO_LD_D_PREINC: 4543 CHECK_REG_PAIR(r1); 4544 temp = tcg_temp_new(); 4545 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4546 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4547 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4548 break; 4549 case OPC2_32_BO_LD_DA_SHORTOFF: 4550 CHECK_REG_PAIR(r1); 4551 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4552 off10, ctx); 4553 break; 4554 case OPC2_32_BO_LD_DA_POSTINC: 4555 CHECK_REG_PAIR(r1); 4556 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4557 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4558 break; 4559 case OPC2_32_BO_LD_DA_PREINC: 4560 CHECK_REG_PAIR(r1); 4561 temp = tcg_temp_new(); 4562 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4563 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4564 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4565 break; 4566 case OPC2_32_BO_LD_H_SHORTOFF: 4567 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4568 break; 4569 case OPC2_32_BO_LD_H_POSTINC: 4570 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4571 MO_LESW); 4572 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4573 break; 4574 case OPC2_32_BO_LD_H_PREINC: 4575 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4576 break; 4577 case OPC2_32_BO_LD_HU_SHORTOFF: 4578 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4579 break; 4580 case OPC2_32_BO_LD_HU_POSTINC: 4581 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4582 MO_LEUW); 4583 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4584 break; 4585 case OPC2_32_BO_LD_HU_PREINC: 4586 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4587 break; 4588 case OPC2_32_BO_LD_Q_SHORTOFF: 4589 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4590 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4591 break; 4592 case OPC2_32_BO_LD_Q_POSTINC: 4593 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4594 MO_LEUW); 4595 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4596 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4597 break; 4598 case OPC2_32_BO_LD_Q_PREINC: 4599 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4600 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4601 break; 4602 case OPC2_32_BO_LD_W_SHORTOFF: 4603 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4604 break; 4605 case OPC2_32_BO_LD_W_POSTINC: 4606 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4607 MO_LEUL); 4608 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4609 break; 4610 case OPC2_32_BO_LD_W_PREINC: 4611 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4612 break; 4613 default: 4614 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4615 } 4616 } 4617 4618 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) 4619 { 4620 uint32_t op2; 4621 uint32_t off10; 4622 int r1, r2; 4623 TCGv temp, temp2, t_off10; 4624 4625 r1 = MASK_OP_BO_S1D(ctx->opcode); 4626 r2 = MASK_OP_BO_S2(ctx->opcode); 4627 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4628 op2 = MASK_OP_BO_OP2(ctx->opcode); 4629 4630 temp = tcg_temp_new(); 4631 temp2 = tcg_temp_new(); 4632 t_off10 = tcg_constant_i32(off10); 4633 CHECK_REG_PAIR(r2); 4634 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4635 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4636 4637 4638 switch (op2) { 4639 case OPC2_32_BO_LD_A_BR: 4640 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4641 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4642 break; 4643 case OPC2_32_BO_LD_A_CIRC: 4644 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4645 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4646 break; 4647 case OPC2_32_BO_LD_B_BR: 4648 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4649 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4650 break; 4651 case OPC2_32_BO_LD_B_CIRC: 4652 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4653 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4654 break; 4655 case OPC2_32_BO_LD_BU_BR: 4656 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4657 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4658 break; 4659 case OPC2_32_BO_LD_BU_CIRC: 4660 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4661 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4662 break; 4663 case OPC2_32_BO_LD_D_BR: 4664 CHECK_REG_PAIR(r1); 4665 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4666 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4667 break; 4668 case OPC2_32_BO_LD_D_CIRC: 4669 CHECK_REG_PAIR(r1); 4670 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4671 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4672 tcg_gen_addi_tl(temp, temp, 4); 4673 tcg_gen_rem_tl(temp, temp, temp2); 4674 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4675 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4676 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4677 break; 4678 case OPC2_32_BO_LD_DA_BR: 4679 CHECK_REG_PAIR(r1); 4680 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4681 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4682 break; 4683 case OPC2_32_BO_LD_DA_CIRC: 4684 CHECK_REG_PAIR(r1); 4685 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4686 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4687 tcg_gen_addi_tl(temp, temp, 4); 4688 tcg_gen_rem_tl(temp, temp, temp2); 4689 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4690 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4691 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4692 break; 4693 case OPC2_32_BO_LD_H_BR: 4694 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4695 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4696 break; 4697 case OPC2_32_BO_LD_H_CIRC: 4698 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4699 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4700 break; 4701 case OPC2_32_BO_LD_HU_BR: 4702 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4703 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4704 break; 4705 case OPC2_32_BO_LD_HU_CIRC: 4706 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4707 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4708 break; 4709 case OPC2_32_BO_LD_Q_BR: 4710 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4711 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4712 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4713 break; 4714 case OPC2_32_BO_LD_Q_CIRC: 4715 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4716 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4717 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4718 break; 4719 case OPC2_32_BO_LD_W_BR: 4720 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4721 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4722 break; 4723 case OPC2_32_BO_LD_W_CIRC: 4724 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4725 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4726 break; 4727 default: 4728 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4729 } 4730 } 4731 4732 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) 4733 { 4734 uint32_t op2; 4735 uint32_t off10; 4736 int r1, r2; 4737 4738 TCGv temp; 4739 4740 r1 = MASK_OP_BO_S1D(ctx->opcode); 4741 r2 = MASK_OP_BO_S2(ctx->opcode); 4742 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4743 op2 = MASK_OP_BO_OP2(ctx->opcode); 4744 4745 4746 temp = tcg_temp_new(); 4747 4748 switch (op2) { 4749 case OPC2_32_BO_LDLCX_SHORTOFF: 4750 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4751 gen_helper_ldlcx(cpu_env, temp); 4752 break; 4753 case OPC2_32_BO_LDMST_SHORTOFF: 4754 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4755 gen_ldmst(ctx, r1, temp); 4756 break; 4757 case OPC2_32_BO_LDMST_POSTINC: 4758 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4759 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4760 break; 4761 case OPC2_32_BO_LDMST_PREINC: 4762 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4763 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4764 break; 4765 case OPC2_32_BO_LDUCX_SHORTOFF: 4766 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4767 gen_helper_lducx(cpu_env, temp); 4768 break; 4769 case OPC2_32_BO_LEA_SHORTOFF: 4770 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); 4771 break; 4772 case OPC2_32_BO_STLCX_SHORTOFF: 4773 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4774 gen_helper_stlcx(cpu_env, temp); 4775 break; 4776 case OPC2_32_BO_STUCX_SHORTOFF: 4777 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4778 gen_helper_stucx(cpu_env, temp); 4779 break; 4780 case OPC2_32_BO_SWAP_W_SHORTOFF: 4781 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4782 gen_swap(ctx, r1, temp); 4783 break; 4784 case OPC2_32_BO_SWAP_W_POSTINC: 4785 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4786 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4787 break; 4788 case OPC2_32_BO_SWAP_W_PREINC: 4789 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4790 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4791 break; 4792 case OPC2_32_BO_CMPSWAP_W_SHORTOFF: 4793 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4794 gen_cmpswap(ctx, r1, temp); 4795 break; 4796 case OPC2_32_BO_CMPSWAP_W_POSTINC: 4797 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4798 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4799 break; 4800 case OPC2_32_BO_CMPSWAP_W_PREINC: 4801 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4802 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4803 break; 4804 case OPC2_32_BO_SWAPMSK_W_SHORTOFF: 4805 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4806 gen_swapmsk(ctx, r1, temp); 4807 break; 4808 case OPC2_32_BO_SWAPMSK_W_POSTINC: 4809 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4810 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4811 break; 4812 case OPC2_32_BO_SWAPMSK_W_PREINC: 4813 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4814 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4815 break; 4816 default: 4817 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4818 } 4819 } 4820 4821 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) 4822 { 4823 uint32_t op2; 4824 uint32_t off10; 4825 int r1, r2; 4826 TCGv temp, temp2, t_off10; 4827 4828 r1 = MASK_OP_BO_S1D(ctx->opcode); 4829 r2 = MASK_OP_BO_S2(ctx->opcode); 4830 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4831 op2 = MASK_OP_BO_OP2(ctx->opcode); 4832 4833 temp = tcg_temp_new(); 4834 temp2 = tcg_temp_new(); 4835 t_off10 = tcg_constant_i32(off10); 4836 CHECK_REG_PAIR(r2); 4837 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4838 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4839 4840 switch (op2) { 4841 case OPC2_32_BO_LDMST_BR: 4842 gen_ldmst(ctx, r1, temp2); 4843 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4844 break; 4845 case OPC2_32_BO_LDMST_CIRC: 4846 gen_ldmst(ctx, r1, temp2); 4847 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4848 break; 4849 case OPC2_32_BO_SWAP_W_BR: 4850 gen_swap(ctx, r1, temp2); 4851 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4852 break; 4853 case OPC2_32_BO_SWAP_W_CIRC: 4854 gen_swap(ctx, r1, temp2); 4855 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4856 break; 4857 case OPC2_32_BO_CMPSWAP_W_BR: 4858 gen_cmpswap(ctx, r1, temp2); 4859 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4860 break; 4861 case OPC2_32_BO_CMPSWAP_W_CIRC: 4862 gen_cmpswap(ctx, r1, temp2); 4863 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4864 break; 4865 case OPC2_32_BO_SWAPMSK_W_BR: 4866 gen_swapmsk(ctx, r1, temp2); 4867 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4868 break; 4869 case OPC2_32_BO_SWAPMSK_W_CIRC: 4870 gen_swapmsk(ctx, r1, temp2); 4871 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4872 break; 4873 default: 4874 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4875 } 4876 } 4877 4878 static void decode_bol_opc(DisasContext *ctx, int32_t op1) 4879 { 4880 int r1, r2; 4881 int32_t address; 4882 TCGv temp; 4883 4884 r1 = MASK_OP_BOL_S1D(ctx->opcode); 4885 r2 = MASK_OP_BOL_S2(ctx->opcode); 4886 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); 4887 4888 switch (op1) { 4889 case OPC1_32_BOL_LD_A_LONGOFF: 4890 temp = tcg_temp_new(); 4891 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4892 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); 4893 break; 4894 case OPC1_32_BOL_LD_W_LONGOFF: 4895 temp = tcg_temp_new(); 4896 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4897 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); 4898 break; 4899 case OPC1_32_BOL_LEA_LONGOFF: 4900 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); 4901 break; 4902 case OPC1_32_BOL_ST_A_LONGOFF: 4903 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4904 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); 4905 } else { 4906 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4907 } 4908 break; 4909 case OPC1_32_BOL_ST_W_LONGOFF: 4910 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); 4911 break; 4912 case OPC1_32_BOL_LD_B_LONGOFF: 4913 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4914 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4915 } else { 4916 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4917 } 4918 break; 4919 case OPC1_32_BOL_LD_BU_LONGOFF: 4920 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4921 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); 4922 } else { 4923 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4924 } 4925 break; 4926 case OPC1_32_BOL_LD_H_LONGOFF: 4927 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4928 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4929 } else { 4930 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4931 } 4932 break; 4933 case OPC1_32_BOL_LD_HU_LONGOFF: 4934 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4935 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); 4936 } else { 4937 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4938 } 4939 break; 4940 case OPC1_32_BOL_ST_B_LONGOFF: 4941 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4942 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4943 } else { 4944 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4945 } 4946 break; 4947 case OPC1_32_BOL_ST_H_LONGOFF: 4948 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4949 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4950 } else { 4951 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4952 } 4953 break; 4954 default: 4955 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4956 } 4957 } 4958 4959 /* RC format */ 4960 static void decode_rc_logical_shift(DisasContext *ctx) 4961 { 4962 uint32_t op2; 4963 int r1, r2; 4964 int32_t const9; 4965 TCGv temp; 4966 4967 r2 = MASK_OP_RC_D(ctx->opcode); 4968 r1 = MASK_OP_RC_S1(ctx->opcode); 4969 const9 = MASK_OP_RC_CONST9(ctx->opcode); 4970 op2 = MASK_OP_RC_OP2(ctx->opcode); 4971 4972 temp = tcg_temp_new(); 4973 4974 switch (op2) { 4975 case OPC2_32_RC_AND: 4976 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4977 break; 4978 case OPC2_32_RC_ANDN: 4979 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4980 break; 4981 case OPC2_32_RC_NAND: 4982 tcg_gen_movi_tl(temp, const9); 4983 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4984 break; 4985 case OPC2_32_RC_NOR: 4986 tcg_gen_movi_tl(temp, const9); 4987 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4988 break; 4989 case OPC2_32_RC_OR: 4990 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4991 break; 4992 case OPC2_32_RC_ORN: 4993 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4994 break; 4995 case OPC2_32_RC_SH: 4996 const9 = sextract32(const9, 0, 6); 4997 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4998 break; 4999 case OPC2_32_RC_SH_H: 5000 const9 = sextract32(const9, 0, 5); 5001 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5002 break; 5003 case OPC2_32_RC_SHA: 5004 const9 = sextract32(const9, 0, 6); 5005 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5006 break; 5007 case OPC2_32_RC_SHA_H: 5008 const9 = sextract32(const9, 0, 5); 5009 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5010 break; 5011 case OPC2_32_RC_SHAS: 5012 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5013 break; 5014 case OPC2_32_RC_XNOR: 5015 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5016 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); 5017 break; 5018 case OPC2_32_RC_XOR: 5019 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5020 break; 5021 case OPC2_32_RC_SHUFFLE: 5022 if (has_feature(ctx, TRICORE_FEATURE_162)) { 5023 TCGv temp = tcg_constant_i32(const9); 5024 gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5025 } else { 5026 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5027 } 5028 break; 5029 default: 5030 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5031 } 5032 } 5033 5034 static void decode_rc_accumulator(DisasContext *ctx) 5035 { 5036 uint32_t op2; 5037 int r1, r2; 5038 int16_t const9; 5039 5040 TCGv temp; 5041 5042 r2 = MASK_OP_RC_D(ctx->opcode); 5043 r1 = MASK_OP_RC_S1(ctx->opcode); 5044 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5045 5046 op2 = MASK_OP_RC_OP2(ctx->opcode); 5047 5048 temp = tcg_temp_new(); 5049 5050 switch (op2) { 5051 case OPC2_32_RC_ABSDIF: 5052 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5053 break; 5054 case OPC2_32_RC_ABSDIFS: 5055 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5056 break; 5057 case OPC2_32_RC_ADD: 5058 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5059 break; 5060 case OPC2_32_RC_ADDC: 5061 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5062 break; 5063 case OPC2_32_RC_ADDS: 5064 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5065 break; 5066 case OPC2_32_RC_ADDS_U: 5067 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5068 break; 5069 case OPC2_32_RC_ADDX: 5070 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5071 break; 5072 case OPC2_32_RC_AND_EQ: 5073 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5074 const9, &tcg_gen_and_tl); 5075 break; 5076 case OPC2_32_RC_AND_GE: 5077 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5078 const9, &tcg_gen_and_tl); 5079 break; 5080 case OPC2_32_RC_AND_GE_U: 5081 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5082 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5083 const9, &tcg_gen_and_tl); 5084 break; 5085 case OPC2_32_RC_AND_LT: 5086 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5087 const9, &tcg_gen_and_tl); 5088 break; 5089 case OPC2_32_RC_AND_LT_U: 5090 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5091 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5092 const9, &tcg_gen_and_tl); 5093 break; 5094 case OPC2_32_RC_AND_NE: 5095 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5096 const9, &tcg_gen_and_tl); 5097 break; 5098 case OPC2_32_RC_EQ: 5099 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5100 break; 5101 case OPC2_32_RC_EQANY_B: 5102 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5103 break; 5104 case OPC2_32_RC_EQANY_H: 5105 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5106 break; 5107 case OPC2_32_RC_GE: 5108 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5109 break; 5110 case OPC2_32_RC_GE_U: 5111 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5112 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5113 break; 5114 case OPC2_32_RC_LT: 5115 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5116 break; 5117 case OPC2_32_RC_LT_U: 5118 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5119 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5120 break; 5121 case OPC2_32_RC_MAX: 5122 tcg_gen_movi_tl(temp, const9); 5123 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5124 cpu_gpr_d[r1], temp); 5125 break; 5126 case OPC2_32_RC_MAX_U: 5127 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5128 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5129 cpu_gpr_d[r1], temp); 5130 break; 5131 case OPC2_32_RC_MIN: 5132 tcg_gen_movi_tl(temp, const9); 5133 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5134 cpu_gpr_d[r1], temp); 5135 break; 5136 case OPC2_32_RC_MIN_U: 5137 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5138 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5139 cpu_gpr_d[r1], temp); 5140 break; 5141 case OPC2_32_RC_NE: 5142 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5143 break; 5144 case OPC2_32_RC_OR_EQ: 5145 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5146 const9, &tcg_gen_or_tl); 5147 break; 5148 case OPC2_32_RC_OR_GE: 5149 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5150 const9, &tcg_gen_or_tl); 5151 break; 5152 case OPC2_32_RC_OR_GE_U: 5153 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5154 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5155 const9, &tcg_gen_or_tl); 5156 break; 5157 case OPC2_32_RC_OR_LT: 5158 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5159 const9, &tcg_gen_or_tl); 5160 break; 5161 case OPC2_32_RC_OR_LT_U: 5162 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5163 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5164 const9, &tcg_gen_or_tl); 5165 break; 5166 case OPC2_32_RC_OR_NE: 5167 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5168 const9, &tcg_gen_or_tl); 5169 break; 5170 case OPC2_32_RC_RSUB: 5171 tcg_gen_movi_tl(temp, const9); 5172 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5173 break; 5174 case OPC2_32_RC_RSUBS: 5175 tcg_gen_movi_tl(temp, const9); 5176 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5177 break; 5178 case OPC2_32_RC_RSUBS_U: 5179 tcg_gen_movi_tl(temp, const9); 5180 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5181 break; 5182 case OPC2_32_RC_SH_EQ: 5183 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5184 break; 5185 case OPC2_32_RC_SH_GE: 5186 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5187 break; 5188 case OPC2_32_RC_SH_GE_U: 5189 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5190 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5191 break; 5192 case OPC2_32_RC_SH_LT: 5193 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5194 break; 5195 case OPC2_32_RC_SH_LT_U: 5196 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5197 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5198 break; 5199 case OPC2_32_RC_SH_NE: 5200 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5201 break; 5202 case OPC2_32_RC_XOR_EQ: 5203 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5204 const9, &tcg_gen_xor_tl); 5205 break; 5206 case OPC2_32_RC_XOR_GE: 5207 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5208 const9, &tcg_gen_xor_tl); 5209 break; 5210 case OPC2_32_RC_XOR_GE_U: 5211 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5212 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5213 const9, &tcg_gen_xor_tl); 5214 break; 5215 case OPC2_32_RC_XOR_LT: 5216 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5217 const9, &tcg_gen_xor_tl); 5218 break; 5219 case OPC2_32_RC_XOR_LT_U: 5220 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5221 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5222 const9, &tcg_gen_xor_tl); 5223 break; 5224 case OPC2_32_RC_XOR_NE: 5225 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5226 const9, &tcg_gen_xor_tl); 5227 break; 5228 default: 5229 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5230 } 5231 } 5232 5233 static void decode_rc_serviceroutine(DisasContext *ctx) 5234 { 5235 uint32_t op2; 5236 uint32_t const9; 5237 5238 op2 = MASK_OP_RC_OP2(ctx->opcode); 5239 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5240 5241 switch (op2) { 5242 case OPC2_32_RC_BISR: 5243 if (ctx->priv == TRICORE_PRIV_SM) { 5244 gen_helper_1arg(bisr, const9); 5245 } else { 5246 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 5247 } 5248 break; 5249 case OPC2_32_RC_SYSCALL: 5250 generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff); 5251 break; 5252 default: 5253 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5254 } 5255 } 5256 5257 static void decode_rc_mul(DisasContext *ctx) 5258 { 5259 uint32_t op2; 5260 int r1, r2; 5261 int16_t const9; 5262 5263 r2 = MASK_OP_RC_D(ctx->opcode); 5264 r1 = MASK_OP_RC_S1(ctx->opcode); 5265 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5266 5267 op2 = MASK_OP_RC_OP2(ctx->opcode); 5268 5269 switch (op2) { 5270 case OPC2_32_RC_MUL_32: 5271 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5272 break; 5273 case OPC2_32_RC_MUL_64: 5274 CHECK_REG_PAIR(r2); 5275 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5276 break; 5277 case OPC2_32_RC_MULS_32: 5278 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5279 break; 5280 case OPC2_32_RC_MUL_U_64: 5281 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5282 CHECK_REG_PAIR(r2); 5283 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5284 break; 5285 case OPC2_32_RC_MULS_U_32: 5286 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5287 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5288 break; 5289 default: 5290 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5291 } 5292 } 5293 5294 /* RCPW format */ 5295 static void decode_rcpw_insert(DisasContext *ctx) 5296 { 5297 uint32_t op2; 5298 int r1, r2; 5299 int32_t pos, width, const4; 5300 5301 TCGv temp; 5302 5303 op2 = MASK_OP_RCPW_OP2(ctx->opcode); 5304 r1 = MASK_OP_RCPW_S1(ctx->opcode); 5305 r2 = MASK_OP_RCPW_D(ctx->opcode); 5306 const4 = MASK_OP_RCPW_CONST4(ctx->opcode); 5307 width = MASK_OP_RCPW_WIDTH(ctx->opcode); 5308 pos = MASK_OP_RCPW_POS(ctx->opcode); 5309 5310 switch (op2) { 5311 case OPC2_32_RCPW_IMASK: 5312 CHECK_REG_PAIR(r2); 5313 /* if pos + width > 32 undefined result */ 5314 if (pos + width <= 32) { 5315 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); 5316 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); 5317 } 5318 break; 5319 case OPC2_32_RCPW_INSERT: 5320 /* if pos + width > 32 undefined result */ 5321 if (pos + width <= 32) { 5322 temp = tcg_constant_i32(const4); 5323 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); 5324 } 5325 break; 5326 default: 5327 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5328 } 5329 } 5330 5331 /* RCRW format */ 5332 5333 static void decode_rcrw_insert(DisasContext *ctx) 5334 { 5335 uint32_t op2; 5336 int r1, r3, r4; 5337 int32_t width, const4; 5338 5339 TCGv temp, temp2, temp3; 5340 5341 op2 = MASK_OP_RCRW_OP2(ctx->opcode); 5342 r1 = MASK_OP_RCRW_S1(ctx->opcode); 5343 r3 = MASK_OP_RCRW_S3(ctx->opcode); 5344 r4 = MASK_OP_RCRW_D(ctx->opcode); 5345 width = MASK_OP_RCRW_WIDTH(ctx->opcode); 5346 const4 = MASK_OP_RCRW_CONST4(ctx->opcode); 5347 5348 temp = tcg_temp_new(); 5349 temp2 = tcg_temp_new(); 5350 5351 switch (op2) { 5352 case OPC2_32_RCRW_IMASK: 5353 CHECK_REG_PAIR(r4); 5354 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 5355 tcg_gen_movi_tl(temp2, (1 << width) - 1); 5356 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); 5357 tcg_gen_movi_tl(temp2, const4); 5358 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); 5359 break; 5360 case OPC2_32_RCRW_INSERT: 5361 temp3 = tcg_temp_new(); 5362 5363 tcg_gen_movi_tl(temp, width); 5364 tcg_gen_movi_tl(temp2, const4); 5365 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 5366 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); 5367 break; 5368 default: 5369 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5370 } 5371 } 5372 5373 /* RCR format */ 5374 5375 static void decode_rcr_cond_select(DisasContext *ctx) 5376 { 5377 uint32_t op2; 5378 int r1, r3, r4; 5379 int32_t const9; 5380 5381 TCGv temp, temp2; 5382 5383 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5384 r1 = MASK_OP_RCR_S1(ctx->opcode); 5385 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5386 r3 = MASK_OP_RCR_S3(ctx->opcode); 5387 r4 = MASK_OP_RCR_D(ctx->opcode); 5388 5389 switch (op2) { 5390 case OPC2_32_RCR_CADD: 5391 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5392 cpu_gpr_d[r3]); 5393 break; 5394 case OPC2_32_RCR_CADDN: 5395 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5396 cpu_gpr_d[r3]); 5397 break; 5398 case OPC2_32_RCR_SEL: 5399 temp = tcg_constant_i32(0); 5400 temp2 = tcg_constant_i32(const9); 5401 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5402 cpu_gpr_d[r1], temp2); 5403 break; 5404 case OPC2_32_RCR_SELN: 5405 temp = tcg_constant_i32(0); 5406 temp2 = tcg_constant_i32(const9); 5407 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5408 cpu_gpr_d[r1], temp2); 5409 break; 5410 default: 5411 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5412 } 5413 } 5414 5415 static void decode_rcr_madd(DisasContext *ctx) 5416 { 5417 uint32_t op2; 5418 int r1, r3, r4; 5419 int32_t const9; 5420 5421 5422 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5423 r1 = MASK_OP_RCR_S1(ctx->opcode); 5424 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5425 r3 = MASK_OP_RCR_S3(ctx->opcode); 5426 r4 = MASK_OP_RCR_D(ctx->opcode); 5427 5428 switch (op2) { 5429 case OPC2_32_RCR_MADD_32: 5430 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5431 break; 5432 case OPC2_32_RCR_MADD_64: 5433 CHECK_REG_PAIR(r4); 5434 CHECK_REG_PAIR(r3); 5435 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5436 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5437 break; 5438 case OPC2_32_RCR_MADDS_32: 5439 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5440 break; 5441 case OPC2_32_RCR_MADDS_64: 5442 CHECK_REG_PAIR(r4); 5443 CHECK_REG_PAIR(r3); 5444 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5445 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5446 break; 5447 case OPC2_32_RCR_MADD_U_64: 5448 CHECK_REG_PAIR(r4); 5449 CHECK_REG_PAIR(r3); 5450 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5451 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5452 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5453 break; 5454 case OPC2_32_RCR_MADDS_U_32: 5455 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5456 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5457 break; 5458 case OPC2_32_RCR_MADDS_U_64: 5459 CHECK_REG_PAIR(r4); 5460 CHECK_REG_PAIR(r3); 5461 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5462 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5463 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5464 break; 5465 default: 5466 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5467 } 5468 } 5469 5470 static void decode_rcr_msub(DisasContext *ctx) 5471 { 5472 uint32_t op2; 5473 int r1, r3, r4; 5474 int32_t const9; 5475 5476 5477 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5478 r1 = MASK_OP_RCR_S1(ctx->opcode); 5479 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5480 r3 = MASK_OP_RCR_S3(ctx->opcode); 5481 r4 = MASK_OP_RCR_D(ctx->opcode); 5482 5483 switch (op2) { 5484 case OPC2_32_RCR_MSUB_32: 5485 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5486 break; 5487 case OPC2_32_RCR_MSUB_64: 5488 CHECK_REG_PAIR(r4); 5489 CHECK_REG_PAIR(r3); 5490 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5491 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5492 break; 5493 case OPC2_32_RCR_MSUBS_32: 5494 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5495 break; 5496 case OPC2_32_RCR_MSUBS_64: 5497 CHECK_REG_PAIR(r4); 5498 CHECK_REG_PAIR(r3); 5499 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5500 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5501 break; 5502 case OPC2_32_RCR_MSUB_U_64: 5503 CHECK_REG_PAIR(r4); 5504 CHECK_REG_PAIR(r3); 5505 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5506 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5507 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5508 break; 5509 case OPC2_32_RCR_MSUBS_U_32: 5510 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5511 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5512 break; 5513 case OPC2_32_RCR_MSUBS_U_64: 5514 CHECK_REG_PAIR(r4); 5515 CHECK_REG_PAIR(r3); 5516 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5517 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5518 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5519 break; 5520 default: 5521 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5522 } 5523 } 5524 5525 /* RLC format */ 5526 5527 static void decode_rlc_opc(DisasContext *ctx, 5528 uint32_t op1) 5529 { 5530 int32_t const16; 5531 int r1, r2; 5532 5533 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); 5534 r1 = MASK_OP_RLC_S1(ctx->opcode); 5535 r2 = MASK_OP_RLC_D(ctx->opcode); 5536 5537 switch (op1) { 5538 case OPC1_32_RLC_ADDI: 5539 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); 5540 break; 5541 case OPC1_32_RLC_ADDIH: 5542 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); 5543 break; 5544 case OPC1_32_RLC_ADDIH_A: 5545 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); 5546 break; 5547 case OPC1_32_RLC_MFCR: 5548 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5549 gen_mfcr(ctx, cpu_gpr_d[r2], const16); 5550 break; 5551 case OPC1_32_RLC_MOV: 5552 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5553 break; 5554 case OPC1_32_RLC_MOV_64: 5555 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5556 CHECK_REG_PAIR(r2); 5557 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5558 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); 5559 } else { 5560 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5561 } 5562 break; 5563 case OPC1_32_RLC_MOV_U: 5564 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5565 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5566 break; 5567 case OPC1_32_RLC_MOV_H: 5568 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); 5569 break; 5570 case OPC1_32_RLC_MOVH_A: 5571 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); 5572 break; 5573 case OPC1_32_RLC_MTCR: 5574 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5575 gen_mtcr(ctx, cpu_gpr_d[r1], const16); 5576 break; 5577 default: 5578 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5579 } 5580 } 5581 5582 /* RR format */ 5583 static void decode_rr_accumulator(DisasContext *ctx) 5584 { 5585 uint32_t op2; 5586 int r3, r2, r1; 5587 5588 TCGv temp; 5589 5590 r3 = MASK_OP_RR_D(ctx->opcode); 5591 r2 = MASK_OP_RR_S2(ctx->opcode); 5592 r1 = MASK_OP_RR_S1(ctx->opcode); 5593 op2 = MASK_OP_RR_OP2(ctx->opcode); 5594 5595 switch (op2) { 5596 case OPC2_32_RR_ABS: 5597 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5598 break; 5599 case OPC2_32_RR_ABS_B: 5600 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5601 break; 5602 case OPC2_32_RR_ABS_H: 5603 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5604 break; 5605 case OPC2_32_RR_ABSDIF: 5606 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5607 break; 5608 case OPC2_32_RR_ABSDIF_B: 5609 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5610 cpu_gpr_d[r2]); 5611 break; 5612 case OPC2_32_RR_ABSDIF_H: 5613 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5614 cpu_gpr_d[r2]); 5615 break; 5616 case OPC2_32_RR_ABSDIFS: 5617 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5618 cpu_gpr_d[r2]); 5619 break; 5620 case OPC2_32_RR_ABSDIFS_H: 5621 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5622 cpu_gpr_d[r2]); 5623 break; 5624 case OPC2_32_RR_ABSS: 5625 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5626 break; 5627 case OPC2_32_RR_ABSS_H: 5628 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5629 break; 5630 case OPC2_32_RR_ADD: 5631 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5632 break; 5633 case OPC2_32_RR_ADD_B: 5634 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5635 break; 5636 case OPC2_32_RR_ADD_H: 5637 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5638 break; 5639 case OPC2_32_RR_ADDC: 5640 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5641 break; 5642 case OPC2_32_RR_ADDS: 5643 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5644 break; 5645 case OPC2_32_RR_ADDS_H: 5646 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5647 cpu_gpr_d[r2]); 5648 break; 5649 case OPC2_32_RR_ADDS_HU: 5650 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5651 cpu_gpr_d[r2]); 5652 break; 5653 case OPC2_32_RR_ADDS_U: 5654 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5655 cpu_gpr_d[r2]); 5656 break; 5657 case OPC2_32_RR_ADDX: 5658 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5659 break; 5660 case OPC2_32_RR_AND_EQ: 5661 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5662 cpu_gpr_d[r2], &tcg_gen_and_tl); 5663 break; 5664 case OPC2_32_RR_AND_GE: 5665 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5666 cpu_gpr_d[r2], &tcg_gen_and_tl); 5667 break; 5668 case OPC2_32_RR_AND_GE_U: 5669 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5670 cpu_gpr_d[r2], &tcg_gen_and_tl); 5671 break; 5672 case OPC2_32_RR_AND_LT: 5673 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5674 cpu_gpr_d[r2], &tcg_gen_and_tl); 5675 break; 5676 case OPC2_32_RR_AND_LT_U: 5677 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5678 cpu_gpr_d[r2], &tcg_gen_and_tl); 5679 break; 5680 case OPC2_32_RR_AND_NE: 5681 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5682 cpu_gpr_d[r2], &tcg_gen_and_tl); 5683 break; 5684 case OPC2_32_RR_EQ: 5685 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5686 cpu_gpr_d[r2]); 5687 break; 5688 case OPC2_32_RR_EQ_B: 5689 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5690 break; 5691 case OPC2_32_RR_EQ_H: 5692 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5693 break; 5694 case OPC2_32_RR_EQ_W: 5695 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5696 break; 5697 case OPC2_32_RR_EQANY_B: 5698 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5699 break; 5700 case OPC2_32_RR_EQANY_H: 5701 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5702 break; 5703 case OPC2_32_RR_GE: 5704 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5705 cpu_gpr_d[r2]); 5706 break; 5707 case OPC2_32_RR_GE_U: 5708 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5709 cpu_gpr_d[r2]); 5710 break; 5711 case OPC2_32_RR_LT: 5712 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5713 cpu_gpr_d[r2]); 5714 break; 5715 case OPC2_32_RR_LT_U: 5716 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5717 cpu_gpr_d[r2]); 5718 break; 5719 case OPC2_32_RR_LT_B: 5720 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5721 break; 5722 case OPC2_32_RR_LT_BU: 5723 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5724 break; 5725 case OPC2_32_RR_LT_H: 5726 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5727 break; 5728 case OPC2_32_RR_LT_HU: 5729 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5730 break; 5731 case OPC2_32_RR_LT_W: 5732 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5733 break; 5734 case OPC2_32_RR_LT_WU: 5735 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5736 break; 5737 case OPC2_32_RR_MAX: 5738 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5739 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5740 break; 5741 case OPC2_32_RR_MAX_U: 5742 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5743 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5744 break; 5745 case OPC2_32_RR_MAX_B: 5746 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5747 break; 5748 case OPC2_32_RR_MAX_BU: 5749 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5750 break; 5751 case OPC2_32_RR_MAX_H: 5752 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5753 break; 5754 case OPC2_32_RR_MAX_HU: 5755 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5756 break; 5757 case OPC2_32_RR_MIN: 5758 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5759 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5760 break; 5761 case OPC2_32_RR_MIN_U: 5762 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5763 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5764 break; 5765 case OPC2_32_RR_MIN_B: 5766 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5767 break; 5768 case OPC2_32_RR_MIN_BU: 5769 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5770 break; 5771 case OPC2_32_RR_MIN_H: 5772 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5773 break; 5774 case OPC2_32_RR_MIN_HU: 5775 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5776 break; 5777 case OPC2_32_RR_MOV: 5778 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5779 break; 5780 case OPC2_32_RR_MOV_64: 5781 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5782 temp = tcg_temp_new(); 5783 5784 CHECK_REG_PAIR(r3); 5785 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 5786 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5787 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 5788 } else { 5789 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5790 } 5791 break; 5792 case OPC2_32_RR_MOVS_64: 5793 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5794 CHECK_REG_PAIR(r3); 5795 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5796 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); 5797 } else { 5798 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5799 } 5800 break; 5801 case OPC2_32_RR_NE: 5802 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5803 cpu_gpr_d[r2]); 5804 break; 5805 case OPC2_32_RR_OR_EQ: 5806 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5807 cpu_gpr_d[r2], &tcg_gen_or_tl); 5808 break; 5809 case OPC2_32_RR_OR_GE: 5810 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5811 cpu_gpr_d[r2], &tcg_gen_or_tl); 5812 break; 5813 case OPC2_32_RR_OR_GE_U: 5814 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5815 cpu_gpr_d[r2], &tcg_gen_or_tl); 5816 break; 5817 case OPC2_32_RR_OR_LT: 5818 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5819 cpu_gpr_d[r2], &tcg_gen_or_tl); 5820 break; 5821 case OPC2_32_RR_OR_LT_U: 5822 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5823 cpu_gpr_d[r2], &tcg_gen_or_tl); 5824 break; 5825 case OPC2_32_RR_OR_NE: 5826 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5827 cpu_gpr_d[r2], &tcg_gen_or_tl); 5828 break; 5829 case OPC2_32_RR_SAT_B: 5830 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); 5831 break; 5832 case OPC2_32_RR_SAT_BU: 5833 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); 5834 break; 5835 case OPC2_32_RR_SAT_H: 5836 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); 5837 break; 5838 case OPC2_32_RR_SAT_HU: 5839 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); 5840 break; 5841 case OPC2_32_RR_SH_EQ: 5842 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5843 cpu_gpr_d[r2]); 5844 break; 5845 case OPC2_32_RR_SH_GE: 5846 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5847 cpu_gpr_d[r2]); 5848 break; 5849 case OPC2_32_RR_SH_GE_U: 5850 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5851 cpu_gpr_d[r2]); 5852 break; 5853 case OPC2_32_RR_SH_LT: 5854 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5855 cpu_gpr_d[r2]); 5856 break; 5857 case OPC2_32_RR_SH_LT_U: 5858 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5859 cpu_gpr_d[r2]); 5860 break; 5861 case OPC2_32_RR_SH_NE: 5862 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5863 cpu_gpr_d[r2]); 5864 break; 5865 case OPC2_32_RR_SUB: 5866 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5867 break; 5868 case OPC2_32_RR_SUB_B: 5869 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5870 break; 5871 case OPC2_32_RR_SUB_H: 5872 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5873 break; 5874 case OPC2_32_RR_SUBC: 5875 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5876 break; 5877 case OPC2_32_RR_SUBS: 5878 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5879 break; 5880 case OPC2_32_RR_SUBS_U: 5881 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5882 break; 5883 case OPC2_32_RR_SUBS_H: 5884 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5885 cpu_gpr_d[r2]); 5886 break; 5887 case OPC2_32_RR_SUBS_HU: 5888 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5889 cpu_gpr_d[r2]); 5890 break; 5891 case OPC2_32_RR_SUBX: 5892 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5893 break; 5894 case OPC2_32_RR_XOR_EQ: 5895 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5896 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5897 break; 5898 case OPC2_32_RR_XOR_GE: 5899 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5900 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5901 break; 5902 case OPC2_32_RR_XOR_GE_U: 5903 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5904 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5905 break; 5906 case OPC2_32_RR_XOR_LT: 5907 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5908 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5909 break; 5910 case OPC2_32_RR_XOR_LT_U: 5911 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5912 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5913 break; 5914 case OPC2_32_RR_XOR_NE: 5915 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5916 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5917 break; 5918 default: 5919 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5920 } 5921 } 5922 5923 static void decode_rr_logical_shift(DisasContext *ctx) 5924 { 5925 uint32_t op2; 5926 int r3, r2, r1; 5927 5928 r3 = MASK_OP_RR_D(ctx->opcode); 5929 r2 = MASK_OP_RR_S2(ctx->opcode); 5930 r1 = MASK_OP_RR_S1(ctx->opcode); 5931 op2 = MASK_OP_RR_OP2(ctx->opcode); 5932 5933 switch (op2) { 5934 case OPC2_32_RR_AND: 5935 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5936 break; 5937 case OPC2_32_RR_ANDN: 5938 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5939 break; 5940 case OPC2_32_RR_CLO: 5941 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5942 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); 5943 break; 5944 case OPC2_32_RR_CLO_H: 5945 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5946 break; 5947 case OPC2_32_RR_CLS: 5948 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5949 break; 5950 case OPC2_32_RR_CLS_H: 5951 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5952 break; 5953 case OPC2_32_RR_CLZ: 5954 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); 5955 break; 5956 case OPC2_32_RR_CLZ_H: 5957 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5958 break; 5959 case OPC2_32_RR_NAND: 5960 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5961 break; 5962 case OPC2_32_RR_NOR: 5963 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5964 break; 5965 case OPC2_32_RR_OR: 5966 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5967 break; 5968 case OPC2_32_RR_ORN: 5969 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5970 break; 5971 case OPC2_32_RR_SH: 5972 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5973 break; 5974 case OPC2_32_RR_SH_H: 5975 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5976 break; 5977 case OPC2_32_RR_SHA: 5978 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5979 break; 5980 case OPC2_32_RR_SHA_H: 5981 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5982 break; 5983 case OPC2_32_RR_SHAS: 5984 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5985 break; 5986 case OPC2_32_RR_XNOR: 5987 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5988 break; 5989 case OPC2_32_RR_XOR: 5990 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5991 break; 5992 default: 5993 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5994 } 5995 } 5996 5997 static void decode_rr_address(DisasContext *ctx) 5998 { 5999 uint32_t op2, n; 6000 int r1, r2, r3; 6001 TCGv temp; 6002 6003 op2 = MASK_OP_RR_OP2(ctx->opcode); 6004 r3 = MASK_OP_RR_D(ctx->opcode); 6005 r2 = MASK_OP_RR_S2(ctx->opcode); 6006 r1 = MASK_OP_RR_S1(ctx->opcode); 6007 n = MASK_OP_RR_N(ctx->opcode); 6008 6009 switch (op2) { 6010 case OPC2_32_RR_ADD_A: 6011 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6012 break; 6013 case OPC2_32_RR_ADDSC_A: 6014 temp = tcg_temp_new(); 6015 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); 6016 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); 6017 break; 6018 case OPC2_32_RR_ADDSC_AT: 6019 temp = tcg_temp_new(); 6020 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); 6021 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); 6022 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); 6023 break; 6024 case OPC2_32_RR_EQ_A: 6025 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 6026 cpu_gpr_a[r2]); 6027 break; 6028 case OPC2_32_RR_EQZ: 6029 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6030 break; 6031 case OPC2_32_RR_GE_A: 6032 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6033 cpu_gpr_a[r2]); 6034 break; 6035 case OPC2_32_RR_LT_A: 6036 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6037 cpu_gpr_a[r2]); 6038 break; 6039 case OPC2_32_RR_MOV_A: 6040 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); 6041 break; 6042 case OPC2_32_RR_MOV_AA: 6043 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); 6044 break; 6045 case OPC2_32_RR_MOV_D: 6046 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); 6047 break; 6048 case OPC2_32_RR_NE_A: 6049 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 6050 cpu_gpr_a[r2]); 6051 break; 6052 case OPC2_32_RR_NEZ_A: 6053 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6054 break; 6055 case OPC2_32_RR_SUB_A: 6056 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6057 break; 6058 default: 6059 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6060 } 6061 } 6062 6063 static void decode_rr_idirect(DisasContext *ctx) 6064 { 6065 uint32_t op2; 6066 int r1; 6067 6068 op2 = MASK_OP_RR_OP2(ctx->opcode); 6069 r1 = MASK_OP_RR_S1(ctx->opcode); 6070 6071 switch (op2) { 6072 case OPC2_32_RR_JI: 6073 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6074 break; 6075 case OPC2_32_RR_JLI: 6076 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6077 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 6078 break; 6079 case OPC2_32_RR_CALLI: 6080 gen_helper_1arg(call, ctx->pc_succ_insn); 6081 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6082 break; 6083 case OPC2_32_RR_FCALLI: 6084 gen_fcall_save_ctx(ctx); 6085 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6086 break; 6087 default: 6088 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6089 return; 6090 } 6091 ctx->base.is_jmp = DISAS_JUMP; 6092 } 6093 6094 static void decode_rr_divide(DisasContext *ctx) 6095 { 6096 uint32_t op2; 6097 int r1, r2, r3; 6098 6099 TCGv temp, temp2, temp3; 6100 6101 op2 = MASK_OP_RR_OP2(ctx->opcode); 6102 r3 = MASK_OP_RR_D(ctx->opcode); 6103 r2 = MASK_OP_RR_S2(ctx->opcode); 6104 r1 = MASK_OP_RR_S1(ctx->opcode); 6105 6106 switch (op2) { 6107 case OPC2_32_RR_BMERGE: 6108 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6109 break; 6110 case OPC2_32_RR_BSPLIT: 6111 CHECK_REG_PAIR(r3); 6112 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6113 break; 6114 case OPC2_32_RR_DVINIT_B: 6115 CHECK_REG_PAIR(r3); 6116 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6117 cpu_gpr_d[r2]); 6118 break; 6119 case OPC2_32_RR_DVINIT_BU: 6120 temp = tcg_temp_new(); 6121 temp2 = tcg_temp_new(); 6122 temp3 = tcg_temp_new(); 6123 CHECK_REG_PAIR(r3); 6124 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); 6125 /* reset av */ 6126 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6127 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6128 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6129 tcg_gen_abs_tl(temp, temp3); 6130 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6131 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6132 } else { 6133 /* overflow = (D[b] == 0) */ 6134 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6135 } 6136 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6137 /* sv */ 6138 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6139 /* write result */ 6140 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); 6141 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6142 break; 6143 case OPC2_32_RR_DVINIT_H: 6144 CHECK_REG_PAIR(r3); 6145 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6146 cpu_gpr_d[r2]); 6147 break; 6148 case OPC2_32_RR_DVINIT_HU: 6149 temp = tcg_temp_new(); 6150 temp2 = tcg_temp_new(); 6151 temp3 = tcg_temp_new(); 6152 CHECK_REG_PAIR(r3); 6153 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); 6154 /* reset av */ 6155 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6156 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6157 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6158 tcg_gen_abs_tl(temp, temp3); 6159 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6160 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6161 } else { 6162 /* overflow = (D[b] == 0) */ 6163 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6164 } 6165 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6166 /* sv */ 6167 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6168 /* write result */ 6169 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); 6170 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6171 break; 6172 case OPC2_32_RR_DVINIT: 6173 temp = tcg_temp_new(); 6174 temp2 = tcg_temp_new(); 6175 CHECK_REG_PAIR(r3); 6176 /* overflow = ((D[b] == 0) || 6177 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ 6178 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); 6179 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); 6180 tcg_gen_and_tl(temp, temp, temp2); 6181 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); 6182 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 6183 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6184 /* sv */ 6185 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6186 /* reset av */ 6187 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6188 /* write result */ 6189 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6190 /* sign extend to high reg */ 6191 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); 6192 break; 6193 case OPC2_32_RR_DVINIT_U: 6194 CHECK_REG_PAIR(r3); 6195 /* overflow = (D[b] == 0) */ 6196 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6197 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6198 /* sv */ 6199 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6200 /* reset av */ 6201 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6202 /* write result */ 6203 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6204 /* zero extend to high reg*/ 6205 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); 6206 break; 6207 case OPC2_32_RR_PARITY: 6208 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6209 break; 6210 case OPC2_32_RR_UNPACK: 6211 CHECK_REG_PAIR(r3); 6212 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6213 break; 6214 case OPC2_32_RR_CRC32_B: 6215 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6216 gen_helper_crc32b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6217 } else { 6218 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6219 } 6220 break; 6221 case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */ 6222 if (has_feature(ctx, TRICORE_FEATURE_161)) { 6223 gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6224 } else { 6225 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6226 } 6227 break; 6228 case OPC2_32_RR_CRC32L_W: 6229 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6230 gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6231 } else { 6232 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6233 } 6234 break; 6235 6236 case OPC2_32_RR_POPCNT_W: 6237 if (has_feature(ctx, TRICORE_FEATURE_162)) { 6238 tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6239 } else { 6240 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6241 } 6242 break; 6243 case OPC2_32_RR_DIV: 6244 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6245 CHECK_REG_PAIR(r3); 6246 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6247 cpu_gpr_d[r2]); 6248 } else { 6249 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6250 } 6251 break; 6252 case OPC2_32_RR_DIV_U: 6253 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6254 CHECK_REG_PAIR(r3); 6255 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], 6256 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6257 } else { 6258 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6259 } 6260 break; 6261 case OPC2_32_RR_MUL_F: 6262 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6263 break; 6264 case OPC2_32_RR_DIV_F: 6265 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6266 break; 6267 case OPC2_32_RR_CMP_F: 6268 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6269 break; 6270 case OPC2_32_RR_FTOI: 6271 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6272 break; 6273 case OPC2_32_RR_ITOF: 6274 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6275 break; 6276 case OPC2_32_RR_FTOUZ: 6277 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6278 break; 6279 case OPC2_32_RR_UPDFL: 6280 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); 6281 break; 6282 case OPC2_32_RR_UTOF: 6283 gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6284 break; 6285 case OPC2_32_RR_FTOIZ: 6286 gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6287 break; 6288 case OPC2_32_RR_QSEED_F: 6289 gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6290 break; 6291 default: 6292 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6293 } 6294 } 6295 6296 /* RR1 Format */ 6297 static void decode_rr1_mul(DisasContext *ctx) 6298 { 6299 uint32_t op2; 6300 6301 int r1, r2, r3; 6302 TCGv n; 6303 TCGv_i64 temp64; 6304 6305 r1 = MASK_OP_RR1_S1(ctx->opcode); 6306 r2 = MASK_OP_RR1_S2(ctx->opcode); 6307 r3 = MASK_OP_RR1_D(ctx->opcode); 6308 n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode)); 6309 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6310 6311 switch (op2) { 6312 case OPC2_32_RR1_MUL_H_32_LL: 6313 temp64 = tcg_temp_new_i64(); 6314 CHECK_REG_PAIR(r3); 6315 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6316 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6317 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6318 break; 6319 case OPC2_32_RR1_MUL_H_32_LU: 6320 temp64 = tcg_temp_new_i64(); 6321 CHECK_REG_PAIR(r3); 6322 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6323 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6324 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6325 break; 6326 case OPC2_32_RR1_MUL_H_32_UL: 6327 temp64 = tcg_temp_new_i64(); 6328 CHECK_REG_PAIR(r3); 6329 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6330 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6331 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6332 break; 6333 case OPC2_32_RR1_MUL_H_32_UU: 6334 temp64 = tcg_temp_new_i64(); 6335 CHECK_REG_PAIR(r3); 6336 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6337 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6338 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6339 break; 6340 case OPC2_32_RR1_MULM_H_64_LL: 6341 temp64 = tcg_temp_new_i64(); 6342 CHECK_REG_PAIR(r3); 6343 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6344 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6345 /* reset V bit */ 6346 tcg_gen_movi_tl(cpu_PSW_V, 0); 6347 /* reset AV bit */ 6348 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6349 break; 6350 case OPC2_32_RR1_MULM_H_64_LU: 6351 temp64 = tcg_temp_new_i64(); 6352 CHECK_REG_PAIR(r3); 6353 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6354 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6355 /* reset V bit */ 6356 tcg_gen_movi_tl(cpu_PSW_V, 0); 6357 /* reset AV bit */ 6358 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6359 break; 6360 case OPC2_32_RR1_MULM_H_64_UL: 6361 temp64 = tcg_temp_new_i64(); 6362 CHECK_REG_PAIR(r3); 6363 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6364 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6365 /* reset V bit */ 6366 tcg_gen_movi_tl(cpu_PSW_V, 0); 6367 /* reset AV bit */ 6368 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6369 break; 6370 case OPC2_32_RR1_MULM_H_64_UU: 6371 temp64 = tcg_temp_new_i64(); 6372 CHECK_REG_PAIR(r3); 6373 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6374 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6375 /* reset V bit */ 6376 tcg_gen_movi_tl(cpu_PSW_V, 0); 6377 /* reset AV bit */ 6378 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6379 break; 6380 case OPC2_32_RR1_MULR_H_16_LL: 6381 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6382 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6383 break; 6384 case OPC2_32_RR1_MULR_H_16_LU: 6385 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6386 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6387 break; 6388 case OPC2_32_RR1_MULR_H_16_UL: 6389 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6390 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6391 break; 6392 case OPC2_32_RR1_MULR_H_16_UU: 6393 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6394 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6395 break; 6396 default: 6397 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6398 } 6399 } 6400 6401 static void decode_rr1_mulq(DisasContext *ctx) 6402 { 6403 uint32_t op2; 6404 int r1, r2, r3; 6405 uint32_t n; 6406 6407 TCGv temp, temp2; 6408 6409 r1 = MASK_OP_RR1_S1(ctx->opcode); 6410 r2 = MASK_OP_RR1_S2(ctx->opcode); 6411 r3 = MASK_OP_RR1_D(ctx->opcode); 6412 n = MASK_OP_RR1_N(ctx->opcode); 6413 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6414 6415 temp = tcg_temp_new(); 6416 temp2 = tcg_temp_new(); 6417 6418 switch (op2) { 6419 case OPC2_32_RR1_MUL_Q_32: 6420 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); 6421 break; 6422 case OPC2_32_RR1_MUL_Q_64: 6423 CHECK_REG_PAIR(r3); 6424 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6425 n, 0); 6426 break; 6427 case OPC2_32_RR1_MUL_Q_32_L: 6428 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6429 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6430 break; 6431 case OPC2_32_RR1_MUL_Q_64_L: 6432 CHECK_REG_PAIR(r3); 6433 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6434 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6435 break; 6436 case OPC2_32_RR1_MUL_Q_32_U: 6437 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6438 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6439 break; 6440 case OPC2_32_RR1_MUL_Q_64_U: 6441 CHECK_REG_PAIR(r3); 6442 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6443 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6444 break; 6445 case OPC2_32_RR1_MUL_Q_32_LL: 6446 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6447 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6448 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6449 break; 6450 case OPC2_32_RR1_MUL_Q_32_UU: 6451 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6452 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6453 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6454 break; 6455 case OPC2_32_RR1_MULR_Q_32_L: 6456 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6457 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6458 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6459 break; 6460 case OPC2_32_RR1_MULR_Q_32_U: 6461 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6462 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6463 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6464 break; 6465 default: 6466 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6467 } 6468 } 6469 6470 /* RR2 format */ 6471 static void decode_rr2_mul(DisasContext *ctx) 6472 { 6473 uint32_t op2; 6474 int r1, r2, r3; 6475 6476 op2 = MASK_OP_RR2_OP2(ctx->opcode); 6477 r1 = MASK_OP_RR2_S1(ctx->opcode); 6478 r2 = MASK_OP_RR2_S2(ctx->opcode); 6479 r3 = MASK_OP_RR2_D(ctx->opcode); 6480 switch (op2) { 6481 case OPC2_32_RR2_MUL_32: 6482 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6483 break; 6484 case OPC2_32_RR2_MUL_64: 6485 CHECK_REG_PAIR(r3); 6486 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6487 cpu_gpr_d[r2]); 6488 break; 6489 case OPC2_32_RR2_MULS_32: 6490 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6491 cpu_gpr_d[r2]); 6492 break; 6493 case OPC2_32_RR2_MUL_U_64: 6494 CHECK_REG_PAIR(r3); 6495 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6496 cpu_gpr_d[r2]); 6497 break; 6498 case OPC2_32_RR2_MULS_U_32: 6499 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6500 cpu_gpr_d[r2]); 6501 break; 6502 default: 6503 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6504 } 6505 } 6506 6507 /* RRPW format */ 6508 static void decode_rrpw_extract_insert(DisasContext *ctx) 6509 { 6510 uint32_t op2; 6511 int r1, r2, r3; 6512 int32_t pos, width; 6513 TCGv temp; 6514 6515 op2 = MASK_OP_RRPW_OP2(ctx->opcode); 6516 r1 = MASK_OP_RRPW_S1(ctx->opcode); 6517 r2 = MASK_OP_RRPW_S2(ctx->opcode); 6518 r3 = MASK_OP_RRPW_D(ctx->opcode); 6519 pos = MASK_OP_RRPW_POS(ctx->opcode); 6520 width = MASK_OP_RRPW_WIDTH(ctx->opcode); 6521 6522 switch (op2) { 6523 case OPC2_32_RRPW_EXTR: 6524 if (width == 0) { 6525 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6526 break; 6527 } 6528 6529 if (pos + width <= 32) { 6530 /* optimize special cases */ 6531 if ((pos == 0) && (width == 8)) { 6532 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6533 } else if ((pos == 0) && (width == 16)) { 6534 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6535 } else { 6536 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width); 6537 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width); 6538 } 6539 } 6540 break; 6541 case OPC2_32_RRPW_EXTR_U: 6542 if (width == 0) { 6543 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6544 } else { 6545 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); 6546 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width)); 6547 } 6548 break; 6549 case OPC2_32_RRPW_IMASK: 6550 CHECK_REG_PAIR(r3); 6551 6552 if (pos + width <= 32) { 6553 temp = tcg_temp_new(); 6554 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); 6555 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); 6556 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 6557 } 6558 6559 break; 6560 case OPC2_32_RRPW_INSERT: 6561 if (pos + width <= 32) { 6562 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 6563 pos, width); 6564 } 6565 break; 6566 default: 6567 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6568 } 6569 } 6570 6571 /* RRR format */ 6572 static void decode_rrr_cond_select(DisasContext *ctx) 6573 { 6574 uint32_t op2; 6575 int r1, r2, r3, r4; 6576 TCGv temp; 6577 6578 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6579 r1 = MASK_OP_RRR_S1(ctx->opcode); 6580 r2 = MASK_OP_RRR_S2(ctx->opcode); 6581 r3 = MASK_OP_RRR_S3(ctx->opcode); 6582 r4 = MASK_OP_RRR_D(ctx->opcode); 6583 6584 switch (op2) { 6585 case OPC2_32_RRR_CADD: 6586 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 6587 cpu_gpr_d[r4], cpu_gpr_d[r3]); 6588 break; 6589 case OPC2_32_RRR_CADDN: 6590 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6591 cpu_gpr_d[r3]); 6592 break; 6593 case OPC2_32_RRR_CSUB: 6594 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6595 cpu_gpr_d[r3]); 6596 break; 6597 case OPC2_32_RRR_CSUBN: 6598 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6599 cpu_gpr_d[r3]); 6600 break; 6601 case OPC2_32_RRR_SEL: 6602 temp = tcg_constant_i32(0); 6603 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6604 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6605 break; 6606 case OPC2_32_RRR_SELN: 6607 temp = tcg_constant_i32(0); 6608 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6609 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6610 break; 6611 default: 6612 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6613 } 6614 } 6615 6616 static void decode_rrr_divide(DisasContext *ctx) 6617 { 6618 uint32_t op2; 6619 6620 int r1, r2, r3, r4; 6621 6622 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6623 r1 = MASK_OP_RRR_S1(ctx->opcode); 6624 r2 = MASK_OP_RRR_S2(ctx->opcode); 6625 r3 = MASK_OP_RRR_S3(ctx->opcode); 6626 r4 = MASK_OP_RRR_D(ctx->opcode); 6627 6628 switch (op2) { 6629 case OPC2_32_RRR_DVADJ: 6630 CHECK_REG_PAIR(r3); 6631 CHECK_REG_PAIR(r4); 6632 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6633 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6634 break; 6635 case OPC2_32_RRR_DVSTEP: 6636 CHECK_REG_PAIR(r3); 6637 CHECK_REG_PAIR(r4); 6638 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6639 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6640 break; 6641 case OPC2_32_RRR_DVSTEP_U: 6642 CHECK_REG_PAIR(r3); 6643 CHECK_REG_PAIR(r4); 6644 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6645 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6646 break; 6647 case OPC2_32_RRR_IXMAX: 6648 CHECK_REG_PAIR(r3); 6649 CHECK_REG_PAIR(r4); 6650 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6651 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6652 break; 6653 case OPC2_32_RRR_IXMAX_U: 6654 CHECK_REG_PAIR(r3); 6655 CHECK_REG_PAIR(r4); 6656 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6657 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6658 break; 6659 case OPC2_32_RRR_IXMIN: 6660 CHECK_REG_PAIR(r3); 6661 CHECK_REG_PAIR(r4); 6662 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6663 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6664 break; 6665 case OPC2_32_RRR_IXMIN_U: 6666 CHECK_REG_PAIR(r3); 6667 CHECK_REG_PAIR(r4); 6668 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6669 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6670 break; 6671 case OPC2_32_RRR_PACK: 6672 CHECK_REG_PAIR(r3); 6673 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], 6674 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6675 break; 6676 case OPC2_32_RRR_ADD_F: 6677 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6678 break; 6679 case OPC2_32_RRR_SUB_F: 6680 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6681 break; 6682 case OPC2_32_RRR_MADD_F: 6683 gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6684 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6685 break; 6686 case OPC2_32_RRR_MSUB_F: 6687 gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6688 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6689 break; 6690 default: 6691 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6692 } 6693 } 6694 6695 /* RRR2 format */ 6696 static void decode_rrr2_madd(DisasContext *ctx) 6697 { 6698 uint32_t op2; 6699 uint32_t r1, r2, r3, r4; 6700 6701 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6702 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6703 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6704 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6705 r4 = MASK_OP_RRR2_D(ctx->opcode); 6706 switch (op2) { 6707 case OPC2_32_RRR2_MADD_32: 6708 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6709 cpu_gpr_d[r2]); 6710 break; 6711 case OPC2_32_RRR2_MADD_64: 6712 CHECK_REG_PAIR(r4); 6713 CHECK_REG_PAIR(r3); 6714 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6715 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6716 break; 6717 case OPC2_32_RRR2_MADDS_32: 6718 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6719 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6720 break; 6721 case OPC2_32_RRR2_MADDS_64: 6722 CHECK_REG_PAIR(r4); 6723 CHECK_REG_PAIR(r3); 6724 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6725 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6726 break; 6727 case OPC2_32_RRR2_MADD_U_64: 6728 CHECK_REG_PAIR(r4); 6729 CHECK_REG_PAIR(r3); 6730 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6731 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6732 break; 6733 case OPC2_32_RRR2_MADDS_U_32: 6734 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6735 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6736 break; 6737 case OPC2_32_RRR2_MADDS_U_64: 6738 CHECK_REG_PAIR(r4); 6739 CHECK_REG_PAIR(r3); 6740 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6741 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6742 break; 6743 default: 6744 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6745 } 6746 } 6747 6748 static void decode_rrr2_msub(DisasContext *ctx) 6749 { 6750 uint32_t op2; 6751 uint32_t r1, r2, r3, r4; 6752 6753 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6754 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6755 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6756 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6757 r4 = MASK_OP_RRR2_D(ctx->opcode); 6758 6759 switch (op2) { 6760 case OPC2_32_RRR2_MSUB_32: 6761 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6762 cpu_gpr_d[r2]); 6763 break; 6764 case OPC2_32_RRR2_MSUB_64: 6765 CHECK_REG_PAIR(r4); 6766 CHECK_REG_PAIR(r3); 6767 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6768 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6769 break; 6770 case OPC2_32_RRR2_MSUBS_32: 6771 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6772 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6773 break; 6774 case OPC2_32_RRR2_MSUBS_64: 6775 CHECK_REG_PAIR(r4); 6776 CHECK_REG_PAIR(r3); 6777 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6778 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6779 break; 6780 case OPC2_32_RRR2_MSUB_U_64: 6781 CHECK_REG_PAIR(r4); 6782 CHECK_REG_PAIR(r3); 6783 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6784 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6785 break; 6786 case OPC2_32_RRR2_MSUBS_U_32: 6787 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6788 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6789 break; 6790 case OPC2_32_RRR2_MSUBS_U_64: 6791 CHECK_REG_PAIR(r4); 6792 CHECK_REG_PAIR(r3); 6793 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6794 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6795 break; 6796 default: 6797 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6798 } 6799 } 6800 6801 /* RRR1 format */ 6802 static void decode_rrr1_madd(DisasContext *ctx) 6803 { 6804 uint32_t op2; 6805 uint32_t r1, r2, r3, r4, n; 6806 6807 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6808 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6809 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6810 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6811 r4 = MASK_OP_RRR1_D(ctx->opcode); 6812 n = MASK_OP_RRR1_N(ctx->opcode); 6813 6814 switch (op2) { 6815 case OPC2_32_RRR1_MADD_H_LL: 6816 CHECK_REG_PAIR(r4); 6817 CHECK_REG_PAIR(r3); 6818 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6819 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6820 break; 6821 case OPC2_32_RRR1_MADD_H_LU: 6822 CHECK_REG_PAIR(r4); 6823 CHECK_REG_PAIR(r3); 6824 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6825 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6826 break; 6827 case OPC2_32_RRR1_MADD_H_UL: 6828 CHECK_REG_PAIR(r4); 6829 CHECK_REG_PAIR(r3); 6830 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6831 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6832 break; 6833 case OPC2_32_RRR1_MADD_H_UU: 6834 CHECK_REG_PAIR(r4); 6835 CHECK_REG_PAIR(r3); 6836 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6837 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6838 break; 6839 case OPC2_32_RRR1_MADDS_H_LL: 6840 CHECK_REG_PAIR(r4); 6841 CHECK_REG_PAIR(r3); 6842 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6843 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6844 break; 6845 case OPC2_32_RRR1_MADDS_H_LU: 6846 CHECK_REG_PAIR(r4); 6847 CHECK_REG_PAIR(r3); 6848 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6849 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6850 break; 6851 case OPC2_32_RRR1_MADDS_H_UL: 6852 CHECK_REG_PAIR(r4); 6853 CHECK_REG_PAIR(r3); 6854 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6855 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6856 break; 6857 case OPC2_32_RRR1_MADDS_H_UU: 6858 CHECK_REG_PAIR(r4); 6859 CHECK_REG_PAIR(r3); 6860 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6861 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6862 break; 6863 case OPC2_32_RRR1_MADDM_H_LL: 6864 CHECK_REG_PAIR(r4); 6865 CHECK_REG_PAIR(r3); 6866 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6867 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6868 break; 6869 case OPC2_32_RRR1_MADDM_H_LU: 6870 CHECK_REG_PAIR(r4); 6871 CHECK_REG_PAIR(r3); 6872 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6873 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6874 break; 6875 case OPC2_32_RRR1_MADDM_H_UL: 6876 CHECK_REG_PAIR(r4); 6877 CHECK_REG_PAIR(r3); 6878 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6879 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6880 break; 6881 case OPC2_32_RRR1_MADDM_H_UU: 6882 CHECK_REG_PAIR(r4); 6883 CHECK_REG_PAIR(r3); 6884 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6885 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6886 break; 6887 case OPC2_32_RRR1_MADDMS_H_LL: 6888 CHECK_REG_PAIR(r4); 6889 CHECK_REG_PAIR(r3); 6890 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6891 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6892 break; 6893 case OPC2_32_RRR1_MADDMS_H_LU: 6894 CHECK_REG_PAIR(r4); 6895 CHECK_REG_PAIR(r3); 6896 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6897 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6898 break; 6899 case OPC2_32_RRR1_MADDMS_H_UL: 6900 CHECK_REG_PAIR(r4); 6901 CHECK_REG_PAIR(r3); 6902 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6903 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6904 break; 6905 case OPC2_32_RRR1_MADDMS_H_UU: 6906 CHECK_REG_PAIR(r4); 6907 CHECK_REG_PAIR(r3); 6908 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6909 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6910 break; 6911 case OPC2_32_RRR1_MADDR_H_LL: 6912 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6913 cpu_gpr_d[r2], n, MODE_LL); 6914 break; 6915 case OPC2_32_RRR1_MADDR_H_LU: 6916 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6917 cpu_gpr_d[r2], n, MODE_LU); 6918 break; 6919 case OPC2_32_RRR1_MADDR_H_UL: 6920 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6921 cpu_gpr_d[r2], n, MODE_UL); 6922 break; 6923 case OPC2_32_RRR1_MADDR_H_UU: 6924 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6925 cpu_gpr_d[r2], n, MODE_UU); 6926 break; 6927 case OPC2_32_RRR1_MADDRS_H_LL: 6928 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6929 cpu_gpr_d[r2], n, MODE_LL); 6930 break; 6931 case OPC2_32_RRR1_MADDRS_H_LU: 6932 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6933 cpu_gpr_d[r2], n, MODE_LU); 6934 break; 6935 case OPC2_32_RRR1_MADDRS_H_UL: 6936 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6937 cpu_gpr_d[r2], n, MODE_UL); 6938 break; 6939 case OPC2_32_RRR1_MADDRS_H_UU: 6940 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6941 cpu_gpr_d[r2], n, MODE_UU); 6942 break; 6943 default: 6944 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6945 } 6946 } 6947 6948 static void decode_rrr1_maddq_h(DisasContext *ctx) 6949 { 6950 uint32_t op2; 6951 uint32_t r1, r2, r3, r4, n; 6952 TCGv temp, temp2; 6953 6954 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6955 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6956 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6957 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6958 r4 = MASK_OP_RRR1_D(ctx->opcode); 6959 n = MASK_OP_RRR1_N(ctx->opcode); 6960 6961 temp = tcg_temp_new(); 6962 temp2 = tcg_temp_new(); 6963 6964 switch (op2) { 6965 case OPC2_32_RRR1_MADD_Q_32: 6966 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6967 cpu_gpr_d[r2], n, 32); 6968 break; 6969 case OPC2_32_RRR1_MADD_Q_64: 6970 CHECK_REG_PAIR(r4); 6971 CHECK_REG_PAIR(r3); 6972 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6973 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6974 n); 6975 break; 6976 case OPC2_32_RRR1_MADD_Q_32_L: 6977 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6978 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6979 temp, n, 16); 6980 break; 6981 case OPC2_32_RRR1_MADD_Q_64_L: 6982 CHECK_REG_PAIR(r4); 6983 CHECK_REG_PAIR(r3); 6984 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6985 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6986 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 6987 n); 6988 break; 6989 case OPC2_32_RRR1_MADD_Q_32_U: 6990 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6991 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6992 temp, n, 16); 6993 break; 6994 case OPC2_32_RRR1_MADD_Q_64_U: 6995 CHECK_REG_PAIR(r4); 6996 CHECK_REG_PAIR(r3); 6997 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6998 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6999 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7000 n); 7001 break; 7002 case OPC2_32_RRR1_MADD_Q_32_LL: 7003 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7004 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7005 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7006 break; 7007 case OPC2_32_RRR1_MADD_Q_64_LL: 7008 CHECK_REG_PAIR(r4); 7009 CHECK_REG_PAIR(r3); 7010 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7011 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7012 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7013 cpu_gpr_d[r3+1], temp, temp2, n); 7014 break; 7015 case OPC2_32_RRR1_MADD_Q_32_UU: 7016 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7017 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7018 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7019 break; 7020 case OPC2_32_RRR1_MADD_Q_64_UU: 7021 CHECK_REG_PAIR(r4); 7022 CHECK_REG_PAIR(r3); 7023 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7024 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7025 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7026 cpu_gpr_d[r3+1], temp, temp2, n); 7027 break; 7028 case OPC2_32_RRR1_MADDS_Q_32: 7029 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7030 cpu_gpr_d[r2], n, 32); 7031 break; 7032 case OPC2_32_RRR1_MADDS_Q_64: 7033 CHECK_REG_PAIR(r4); 7034 CHECK_REG_PAIR(r3); 7035 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7036 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7037 n); 7038 break; 7039 case OPC2_32_RRR1_MADDS_Q_32_L: 7040 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7041 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7042 temp, n, 16); 7043 break; 7044 case OPC2_32_RRR1_MADDS_Q_64_L: 7045 CHECK_REG_PAIR(r4); 7046 CHECK_REG_PAIR(r3); 7047 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7048 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7049 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7050 n); 7051 break; 7052 case OPC2_32_RRR1_MADDS_Q_32_U: 7053 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7054 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7055 temp, n, 16); 7056 break; 7057 case OPC2_32_RRR1_MADDS_Q_64_U: 7058 CHECK_REG_PAIR(r4); 7059 CHECK_REG_PAIR(r3); 7060 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7061 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7062 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7063 n); 7064 break; 7065 case OPC2_32_RRR1_MADDS_Q_32_LL: 7066 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7067 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7068 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7069 break; 7070 case OPC2_32_RRR1_MADDS_Q_64_LL: 7071 CHECK_REG_PAIR(r4); 7072 CHECK_REG_PAIR(r3); 7073 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7074 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7075 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7076 cpu_gpr_d[r3+1], temp, temp2, n); 7077 break; 7078 case OPC2_32_RRR1_MADDS_Q_32_UU: 7079 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7080 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7081 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7082 break; 7083 case OPC2_32_RRR1_MADDS_Q_64_UU: 7084 CHECK_REG_PAIR(r4); 7085 CHECK_REG_PAIR(r3); 7086 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7087 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7088 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7089 cpu_gpr_d[r3+1], temp, temp2, n); 7090 break; 7091 case OPC2_32_RRR1_MADDR_H_64_UL: 7092 CHECK_REG_PAIR(r3); 7093 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7094 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7095 break; 7096 case OPC2_32_RRR1_MADDRS_H_64_UL: 7097 CHECK_REG_PAIR(r3); 7098 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7099 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7100 break; 7101 case OPC2_32_RRR1_MADDR_Q_32_LL: 7102 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7103 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7104 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7105 break; 7106 case OPC2_32_RRR1_MADDR_Q_32_UU: 7107 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7108 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7109 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7110 break; 7111 case OPC2_32_RRR1_MADDRS_Q_32_LL: 7112 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7113 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7114 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7115 break; 7116 case OPC2_32_RRR1_MADDRS_Q_32_UU: 7117 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7118 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7119 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7120 break; 7121 default: 7122 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7123 } 7124 } 7125 7126 static void decode_rrr1_maddsu_h(DisasContext *ctx) 7127 { 7128 uint32_t op2; 7129 uint32_t r1, r2, r3, r4, n; 7130 7131 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7132 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7133 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7134 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7135 r4 = MASK_OP_RRR1_D(ctx->opcode); 7136 n = MASK_OP_RRR1_N(ctx->opcode); 7137 7138 switch (op2) { 7139 case OPC2_32_RRR1_MADDSU_H_32_LL: 7140 CHECK_REG_PAIR(r4); 7141 CHECK_REG_PAIR(r3); 7142 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7143 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7144 break; 7145 case OPC2_32_RRR1_MADDSU_H_32_LU: 7146 CHECK_REG_PAIR(r4); 7147 CHECK_REG_PAIR(r3); 7148 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7149 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7150 break; 7151 case OPC2_32_RRR1_MADDSU_H_32_UL: 7152 CHECK_REG_PAIR(r4); 7153 CHECK_REG_PAIR(r3); 7154 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7155 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7156 break; 7157 case OPC2_32_RRR1_MADDSU_H_32_UU: 7158 CHECK_REG_PAIR(r4); 7159 CHECK_REG_PAIR(r3); 7160 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7161 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7162 break; 7163 case OPC2_32_RRR1_MADDSUS_H_32_LL: 7164 CHECK_REG_PAIR(r4); 7165 CHECK_REG_PAIR(r3); 7166 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7167 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7168 n, MODE_LL); 7169 break; 7170 case OPC2_32_RRR1_MADDSUS_H_32_LU: 7171 CHECK_REG_PAIR(r4); 7172 CHECK_REG_PAIR(r3); 7173 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7174 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7175 n, MODE_LU); 7176 break; 7177 case OPC2_32_RRR1_MADDSUS_H_32_UL: 7178 CHECK_REG_PAIR(r4); 7179 CHECK_REG_PAIR(r3); 7180 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7181 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7182 n, MODE_UL); 7183 break; 7184 case OPC2_32_RRR1_MADDSUS_H_32_UU: 7185 CHECK_REG_PAIR(r4); 7186 CHECK_REG_PAIR(r3); 7187 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7188 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7189 n, MODE_UU); 7190 break; 7191 case OPC2_32_RRR1_MADDSUM_H_64_LL: 7192 CHECK_REG_PAIR(r4); 7193 CHECK_REG_PAIR(r3); 7194 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7195 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7196 n, MODE_LL); 7197 break; 7198 case OPC2_32_RRR1_MADDSUM_H_64_LU: 7199 CHECK_REG_PAIR(r4); 7200 CHECK_REG_PAIR(r3); 7201 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7202 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7203 n, MODE_LU); 7204 break; 7205 case OPC2_32_RRR1_MADDSUM_H_64_UL: 7206 CHECK_REG_PAIR(r4); 7207 CHECK_REG_PAIR(r3); 7208 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7209 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7210 n, MODE_UL); 7211 break; 7212 case OPC2_32_RRR1_MADDSUM_H_64_UU: 7213 CHECK_REG_PAIR(r4); 7214 CHECK_REG_PAIR(r3); 7215 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7216 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7217 n, MODE_UU); 7218 break; 7219 case OPC2_32_RRR1_MADDSUMS_H_64_LL: 7220 CHECK_REG_PAIR(r4); 7221 CHECK_REG_PAIR(r3); 7222 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7223 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7224 n, MODE_LL); 7225 break; 7226 case OPC2_32_RRR1_MADDSUMS_H_64_LU: 7227 CHECK_REG_PAIR(r4); 7228 CHECK_REG_PAIR(r3); 7229 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7230 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7231 n, MODE_LU); 7232 break; 7233 case OPC2_32_RRR1_MADDSUMS_H_64_UL: 7234 CHECK_REG_PAIR(r4); 7235 CHECK_REG_PAIR(r3); 7236 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7237 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7238 n, MODE_UL); 7239 break; 7240 case OPC2_32_RRR1_MADDSUMS_H_64_UU: 7241 CHECK_REG_PAIR(r4); 7242 CHECK_REG_PAIR(r3); 7243 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7244 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7245 n, MODE_UU); 7246 break; 7247 case OPC2_32_RRR1_MADDSUR_H_16_LL: 7248 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7249 cpu_gpr_d[r2], n, MODE_LL); 7250 break; 7251 case OPC2_32_RRR1_MADDSUR_H_16_LU: 7252 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7253 cpu_gpr_d[r2], n, MODE_LU); 7254 break; 7255 case OPC2_32_RRR1_MADDSUR_H_16_UL: 7256 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7257 cpu_gpr_d[r2], n, MODE_UL); 7258 break; 7259 case OPC2_32_RRR1_MADDSUR_H_16_UU: 7260 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7261 cpu_gpr_d[r2], n, MODE_UU); 7262 break; 7263 case OPC2_32_RRR1_MADDSURS_H_16_LL: 7264 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7265 cpu_gpr_d[r2], n, MODE_LL); 7266 break; 7267 case OPC2_32_RRR1_MADDSURS_H_16_LU: 7268 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7269 cpu_gpr_d[r2], n, MODE_LU); 7270 break; 7271 case OPC2_32_RRR1_MADDSURS_H_16_UL: 7272 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7273 cpu_gpr_d[r2], n, MODE_UL); 7274 break; 7275 case OPC2_32_RRR1_MADDSURS_H_16_UU: 7276 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7277 cpu_gpr_d[r2], n, MODE_UU); 7278 break; 7279 default: 7280 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7281 } 7282 } 7283 7284 static void decode_rrr1_msub(DisasContext *ctx) 7285 { 7286 uint32_t op2; 7287 uint32_t r1, r2, r3, r4, n; 7288 7289 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7290 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7291 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7292 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7293 r4 = MASK_OP_RRR1_D(ctx->opcode); 7294 n = MASK_OP_RRR1_N(ctx->opcode); 7295 7296 switch (op2) { 7297 case OPC2_32_RRR1_MSUB_H_LL: 7298 CHECK_REG_PAIR(r4); 7299 CHECK_REG_PAIR(r3); 7300 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7301 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7302 break; 7303 case OPC2_32_RRR1_MSUB_H_LU: 7304 CHECK_REG_PAIR(r4); 7305 CHECK_REG_PAIR(r3); 7306 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7307 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7308 break; 7309 case OPC2_32_RRR1_MSUB_H_UL: 7310 CHECK_REG_PAIR(r4); 7311 CHECK_REG_PAIR(r3); 7312 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7313 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7314 break; 7315 case OPC2_32_RRR1_MSUB_H_UU: 7316 CHECK_REG_PAIR(r4); 7317 CHECK_REG_PAIR(r3); 7318 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7319 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7320 break; 7321 case OPC2_32_RRR1_MSUBS_H_LL: 7322 CHECK_REG_PAIR(r4); 7323 CHECK_REG_PAIR(r3); 7324 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7325 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7326 break; 7327 case OPC2_32_RRR1_MSUBS_H_LU: 7328 CHECK_REG_PAIR(r4); 7329 CHECK_REG_PAIR(r3); 7330 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7331 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7332 break; 7333 case OPC2_32_RRR1_MSUBS_H_UL: 7334 CHECK_REG_PAIR(r4); 7335 CHECK_REG_PAIR(r3); 7336 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7337 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7338 break; 7339 case OPC2_32_RRR1_MSUBS_H_UU: 7340 CHECK_REG_PAIR(r4); 7341 CHECK_REG_PAIR(r3); 7342 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7343 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7344 break; 7345 case OPC2_32_RRR1_MSUBM_H_LL: 7346 CHECK_REG_PAIR(r4); 7347 CHECK_REG_PAIR(r3); 7348 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7349 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7350 break; 7351 case OPC2_32_RRR1_MSUBM_H_LU: 7352 CHECK_REG_PAIR(r4); 7353 CHECK_REG_PAIR(r3); 7354 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7355 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7356 break; 7357 case OPC2_32_RRR1_MSUBM_H_UL: 7358 CHECK_REG_PAIR(r4); 7359 CHECK_REG_PAIR(r3); 7360 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7361 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7362 break; 7363 case OPC2_32_RRR1_MSUBM_H_UU: 7364 CHECK_REG_PAIR(r4); 7365 CHECK_REG_PAIR(r3); 7366 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7367 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7368 break; 7369 case OPC2_32_RRR1_MSUBMS_H_LL: 7370 CHECK_REG_PAIR(r4); 7371 CHECK_REG_PAIR(r3); 7372 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7373 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7374 break; 7375 case OPC2_32_RRR1_MSUBMS_H_LU: 7376 CHECK_REG_PAIR(r4); 7377 CHECK_REG_PAIR(r3); 7378 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7379 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7380 break; 7381 case OPC2_32_RRR1_MSUBMS_H_UL: 7382 CHECK_REG_PAIR(r4); 7383 CHECK_REG_PAIR(r3); 7384 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7385 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7386 break; 7387 case OPC2_32_RRR1_MSUBMS_H_UU: 7388 CHECK_REG_PAIR(r4); 7389 CHECK_REG_PAIR(r3); 7390 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7391 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7392 break; 7393 case OPC2_32_RRR1_MSUBR_H_LL: 7394 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7395 cpu_gpr_d[r2], n, MODE_LL); 7396 break; 7397 case OPC2_32_RRR1_MSUBR_H_LU: 7398 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7399 cpu_gpr_d[r2], n, MODE_LU); 7400 break; 7401 case OPC2_32_RRR1_MSUBR_H_UL: 7402 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7403 cpu_gpr_d[r2], n, MODE_UL); 7404 break; 7405 case OPC2_32_RRR1_MSUBR_H_UU: 7406 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7407 cpu_gpr_d[r2], n, MODE_UU); 7408 break; 7409 case OPC2_32_RRR1_MSUBRS_H_LL: 7410 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7411 cpu_gpr_d[r2], n, MODE_LL); 7412 break; 7413 case OPC2_32_RRR1_MSUBRS_H_LU: 7414 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7415 cpu_gpr_d[r2], n, MODE_LU); 7416 break; 7417 case OPC2_32_RRR1_MSUBRS_H_UL: 7418 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7419 cpu_gpr_d[r2], n, MODE_UL); 7420 break; 7421 case OPC2_32_RRR1_MSUBRS_H_UU: 7422 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7423 cpu_gpr_d[r2], n, MODE_UU); 7424 break; 7425 default: 7426 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7427 } 7428 } 7429 7430 static void decode_rrr1_msubq_h(DisasContext *ctx) 7431 { 7432 uint32_t op2; 7433 uint32_t r1, r2, r3, r4, n; 7434 TCGv temp, temp2; 7435 7436 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7437 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7438 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7439 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7440 r4 = MASK_OP_RRR1_D(ctx->opcode); 7441 n = MASK_OP_RRR1_N(ctx->opcode); 7442 7443 temp = tcg_temp_new(); 7444 temp2 = tcg_temp_new(); 7445 7446 switch (op2) { 7447 case OPC2_32_RRR1_MSUB_Q_32: 7448 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7449 cpu_gpr_d[r2], n, 32); 7450 break; 7451 case OPC2_32_RRR1_MSUB_Q_64: 7452 CHECK_REG_PAIR(r4); 7453 CHECK_REG_PAIR(r3); 7454 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7455 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7456 n); 7457 break; 7458 case OPC2_32_RRR1_MSUB_Q_32_L: 7459 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7460 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7461 temp, n, 16); 7462 break; 7463 case OPC2_32_RRR1_MSUB_Q_64_L: 7464 CHECK_REG_PAIR(r4); 7465 CHECK_REG_PAIR(r3); 7466 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7467 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7468 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7469 n); 7470 break; 7471 case OPC2_32_RRR1_MSUB_Q_32_U: 7472 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7473 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7474 temp, n, 16); 7475 break; 7476 case OPC2_32_RRR1_MSUB_Q_64_U: 7477 CHECK_REG_PAIR(r4); 7478 CHECK_REG_PAIR(r3); 7479 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7480 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7481 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7482 n); 7483 break; 7484 case OPC2_32_RRR1_MSUB_Q_32_LL: 7485 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7486 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7487 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7488 break; 7489 case OPC2_32_RRR1_MSUB_Q_64_LL: 7490 CHECK_REG_PAIR(r4); 7491 CHECK_REG_PAIR(r3); 7492 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7493 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7494 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7495 cpu_gpr_d[r3+1], temp, temp2, n); 7496 break; 7497 case OPC2_32_RRR1_MSUB_Q_32_UU: 7498 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7499 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7500 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7501 break; 7502 case OPC2_32_RRR1_MSUB_Q_64_UU: 7503 CHECK_REG_PAIR(r4); 7504 CHECK_REG_PAIR(r3); 7505 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7506 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7507 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7508 cpu_gpr_d[r3+1], temp, temp2, n); 7509 break; 7510 case OPC2_32_RRR1_MSUBS_Q_32: 7511 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7512 cpu_gpr_d[r2], n, 32); 7513 break; 7514 case OPC2_32_RRR1_MSUBS_Q_64: 7515 CHECK_REG_PAIR(r4); 7516 CHECK_REG_PAIR(r3); 7517 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7518 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7519 n); 7520 break; 7521 case OPC2_32_RRR1_MSUBS_Q_32_L: 7522 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7523 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7524 temp, n, 16); 7525 break; 7526 case OPC2_32_RRR1_MSUBS_Q_64_L: 7527 CHECK_REG_PAIR(r4); 7528 CHECK_REG_PAIR(r3); 7529 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7530 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7531 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7532 n); 7533 break; 7534 case OPC2_32_RRR1_MSUBS_Q_32_U: 7535 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7536 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7537 temp, n, 16); 7538 break; 7539 case OPC2_32_RRR1_MSUBS_Q_64_U: 7540 CHECK_REG_PAIR(r4); 7541 CHECK_REG_PAIR(r3); 7542 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7543 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7544 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7545 n); 7546 break; 7547 case OPC2_32_RRR1_MSUBS_Q_32_LL: 7548 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7549 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7550 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7551 break; 7552 case OPC2_32_RRR1_MSUBS_Q_64_LL: 7553 CHECK_REG_PAIR(r4); 7554 CHECK_REG_PAIR(r3); 7555 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7556 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7557 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7558 cpu_gpr_d[r3+1], temp, temp2, n); 7559 break; 7560 case OPC2_32_RRR1_MSUBS_Q_32_UU: 7561 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7562 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7563 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7564 break; 7565 case OPC2_32_RRR1_MSUBS_Q_64_UU: 7566 CHECK_REG_PAIR(r4); 7567 CHECK_REG_PAIR(r3); 7568 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7569 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7570 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7571 cpu_gpr_d[r3+1], temp, temp2, n); 7572 break; 7573 case OPC2_32_RRR1_MSUBR_H_64_UL: 7574 CHECK_REG_PAIR(r3); 7575 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7576 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7577 break; 7578 case OPC2_32_RRR1_MSUBRS_H_64_UL: 7579 CHECK_REG_PAIR(r3); 7580 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7581 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7582 break; 7583 case OPC2_32_RRR1_MSUBR_Q_32_LL: 7584 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7585 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7586 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7587 break; 7588 case OPC2_32_RRR1_MSUBR_Q_32_UU: 7589 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7590 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7591 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7592 break; 7593 case OPC2_32_RRR1_MSUBRS_Q_32_LL: 7594 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7595 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7596 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7597 break; 7598 case OPC2_32_RRR1_MSUBRS_Q_32_UU: 7599 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7600 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7601 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7602 break; 7603 default: 7604 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7605 } 7606 } 7607 7608 static void decode_rrr1_msubad_h(DisasContext *ctx) 7609 { 7610 uint32_t op2; 7611 uint32_t r1, r2, r3, r4, n; 7612 7613 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7614 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7615 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7616 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7617 r4 = MASK_OP_RRR1_D(ctx->opcode); 7618 n = MASK_OP_RRR1_N(ctx->opcode); 7619 7620 switch (op2) { 7621 case OPC2_32_RRR1_MSUBAD_H_32_LL: 7622 CHECK_REG_PAIR(r4); 7623 CHECK_REG_PAIR(r3); 7624 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7625 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7626 break; 7627 case OPC2_32_RRR1_MSUBAD_H_32_LU: 7628 CHECK_REG_PAIR(r4); 7629 CHECK_REG_PAIR(r3); 7630 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7631 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7632 break; 7633 case OPC2_32_RRR1_MSUBAD_H_32_UL: 7634 CHECK_REG_PAIR(r4); 7635 CHECK_REG_PAIR(r3); 7636 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7637 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7638 break; 7639 case OPC2_32_RRR1_MSUBAD_H_32_UU: 7640 CHECK_REG_PAIR(r4); 7641 CHECK_REG_PAIR(r3); 7642 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7643 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7644 break; 7645 case OPC2_32_RRR1_MSUBADS_H_32_LL: 7646 CHECK_REG_PAIR(r4); 7647 CHECK_REG_PAIR(r3); 7648 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7649 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7650 n, MODE_LL); 7651 break; 7652 case OPC2_32_RRR1_MSUBADS_H_32_LU: 7653 CHECK_REG_PAIR(r4); 7654 CHECK_REG_PAIR(r3); 7655 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7656 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7657 n, MODE_LU); 7658 break; 7659 case OPC2_32_RRR1_MSUBADS_H_32_UL: 7660 CHECK_REG_PAIR(r4); 7661 CHECK_REG_PAIR(r3); 7662 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7663 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7664 n, MODE_UL); 7665 break; 7666 case OPC2_32_RRR1_MSUBADS_H_32_UU: 7667 CHECK_REG_PAIR(r4); 7668 CHECK_REG_PAIR(r3); 7669 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7670 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7671 n, MODE_UU); 7672 break; 7673 case OPC2_32_RRR1_MSUBADM_H_64_LL: 7674 CHECK_REG_PAIR(r4); 7675 CHECK_REG_PAIR(r3); 7676 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7677 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7678 n, MODE_LL); 7679 break; 7680 case OPC2_32_RRR1_MSUBADM_H_64_LU: 7681 CHECK_REG_PAIR(r4); 7682 CHECK_REG_PAIR(r3); 7683 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7684 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7685 n, MODE_LU); 7686 break; 7687 case OPC2_32_RRR1_MSUBADM_H_64_UL: 7688 CHECK_REG_PAIR(r4); 7689 CHECK_REG_PAIR(r3); 7690 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7691 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7692 n, MODE_UL); 7693 break; 7694 case OPC2_32_RRR1_MSUBADM_H_64_UU: 7695 CHECK_REG_PAIR(r4); 7696 CHECK_REG_PAIR(r3); 7697 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7698 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7699 n, MODE_UU); 7700 break; 7701 case OPC2_32_RRR1_MSUBADMS_H_64_LL: 7702 CHECK_REG_PAIR(r4); 7703 CHECK_REG_PAIR(r3); 7704 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7705 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7706 n, MODE_LL); 7707 break; 7708 case OPC2_32_RRR1_MSUBADMS_H_64_LU: 7709 CHECK_REG_PAIR(r4); 7710 CHECK_REG_PAIR(r3); 7711 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7712 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7713 n, MODE_LU); 7714 break; 7715 case OPC2_32_RRR1_MSUBADMS_H_64_UL: 7716 CHECK_REG_PAIR(r4); 7717 CHECK_REG_PAIR(r3); 7718 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7719 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7720 n, MODE_UL); 7721 break; 7722 case OPC2_32_RRR1_MSUBADMS_H_64_UU: 7723 CHECK_REG_PAIR(r4); 7724 CHECK_REG_PAIR(r3); 7725 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7726 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7727 n, MODE_UU); 7728 break; 7729 case OPC2_32_RRR1_MSUBADR_H_16_LL: 7730 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7731 cpu_gpr_d[r2], n, MODE_LL); 7732 break; 7733 case OPC2_32_RRR1_MSUBADR_H_16_LU: 7734 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7735 cpu_gpr_d[r2], n, MODE_LU); 7736 break; 7737 case OPC2_32_RRR1_MSUBADR_H_16_UL: 7738 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7739 cpu_gpr_d[r2], n, MODE_UL); 7740 break; 7741 case OPC2_32_RRR1_MSUBADR_H_16_UU: 7742 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7743 cpu_gpr_d[r2], n, MODE_UU); 7744 break; 7745 case OPC2_32_RRR1_MSUBADRS_H_16_LL: 7746 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7747 cpu_gpr_d[r2], n, MODE_LL); 7748 break; 7749 case OPC2_32_RRR1_MSUBADRS_H_16_LU: 7750 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7751 cpu_gpr_d[r2], n, MODE_LU); 7752 break; 7753 case OPC2_32_RRR1_MSUBADRS_H_16_UL: 7754 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7755 cpu_gpr_d[r2], n, MODE_UL); 7756 break; 7757 case OPC2_32_RRR1_MSUBADRS_H_16_UU: 7758 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7759 cpu_gpr_d[r2], n, MODE_UU); 7760 break; 7761 default: 7762 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7763 } 7764 } 7765 7766 /* RRRR format */ 7767 static void decode_rrrr_extract_insert(DisasContext *ctx) 7768 { 7769 uint32_t op2; 7770 int r1, r2, r3, r4; 7771 TCGv tmp_width, tmp_pos; 7772 7773 r1 = MASK_OP_RRRR_S1(ctx->opcode); 7774 r2 = MASK_OP_RRRR_S2(ctx->opcode); 7775 r3 = MASK_OP_RRRR_S3(ctx->opcode); 7776 r4 = MASK_OP_RRRR_D(ctx->opcode); 7777 op2 = MASK_OP_RRRR_OP2(ctx->opcode); 7778 7779 tmp_pos = tcg_temp_new(); 7780 tmp_width = tcg_temp_new(); 7781 7782 switch (op2) { 7783 case OPC2_32_RRRR_DEXTR: 7784 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7785 if (r1 == r2) { 7786 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7787 } else { 7788 TCGv msw = tcg_temp_new(); 7789 TCGv zero = tcg_constant_tl(0); 7790 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); 7791 tcg_gen_subfi_tl(msw, 32, tmp_pos); 7792 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw); 7793 /* 7794 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined 7795 * behaviour. So check that case here and set the low bits to zero 7796 * which effectivly returns cpu_gpr_d[r1] 7797 */ 7798 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); 7799 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); 7800 } 7801 break; 7802 case OPC2_32_RRRR_EXTR: 7803 case OPC2_32_RRRR_EXTR_U: 7804 CHECK_REG_PAIR(r3); 7805 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7806 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7807 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); 7808 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 7809 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7810 tcg_gen_subfi_tl(tmp_width, 32, tmp_width); 7811 if (op2 == OPC2_32_RRRR_EXTR) { 7812 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7813 } else { 7814 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7815 } 7816 break; 7817 case OPC2_32_RRRR_INSERT: 7818 CHECK_REG_PAIR(r3); 7819 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7820 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7821 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, 7822 tmp_pos); 7823 break; 7824 default: 7825 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7826 } 7827 } 7828 7829 /* RRRW format */ 7830 static void decode_rrrw_extract_insert(DisasContext *ctx) 7831 { 7832 uint32_t op2; 7833 int r1, r2, r3, r4; 7834 int32_t width; 7835 7836 TCGv temp, temp2; 7837 7838 op2 = MASK_OP_RRRW_OP2(ctx->opcode); 7839 r1 = MASK_OP_RRRW_S1(ctx->opcode); 7840 r2 = MASK_OP_RRRW_S2(ctx->opcode); 7841 r3 = MASK_OP_RRRW_S3(ctx->opcode); 7842 r4 = MASK_OP_RRRW_D(ctx->opcode); 7843 width = MASK_OP_RRRW_WIDTH(ctx->opcode); 7844 7845 temp = tcg_temp_new(); 7846 7847 switch (op2) { 7848 case OPC2_32_RRRW_EXTR: 7849 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7850 tcg_gen_addi_tl(temp, temp, width); 7851 tcg_gen_subfi_tl(temp, 32, temp); 7852 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7853 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); 7854 break; 7855 case OPC2_32_RRRW_EXTR_U: 7856 if (width == 0) { 7857 tcg_gen_movi_tl(cpu_gpr_d[r4], 0); 7858 } else { 7859 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7860 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7861 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); 7862 } 7863 break; 7864 case OPC2_32_RRRW_IMASK: 7865 temp2 = tcg_temp_new(); 7866 CHECK_REG_PAIR(r4); 7867 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7868 tcg_gen_movi_tl(temp2, (1 << width) - 1); 7869 tcg_gen_shl_tl(temp2, temp2, temp); 7870 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); 7871 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); 7872 break; 7873 case OPC2_32_RRRW_INSERT: 7874 temp2 = tcg_temp_new(); 7875 7876 tcg_gen_movi_tl(temp, width); 7877 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); 7878 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); 7879 break; 7880 default: 7881 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7882 } 7883 } 7884 7885 /* SYS Format*/ 7886 static void decode_sys_interrupts(DisasContext *ctx) 7887 { 7888 uint32_t op2; 7889 uint32_t r1; 7890 TCGLabel *l1; 7891 TCGv tmp; 7892 7893 op2 = MASK_OP_SYS_OP2(ctx->opcode); 7894 r1 = MASK_OP_SYS_S1D(ctx->opcode); 7895 7896 switch (op2) { 7897 case OPC2_32_SYS_DEBUG: 7898 /* raise EXCP_DEBUG */ 7899 break; 7900 case OPC2_32_SYS_DISABLE: 7901 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7902 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); 7903 } else { 7904 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7905 } 7906 break; 7907 case OPC2_32_SYS_DISABLE_D: 7908 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7909 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7910 tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, 7911 ctx->icr_ie_offset, 1); 7912 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); 7913 } else { 7914 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7915 } 7916 } else { 7917 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7918 } 7919 case OPC2_32_SYS_DSYNC: 7920 break; 7921 case OPC2_32_SYS_ENABLE: 7922 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7923 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask); 7924 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7925 } else { 7926 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7927 } 7928 break; 7929 case OPC2_32_SYS_ISYNC: 7930 break; 7931 case OPC2_32_SYS_NOP: 7932 break; 7933 case OPC2_32_SYS_RET: 7934 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 7935 break; 7936 case OPC2_32_SYS_FRET: 7937 gen_fret(ctx); 7938 break; 7939 case OPC2_32_SYS_RFE: 7940 gen_helper_rfe(cpu_env); 7941 ctx->base.is_jmp = DISAS_EXIT; 7942 break; 7943 case OPC2_32_SYS_RFM: 7944 if (ctx->priv == TRICORE_PRIV_SM) { 7945 tmp = tcg_temp_new(); 7946 l1 = gen_new_label(); 7947 7948 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR)); 7949 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); 7950 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); 7951 gen_helper_rfm(cpu_env); 7952 gen_set_label(l1); 7953 ctx->base.is_jmp = DISAS_EXIT; 7954 } else { 7955 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7956 } 7957 break; 7958 case OPC2_32_SYS_RSLCX: 7959 gen_helper_rslcx(cpu_env); 7960 break; 7961 case OPC2_32_SYS_SVLCX: 7962 gen_helper_svlcx(cpu_env); 7963 break; 7964 case OPC2_32_SYS_RESTORE: 7965 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7966 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { 7967 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 7968 ctx->icr_ie_offset, 1); 7969 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7970 } else { 7971 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); 7972 } 7973 } else { 7974 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7975 } 7976 break; 7977 case OPC2_32_SYS_TRAPSV: 7978 l1 = gen_new_label(); 7979 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); 7980 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); 7981 gen_set_label(l1); 7982 break; 7983 case OPC2_32_SYS_TRAPV: 7984 l1 = gen_new_label(); 7985 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); 7986 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); 7987 gen_set_label(l1); 7988 break; 7989 default: 7990 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7991 } 7992 } 7993 7994 static void decode_32Bit_opc(DisasContext *ctx) 7995 { 7996 int op1, op2; 7997 int32_t r1, r2, r3; 7998 int32_t address, const16; 7999 int8_t b, const4; 8000 int32_t bpos; 8001 TCGv temp, temp2, temp3; 8002 8003 op1 = MASK_OP_MAJOR(ctx->opcode); 8004 8005 /* handle JNZ.T opcode only being 7 bit long */ 8006 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { 8007 op1 = OPCM_32_BRN_JTT; 8008 } 8009 8010 switch (op1) { 8011 /* ABS-format */ 8012 case OPCM_32_ABS_LDW: 8013 decode_abs_ldw(ctx); 8014 break; 8015 case OPCM_32_ABS_LDB: 8016 decode_abs_ldb(ctx); 8017 break; 8018 case OPCM_32_ABS_LDMST_SWAP: 8019 decode_abs_ldst_swap(ctx); 8020 break; 8021 case OPCM_32_ABS_LDST_CONTEXT: 8022 decode_abs_ldst_context(ctx); 8023 break; 8024 case OPCM_32_ABS_STORE: 8025 decode_abs_store(ctx); 8026 break; 8027 case OPCM_32_ABS_STOREB_H: 8028 decode_abs_storeb_h(ctx); 8029 break; 8030 case OPC1_32_ABS_STOREQ: 8031 address = MASK_OP_ABS_OFF18(ctx->opcode); 8032 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8033 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8034 temp2 = tcg_temp_new(); 8035 8036 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); 8037 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); 8038 break; 8039 case OPC1_32_ABS_LD_Q: 8040 address = MASK_OP_ABS_OFF18(ctx->opcode); 8041 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8042 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8043 8044 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 8045 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 8046 break; 8047 case OPCM_32_ABS_LEA_LHA: 8048 address = MASK_OP_ABS_OFF18(ctx->opcode); 8049 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8050 8051 if (has_feature(ctx, TRICORE_FEATURE_162)) { 8052 op2 = MASK_OP_ABS_OP2(ctx->opcode); 8053 if (op2 == OPC2_32_ABS_LHA) { 8054 tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14); 8055 break; 8056 } 8057 /* otherwise translate regular LEA */ 8058 } 8059 8060 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); 8061 break; 8062 /* ABSB-format */ 8063 case OPC1_32_ABSB_ST_T: 8064 address = MASK_OP_ABS_OFF18(ctx->opcode); 8065 b = MASK_OP_ABSB_B(ctx->opcode); 8066 bpos = MASK_OP_ABSB_BPOS(ctx->opcode); 8067 8068 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 8069 temp2 = tcg_temp_new(); 8070 8071 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); 8072 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); 8073 tcg_gen_ori_tl(temp2, temp2, (b << bpos)); 8074 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); 8075 break; 8076 /* B-format */ 8077 case OPC1_32_B_CALL: 8078 case OPC1_32_B_CALLA: 8079 case OPC1_32_B_FCALL: 8080 case OPC1_32_B_FCALLA: 8081 case OPC1_32_B_J: 8082 case OPC1_32_B_JA: 8083 case OPC1_32_B_JL: 8084 case OPC1_32_B_JLA: 8085 address = MASK_OP_B_DISP24_SEXT(ctx->opcode); 8086 gen_compute_branch(ctx, op1, 0, 0, 0, address); 8087 break; 8088 /* Bit-format */ 8089 case OPCM_32_BIT_ANDACC: 8090 decode_bit_andacc(ctx); 8091 break; 8092 case OPCM_32_BIT_LOGICAL_T1: 8093 decode_bit_logical_t(ctx); 8094 break; 8095 case OPCM_32_BIT_INSERT: 8096 decode_bit_insert(ctx); 8097 break; 8098 case OPCM_32_BIT_LOGICAL_T2: 8099 decode_bit_logical_t2(ctx); 8100 break; 8101 case OPCM_32_BIT_ORAND: 8102 decode_bit_orand(ctx); 8103 break; 8104 case OPCM_32_BIT_SH_LOGIC1: 8105 decode_bit_sh_logic1(ctx); 8106 break; 8107 case OPCM_32_BIT_SH_LOGIC2: 8108 decode_bit_sh_logic2(ctx); 8109 break; 8110 /* BO Format */ 8111 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: 8112 decode_bo_addrmode_post_pre_base(ctx); 8113 break; 8114 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: 8115 decode_bo_addrmode_bitreverse_circular(ctx); 8116 break; 8117 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: 8118 decode_bo_addrmode_ld_post_pre_base(ctx); 8119 break; 8120 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: 8121 decode_bo_addrmode_ld_bitreverse_circular(ctx); 8122 break; 8123 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: 8124 decode_bo_addrmode_stctx_post_pre_base(ctx); 8125 break; 8126 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: 8127 decode_bo_addrmode_ldmst_bitreverse_circular(ctx); 8128 break; 8129 /* BOL-format */ 8130 case OPC1_32_BOL_LD_A_LONGOFF: 8131 case OPC1_32_BOL_LD_W_LONGOFF: 8132 case OPC1_32_BOL_LEA_LONGOFF: 8133 case OPC1_32_BOL_ST_W_LONGOFF: 8134 case OPC1_32_BOL_ST_A_LONGOFF: 8135 case OPC1_32_BOL_LD_B_LONGOFF: 8136 case OPC1_32_BOL_LD_BU_LONGOFF: 8137 case OPC1_32_BOL_LD_H_LONGOFF: 8138 case OPC1_32_BOL_LD_HU_LONGOFF: 8139 case OPC1_32_BOL_ST_B_LONGOFF: 8140 case OPC1_32_BOL_ST_H_LONGOFF: 8141 decode_bol_opc(ctx, op1); 8142 break; 8143 /* BRC Format */ 8144 case OPCM_32_BRC_EQ_NEQ: 8145 case OPCM_32_BRC_GE: 8146 case OPCM_32_BRC_JLT: 8147 case OPCM_32_BRC_JNE: 8148 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); 8149 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); 8150 r1 = MASK_OP_BRC_S1(ctx->opcode); 8151 gen_compute_branch(ctx, op1, r1, 0, const4, address); 8152 break; 8153 /* BRN Format */ 8154 case OPCM_32_BRN_JTT: 8155 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); 8156 r1 = MASK_OP_BRN_S1(ctx->opcode); 8157 gen_compute_branch(ctx, op1, r1, 0, 0, address); 8158 break; 8159 /* BRR Format */ 8160 case OPCM_32_BRR_EQ_NEQ: 8161 case OPCM_32_BRR_ADDR_EQ_NEQ: 8162 case OPCM_32_BRR_GE: 8163 case OPCM_32_BRR_JLT: 8164 case OPCM_32_BRR_JNE: 8165 case OPCM_32_BRR_JNZ: 8166 case OPCM_32_BRR_LOOP: 8167 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); 8168 r2 = MASK_OP_BRR_S2(ctx->opcode); 8169 r1 = MASK_OP_BRR_S1(ctx->opcode); 8170 gen_compute_branch(ctx, op1, r1, r2, 0, address); 8171 break; 8172 /* RC Format */ 8173 case OPCM_32_RC_LOGICAL_SHIFT: 8174 decode_rc_logical_shift(ctx); 8175 break; 8176 case OPCM_32_RC_ACCUMULATOR: 8177 decode_rc_accumulator(ctx); 8178 break; 8179 case OPCM_32_RC_SERVICEROUTINE: 8180 decode_rc_serviceroutine(ctx); 8181 break; 8182 case OPCM_32_RC_MUL: 8183 decode_rc_mul(ctx); 8184 break; 8185 /* RCPW Format */ 8186 case OPCM_32_RCPW_MASK_INSERT: 8187 decode_rcpw_insert(ctx); 8188 break; 8189 /* RCRR Format */ 8190 case OPC1_32_RCRR_INSERT: 8191 r1 = MASK_OP_RCRR_S1(ctx->opcode); 8192 r2 = MASK_OP_RCRR_S3(ctx->opcode); 8193 r3 = MASK_OP_RCRR_D(ctx->opcode); 8194 const16 = MASK_OP_RCRR_CONST4(ctx->opcode); 8195 temp = tcg_constant_i32(const16); 8196 temp2 = tcg_temp_new(); /* width*/ 8197 temp3 = tcg_temp_new(); /* pos */ 8198 8199 CHECK_REG_PAIR(r3); 8200 8201 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f); 8202 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 8203 8204 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); 8205 break; 8206 /* RCRW Format */ 8207 case OPCM_32_RCRW_MASK_INSERT: 8208 decode_rcrw_insert(ctx); 8209 break; 8210 /* RCR Format */ 8211 case OPCM_32_RCR_COND_SELECT: 8212 decode_rcr_cond_select(ctx); 8213 break; 8214 case OPCM_32_RCR_MADD: 8215 decode_rcr_madd(ctx); 8216 break; 8217 case OPCM_32_RCR_MSUB: 8218 decode_rcr_msub(ctx); 8219 break; 8220 /* RLC Format */ 8221 case OPC1_32_RLC_ADDI: 8222 case OPC1_32_RLC_ADDIH: 8223 case OPC1_32_RLC_ADDIH_A: 8224 case OPC1_32_RLC_MFCR: 8225 case OPC1_32_RLC_MOV: 8226 case OPC1_32_RLC_MOV_64: 8227 case OPC1_32_RLC_MOV_U: 8228 case OPC1_32_RLC_MOV_H: 8229 case OPC1_32_RLC_MOVH_A: 8230 case OPC1_32_RLC_MTCR: 8231 decode_rlc_opc(ctx, op1); 8232 break; 8233 /* RR Format */ 8234 case OPCM_32_RR_ACCUMULATOR: 8235 decode_rr_accumulator(ctx); 8236 break; 8237 case OPCM_32_RR_LOGICAL_SHIFT: 8238 decode_rr_logical_shift(ctx); 8239 break; 8240 case OPCM_32_RR_ADDRESS: 8241 decode_rr_address(ctx); 8242 break; 8243 case OPCM_32_RR_IDIRECT: 8244 decode_rr_idirect(ctx); 8245 break; 8246 case OPCM_32_RR_DIVIDE: 8247 decode_rr_divide(ctx); 8248 break; 8249 /* RR1 Format */ 8250 case OPCM_32_RR1_MUL: 8251 decode_rr1_mul(ctx); 8252 break; 8253 case OPCM_32_RR1_MULQ: 8254 decode_rr1_mulq(ctx); 8255 break; 8256 /* RR2 format */ 8257 case OPCM_32_RR2_MUL: 8258 decode_rr2_mul(ctx); 8259 break; 8260 /* RRPW format */ 8261 case OPCM_32_RRPW_EXTRACT_INSERT: 8262 decode_rrpw_extract_insert(ctx); 8263 break; 8264 case OPC1_32_RRPW_DEXTR: 8265 r1 = MASK_OP_RRPW_S1(ctx->opcode); 8266 r2 = MASK_OP_RRPW_S2(ctx->opcode); 8267 r3 = MASK_OP_RRPW_D(ctx->opcode); 8268 const16 = MASK_OP_RRPW_POS(ctx->opcode); 8269 8270 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1], 8271 32 - const16); 8272 break; 8273 /* RRR Format */ 8274 case OPCM_32_RRR_COND_SELECT: 8275 decode_rrr_cond_select(ctx); 8276 break; 8277 case OPCM_32_RRR_DIVIDE: 8278 decode_rrr_divide(ctx); 8279 break; 8280 /* RRR2 Format */ 8281 case OPCM_32_RRR2_MADD: 8282 decode_rrr2_madd(ctx); 8283 break; 8284 case OPCM_32_RRR2_MSUB: 8285 decode_rrr2_msub(ctx); 8286 break; 8287 /* RRR1 format */ 8288 case OPCM_32_RRR1_MADD: 8289 decode_rrr1_madd(ctx); 8290 break; 8291 case OPCM_32_RRR1_MADDQ_H: 8292 decode_rrr1_maddq_h(ctx); 8293 break; 8294 case OPCM_32_RRR1_MADDSU_H: 8295 decode_rrr1_maddsu_h(ctx); 8296 break; 8297 case OPCM_32_RRR1_MSUB_H: 8298 decode_rrr1_msub(ctx); 8299 break; 8300 case OPCM_32_RRR1_MSUB_Q: 8301 decode_rrr1_msubq_h(ctx); 8302 break; 8303 case OPCM_32_RRR1_MSUBAD_H: 8304 decode_rrr1_msubad_h(ctx); 8305 break; 8306 /* RRRR format */ 8307 case OPCM_32_RRRR_EXTRACT_INSERT: 8308 decode_rrrr_extract_insert(ctx); 8309 break; 8310 /* RRRW format */ 8311 case OPCM_32_RRRW_EXTRACT_INSERT: 8312 decode_rrrw_extract_insert(ctx); 8313 break; 8314 /* SYS format */ 8315 case OPCM_32_SYS_INTERRUPTS: 8316 decode_sys_interrupts(ctx); 8317 break; 8318 case OPC1_32_SYS_RSTV: 8319 tcg_gen_movi_tl(cpu_PSW_V, 0); 8320 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); 8321 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 8322 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); 8323 break; 8324 default: 8325 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8326 } 8327 } 8328 8329 static bool tricore_insn_is_16bit(uint32_t insn) 8330 { 8331 return (insn & 0x1) == 0; 8332 } 8333 8334 static void tricore_tr_init_disas_context(DisasContextBase *dcbase, 8335 CPUState *cs) 8336 { 8337 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8338 CPUTriCoreState *env = cs->env_ptr; 8339 ctx->mem_idx = cpu_mmu_index(env, false); 8340 8341 uint32_t tb_flags = (uint32_t)ctx->base.tb->flags; 8342 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 8343 8344 ctx->features = env->features; 8345 if (has_feature(ctx, TRICORE_FEATURE_161)) { 8346 ctx->icr_ie_mask = R_ICR_IE_161_MASK; 8347 ctx->icr_ie_offset = R_ICR_IE_161_SHIFT; 8348 } else { 8349 ctx->icr_ie_mask = R_ICR_IE_13_MASK; 8350 ctx->icr_ie_offset = R_ICR_IE_13_SHIFT; 8351 } 8352 } 8353 8354 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) 8355 { 8356 } 8357 8358 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 8359 { 8360 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8361 8362 tcg_gen_insn_start(ctx->base.pc_next); 8363 } 8364 8365 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) 8366 { 8367 /* 8368 * Return true if the insn at ctx->base.pc_next might cross a page boundary. 8369 * (False positives are OK, false negatives are not.) 8370 * Our caller ensures we are only called if dc->base.pc_next is less than 8371 * 4 bytes from the page boundary, so we cross the page if the first 8372 * 16 bits indicate that this is a 32 bit insn. 8373 */ 8374 uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next); 8375 8376 return !tricore_insn_is_16bit(insn); 8377 } 8378 8379 8380 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 8381 { 8382 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8383 CPUTriCoreState *env = cpu->env_ptr; 8384 uint16_t insn_lo; 8385 bool is_16bit; 8386 8387 insn_lo = cpu_lduw_code(env, ctx->base.pc_next); 8388 is_16bit = tricore_insn_is_16bit(insn_lo); 8389 if (is_16bit) { 8390 ctx->opcode = insn_lo; 8391 ctx->pc_succ_insn = ctx->base.pc_next + 2; 8392 decode_16Bit_opc(ctx); 8393 } else { 8394 uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2); 8395 ctx->opcode = insn_hi << 16 | insn_lo; 8396 ctx->pc_succ_insn = ctx->base.pc_next + 4; 8397 decode_32Bit_opc(ctx); 8398 } 8399 ctx->base.pc_next = ctx->pc_succ_insn; 8400 8401 if (ctx->base.is_jmp == DISAS_NEXT) { 8402 target_ulong page_start; 8403 8404 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 8405 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE 8406 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 8407 && insn_crosses_page(env, ctx))) { 8408 ctx->base.is_jmp = DISAS_TOO_MANY; 8409 } 8410 } 8411 } 8412 8413 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 8414 { 8415 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8416 8417 switch (ctx->base.is_jmp) { 8418 case DISAS_TOO_MANY: 8419 gen_goto_tb(ctx, 0, ctx->base.pc_next); 8420 break; 8421 case DISAS_EXIT_UPDATE: 8422 gen_save_pc(ctx->base.pc_next); 8423 /* fall through */ 8424 case DISAS_EXIT: 8425 tcg_gen_exit_tb(NULL, 0); 8426 break; 8427 case DISAS_JUMP: 8428 tcg_gen_lookup_and_goto_ptr(); 8429 break; 8430 case DISAS_NORETURN: 8431 break; 8432 default: 8433 g_assert_not_reached(); 8434 } 8435 } 8436 8437 static void tricore_tr_disas_log(const DisasContextBase *dcbase, 8438 CPUState *cpu, FILE *logfile) 8439 { 8440 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 8441 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 8442 } 8443 8444 static const TranslatorOps tricore_tr_ops = { 8445 .init_disas_context = tricore_tr_init_disas_context, 8446 .tb_start = tricore_tr_tb_start, 8447 .insn_start = tricore_tr_insn_start, 8448 .translate_insn = tricore_tr_translate_insn, 8449 .tb_stop = tricore_tr_tb_stop, 8450 .disas_log = tricore_tr_disas_log, 8451 }; 8452 8453 8454 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 8455 target_ulong pc, void *host_pc) 8456 { 8457 DisasContext ctx; 8458 translator_loop(cs, tb, max_insns, pc, host_pc, 8459 &tricore_tr_ops, &ctx.base); 8460 } 8461 8462 /* 8463 * 8464 * Initialization 8465 * 8466 */ 8467 8468 void cpu_state_reset(CPUTriCoreState *env) 8469 { 8470 /* Reset Regs to Default Value */ 8471 env->PSW = 0xb80; 8472 fpu_set_state(env); 8473 } 8474 8475 static void tricore_tcg_init_csfr(void) 8476 { 8477 cpu_PCXI = tcg_global_mem_new(cpu_env, 8478 offsetof(CPUTriCoreState, PCXI), "PCXI"); 8479 cpu_PSW = tcg_global_mem_new(cpu_env, 8480 offsetof(CPUTriCoreState, PSW), "PSW"); 8481 cpu_PC = tcg_global_mem_new(cpu_env, 8482 offsetof(CPUTriCoreState, PC), "PC"); 8483 cpu_ICR = tcg_global_mem_new(cpu_env, 8484 offsetof(CPUTriCoreState, ICR), "ICR"); 8485 } 8486 8487 void tricore_tcg_init(void) 8488 { 8489 int i; 8490 8491 /* reg init */ 8492 for (i = 0 ; i < 16 ; i++) { 8493 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, 8494 offsetof(CPUTriCoreState, gpr_a[i]), 8495 regnames_a[i]); 8496 } 8497 for (i = 0 ; i < 16 ; i++) { 8498 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env, 8499 offsetof(CPUTriCoreState, gpr_d[i]), 8500 regnames_d[i]); 8501 } 8502 tricore_tcg_init_csfr(); 8503 /* init PSW flag cache */ 8504 cpu_PSW_C = tcg_global_mem_new(cpu_env, 8505 offsetof(CPUTriCoreState, PSW_USB_C), 8506 "PSW_C"); 8507 cpu_PSW_V = tcg_global_mem_new(cpu_env, 8508 offsetof(CPUTriCoreState, PSW_USB_V), 8509 "PSW_V"); 8510 cpu_PSW_SV = tcg_global_mem_new(cpu_env, 8511 offsetof(CPUTriCoreState, PSW_USB_SV), 8512 "PSW_SV"); 8513 cpu_PSW_AV = tcg_global_mem_new(cpu_env, 8514 offsetof(CPUTriCoreState, PSW_USB_AV), 8515 "PSW_AV"); 8516 cpu_PSW_SAV = tcg_global_mem_new(cpu_env, 8517 offsetof(CPUTriCoreState, PSW_USB_SAV), 8518 "PSW_SAV"); 8519 } 8520