1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "disas/disas.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "exec/cpu_ldst.h" 27 #include "qemu/qemu-print.h" 28 29 #include "exec/helper-proto.h" 30 #include "exec/helper-gen.h" 31 32 #include "tricore-opcodes.h" 33 #include "exec/translator.h" 34 #include "exec/log.h" 35 36 /* 37 * TCG registers 38 */ 39 static TCGv cpu_PC; 40 static TCGv cpu_PCXI; 41 static TCGv cpu_PSW; 42 static TCGv cpu_ICR; 43 /* GPR registers */ 44 static TCGv cpu_gpr_a[16]; 45 static TCGv cpu_gpr_d[16]; 46 /* PSW Flag cache */ 47 static TCGv cpu_PSW_C; 48 static TCGv cpu_PSW_V; 49 static TCGv cpu_PSW_SV; 50 static TCGv cpu_PSW_AV; 51 static TCGv cpu_PSW_SAV; 52 53 #include "exec/gen-icount.h" 54 55 static const char *regnames_a[] = { 56 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , 57 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , 58 "a12" , "a13" , "a14" , "a15", 59 }; 60 61 static const char *regnames_d[] = { 62 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , 63 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , 64 "d12" , "d13" , "d14" , "d15", 65 }; 66 67 typedef struct DisasContext { 68 DisasContextBase base; 69 target_ulong pc_succ_insn; 70 uint32_t opcode; 71 /* Routine used to access memory */ 72 int mem_idx; 73 uint32_t hflags, saved_hflags; 74 uint64_t features; 75 } DisasContext; 76 77 static int has_feature(DisasContext *ctx, int feature) 78 { 79 return (ctx->features & (1ULL << feature)) != 0; 80 } 81 82 enum { 83 MODE_LL = 0, 84 MODE_LU = 1, 85 MODE_UL = 2, 86 MODE_UU = 3, 87 }; 88 89 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) 90 { 91 TriCoreCPU *cpu = TRICORE_CPU(cs); 92 CPUTriCoreState *env = &cpu->env; 93 uint32_t psw; 94 int i; 95 96 psw = psw_read(env); 97 98 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); 99 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); 100 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); 101 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); 102 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); 103 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); 104 105 for (i = 0; i < 16; ++i) { 106 if ((i & 3) == 0) { 107 qemu_fprintf(f, "\nGPR A%02d:", i); 108 } 109 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); 110 } 111 for (i = 0; i < 16; ++i) { 112 if ((i & 3) == 0) { 113 qemu_fprintf(f, "\nGPR D%02d:", i); 114 } 115 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); 116 } 117 qemu_fprintf(f, "\n"); 118 } 119 120 /* 121 * Functions to generate micro-ops 122 */ 123 124 /* Makros for generating helpers */ 125 126 #define gen_helper_1arg(name, arg) do { \ 127 TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ 128 gen_helper_##name(cpu_env, helper_tmp); \ 129 } while (0) 130 131 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ 132 TCGv arg00 = tcg_temp_new(); \ 133 TCGv arg01 = tcg_temp_new(); \ 134 TCGv arg11 = tcg_temp_new(); \ 135 tcg_gen_sari_tl(arg00, arg0, 16); \ 136 tcg_gen_ext16s_tl(arg01, arg0); \ 137 tcg_gen_ext16s_tl(arg11, arg1); \ 138 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 139 } while (0) 140 141 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ 142 TCGv arg00 = tcg_temp_new(); \ 143 TCGv arg01 = tcg_temp_new(); \ 144 TCGv arg10 = tcg_temp_new(); \ 145 TCGv arg11 = tcg_temp_new(); \ 146 tcg_gen_sari_tl(arg00, arg0, 16); \ 147 tcg_gen_ext16s_tl(arg01, arg0); \ 148 tcg_gen_sari_tl(arg11, arg1, 16); \ 149 tcg_gen_ext16s_tl(arg10, arg1); \ 150 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 151 } while (0) 152 153 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ 154 TCGv arg00 = tcg_temp_new(); \ 155 TCGv arg01 = tcg_temp_new(); \ 156 TCGv arg10 = tcg_temp_new(); \ 157 TCGv arg11 = tcg_temp_new(); \ 158 tcg_gen_sari_tl(arg00, arg0, 16); \ 159 tcg_gen_ext16s_tl(arg01, arg0); \ 160 tcg_gen_sari_tl(arg10, arg1, 16); \ 161 tcg_gen_ext16s_tl(arg11, arg1); \ 162 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 163 } while (0) 164 165 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ 166 TCGv arg00 = tcg_temp_new(); \ 167 TCGv arg01 = tcg_temp_new(); \ 168 TCGv arg11 = tcg_temp_new(); \ 169 tcg_gen_sari_tl(arg01, arg0, 16); \ 170 tcg_gen_ext16s_tl(arg00, arg0); \ 171 tcg_gen_sari_tl(arg11, arg1, 16); \ 172 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 173 } while (0) 174 175 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ 176 TCGv_i64 ret = tcg_temp_new_i64(); \ 177 TCGv_i64 arg1 = tcg_temp_new_i64(); \ 178 \ 179 tcg_gen_concat_i32_i64(arg1, al1, ah1); \ 180 gen_helper_##name(ret, arg1, arg2); \ 181 tcg_gen_extr_i64_i32(rl, rh, ret); \ 182 } while (0) 183 184 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ 185 TCGv_i64 ret = tcg_temp_new_i64(); \ 186 \ 187 gen_helper_##name(ret, cpu_env, arg1, arg2); \ 188 tcg_gen_extr_i64_i32(rl, rh, ret); \ 189 } while (0) 190 191 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) 192 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ 193 ((offset & 0x0fffff) << 1)) 194 195 /* For two 32-bit registers used a 64-bit register, the first 196 registernumber needs to be even. Otherwise we trap. */ 197 static inline void generate_trap(DisasContext *ctx, int class, int tin); 198 #define CHECK_REG_PAIR(reg) do { \ 199 if (reg & 0x1) { \ 200 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ 201 } \ 202 } while (0) 203 204 /* Functions for load/save to/from memory */ 205 206 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, 207 int16_t con, MemOp mop) 208 { 209 TCGv temp = tcg_temp_new(); 210 tcg_gen_addi_tl(temp, r2, con); 211 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 212 } 213 214 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, 215 int16_t con, MemOp mop) 216 { 217 TCGv temp = tcg_temp_new(); 218 tcg_gen_addi_tl(temp, r2, con); 219 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 220 } 221 222 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 223 { 224 TCGv_i64 temp = tcg_temp_new_i64(); 225 226 tcg_gen_concat_i32_i64(temp, rl, rh); 227 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); 228 } 229 230 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 231 DisasContext *ctx) 232 { 233 TCGv temp = tcg_temp_new(); 234 tcg_gen_addi_tl(temp, base, con); 235 gen_st_2regs_64(rh, rl, temp, ctx); 236 } 237 238 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 239 { 240 TCGv_i64 temp = tcg_temp_new_i64(); 241 242 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ); 243 /* write back to two 32 bit regs */ 244 tcg_gen_extr_i64_i32(rl, rh, temp); 245 } 246 247 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 248 DisasContext *ctx) 249 { 250 TCGv temp = tcg_temp_new(); 251 tcg_gen_addi_tl(temp, base, con); 252 gen_ld_2regs_64(rh, rl, temp, ctx); 253 } 254 255 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 256 MemOp mop) 257 { 258 TCGv temp = tcg_temp_new(); 259 tcg_gen_addi_tl(temp, r2, off); 260 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 261 tcg_gen_mov_tl(r2, temp); 262 } 263 264 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 265 MemOp mop) 266 { 267 TCGv temp = tcg_temp_new(); 268 tcg_gen_addi_tl(temp, r2, off); 269 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 270 tcg_gen_mov_tl(r2, temp); 271 } 272 273 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ 274 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) 275 { 276 TCGv temp = tcg_temp_new(); 277 TCGv temp2 = tcg_temp_new(); 278 279 CHECK_REG_PAIR(ereg); 280 /* temp = (M(EA, word) */ 281 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 282 /* temp = temp & ~E[a][63:32]) */ 283 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); 284 /* temp2 = (E[a][31:0] & E[a][63:32]); */ 285 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); 286 /* temp = temp | temp2; */ 287 tcg_gen_or_tl(temp, temp, temp2); 288 /* M(EA, word) = temp; */ 289 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); 290 } 291 292 /* tmp = M(EA, word); 293 M(EA, word) = D[a]; 294 D[a] = tmp[31:0];*/ 295 static void gen_swap(DisasContext *ctx, int reg, TCGv ea) 296 { 297 TCGv temp = tcg_temp_new(); 298 299 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 300 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); 301 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 302 } 303 304 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) 305 { 306 TCGv temp = tcg_temp_new(); 307 TCGv temp2 = tcg_temp_new(); 308 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 309 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, 310 cpu_gpr_d[reg], temp); 311 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 312 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 313 } 314 315 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) 316 { 317 TCGv temp = tcg_temp_new(); 318 TCGv temp2 = tcg_temp_new(); 319 TCGv temp3 = tcg_temp_new(); 320 321 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 322 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); 323 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); 324 tcg_gen_or_tl(temp2, temp2, temp3); 325 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 326 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 327 } 328 329 330 /* We generate loads and store to core special function register (csfr) through 331 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 332 makros R, A and E, which allow read-only, all and endinit protected access. 333 These makros also specify in which ISA version the csfr was introduced. */ 334 #define R(ADDRESS, REG, FEATURE) \ 335 case ADDRESS: \ 336 if (has_feature(ctx, FEATURE)) { \ 337 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ 338 } \ 339 break; 340 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 341 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 342 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) 343 { 344 /* since we're caching PSW make this a special case */ 345 if (offset == 0xfe04) { 346 gen_helper_psw_read(ret, cpu_env); 347 } else { 348 switch (offset) { 349 #include "csfr.h.inc" 350 } 351 } 352 } 353 #undef R 354 #undef A 355 #undef E 356 357 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, 358 since no execption occurs */ 359 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ 360 case ADDRESS: \ 361 if (has_feature(ctx, FEATURE)) { \ 362 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ 363 } \ 364 break; 365 /* Endinit protected registers 366 TODO: Since the endinit bit is in a register of a not yet implemented 367 watchdog device, we handle endinit protected registers like 368 all-access registers for now. */ 369 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) 370 static inline void gen_mtcr(DisasContext *ctx, TCGv r1, 371 int32_t offset) 372 { 373 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 374 /* since we're caching PSW make this a special case */ 375 if (offset == 0xfe04) { 376 gen_helper_psw_write(cpu_env, r1); 377 } else { 378 switch (offset) { 379 #include "csfr.h.inc" 380 } 381 } 382 } else { 383 /* generate privilege trap */ 384 } 385 } 386 387 /* Functions for arithmetic instructions */ 388 389 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) 390 { 391 TCGv t0 = tcg_temp_new_i32(); 392 TCGv result = tcg_temp_new_i32(); 393 /* Addition and set V/SV bits */ 394 tcg_gen_add_tl(result, r1, r2); 395 /* calc V bit */ 396 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 397 tcg_gen_xor_tl(t0, r1, r2); 398 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 399 /* Calc SV bit */ 400 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 401 /* Calc AV/SAV bits */ 402 tcg_gen_add_tl(cpu_PSW_AV, result, result); 403 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 404 /* calc SAV */ 405 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 406 /* write back result */ 407 tcg_gen_mov_tl(ret, result); 408 } 409 410 static inline void 411 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 412 { 413 TCGv temp = tcg_temp_new(); 414 TCGv_i64 t0 = tcg_temp_new_i64(); 415 TCGv_i64 t1 = tcg_temp_new_i64(); 416 TCGv_i64 result = tcg_temp_new_i64(); 417 418 tcg_gen_add_i64(result, r1, r2); 419 /* calc v bit */ 420 tcg_gen_xor_i64(t1, result, r1); 421 tcg_gen_xor_i64(t0, r1, r2); 422 tcg_gen_andc_i64(t1, t1, t0); 423 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 424 /* calc SV bit */ 425 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 426 /* calc AV/SAV bits */ 427 tcg_gen_extrh_i64_i32(temp, result); 428 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 429 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 430 /* calc SAV */ 431 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 432 /* write back result */ 433 tcg_gen_mov_i64(ret, result); 434 } 435 436 static inline void 437 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 438 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), 439 void(*op2)(TCGv, TCGv, TCGv)) 440 { 441 TCGv temp = tcg_temp_new(); 442 TCGv temp2 = tcg_temp_new(); 443 TCGv temp3 = tcg_temp_new(); 444 TCGv temp4 = tcg_temp_new(); 445 446 (*op1)(temp, r1_low, r2); 447 /* calc V0 bit */ 448 tcg_gen_xor_tl(temp2, temp, r1_low); 449 tcg_gen_xor_tl(temp3, r1_low, r2); 450 if (op1 == tcg_gen_add_tl) { 451 tcg_gen_andc_tl(temp2, temp2, temp3); 452 } else { 453 tcg_gen_and_tl(temp2, temp2, temp3); 454 } 455 456 (*op2)(temp3, r1_high, r3); 457 /* calc V1 bit */ 458 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); 459 tcg_gen_xor_tl(temp4, r1_high, r3); 460 if (op2 == tcg_gen_add_tl) { 461 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); 462 } else { 463 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); 464 } 465 /* combine V0/V1 bits */ 466 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); 467 /* calc sv bit */ 468 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 469 /* write result */ 470 tcg_gen_mov_tl(ret_low, temp); 471 tcg_gen_mov_tl(ret_high, temp3); 472 /* calc AV bit */ 473 tcg_gen_add_tl(temp, ret_low, ret_low); 474 tcg_gen_xor_tl(temp, temp, ret_low); 475 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 476 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); 477 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 478 /* calc SAV bit */ 479 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 480 } 481 482 /* ret = r2 + (r1 * r3); */ 483 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 484 { 485 TCGv_i64 t1 = tcg_temp_new_i64(); 486 TCGv_i64 t2 = tcg_temp_new_i64(); 487 TCGv_i64 t3 = tcg_temp_new_i64(); 488 489 tcg_gen_ext_i32_i64(t1, r1); 490 tcg_gen_ext_i32_i64(t2, r2); 491 tcg_gen_ext_i32_i64(t3, r3); 492 493 tcg_gen_mul_i64(t1, t1, t3); 494 tcg_gen_add_i64(t1, t2, t1); 495 496 tcg_gen_extrl_i64_i32(ret, t1); 497 /* calc V 498 t1 > 0x7fffffff */ 499 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 500 /* t1 < -0x80000000 */ 501 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 502 tcg_gen_or_i64(t2, t2, t3); 503 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 504 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 505 /* Calc SV bit */ 506 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 507 /* Calc AV/SAV bits */ 508 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 509 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 510 /* calc SAV */ 511 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 512 } 513 514 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 515 { 516 TCGv temp = tcg_constant_i32(con); 517 gen_madd32_d(ret, r1, r2, temp); 518 } 519 520 static inline void 521 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 522 TCGv r3) 523 { 524 TCGv t1 = tcg_temp_new(); 525 TCGv t2 = tcg_temp_new(); 526 TCGv t3 = tcg_temp_new(); 527 TCGv t4 = tcg_temp_new(); 528 529 tcg_gen_muls2_tl(t1, t2, r1, r3); 530 /* only the add can overflow */ 531 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); 532 /* calc V bit */ 533 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 534 tcg_gen_xor_tl(t1, r2_high, t2); 535 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); 536 /* Calc SV bit */ 537 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 538 /* Calc AV/SAV bits */ 539 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 540 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 541 /* calc SAV */ 542 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 543 /* write back the result */ 544 tcg_gen_mov_tl(ret_low, t3); 545 tcg_gen_mov_tl(ret_high, t4); 546 } 547 548 static inline void 549 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 550 TCGv r3) 551 { 552 TCGv_i64 t1 = tcg_temp_new_i64(); 553 TCGv_i64 t2 = tcg_temp_new_i64(); 554 TCGv_i64 t3 = tcg_temp_new_i64(); 555 556 tcg_gen_extu_i32_i64(t1, r1); 557 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 558 tcg_gen_extu_i32_i64(t3, r3); 559 560 tcg_gen_mul_i64(t1, t1, t3); 561 tcg_gen_add_i64(t2, t2, t1); 562 /* write back result */ 563 tcg_gen_extr_i64_i32(ret_low, ret_high, t2); 564 /* only the add overflows, if t2 < t1 565 calc V bit */ 566 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); 567 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 568 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 569 /* Calc SV bit */ 570 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 571 /* Calc AV/SAV bits */ 572 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 573 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 574 /* calc SAV */ 575 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 576 } 577 578 static inline void 579 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 580 int32_t con) 581 { 582 TCGv temp = tcg_constant_i32(con); 583 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 584 } 585 586 static inline void 587 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 588 int32_t con) 589 { 590 TCGv temp = tcg_constant_i32(con); 591 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 592 } 593 594 static inline void 595 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 596 TCGv r3, uint32_t n, uint32_t mode) 597 { 598 TCGv t_n = tcg_constant_i32(n); 599 TCGv temp = tcg_temp_new(); 600 TCGv temp2 = tcg_temp_new(); 601 TCGv_i64 temp64 = tcg_temp_new_i64(); 602 switch (mode) { 603 case MODE_LL: 604 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 605 break; 606 case MODE_LU: 607 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 608 break; 609 case MODE_UL: 610 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 611 break; 612 case MODE_UU: 613 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 614 break; 615 } 616 tcg_gen_extr_i64_i32(temp, temp2, temp64); 617 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 618 tcg_gen_add_tl, tcg_gen_add_tl); 619 } 620 621 static inline void 622 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 623 TCGv r3, uint32_t n, uint32_t mode) 624 { 625 TCGv t_n = tcg_constant_i32(n); 626 TCGv temp = tcg_temp_new(); 627 TCGv temp2 = tcg_temp_new(); 628 TCGv_i64 temp64 = tcg_temp_new_i64(); 629 switch (mode) { 630 case MODE_LL: 631 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 632 break; 633 case MODE_LU: 634 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 635 break; 636 case MODE_UL: 637 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 638 break; 639 case MODE_UU: 640 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 641 break; 642 } 643 tcg_gen_extr_i64_i32(temp, temp2, temp64); 644 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 645 tcg_gen_sub_tl, tcg_gen_add_tl); 646 } 647 648 static inline void 649 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 650 TCGv r3, uint32_t n, uint32_t mode) 651 { 652 TCGv t_n = tcg_constant_i32(n); 653 TCGv_i64 temp64 = tcg_temp_new_i64(); 654 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 655 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 656 switch (mode) { 657 case MODE_LL: 658 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 659 break; 660 case MODE_LU: 661 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 662 break; 663 case MODE_UL: 664 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 665 break; 666 case MODE_UU: 667 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 668 break; 669 } 670 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 671 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 672 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 673 tcg_gen_sub_i64(temp64, temp64_2, temp64); 674 tcg_gen_shli_i64(temp64, temp64, 16); 675 676 gen_add64_d(temp64_2, temp64_3, temp64); 677 /* write back result */ 678 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 679 } 680 681 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); 682 683 static inline void 684 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 685 TCGv r3, uint32_t n, uint32_t mode) 686 { 687 TCGv t_n = tcg_constant_i32(n); 688 TCGv temp = tcg_temp_new(); 689 TCGv temp2 = tcg_temp_new(); 690 TCGv temp3 = tcg_temp_new(); 691 TCGv_i64 temp64 = tcg_temp_new_i64(); 692 693 switch (mode) { 694 case MODE_LL: 695 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 696 break; 697 case MODE_LU: 698 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 699 break; 700 case MODE_UL: 701 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 702 break; 703 case MODE_UU: 704 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 705 break; 706 } 707 tcg_gen_extr_i64_i32(temp, temp2, temp64); 708 gen_adds(ret_low, r1_low, temp); 709 tcg_gen_mov_tl(temp, cpu_PSW_V); 710 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 711 gen_adds(ret_high, r1_high, temp2); 712 /* combine v bits */ 713 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 714 /* combine av bits */ 715 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 716 } 717 718 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); 719 720 static inline void 721 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 722 TCGv r3, uint32_t n, uint32_t mode) 723 { 724 TCGv t_n = tcg_constant_i32(n); 725 TCGv temp = tcg_temp_new(); 726 TCGv temp2 = tcg_temp_new(); 727 TCGv temp3 = tcg_temp_new(); 728 TCGv_i64 temp64 = tcg_temp_new_i64(); 729 730 switch (mode) { 731 case MODE_LL: 732 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 733 break; 734 case MODE_LU: 735 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 736 break; 737 case MODE_UL: 738 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 739 break; 740 case MODE_UU: 741 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 742 break; 743 } 744 tcg_gen_extr_i64_i32(temp, temp2, temp64); 745 gen_subs(ret_low, r1_low, temp); 746 tcg_gen_mov_tl(temp, cpu_PSW_V); 747 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 748 gen_adds(ret_high, r1_high, temp2); 749 /* combine v bits */ 750 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 751 /* combine av bits */ 752 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 753 } 754 755 static inline void 756 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 757 TCGv r3, uint32_t n, uint32_t mode) 758 { 759 TCGv t_n = tcg_constant_i32(n); 760 TCGv_i64 temp64 = tcg_temp_new_i64(); 761 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 762 763 switch (mode) { 764 case MODE_LL: 765 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 766 break; 767 case MODE_LU: 768 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 769 break; 770 case MODE_UL: 771 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 772 break; 773 case MODE_UU: 774 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 775 break; 776 } 777 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 778 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 779 tcg_gen_sub_i64(temp64, temp64_2, temp64); 780 tcg_gen_shli_i64(temp64, temp64, 16); 781 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 782 783 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 784 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 785 } 786 787 788 static inline void 789 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 790 TCGv r3, uint32_t n, uint32_t mode) 791 { 792 TCGv t_n = tcg_constant_i32(n); 793 TCGv_i64 temp64 = tcg_temp_new_i64(); 794 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 795 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 796 switch (mode) { 797 case MODE_LL: 798 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 799 break; 800 case MODE_LU: 801 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 802 break; 803 case MODE_UL: 804 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 805 break; 806 case MODE_UU: 807 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 808 break; 809 } 810 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 811 gen_add64_d(temp64_3, temp64_2, temp64); 812 /* write back result */ 813 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 814 } 815 816 static inline void 817 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 818 TCGv r3, uint32_t n, uint32_t mode) 819 { 820 TCGv t_n = tcg_constant_i32(n); 821 TCGv_i64 temp64 = tcg_temp_new_i64(); 822 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 823 switch (mode) { 824 case MODE_LL: 825 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 826 break; 827 case MODE_LU: 828 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 829 break; 830 case MODE_UL: 831 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 832 break; 833 case MODE_UU: 834 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 835 break; 836 } 837 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 838 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 839 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 840 } 841 842 static inline void 843 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 844 uint32_t mode) 845 { 846 TCGv t_n = tcg_constant_i32(n); 847 TCGv_i64 temp64 = tcg_temp_new_i64(); 848 switch (mode) { 849 case MODE_LL: 850 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 851 break; 852 case MODE_LU: 853 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 854 break; 855 case MODE_UL: 856 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 857 break; 858 case MODE_UU: 859 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 860 break; 861 } 862 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); 863 } 864 865 static inline void 866 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 867 { 868 TCGv temp = tcg_temp_new(); 869 TCGv temp2 = tcg_temp_new(); 870 871 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 872 tcg_gen_shli_tl(temp, r1, 16); 873 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); 874 } 875 876 static inline void 877 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 878 { 879 TCGv t_n = tcg_constant_i32(n); 880 TCGv temp = tcg_temp_new(); 881 TCGv temp2 = tcg_temp_new(); 882 TCGv_i64 temp64 = tcg_temp_new_i64(); 883 switch (mode) { 884 case MODE_LL: 885 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 886 break; 887 case MODE_LU: 888 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 889 break; 890 case MODE_UL: 891 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 892 break; 893 case MODE_UU: 894 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 895 break; 896 } 897 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 898 tcg_gen_shli_tl(temp, r1, 16); 899 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); 900 } 901 902 903 static inline void 904 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 905 uint32_t n, uint32_t mode) 906 { 907 TCGv t_n = tcg_constant_i32(n); 908 TCGv_i64 temp64 = tcg_temp_new_i64(); 909 switch (mode) { 910 case MODE_LL: 911 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 912 break; 913 case MODE_LU: 914 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 915 break; 916 case MODE_UL: 917 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 918 break; 919 case MODE_UU: 920 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 921 break; 922 } 923 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 924 } 925 926 static inline void 927 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 928 { 929 TCGv temp = tcg_temp_new(); 930 TCGv temp2 = tcg_temp_new(); 931 932 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 933 tcg_gen_shli_tl(temp, r1, 16); 934 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); 935 } 936 937 static inline void 938 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 939 { 940 TCGv t_n = tcg_constant_i32(n); 941 TCGv temp = tcg_temp_new(); 942 TCGv temp2 = tcg_temp_new(); 943 TCGv_i64 temp64 = tcg_temp_new_i64(); 944 switch (mode) { 945 case MODE_LL: 946 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 947 break; 948 case MODE_LU: 949 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 950 break; 951 case MODE_UL: 952 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 953 break; 954 case MODE_UU: 955 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 956 break; 957 } 958 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 959 tcg_gen_shli_tl(temp, r1, 16); 960 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); 961 } 962 963 static inline void 964 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 965 { 966 TCGv t_n = tcg_constant_i32(n); 967 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n); 968 } 969 970 static inline void 971 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 972 { 973 TCGv t_n = tcg_constant_i32(n); 974 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n); 975 } 976 977 static inline void 978 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 979 uint32_t up_shift) 980 { 981 TCGv temp = tcg_temp_new(); 982 TCGv temp2 = tcg_temp_new(); 983 TCGv temp3 = tcg_temp_new(); 984 TCGv_i64 t1 = tcg_temp_new_i64(); 985 TCGv_i64 t2 = tcg_temp_new_i64(); 986 TCGv_i64 t3 = tcg_temp_new_i64(); 987 988 tcg_gen_ext_i32_i64(t2, arg2); 989 tcg_gen_ext_i32_i64(t3, arg3); 990 991 tcg_gen_mul_i64(t2, t2, t3); 992 tcg_gen_shli_i64(t2, t2, n); 993 994 tcg_gen_ext_i32_i64(t1, arg1); 995 tcg_gen_sari_i64(t2, t2, up_shift); 996 997 tcg_gen_add_i64(t3, t1, t2); 998 tcg_gen_extrl_i64_i32(temp3, t3); 999 /* calc v bit */ 1000 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1001 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1002 tcg_gen_or_i64(t1, t1, t2); 1003 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1004 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1005 /* We produce an overflow on the host if the mul before was 1006 (0x80000000 * 0x80000000) << 1). If this is the 1007 case, we negate the ovf. */ 1008 if (n == 1) { 1009 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1010 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1011 tcg_gen_and_tl(temp, temp, temp2); 1012 tcg_gen_shli_tl(temp, temp, 31); 1013 /* negate v bit, if special condition */ 1014 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1015 } 1016 /* Calc SV bit */ 1017 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1018 /* Calc AV/SAV bits */ 1019 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1020 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1021 /* calc SAV */ 1022 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1023 /* write back result */ 1024 tcg_gen_mov_tl(ret, temp3); 1025 } 1026 1027 static inline void 1028 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1029 { 1030 TCGv temp = tcg_temp_new(); 1031 TCGv temp2 = tcg_temp_new(); 1032 if (n == 0) { 1033 tcg_gen_mul_tl(temp, arg2, arg3); 1034 } else { /* n is expected to be 1 */ 1035 tcg_gen_mul_tl(temp, arg2, arg3); 1036 tcg_gen_shli_tl(temp, temp, 1); 1037 /* catch special case r1 = r2 = 0x8000 */ 1038 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1039 tcg_gen_sub_tl(temp, temp, temp2); 1040 } 1041 gen_add_d(ret, arg1, temp); 1042 } 1043 1044 static inline void 1045 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1046 { 1047 TCGv temp = tcg_temp_new(); 1048 TCGv temp2 = tcg_temp_new(); 1049 if (n == 0) { 1050 tcg_gen_mul_tl(temp, arg2, arg3); 1051 } else { /* n is expected to be 1 */ 1052 tcg_gen_mul_tl(temp, arg2, arg3); 1053 tcg_gen_shli_tl(temp, temp, 1); 1054 /* catch special case r1 = r2 = 0x8000 */ 1055 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1056 tcg_gen_sub_tl(temp, temp, temp2); 1057 } 1058 gen_adds(ret, arg1, temp); 1059 } 1060 1061 static inline void 1062 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1063 TCGv arg3, uint32_t n) 1064 { 1065 TCGv temp = tcg_temp_new(); 1066 TCGv temp2 = tcg_temp_new(); 1067 TCGv_i64 t1 = tcg_temp_new_i64(); 1068 TCGv_i64 t2 = tcg_temp_new_i64(); 1069 TCGv_i64 t3 = tcg_temp_new_i64(); 1070 1071 if (n == 0) { 1072 tcg_gen_mul_tl(temp, arg2, arg3); 1073 } else { /* n is expected to be 1 */ 1074 tcg_gen_mul_tl(temp, arg2, arg3); 1075 tcg_gen_shli_tl(temp, temp, 1); 1076 /* catch special case r1 = r2 = 0x8000 */ 1077 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1078 tcg_gen_sub_tl(temp, temp, temp2); 1079 } 1080 tcg_gen_ext_i32_i64(t2, temp); 1081 tcg_gen_shli_i64(t2, t2, 16); 1082 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1083 gen_add64_d(t3, t1, t2); 1084 /* write back result */ 1085 tcg_gen_extr_i64_i32(rl, rh, t3); 1086 } 1087 1088 static inline void 1089 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1090 TCGv arg3, uint32_t n) 1091 { 1092 TCGv temp = tcg_temp_new(); 1093 TCGv temp2 = tcg_temp_new(); 1094 TCGv_i64 t1 = tcg_temp_new_i64(); 1095 TCGv_i64 t2 = tcg_temp_new_i64(); 1096 1097 if (n == 0) { 1098 tcg_gen_mul_tl(temp, arg2, arg3); 1099 } else { /* n is expected to be 1 */ 1100 tcg_gen_mul_tl(temp, arg2, arg3); 1101 tcg_gen_shli_tl(temp, temp, 1); 1102 /* catch special case r1 = r2 = 0x8000 */ 1103 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1104 tcg_gen_sub_tl(temp, temp, temp2); 1105 } 1106 tcg_gen_ext_i32_i64(t2, temp); 1107 tcg_gen_shli_i64(t2, t2, 16); 1108 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1109 1110 gen_helper_add64_ssov(t1, cpu_env, t1, t2); 1111 tcg_gen_extr_i64_i32(rl, rh, t1); 1112 } 1113 1114 static inline void 1115 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1116 TCGv arg3, uint32_t n) 1117 { 1118 TCGv_i64 t1 = tcg_temp_new_i64(); 1119 TCGv_i64 t2 = tcg_temp_new_i64(); 1120 TCGv_i64 t3 = tcg_temp_new_i64(); 1121 TCGv_i64 t4 = tcg_temp_new_i64(); 1122 TCGv temp, temp2; 1123 1124 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1125 tcg_gen_ext_i32_i64(t2, arg2); 1126 tcg_gen_ext_i32_i64(t3, arg3); 1127 1128 tcg_gen_mul_i64(t2, t2, t3); 1129 if (n != 0) { 1130 tcg_gen_shli_i64(t2, t2, 1); 1131 } 1132 tcg_gen_add_i64(t4, t1, t2); 1133 /* calc v bit */ 1134 tcg_gen_xor_i64(t3, t4, t1); 1135 tcg_gen_xor_i64(t2, t1, t2); 1136 tcg_gen_andc_i64(t3, t3, t2); 1137 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1138 /* We produce an overflow on the host if the mul before was 1139 (0x80000000 * 0x80000000) << 1). If this is the 1140 case, we negate the ovf. */ 1141 if (n == 1) { 1142 temp = tcg_temp_new(); 1143 temp2 = tcg_temp_new(); 1144 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1145 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1146 tcg_gen_and_tl(temp, temp, temp2); 1147 tcg_gen_shli_tl(temp, temp, 31); 1148 /* negate v bit, if special condition */ 1149 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1150 } 1151 /* write back result */ 1152 tcg_gen_extr_i64_i32(rl, rh, t4); 1153 /* Calc SV bit */ 1154 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1155 /* Calc AV/SAV bits */ 1156 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1157 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1158 /* calc SAV */ 1159 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1160 } 1161 1162 static inline void 1163 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1164 uint32_t up_shift) 1165 { 1166 TCGv_i64 t1 = tcg_temp_new_i64(); 1167 TCGv_i64 t2 = tcg_temp_new_i64(); 1168 TCGv_i64 t3 = tcg_temp_new_i64(); 1169 1170 tcg_gen_ext_i32_i64(t1, arg1); 1171 tcg_gen_ext_i32_i64(t2, arg2); 1172 tcg_gen_ext_i32_i64(t3, arg3); 1173 1174 tcg_gen_mul_i64(t2, t2, t3); 1175 tcg_gen_sari_i64(t2, t2, up_shift - n); 1176 1177 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); 1178 } 1179 1180 static inline void 1181 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1182 TCGv arg3, uint32_t n) 1183 { 1184 TCGv_i64 r1 = tcg_temp_new_i64(); 1185 TCGv t_n = tcg_constant_i32(n); 1186 1187 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1188 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); 1189 tcg_gen_extr_i64_i32(rl, rh, r1); 1190 } 1191 1192 /* ret = r2 - (r1 * r3); */ 1193 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 1194 { 1195 TCGv_i64 t1 = tcg_temp_new_i64(); 1196 TCGv_i64 t2 = tcg_temp_new_i64(); 1197 TCGv_i64 t3 = tcg_temp_new_i64(); 1198 1199 tcg_gen_ext_i32_i64(t1, r1); 1200 tcg_gen_ext_i32_i64(t2, r2); 1201 tcg_gen_ext_i32_i64(t3, r3); 1202 1203 tcg_gen_mul_i64(t1, t1, t3); 1204 tcg_gen_sub_i64(t1, t2, t1); 1205 1206 tcg_gen_extrl_i64_i32(ret, t1); 1207 /* calc V 1208 t2 > 0x7fffffff */ 1209 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 1210 /* result < -0x80000000 */ 1211 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 1212 tcg_gen_or_i64(t2, t2, t3); 1213 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 1214 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1215 1216 /* Calc SV bit */ 1217 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1218 /* Calc AV/SAV bits */ 1219 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 1220 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 1221 /* calc SAV */ 1222 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1223 } 1224 1225 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 1226 { 1227 TCGv temp = tcg_constant_i32(con); 1228 gen_msub32_d(ret, r1, r2, temp); 1229 } 1230 1231 static inline void 1232 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1233 TCGv r3) 1234 { 1235 TCGv t1 = tcg_temp_new(); 1236 TCGv t2 = tcg_temp_new(); 1237 TCGv t3 = tcg_temp_new(); 1238 TCGv t4 = tcg_temp_new(); 1239 1240 tcg_gen_muls2_tl(t1, t2, r1, r3); 1241 /* only the sub can overflow */ 1242 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); 1243 /* calc V bit */ 1244 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 1245 tcg_gen_xor_tl(t1, r2_high, t2); 1246 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); 1247 /* Calc SV bit */ 1248 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1249 /* Calc AV/SAV bits */ 1250 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 1251 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 1252 /* calc SAV */ 1253 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1254 /* write back the result */ 1255 tcg_gen_mov_tl(ret_low, t3); 1256 tcg_gen_mov_tl(ret_high, t4); 1257 } 1258 1259 static inline void 1260 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1261 int32_t con) 1262 { 1263 TCGv temp = tcg_constant_i32(con); 1264 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1265 } 1266 1267 static inline void 1268 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1269 TCGv r3) 1270 { 1271 TCGv_i64 t1 = tcg_temp_new_i64(); 1272 TCGv_i64 t2 = tcg_temp_new_i64(); 1273 TCGv_i64 t3 = tcg_temp_new_i64(); 1274 1275 tcg_gen_extu_i32_i64(t1, r1); 1276 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 1277 tcg_gen_extu_i32_i64(t3, r3); 1278 1279 tcg_gen_mul_i64(t1, t1, t3); 1280 tcg_gen_sub_i64(t3, t2, t1); 1281 tcg_gen_extr_i64_i32(ret_low, ret_high, t3); 1282 /* calc V bit, only the sub can overflow, if t1 > t2 */ 1283 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); 1284 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1285 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1286 /* Calc SV bit */ 1287 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1288 /* Calc AV/SAV bits */ 1289 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 1290 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 1291 /* calc SAV */ 1292 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1293 } 1294 1295 static inline void 1296 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1297 int32_t con) 1298 { 1299 TCGv temp = tcg_constant_i32(con); 1300 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1301 } 1302 1303 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) 1304 { 1305 TCGv temp = tcg_constant_i32(r2); 1306 gen_add_d(ret, r1, temp); 1307 } 1308 1309 /* calculate the carry bit too */ 1310 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) 1311 { 1312 TCGv t0 = tcg_temp_new_i32(); 1313 TCGv result = tcg_temp_new_i32(); 1314 1315 tcg_gen_movi_tl(t0, 0); 1316 /* Addition and set C/V/SV bits */ 1317 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); 1318 /* calc V bit */ 1319 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1320 tcg_gen_xor_tl(t0, r1, r2); 1321 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1322 /* Calc SV bit */ 1323 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1324 /* Calc AV/SAV bits */ 1325 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1326 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1327 /* calc SAV */ 1328 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1329 /* write back result */ 1330 tcg_gen_mov_tl(ret, result); 1331 } 1332 1333 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) 1334 { 1335 TCGv temp = tcg_constant_i32(con); 1336 gen_add_CC(ret, r1, temp); 1337 } 1338 1339 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) 1340 { 1341 TCGv carry = tcg_temp_new_i32(); 1342 TCGv t0 = tcg_temp_new_i32(); 1343 TCGv result = tcg_temp_new_i32(); 1344 1345 tcg_gen_movi_tl(t0, 0); 1346 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); 1347 /* Addition, carry and set C/V/SV bits */ 1348 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); 1349 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); 1350 /* calc V bit */ 1351 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1352 tcg_gen_xor_tl(t0, r1, r2); 1353 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1354 /* Calc SV bit */ 1355 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1356 /* Calc AV/SAV bits */ 1357 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1358 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1359 /* calc SAV */ 1360 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1361 /* write back result */ 1362 tcg_gen_mov_tl(ret, result); 1363 } 1364 1365 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) 1366 { 1367 TCGv temp = tcg_constant_i32(con); 1368 gen_addc_CC(ret, r1, temp); 1369 } 1370 1371 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1372 TCGv r4) 1373 { 1374 TCGv temp = tcg_temp_new(); 1375 TCGv temp2 = tcg_temp_new(); 1376 TCGv result = tcg_temp_new(); 1377 TCGv mask = tcg_temp_new(); 1378 TCGv t0 = tcg_constant_i32(0); 1379 1380 /* create mask for sticky bits */ 1381 tcg_gen_setcond_tl(cond, mask, r4, t0); 1382 tcg_gen_shli_tl(mask, mask, 31); 1383 1384 tcg_gen_add_tl(result, r1, r2); 1385 /* Calc PSW_V */ 1386 tcg_gen_xor_tl(temp, result, r1); 1387 tcg_gen_xor_tl(temp2, r1, r2); 1388 tcg_gen_andc_tl(temp, temp, temp2); 1389 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1390 /* Set PSW_SV */ 1391 tcg_gen_and_tl(temp, temp, mask); 1392 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1393 /* calc AV bit */ 1394 tcg_gen_add_tl(temp, result, result); 1395 tcg_gen_xor_tl(temp, temp, result); 1396 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1397 /* calc SAV bit */ 1398 tcg_gen_and_tl(temp, temp, mask); 1399 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1400 /* write back result */ 1401 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1402 } 1403 1404 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, 1405 TCGv r3, TCGv r4) 1406 { 1407 TCGv temp = tcg_constant_i32(r2); 1408 gen_cond_add(cond, r1, temp, r3, r4); 1409 } 1410 1411 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) 1412 { 1413 TCGv temp = tcg_temp_new_i32(); 1414 TCGv result = tcg_temp_new_i32(); 1415 1416 tcg_gen_sub_tl(result, r1, r2); 1417 /* calc V bit */ 1418 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1419 tcg_gen_xor_tl(temp, r1, r2); 1420 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1421 /* calc SV bit */ 1422 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1423 /* Calc AV bit */ 1424 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1425 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1426 /* calc SAV bit */ 1427 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1428 /* write back result */ 1429 tcg_gen_mov_tl(ret, result); 1430 } 1431 1432 static inline void 1433 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 1434 { 1435 TCGv temp = tcg_temp_new(); 1436 TCGv_i64 t0 = tcg_temp_new_i64(); 1437 TCGv_i64 t1 = tcg_temp_new_i64(); 1438 TCGv_i64 result = tcg_temp_new_i64(); 1439 1440 tcg_gen_sub_i64(result, r1, r2); 1441 /* calc v bit */ 1442 tcg_gen_xor_i64(t1, result, r1); 1443 tcg_gen_xor_i64(t0, r1, r2); 1444 tcg_gen_and_i64(t1, t1, t0); 1445 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 1446 /* calc SV bit */ 1447 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1448 /* calc AV/SAV bits */ 1449 tcg_gen_extrh_i64_i32(temp, result); 1450 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 1451 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 1452 /* calc SAV */ 1453 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1454 /* write back result */ 1455 tcg_gen_mov_i64(ret, result); 1456 } 1457 1458 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) 1459 { 1460 TCGv result = tcg_temp_new(); 1461 TCGv temp = tcg_temp_new(); 1462 1463 tcg_gen_sub_tl(result, r1, r2); 1464 /* calc C bit */ 1465 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); 1466 /* calc V bit */ 1467 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1468 tcg_gen_xor_tl(temp, r1, r2); 1469 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1470 /* calc SV bit */ 1471 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1472 /* Calc AV bit */ 1473 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1474 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1475 /* calc SAV bit */ 1476 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1477 /* write back result */ 1478 tcg_gen_mov_tl(ret, result); 1479 } 1480 1481 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) 1482 { 1483 TCGv temp = tcg_temp_new(); 1484 tcg_gen_not_tl(temp, r2); 1485 gen_addc_CC(ret, r1, temp); 1486 } 1487 1488 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1489 TCGv r4) 1490 { 1491 TCGv temp = tcg_temp_new(); 1492 TCGv temp2 = tcg_temp_new(); 1493 TCGv result = tcg_temp_new(); 1494 TCGv mask = tcg_temp_new(); 1495 TCGv t0 = tcg_constant_i32(0); 1496 1497 /* create mask for sticky bits */ 1498 tcg_gen_setcond_tl(cond, mask, r4, t0); 1499 tcg_gen_shli_tl(mask, mask, 31); 1500 1501 tcg_gen_sub_tl(result, r1, r2); 1502 /* Calc PSW_V */ 1503 tcg_gen_xor_tl(temp, result, r1); 1504 tcg_gen_xor_tl(temp2, r1, r2); 1505 tcg_gen_and_tl(temp, temp, temp2); 1506 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1507 /* Set PSW_SV */ 1508 tcg_gen_and_tl(temp, temp, mask); 1509 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1510 /* calc AV bit */ 1511 tcg_gen_add_tl(temp, result, result); 1512 tcg_gen_xor_tl(temp, temp, result); 1513 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1514 /* calc SAV bit */ 1515 tcg_gen_and_tl(temp, temp, mask); 1516 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1517 /* write back result */ 1518 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1519 } 1520 1521 static inline void 1522 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1523 TCGv r3, uint32_t n, uint32_t mode) 1524 { 1525 TCGv t_n = tcg_constant_i32(n); 1526 TCGv temp = tcg_temp_new(); 1527 TCGv temp2 = tcg_temp_new(); 1528 TCGv_i64 temp64 = tcg_temp_new_i64(); 1529 switch (mode) { 1530 case MODE_LL: 1531 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1532 break; 1533 case MODE_LU: 1534 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1535 break; 1536 case MODE_UL: 1537 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1538 break; 1539 case MODE_UU: 1540 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1541 break; 1542 } 1543 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1544 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1545 tcg_gen_sub_tl, tcg_gen_sub_tl); 1546 } 1547 1548 static inline void 1549 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1550 TCGv r3, uint32_t n, uint32_t mode) 1551 { 1552 TCGv t_n = tcg_constant_i32(n); 1553 TCGv temp = tcg_temp_new(); 1554 TCGv temp2 = tcg_temp_new(); 1555 TCGv temp3 = tcg_temp_new(); 1556 TCGv_i64 temp64 = tcg_temp_new_i64(); 1557 1558 switch (mode) { 1559 case MODE_LL: 1560 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1561 break; 1562 case MODE_LU: 1563 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1564 break; 1565 case MODE_UL: 1566 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1567 break; 1568 case MODE_UU: 1569 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1570 break; 1571 } 1572 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1573 gen_subs(ret_low, r1_low, temp); 1574 tcg_gen_mov_tl(temp, cpu_PSW_V); 1575 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 1576 gen_subs(ret_high, r1_high, temp2); 1577 /* combine v bits */ 1578 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 1579 /* combine av bits */ 1580 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 1581 } 1582 1583 static inline void 1584 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1585 TCGv r3, uint32_t n, uint32_t mode) 1586 { 1587 TCGv t_n = tcg_constant_i32(n); 1588 TCGv_i64 temp64 = tcg_temp_new_i64(); 1589 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1590 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1591 switch (mode) { 1592 case MODE_LL: 1593 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1594 break; 1595 case MODE_LU: 1596 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1597 break; 1598 case MODE_UL: 1599 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1600 break; 1601 case MODE_UU: 1602 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1603 break; 1604 } 1605 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1606 gen_sub64_d(temp64_3, temp64_2, temp64); 1607 /* write back result */ 1608 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 1609 } 1610 1611 static inline void 1612 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1613 TCGv r3, uint32_t n, uint32_t mode) 1614 { 1615 TCGv t_n = tcg_constant_i32(n); 1616 TCGv_i64 temp64 = tcg_temp_new_i64(); 1617 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1618 switch (mode) { 1619 case MODE_LL: 1620 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1621 break; 1622 case MODE_LU: 1623 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1624 break; 1625 case MODE_UL: 1626 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1627 break; 1628 case MODE_UU: 1629 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1630 break; 1631 } 1632 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1633 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 1634 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 1635 } 1636 1637 static inline void 1638 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 1639 uint32_t mode) 1640 { 1641 TCGv t_n = tcg_constant_i32(n); 1642 TCGv_i64 temp64 = tcg_temp_new_i64(); 1643 switch (mode) { 1644 case MODE_LL: 1645 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1646 break; 1647 case MODE_LU: 1648 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1649 break; 1650 case MODE_UL: 1651 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1652 break; 1653 case MODE_UU: 1654 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1655 break; 1656 } 1657 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); 1658 } 1659 1660 static inline void 1661 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1662 { 1663 TCGv temp = tcg_temp_new(); 1664 TCGv temp2 = tcg_temp_new(); 1665 1666 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1667 tcg_gen_shli_tl(temp, r1, 16); 1668 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); 1669 } 1670 1671 static inline void 1672 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1673 uint32_t n, uint32_t mode) 1674 { 1675 TCGv t_n = tcg_constant_i32(n); 1676 TCGv_i64 temp64 = tcg_temp_new_i64(); 1677 switch (mode) { 1678 case MODE_LL: 1679 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1680 break; 1681 case MODE_LU: 1682 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1683 break; 1684 case MODE_UL: 1685 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1686 break; 1687 case MODE_UU: 1688 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1689 break; 1690 } 1691 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 1692 } 1693 1694 static inline void 1695 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1696 { 1697 TCGv temp = tcg_temp_new(); 1698 TCGv temp2 = tcg_temp_new(); 1699 1700 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1701 tcg_gen_shli_tl(temp, r1, 16); 1702 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); 1703 } 1704 1705 static inline void 1706 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1707 { 1708 TCGv temp = tcg_constant_i32(n); 1709 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); 1710 } 1711 1712 static inline void 1713 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1714 { 1715 TCGv temp = tcg_constant_i32(n); 1716 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); 1717 } 1718 1719 static inline void 1720 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1721 uint32_t up_shift) 1722 { 1723 TCGv temp3 = tcg_temp_new(); 1724 TCGv_i64 t1 = tcg_temp_new_i64(); 1725 TCGv_i64 t2 = tcg_temp_new_i64(); 1726 TCGv_i64 t3 = tcg_temp_new_i64(); 1727 TCGv_i64 t4 = tcg_temp_new_i64(); 1728 1729 tcg_gen_ext_i32_i64(t2, arg2); 1730 tcg_gen_ext_i32_i64(t3, arg3); 1731 1732 tcg_gen_mul_i64(t2, t2, t3); 1733 1734 tcg_gen_ext_i32_i64(t1, arg1); 1735 /* if we shift part of the fraction out, we need to round up */ 1736 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1737 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1738 tcg_gen_sari_i64(t2, t2, up_shift - n); 1739 tcg_gen_add_i64(t2, t2, t4); 1740 1741 tcg_gen_sub_i64(t3, t1, t2); 1742 tcg_gen_extrl_i64_i32(temp3, t3); 1743 /* calc v bit */ 1744 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1745 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1746 tcg_gen_or_i64(t1, t1, t2); 1747 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1748 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1749 /* Calc SV bit */ 1750 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1751 /* Calc AV/SAV bits */ 1752 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1753 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1754 /* calc SAV */ 1755 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1756 /* write back result */ 1757 tcg_gen_mov_tl(ret, temp3); 1758 } 1759 1760 static inline void 1761 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1762 { 1763 TCGv temp = tcg_temp_new(); 1764 TCGv temp2 = tcg_temp_new(); 1765 if (n == 0) { 1766 tcg_gen_mul_tl(temp, arg2, arg3); 1767 } else { /* n is expected to be 1 */ 1768 tcg_gen_mul_tl(temp, arg2, arg3); 1769 tcg_gen_shli_tl(temp, temp, 1); 1770 /* catch special case r1 = r2 = 0x8000 */ 1771 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1772 tcg_gen_sub_tl(temp, temp, temp2); 1773 } 1774 gen_sub_d(ret, arg1, temp); 1775 } 1776 1777 static inline void 1778 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1779 { 1780 TCGv temp = tcg_temp_new(); 1781 TCGv temp2 = tcg_temp_new(); 1782 if (n == 0) { 1783 tcg_gen_mul_tl(temp, arg2, arg3); 1784 } else { /* n is expected to be 1 */ 1785 tcg_gen_mul_tl(temp, arg2, arg3); 1786 tcg_gen_shli_tl(temp, temp, 1); 1787 /* catch special case r1 = r2 = 0x8000 */ 1788 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1789 tcg_gen_sub_tl(temp, temp, temp2); 1790 } 1791 gen_subs(ret, arg1, temp); 1792 } 1793 1794 static inline void 1795 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1796 TCGv arg3, uint32_t n) 1797 { 1798 TCGv temp = tcg_temp_new(); 1799 TCGv temp2 = tcg_temp_new(); 1800 TCGv_i64 t1 = tcg_temp_new_i64(); 1801 TCGv_i64 t2 = tcg_temp_new_i64(); 1802 TCGv_i64 t3 = tcg_temp_new_i64(); 1803 1804 if (n == 0) { 1805 tcg_gen_mul_tl(temp, arg2, arg3); 1806 } else { /* n is expected to be 1 */ 1807 tcg_gen_mul_tl(temp, arg2, arg3); 1808 tcg_gen_shli_tl(temp, temp, 1); 1809 /* catch special case r1 = r2 = 0x8000 */ 1810 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1811 tcg_gen_sub_tl(temp, temp, temp2); 1812 } 1813 tcg_gen_ext_i32_i64(t2, temp); 1814 tcg_gen_shli_i64(t2, t2, 16); 1815 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1816 gen_sub64_d(t3, t1, t2); 1817 /* write back result */ 1818 tcg_gen_extr_i64_i32(rl, rh, t3); 1819 } 1820 1821 static inline void 1822 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1823 TCGv arg3, uint32_t n) 1824 { 1825 TCGv temp = tcg_temp_new(); 1826 TCGv temp2 = tcg_temp_new(); 1827 TCGv_i64 t1 = tcg_temp_new_i64(); 1828 TCGv_i64 t2 = tcg_temp_new_i64(); 1829 1830 if (n == 0) { 1831 tcg_gen_mul_tl(temp, arg2, arg3); 1832 } else { /* n is expected to be 1 */ 1833 tcg_gen_mul_tl(temp, arg2, arg3); 1834 tcg_gen_shli_tl(temp, temp, 1); 1835 /* catch special case r1 = r2 = 0x8000 */ 1836 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1837 tcg_gen_sub_tl(temp, temp, temp2); 1838 } 1839 tcg_gen_ext_i32_i64(t2, temp); 1840 tcg_gen_shli_i64(t2, t2, 16); 1841 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1842 1843 gen_helper_sub64_ssov(t1, cpu_env, t1, t2); 1844 tcg_gen_extr_i64_i32(rl, rh, t1); 1845 } 1846 1847 static inline void 1848 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1849 TCGv arg3, uint32_t n) 1850 { 1851 TCGv_i64 t1 = tcg_temp_new_i64(); 1852 TCGv_i64 t2 = tcg_temp_new_i64(); 1853 TCGv_i64 t3 = tcg_temp_new_i64(); 1854 TCGv_i64 t4 = tcg_temp_new_i64(); 1855 TCGv temp, temp2; 1856 1857 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1858 tcg_gen_ext_i32_i64(t2, arg2); 1859 tcg_gen_ext_i32_i64(t3, arg3); 1860 1861 tcg_gen_mul_i64(t2, t2, t3); 1862 if (n != 0) { 1863 tcg_gen_shli_i64(t2, t2, 1); 1864 } 1865 tcg_gen_sub_i64(t4, t1, t2); 1866 /* calc v bit */ 1867 tcg_gen_xor_i64(t3, t4, t1); 1868 tcg_gen_xor_i64(t2, t1, t2); 1869 tcg_gen_and_i64(t3, t3, t2); 1870 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1871 /* We produce an overflow on the host if the mul before was 1872 (0x80000000 * 0x80000000) << 1). If this is the 1873 case, we negate the ovf. */ 1874 if (n == 1) { 1875 temp = tcg_temp_new(); 1876 temp2 = tcg_temp_new(); 1877 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1878 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1879 tcg_gen_and_tl(temp, temp, temp2); 1880 tcg_gen_shli_tl(temp, temp, 31); 1881 /* negate v bit, if special condition */ 1882 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1883 } 1884 /* write back result */ 1885 tcg_gen_extr_i64_i32(rl, rh, t4); 1886 /* Calc SV bit */ 1887 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1888 /* Calc AV/SAV bits */ 1889 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1890 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1891 /* calc SAV */ 1892 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1893 } 1894 1895 static inline void 1896 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1897 uint32_t up_shift) 1898 { 1899 TCGv_i64 t1 = tcg_temp_new_i64(); 1900 TCGv_i64 t2 = tcg_temp_new_i64(); 1901 TCGv_i64 t3 = tcg_temp_new_i64(); 1902 TCGv_i64 t4 = tcg_temp_new_i64(); 1903 1904 tcg_gen_ext_i32_i64(t1, arg1); 1905 tcg_gen_ext_i32_i64(t2, arg2); 1906 tcg_gen_ext_i32_i64(t3, arg3); 1907 1908 tcg_gen_mul_i64(t2, t2, t3); 1909 /* if we shift part of the fraction out, we need to round up */ 1910 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1911 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1912 tcg_gen_sari_i64(t3, t2, up_shift - n); 1913 tcg_gen_add_i64(t3, t3, t4); 1914 1915 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); 1916 } 1917 1918 static inline void 1919 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1920 TCGv arg3, uint32_t n) 1921 { 1922 TCGv_i64 r1 = tcg_temp_new_i64(); 1923 TCGv t_n = tcg_constant_i32(n); 1924 1925 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1926 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); 1927 tcg_gen_extr_i64_i32(rl, rh, r1); 1928 } 1929 1930 static inline void 1931 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1932 TCGv r3, uint32_t n, uint32_t mode) 1933 { 1934 TCGv t_n = tcg_constant_i32(n); 1935 TCGv temp = tcg_temp_new(); 1936 TCGv temp2 = tcg_temp_new(); 1937 TCGv_i64 temp64 = tcg_temp_new_i64(); 1938 switch (mode) { 1939 case MODE_LL: 1940 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1941 break; 1942 case MODE_LU: 1943 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1944 break; 1945 case MODE_UL: 1946 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1947 break; 1948 case MODE_UU: 1949 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1950 break; 1951 } 1952 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1953 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1954 tcg_gen_add_tl, tcg_gen_sub_tl); 1955 } 1956 1957 static inline void 1958 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1959 TCGv r3, uint32_t n, uint32_t mode) 1960 { 1961 TCGv t_n = tcg_constant_i32(n); 1962 TCGv_i64 temp64 = tcg_temp_new_i64(); 1963 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1964 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1965 switch (mode) { 1966 case MODE_LL: 1967 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1968 break; 1969 case MODE_LU: 1970 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1971 break; 1972 case MODE_UL: 1973 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1974 break; 1975 case MODE_UU: 1976 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1977 break; 1978 } 1979 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 1980 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 1981 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 1982 tcg_gen_sub_i64(temp64, temp64_2, temp64); 1983 tcg_gen_shli_i64(temp64, temp64, 16); 1984 1985 gen_sub64_d(temp64_2, temp64_3, temp64); 1986 /* write back result */ 1987 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 1988 } 1989 1990 static inline void 1991 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1992 { 1993 TCGv t_n = tcg_constant_i32(n); 1994 TCGv temp = tcg_temp_new(); 1995 TCGv temp2 = tcg_temp_new(); 1996 TCGv_i64 temp64 = tcg_temp_new_i64(); 1997 switch (mode) { 1998 case MODE_LL: 1999 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2000 break; 2001 case MODE_LU: 2002 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2003 break; 2004 case MODE_UL: 2005 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2006 break; 2007 case MODE_UU: 2008 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2009 break; 2010 } 2011 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2012 tcg_gen_shli_tl(temp, r1, 16); 2013 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); 2014 } 2015 2016 static inline void 2017 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2018 TCGv r3, uint32_t n, uint32_t mode) 2019 { 2020 TCGv t_n = tcg_constant_i32(n); 2021 TCGv temp = tcg_temp_new(); 2022 TCGv temp2 = tcg_temp_new(); 2023 TCGv temp3 = tcg_temp_new(); 2024 TCGv_i64 temp64 = tcg_temp_new_i64(); 2025 2026 switch (mode) { 2027 case MODE_LL: 2028 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2029 break; 2030 case MODE_LU: 2031 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2032 break; 2033 case MODE_UL: 2034 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2035 break; 2036 case MODE_UU: 2037 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2038 break; 2039 } 2040 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2041 gen_adds(ret_low, r1_low, temp); 2042 tcg_gen_mov_tl(temp, cpu_PSW_V); 2043 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 2044 gen_subs(ret_high, r1_high, temp2); 2045 /* combine v bits */ 2046 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 2047 /* combine av bits */ 2048 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 2049 } 2050 2051 static inline void 2052 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2053 TCGv r3, uint32_t n, uint32_t mode) 2054 { 2055 TCGv t_n = tcg_constant_i32(n); 2056 TCGv_i64 temp64 = tcg_temp_new_i64(); 2057 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2058 2059 switch (mode) { 2060 case MODE_LL: 2061 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2062 break; 2063 case MODE_LU: 2064 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2065 break; 2066 case MODE_UL: 2067 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2068 break; 2069 case MODE_UU: 2070 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2071 break; 2072 } 2073 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2074 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2075 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2076 tcg_gen_shli_i64(temp64, temp64, 16); 2077 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 2078 2079 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 2080 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2081 } 2082 2083 static inline void 2084 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2085 { 2086 TCGv t_n = tcg_constant_i32(n); 2087 TCGv temp = tcg_temp_new(); 2088 TCGv temp2 = tcg_temp_new(); 2089 TCGv_i64 temp64 = tcg_temp_new_i64(); 2090 switch (mode) { 2091 case MODE_LL: 2092 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2093 break; 2094 case MODE_LU: 2095 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2096 break; 2097 case MODE_UL: 2098 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2099 break; 2100 case MODE_UU: 2101 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2102 break; 2103 } 2104 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2105 tcg_gen_shli_tl(temp, r1, 16); 2106 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); 2107 } 2108 2109 static inline void gen_abs(TCGv ret, TCGv r1) 2110 { 2111 tcg_gen_abs_tl(ret, r1); 2112 /* overflow can only happen, if r1 = 0x80000000 */ 2113 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); 2114 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2115 /* calc SV bit */ 2116 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2117 /* Calc AV bit */ 2118 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2119 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2120 /* calc SAV bit */ 2121 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2122 } 2123 2124 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) 2125 { 2126 TCGv temp = tcg_temp_new_i32(); 2127 TCGv result = tcg_temp_new_i32(); 2128 2129 tcg_gen_sub_tl(result, r1, r2); 2130 tcg_gen_sub_tl(temp, r2, r1); 2131 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); 2132 2133 /* calc V bit */ 2134 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 2135 tcg_gen_xor_tl(temp, result, r2); 2136 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); 2137 tcg_gen_xor_tl(temp, r1, r2); 2138 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 2139 /* calc SV bit */ 2140 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2141 /* Calc AV bit */ 2142 tcg_gen_add_tl(cpu_PSW_AV, result, result); 2143 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 2144 /* calc SAV bit */ 2145 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2146 /* write back result */ 2147 tcg_gen_mov_tl(ret, result); 2148 } 2149 2150 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) 2151 { 2152 TCGv temp = tcg_constant_i32(con); 2153 gen_absdif(ret, r1, temp); 2154 } 2155 2156 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) 2157 { 2158 TCGv temp = tcg_constant_i32(con); 2159 gen_helper_absdif_ssov(ret, cpu_env, r1, temp); 2160 } 2161 2162 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) 2163 { 2164 TCGv high = tcg_temp_new(); 2165 TCGv low = tcg_temp_new(); 2166 2167 tcg_gen_muls2_tl(low, high, r1, r2); 2168 tcg_gen_mov_tl(ret, low); 2169 /* calc V bit */ 2170 tcg_gen_sari_tl(low, low, 31); 2171 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); 2172 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2173 /* calc SV bit */ 2174 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2175 /* Calc AV bit */ 2176 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2177 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2178 /* calc SAV bit */ 2179 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2180 } 2181 2182 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) 2183 { 2184 TCGv temp = tcg_constant_i32(con); 2185 gen_mul_i32s(ret, r1, temp); 2186 } 2187 2188 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2189 { 2190 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); 2191 /* clear V bit */ 2192 tcg_gen_movi_tl(cpu_PSW_V, 0); 2193 /* calc SV bit */ 2194 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2195 /* Calc AV bit */ 2196 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2197 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2198 /* calc SAV bit */ 2199 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2200 } 2201 2202 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, 2203 int32_t con) 2204 { 2205 TCGv temp = tcg_constant_i32(con); 2206 gen_mul_i64s(ret_low, ret_high, r1, temp); 2207 } 2208 2209 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2210 { 2211 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); 2212 /* clear V bit */ 2213 tcg_gen_movi_tl(cpu_PSW_V, 0); 2214 /* calc SV bit */ 2215 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2216 /* Calc AV bit */ 2217 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2218 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2219 /* calc SAV bit */ 2220 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2221 } 2222 2223 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, 2224 int32_t con) 2225 { 2226 TCGv temp = tcg_constant_i32(con); 2227 gen_mul_i64u(ret_low, ret_high, r1, temp); 2228 } 2229 2230 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) 2231 { 2232 TCGv temp = tcg_constant_i32(con); 2233 gen_helper_mul_ssov(ret, cpu_env, r1, temp); 2234 } 2235 2236 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) 2237 { 2238 TCGv temp = tcg_constant_i32(con); 2239 gen_helper_mul_suov(ret, cpu_env, r1, temp); 2240 } 2241 2242 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ 2243 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2244 { 2245 TCGv temp = tcg_constant_i32(con); 2246 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); 2247 } 2248 2249 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2250 { 2251 TCGv temp = tcg_constant_i32(con); 2252 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); 2253 } 2254 2255 static void 2256 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) 2257 { 2258 TCGv_i64 temp_64 = tcg_temp_new_i64(); 2259 TCGv_i64 temp2_64 = tcg_temp_new_i64(); 2260 2261 if (n == 0) { 2262 if (up_shift == 32) { 2263 tcg_gen_muls2_tl(rh, rl, arg1, arg2); 2264 } else if (up_shift == 16) { 2265 tcg_gen_ext_i32_i64(temp_64, arg1); 2266 tcg_gen_ext_i32_i64(temp2_64, arg2); 2267 2268 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2269 tcg_gen_shri_i64(temp_64, temp_64, up_shift); 2270 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2271 } else { 2272 tcg_gen_muls2_tl(rl, rh, arg1, arg2); 2273 } 2274 /* reset v bit */ 2275 tcg_gen_movi_tl(cpu_PSW_V, 0); 2276 } else { /* n is expected to be 1 */ 2277 tcg_gen_ext_i32_i64(temp_64, arg1); 2278 tcg_gen_ext_i32_i64(temp2_64, arg2); 2279 2280 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2281 2282 if (up_shift == 0) { 2283 tcg_gen_shli_i64(temp_64, temp_64, 1); 2284 } else { 2285 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); 2286 } 2287 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2288 /* overflow only occurs if r1 = r2 = 0x8000 */ 2289 if (up_shift == 0) {/* result is 64 bit */ 2290 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, 2291 0x80000000); 2292 } else { /* result is 32 bit */ 2293 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, 2294 0x80000000); 2295 } 2296 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2297 /* calc sv overflow bit */ 2298 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2299 } 2300 /* calc av overflow bit */ 2301 if (up_shift == 0) { 2302 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2303 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2304 } else { 2305 tcg_gen_add_tl(cpu_PSW_AV, rl, rl); 2306 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); 2307 } 2308 /* calc sav overflow bit */ 2309 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2310 } 2311 2312 static void 2313 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2314 { 2315 TCGv temp = tcg_temp_new(); 2316 if (n == 0) { 2317 tcg_gen_mul_tl(ret, arg1, arg2); 2318 } else { /* n is expected to be 1 */ 2319 tcg_gen_mul_tl(ret, arg1, arg2); 2320 tcg_gen_shli_tl(ret, ret, 1); 2321 /* catch special case r1 = r2 = 0x8000 */ 2322 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); 2323 tcg_gen_sub_tl(ret, ret, temp); 2324 } 2325 /* reset v bit */ 2326 tcg_gen_movi_tl(cpu_PSW_V, 0); 2327 /* calc av overflow bit */ 2328 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2329 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2330 /* calc sav overflow bit */ 2331 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2332 } 2333 2334 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2335 { 2336 TCGv temp = tcg_temp_new(); 2337 if (n == 0) { 2338 tcg_gen_mul_tl(ret, arg1, arg2); 2339 tcg_gen_addi_tl(ret, ret, 0x8000); 2340 } else { 2341 tcg_gen_mul_tl(ret, arg1, arg2); 2342 tcg_gen_shli_tl(ret, ret, 1); 2343 tcg_gen_addi_tl(ret, ret, 0x8000); 2344 /* catch special case r1 = r2 = 0x8000 */ 2345 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); 2346 tcg_gen_muli_tl(temp, temp, 0x8001); 2347 tcg_gen_sub_tl(ret, ret, temp); 2348 } 2349 /* reset v bit */ 2350 tcg_gen_movi_tl(cpu_PSW_V, 0); 2351 /* calc av overflow bit */ 2352 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2353 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2354 /* calc sav overflow bit */ 2355 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2356 /* cut halfword off */ 2357 tcg_gen_andi_tl(ret, ret, 0xffff0000); 2358 } 2359 2360 static inline void 2361 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2362 TCGv r3) 2363 { 2364 TCGv_i64 temp64 = tcg_temp_new_i64(); 2365 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2366 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); 2367 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2368 } 2369 2370 static inline void 2371 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2372 int32_t con) 2373 { 2374 TCGv temp = tcg_constant_i32(con); 2375 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2376 } 2377 2378 static inline void 2379 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2380 TCGv r3) 2381 { 2382 TCGv_i64 temp64 = tcg_temp_new_i64(); 2383 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2384 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); 2385 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2386 } 2387 2388 static inline void 2389 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2390 int32_t con) 2391 { 2392 TCGv temp = tcg_constant_i32(con); 2393 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2394 } 2395 2396 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2397 { 2398 TCGv temp = tcg_constant_i32(con); 2399 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); 2400 } 2401 2402 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2403 { 2404 TCGv temp = tcg_constant_i32(con); 2405 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); 2406 } 2407 2408 static inline void 2409 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2410 TCGv r3) 2411 { 2412 TCGv_i64 temp64 = tcg_temp_new_i64(); 2413 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2414 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); 2415 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2416 } 2417 2418 static inline void 2419 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2420 int32_t con) 2421 { 2422 TCGv temp = tcg_constant_i32(con); 2423 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2424 } 2425 2426 static inline void 2427 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2428 TCGv r3) 2429 { 2430 TCGv_i64 temp64 = tcg_temp_new_i64(); 2431 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2432 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); 2433 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2434 } 2435 2436 static inline void 2437 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2438 int32_t con) 2439 { 2440 TCGv temp = tcg_constant_i32(con); 2441 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2442 } 2443 2444 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) 2445 { 2446 tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low)); 2447 tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up)); 2448 } 2449 2450 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) 2451 { 2452 tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up)); 2453 } 2454 2455 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) 2456 { 2457 if (shift_count == -32) { 2458 tcg_gen_movi_tl(ret, 0); 2459 } else if (shift_count >= 0) { 2460 tcg_gen_shli_tl(ret, r1, shift_count); 2461 } else { 2462 tcg_gen_shri_tl(ret, r1, -shift_count); 2463 } 2464 } 2465 2466 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) 2467 { 2468 TCGv temp_low, temp_high; 2469 2470 if (shiftcount == -16) { 2471 tcg_gen_movi_tl(ret, 0); 2472 } else { 2473 temp_high = tcg_temp_new(); 2474 temp_low = tcg_temp_new(); 2475 2476 tcg_gen_andi_tl(temp_low, r1, 0xffff); 2477 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); 2478 gen_shi(temp_low, temp_low, shiftcount); 2479 gen_shi(ret, temp_high, shiftcount); 2480 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); 2481 } 2482 } 2483 2484 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) 2485 { 2486 uint32_t msk, msk_start; 2487 TCGv temp = tcg_temp_new(); 2488 TCGv temp2 = tcg_temp_new(); 2489 2490 if (shift_count == 0) { 2491 /* Clear PSW.C and PSW.V */ 2492 tcg_gen_movi_tl(cpu_PSW_C, 0); 2493 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); 2494 tcg_gen_mov_tl(ret, r1); 2495 } else if (shift_count == -32) { 2496 /* set PSW.C */ 2497 tcg_gen_mov_tl(cpu_PSW_C, r1); 2498 /* fill ret completely with sign bit */ 2499 tcg_gen_sari_tl(ret, r1, 31); 2500 /* clear PSW.V */ 2501 tcg_gen_movi_tl(cpu_PSW_V, 0); 2502 } else if (shift_count > 0) { 2503 TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count); 2504 TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count); 2505 2506 /* calc carry */ 2507 msk_start = 32 - shift_count; 2508 msk = ((1 << shift_count) - 1) << msk_start; 2509 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2510 /* calc v/sv bits */ 2511 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); 2512 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); 2513 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 2514 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2515 /* calc sv */ 2516 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); 2517 /* do shift */ 2518 tcg_gen_shli_tl(ret, r1, shift_count); 2519 } else { 2520 /* clear PSW.V */ 2521 tcg_gen_movi_tl(cpu_PSW_V, 0); 2522 /* calc carry */ 2523 msk = (1 << -shift_count) - 1; 2524 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2525 /* do shift */ 2526 tcg_gen_sari_tl(ret, r1, -shift_count); 2527 } 2528 /* calc av overflow bit */ 2529 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2530 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2531 /* calc sav overflow bit */ 2532 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2533 } 2534 2535 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) 2536 { 2537 gen_helper_sha_ssov(ret, cpu_env, r1, r2); 2538 } 2539 2540 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) 2541 { 2542 TCGv temp = tcg_constant_i32(con); 2543 gen_shas(ret, r1, temp); 2544 } 2545 2546 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) 2547 { 2548 TCGv low, high; 2549 2550 if (shift_count == 0) { 2551 tcg_gen_mov_tl(ret, r1); 2552 } else if (shift_count > 0) { 2553 low = tcg_temp_new(); 2554 high = tcg_temp_new(); 2555 2556 tcg_gen_andi_tl(high, r1, 0xffff0000); 2557 tcg_gen_shli_tl(low, r1, shift_count); 2558 tcg_gen_shli_tl(ret, high, shift_count); 2559 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2560 } else { 2561 low = tcg_temp_new(); 2562 high = tcg_temp_new(); 2563 2564 tcg_gen_ext16s_tl(low, r1); 2565 tcg_gen_sari_tl(low, low, -shift_count); 2566 tcg_gen_sari_tl(ret, r1, -shift_count); 2567 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2568 } 2569 } 2570 2571 /* ret = {ret[30:0], (r1 cond r2)}; */ 2572 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) 2573 { 2574 TCGv temp = tcg_temp_new(); 2575 TCGv temp2 = tcg_temp_new(); 2576 2577 tcg_gen_shli_tl(temp, ret, 1); 2578 tcg_gen_setcond_tl(cond, temp2, r1, r2); 2579 tcg_gen_or_tl(ret, temp, temp2); 2580 } 2581 2582 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) 2583 { 2584 TCGv temp = tcg_constant_i32(con); 2585 gen_sh_cond(cond, ret, r1, temp); 2586 } 2587 2588 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) 2589 { 2590 gen_helper_add_ssov(ret, cpu_env, r1, r2); 2591 } 2592 2593 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) 2594 { 2595 TCGv temp = tcg_constant_i32(con); 2596 gen_helper_add_ssov(ret, cpu_env, r1, temp); 2597 } 2598 2599 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) 2600 { 2601 TCGv temp = tcg_constant_i32(con); 2602 gen_helper_add_suov(ret, cpu_env, r1, temp); 2603 } 2604 2605 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) 2606 { 2607 gen_helper_sub_ssov(ret, cpu_env, r1, r2); 2608 } 2609 2610 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) 2611 { 2612 gen_helper_sub_suov(ret, cpu_env, r1, r2); 2613 } 2614 2615 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, 2616 int pos1, int pos2, 2617 void(*op1)(TCGv, TCGv, TCGv), 2618 void(*op2)(TCGv, TCGv, TCGv)) 2619 { 2620 TCGv temp1, temp2; 2621 2622 temp1 = tcg_temp_new(); 2623 temp2 = tcg_temp_new(); 2624 2625 tcg_gen_shri_tl(temp2, r2, pos2); 2626 tcg_gen_shri_tl(temp1, r1, pos1); 2627 2628 (*op1)(temp1, temp1, temp2); 2629 (*op2)(temp1 , ret, temp1); 2630 2631 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); 2632 } 2633 2634 /* ret = r1[pos1] op1 r2[pos2]; */ 2635 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, 2636 int pos1, int pos2, 2637 void(*op1)(TCGv, TCGv, TCGv)) 2638 { 2639 TCGv temp1, temp2; 2640 2641 temp1 = tcg_temp_new(); 2642 temp2 = tcg_temp_new(); 2643 2644 tcg_gen_shri_tl(temp2, r2, pos2); 2645 tcg_gen_shri_tl(temp1, r1, pos1); 2646 2647 (*op1)(ret, temp1, temp2); 2648 2649 tcg_gen_andi_tl(ret, ret, 0x1); 2650 } 2651 2652 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, 2653 void(*op)(TCGv, TCGv, TCGv)) 2654 { 2655 TCGv temp = tcg_temp_new(); 2656 TCGv temp2 = tcg_temp_new(); 2657 /* temp = (arg1 cond arg2 )*/ 2658 tcg_gen_setcond_tl(cond, temp, r1, r2); 2659 /* temp2 = ret[0]*/ 2660 tcg_gen_andi_tl(temp2, ret, 0x1); 2661 /* temp = temp insn temp2 */ 2662 (*op)(temp, temp, temp2); 2663 /* ret = {ret[31:1], temp} */ 2664 tcg_gen_deposit_tl(ret, ret, temp, 0, 1); 2665 } 2666 2667 static inline void 2668 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, 2669 void(*op)(TCGv, TCGv, TCGv)) 2670 { 2671 TCGv temp = tcg_constant_i32(con); 2672 gen_accumulating_cond(cond, ret, r1, temp, op); 2673 } 2674 2675 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ 2676 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2) 2677 { 2678 tcg_gen_setcond_tl(cond, ret, r1, r2); 2679 tcg_gen_neg_tl(ret, ret); 2680 } 2681 2682 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) 2683 { 2684 TCGv b0 = tcg_temp_new(); 2685 TCGv b1 = tcg_temp_new(); 2686 TCGv b2 = tcg_temp_new(); 2687 TCGv b3 = tcg_temp_new(); 2688 2689 /* byte 0 */ 2690 tcg_gen_andi_tl(b0, r1, 0xff); 2691 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); 2692 2693 /* byte 1 */ 2694 tcg_gen_andi_tl(b1, r1, 0xff00); 2695 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); 2696 2697 /* byte 2 */ 2698 tcg_gen_andi_tl(b2, r1, 0xff0000); 2699 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); 2700 2701 /* byte 3 */ 2702 tcg_gen_andi_tl(b3, r1, 0xff000000); 2703 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); 2704 2705 /* combine them */ 2706 tcg_gen_or_tl(ret, b0, b1); 2707 tcg_gen_or_tl(ret, ret, b2); 2708 tcg_gen_or_tl(ret, ret, b3); 2709 } 2710 2711 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) 2712 { 2713 TCGv h0 = tcg_temp_new(); 2714 TCGv h1 = tcg_temp_new(); 2715 2716 /* halfword 0 */ 2717 tcg_gen_andi_tl(h0, r1, 0xffff); 2718 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); 2719 2720 /* halfword 1 */ 2721 tcg_gen_andi_tl(h1, r1, 0xffff0000); 2722 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); 2723 2724 /* combine them */ 2725 tcg_gen_or_tl(ret, h0, h1); 2726 } 2727 2728 /* mask = ((1 << width) -1) << pos; 2729 ret = (r1 & ~mask) | (r2 << pos) & mask); */ 2730 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) 2731 { 2732 TCGv mask = tcg_temp_new(); 2733 TCGv temp = tcg_temp_new(); 2734 TCGv temp2 = tcg_temp_new(); 2735 2736 tcg_gen_movi_tl(mask, 1); 2737 tcg_gen_shl_tl(mask, mask, width); 2738 tcg_gen_subi_tl(mask, mask, 1); 2739 tcg_gen_shl_tl(mask, mask, pos); 2740 2741 tcg_gen_shl_tl(temp, r2, pos); 2742 tcg_gen_and_tl(temp, temp, mask); 2743 tcg_gen_andc_tl(temp2, r1, mask); 2744 tcg_gen_or_tl(ret, temp, temp2); 2745 } 2746 2747 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) 2748 { 2749 TCGv_i64 temp = tcg_temp_new_i64(); 2750 2751 gen_helper_bsplit(temp, r1); 2752 tcg_gen_extr_i64_i32(rl, rh, temp); 2753 } 2754 2755 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) 2756 { 2757 TCGv_i64 temp = tcg_temp_new_i64(); 2758 2759 gen_helper_unpack(temp, r1); 2760 tcg_gen_extr_i64_i32(rl, rh, temp); 2761 } 2762 2763 static inline void 2764 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2765 { 2766 TCGv_i64 ret = tcg_temp_new_i64(); 2767 2768 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2769 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); 2770 } else { 2771 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); 2772 } 2773 tcg_gen_extr_i64_i32(rl, rh, ret); 2774 } 2775 2776 static inline void 2777 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2778 { 2779 TCGv_i64 ret = tcg_temp_new_i64(); 2780 2781 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2782 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); 2783 } else { 2784 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); 2785 } 2786 tcg_gen_extr_i64_i32(rl, rh, ret); 2787 } 2788 2789 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) 2790 { 2791 TCGv temp = tcg_temp_new(); 2792 /* calc AV bit */ 2793 tcg_gen_add_tl(temp, arg_low, arg_low); 2794 tcg_gen_xor_tl(temp, temp, arg_low); 2795 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); 2796 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); 2797 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2798 /* calc SAV bit */ 2799 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2800 tcg_gen_movi_tl(cpu_PSW_V, 0); 2801 } 2802 2803 static void gen_calc_usb_mulr_h(TCGv arg) 2804 { 2805 TCGv temp = tcg_temp_new(); 2806 /* calc AV bit */ 2807 tcg_gen_add_tl(temp, arg, arg); 2808 tcg_gen_xor_tl(temp, temp, arg); 2809 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); 2810 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2811 /* calc SAV bit */ 2812 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2813 /* clear V bit */ 2814 tcg_gen_movi_tl(cpu_PSW_V, 0); 2815 } 2816 2817 /* helpers for generating program flow micro-ops */ 2818 2819 static inline void gen_save_pc(target_ulong pc) 2820 { 2821 tcg_gen_movi_tl(cpu_PC, pc); 2822 } 2823 2824 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 2825 { 2826 if (translator_use_goto_tb(&ctx->base, dest)) { 2827 tcg_gen_goto_tb(n); 2828 gen_save_pc(dest); 2829 tcg_gen_exit_tb(ctx->base.tb, n); 2830 } else { 2831 gen_save_pc(dest); 2832 tcg_gen_lookup_and_goto_ptr(); 2833 } 2834 } 2835 2836 static void generate_trap(DisasContext *ctx, int class, int tin) 2837 { 2838 TCGv_i32 classtemp = tcg_constant_i32(class); 2839 TCGv_i32 tintemp = tcg_constant_i32(tin); 2840 2841 gen_save_pc(ctx->base.pc_next); 2842 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); 2843 ctx->base.is_jmp = DISAS_NORETURN; 2844 } 2845 2846 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, 2847 TCGv r2, int16_t address) 2848 { 2849 TCGLabel *jumpLabel = gen_new_label(); 2850 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); 2851 2852 gen_goto_tb(ctx, 1, ctx->pc_succ_insn); 2853 2854 gen_set_label(jumpLabel); 2855 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); 2856 } 2857 2858 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, 2859 int r2, int16_t address) 2860 { 2861 TCGv temp = tcg_constant_i32(r2); 2862 gen_branch_cond(ctx, cond, r1, temp, address); 2863 } 2864 2865 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) 2866 { 2867 TCGLabel *l1 = gen_new_label(); 2868 2869 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); 2870 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); 2871 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); 2872 gen_set_label(l1); 2873 gen_goto_tb(ctx, 0, ctx->pc_succ_insn); 2874 } 2875 2876 static void gen_fcall_save_ctx(DisasContext *ctx) 2877 { 2878 TCGv temp = tcg_temp_new(); 2879 2880 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); 2881 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); 2882 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 2883 tcg_gen_mov_tl(cpu_gpr_a[10], temp); 2884 } 2885 2886 static void gen_fret(DisasContext *ctx) 2887 { 2888 TCGv temp = tcg_temp_new(); 2889 2890 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); 2891 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); 2892 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); 2893 tcg_gen_mov_tl(cpu_PC, temp); 2894 tcg_gen_exit_tb(NULL, 0); 2895 ctx->base.is_jmp = DISAS_NORETURN; 2896 } 2897 2898 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 2899 int r2 , int32_t constant , int32_t offset) 2900 { 2901 TCGv temp, temp2; 2902 int n; 2903 2904 switch (opc) { 2905 /* SB-format jumps */ 2906 case OPC1_16_SB_J: 2907 case OPC1_32_B_J: 2908 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2909 break; 2910 case OPC1_32_B_CALL: 2911 case OPC1_16_SB_CALL: 2912 gen_helper_1arg(call, ctx->pc_succ_insn); 2913 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2914 break; 2915 case OPC1_16_SB_JZ: 2916 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); 2917 break; 2918 case OPC1_16_SB_JNZ: 2919 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); 2920 break; 2921 /* SBC-format jumps */ 2922 case OPC1_16_SBC_JEQ: 2923 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); 2924 break; 2925 case OPC1_16_SBC_JEQ2: 2926 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, 2927 offset + 16); 2928 break; 2929 case OPC1_16_SBC_JNE: 2930 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); 2931 break; 2932 case OPC1_16_SBC_JNE2: 2933 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 2934 constant, offset + 16); 2935 break; 2936 /* SBRN-format jumps */ 2937 case OPC1_16_SBRN_JZ_T: 2938 temp = tcg_temp_new(); 2939 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2940 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 2941 break; 2942 case OPC1_16_SBRN_JNZ_T: 2943 temp = tcg_temp_new(); 2944 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2945 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 2946 break; 2947 /* SBR-format jumps */ 2948 case OPC1_16_SBR_JEQ: 2949 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2950 offset); 2951 break; 2952 case OPC1_16_SBR_JEQ2: 2953 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2954 offset + 16); 2955 break; 2956 case OPC1_16_SBR_JNE: 2957 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2958 offset); 2959 break; 2960 case OPC1_16_SBR_JNE2: 2961 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2962 offset + 16); 2963 break; 2964 case OPC1_16_SBR_JNZ: 2965 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); 2966 break; 2967 case OPC1_16_SBR_JNZ_A: 2968 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 2969 break; 2970 case OPC1_16_SBR_JGEZ: 2971 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); 2972 break; 2973 case OPC1_16_SBR_JGTZ: 2974 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); 2975 break; 2976 case OPC1_16_SBR_JLEZ: 2977 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); 2978 break; 2979 case OPC1_16_SBR_JLTZ: 2980 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); 2981 break; 2982 case OPC1_16_SBR_JZ: 2983 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); 2984 break; 2985 case OPC1_16_SBR_JZ_A: 2986 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 2987 break; 2988 case OPC1_16_SBR_LOOP: 2989 gen_loop(ctx, r1, offset * 2 - 32); 2990 break; 2991 /* SR-format jumps */ 2992 case OPC1_16_SR_JI: 2993 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); 2994 tcg_gen_exit_tb(NULL, 0); 2995 break; 2996 case OPC2_32_SYS_RET: 2997 case OPC2_16_SR_RET: 2998 gen_helper_ret(cpu_env); 2999 tcg_gen_exit_tb(NULL, 0); 3000 break; 3001 /* B-format */ 3002 case OPC1_32_B_CALLA: 3003 gen_helper_1arg(call, ctx->pc_succ_insn); 3004 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3005 break; 3006 case OPC1_32_B_FCALL: 3007 gen_fcall_save_ctx(ctx); 3008 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3009 break; 3010 case OPC1_32_B_FCALLA: 3011 gen_fcall_save_ctx(ctx); 3012 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3013 break; 3014 case OPC1_32_B_JLA: 3015 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3016 /* fall through */ 3017 case OPC1_32_B_JA: 3018 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3019 break; 3020 case OPC1_32_B_JL: 3021 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3022 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3023 break; 3024 /* BOL format */ 3025 case OPCM_32_BRC_EQ_NEQ: 3026 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { 3027 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); 3028 } else { 3029 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); 3030 } 3031 break; 3032 case OPCM_32_BRC_GE: 3033 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { 3034 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); 3035 } else { 3036 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3037 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, 3038 offset); 3039 } 3040 break; 3041 case OPCM_32_BRC_JLT: 3042 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { 3043 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); 3044 } else { 3045 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3046 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, 3047 offset); 3048 } 3049 break; 3050 case OPCM_32_BRC_JNE: 3051 temp = tcg_temp_new(); 3052 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { 3053 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3054 /* subi is unconditional */ 3055 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3056 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3057 } else { 3058 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3059 /* addi is unconditional */ 3060 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3061 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3062 } 3063 break; 3064 /* BRN format */ 3065 case OPCM_32_BRN_JTT: 3066 n = MASK_OP_BRN_N(ctx->opcode); 3067 3068 temp = tcg_temp_new(); 3069 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); 3070 3071 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { 3072 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3073 } else { 3074 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3075 } 3076 break; 3077 /* BRR Format */ 3078 case OPCM_32_BRR_EQ_NEQ: 3079 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { 3080 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], 3081 offset); 3082 } else { 3083 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3084 offset); 3085 } 3086 break; 3087 case OPCM_32_BRR_ADDR_EQ_NEQ: 3088 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { 3089 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], 3090 offset); 3091 } else { 3092 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], 3093 offset); 3094 } 3095 break; 3096 case OPCM_32_BRR_GE: 3097 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { 3098 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3099 offset); 3100 } else { 3101 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3102 offset); 3103 } 3104 break; 3105 case OPCM_32_BRR_JLT: 3106 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { 3107 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], 3108 offset); 3109 } else { 3110 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3111 offset); 3112 } 3113 break; 3114 case OPCM_32_BRR_LOOP: 3115 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { 3116 gen_loop(ctx, r2, offset * 2); 3117 } else { 3118 /* OPC2_32_BRR_LOOPU */ 3119 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3120 } 3121 break; 3122 case OPCM_32_BRR_JNE: 3123 temp = tcg_temp_new(); 3124 temp2 = tcg_temp_new(); 3125 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { 3126 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3127 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3128 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3129 /* subi is unconditional */ 3130 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3131 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3132 } else { 3133 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3134 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3135 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3136 /* addi is unconditional */ 3137 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3138 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3139 } 3140 break; 3141 case OPCM_32_BRR_JNZ: 3142 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { 3143 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3144 } else { 3145 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3146 } 3147 break; 3148 default: 3149 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3150 } 3151 ctx->base.is_jmp = DISAS_NORETURN; 3152 } 3153 3154 3155 /* 3156 * Functions for decoding instructions 3157 */ 3158 3159 static void decode_src_opc(DisasContext *ctx, int op1) 3160 { 3161 int r1; 3162 int32_t const4; 3163 TCGv temp, temp2; 3164 3165 r1 = MASK_OP_SRC_S1D(ctx->opcode); 3166 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); 3167 3168 switch (op1) { 3169 case OPC1_16_SRC_ADD: 3170 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3171 break; 3172 case OPC1_16_SRC_ADD_A15: 3173 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); 3174 break; 3175 case OPC1_16_SRC_ADD_15A: 3176 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); 3177 break; 3178 case OPC1_16_SRC_ADD_A: 3179 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); 3180 break; 3181 case OPC1_16_SRC_CADD: 3182 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3183 cpu_gpr_d[15]); 3184 break; 3185 case OPC1_16_SRC_CADDN: 3186 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3187 cpu_gpr_d[15]); 3188 break; 3189 case OPC1_16_SRC_CMOV: 3190 temp = tcg_constant_tl(0); 3191 temp2 = tcg_constant_tl(const4); 3192 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3193 temp2, cpu_gpr_d[r1]); 3194 break; 3195 case OPC1_16_SRC_CMOVN: 3196 temp = tcg_constant_tl(0); 3197 temp2 = tcg_constant_tl(const4); 3198 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3199 temp2, cpu_gpr_d[r1]); 3200 break; 3201 case OPC1_16_SRC_EQ: 3202 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3203 const4); 3204 break; 3205 case OPC1_16_SRC_LT: 3206 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3207 const4); 3208 break; 3209 case OPC1_16_SRC_MOV: 3210 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3211 break; 3212 case OPC1_16_SRC_MOV_A: 3213 const4 = MASK_OP_SRC_CONST4(ctx->opcode); 3214 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); 3215 break; 3216 case OPC1_16_SRC_MOV_E: 3217 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3218 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3219 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); 3220 } else { 3221 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3222 } 3223 break; 3224 case OPC1_16_SRC_SH: 3225 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3226 break; 3227 case OPC1_16_SRC_SHA: 3228 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3229 break; 3230 default: 3231 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3232 } 3233 } 3234 3235 static void decode_srr_opc(DisasContext *ctx, int op1) 3236 { 3237 int r1, r2; 3238 TCGv temp; 3239 3240 r1 = MASK_OP_SRR_S1D(ctx->opcode); 3241 r2 = MASK_OP_SRR_S2(ctx->opcode); 3242 3243 switch (op1) { 3244 case OPC1_16_SRR_ADD: 3245 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3246 break; 3247 case OPC1_16_SRR_ADD_A15: 3248 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3249 break; 3250 case OPC1_16_SRR_ADD_15A: 3251 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3252 break; 3253 case OPC1_16_SRR_ADD_A: 3254 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); 3255 break; 3256 case OPC1_16_SRR_ADDS: 3257 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3258 break; 3259 case OPC1_16_SRR_AND: 3260 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3261 break; 3262 case OPC1_16_SRR_CMOV: 3263 temp = tcg_constant_tl(0); 3264 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3265 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3266 break; 3267 case OPC1_16_SRR_CMOVN: 3268 temp = tcg_constant_tl(0); 3269 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3270 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3271 break; 3272 case OPC1_16_SRR_EQ: 3273 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3274 cpu_gpr_d[r2]); 3275 break; 3276 case OPC1_16_SRR_LT: 3277 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3278 cpu_gpr_d[r2]); 3279 break; 3280 case OPC1_16_SRR_MOV: 3281 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); 3282 break; 3283 case OPC1_16_SRR_MOV_A: 3284 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); 3285 break; 3286 case OPC1_16_SRR_MOV_AA: 3287 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); 3288 break; 3289 case OPC1_16_SRR_MOV_D: 3290 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); 3291 break; 3292 case OPC1_16_SRR_MUL: 3293 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3294 break; 3295 case OPC1_16_SRR_OR: 3296 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3297 break; 3298 case OPC1_16_SRR_SUB: 3299 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3300 break; 3301 case OPC1_16_SRR_SUB_A15B: 3302 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3303 break; 3304 case OPC1_16_SRR_SUB_15AB: 3305 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3306 break; 3307 case OPC1_16_SRR_SUBS: 3308 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3309 break; 3310 case OPC1_16_SRR_XOR: 3311 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3312 break; 3313 default: 3314 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3315 } 3316 } 3317 3318 static void decode_ssr_opc(DisasContext *ctx, int op1) 3319 { 3320 int r1, r2; 3321 3322 r1 = MASK_OP_SSR_S1(ctx->opcode); 3323 r2 = MASK_OP_SSR_S2(ctx->opcode); 3324 3325 switch (op1) { 3326 case OPC1_16_SSR_ST_A: 3327 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3328 break; 3329 case OPC1_16_SSR_ST_A_POSTINC: 3330 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3331 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3332 break; 3333 case OPC1_16_SSR_ST_B: 3334 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3335 break; 3336 case OPC1_16_SSR_ST_B_POSTINC: 3337 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3338 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3339 break; 3340 case OPC1_16_SSR_ST_H: 3341 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3342 break; 3343 case OPC1_16_SSR_ST_H_POSTINC: 3344 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3345 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3346 break; 3347 case OPC1_16_SSR_ST_W: 3348 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3349 break; 3350 case OPC1_16_SSR_ST_W_POSTINC: 3351 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3352 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3353 break; 3354 default: 3355 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3356 } 3357 } 3358 3359 static void decode_sc_opc(DisasContext *ctx, int op1) 3360 { 3361 int32_t const16; 3362 3363 const16 = MASK_OP_SC_CONST8(ctx->opcode); 3364 3365 switch (op1) { 3366 case OPC1_16_SC_AND: 3367 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3368 break; 3369 case OPC1_16_SC_BISR: 3370 gen_helper_1arg(bisr, const16 & 0xff); 3371 break; 3372 case OPC1_16_SC_LD_A: 3373 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3374 break; 3375 case OPC1_16_SC_LD_W: 3376 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3377 break; 3378 case OPC1_16_SC_MOV: 3379 tcg_gen_movi_tl(cpu_gpr_d[15], const16); 3380 break; 3381 case OPC1_16_SC_OR: 3382 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3383 break; 3384 case OPC1_16_SC_ST_A: 3385 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3386 break; 3387 case OPC1_16_SC_ST_W: 3388 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3389 break; 3390 case OPC1_16_SC_SUB_A: 3391 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); 3392 break; 3393 default: 3394 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3395 } 3396 } 3397 3398 static void decode_slr_opc(DisasContext *ctx, int op1) 3399 { 3400 int r1, r2; 3401 3402 r1 = MASK_OP_SLR_D(ctx->opcode); 3403 r2 = MASK_OP_SLR_S2(ctx->opcode); 3404 3405 switch (op1) { 3406 /* SLR-format */ 3407 case OPC1_16_SLR_LD_A: 3408 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3409 break; 3410 case OPC1_16_SLR_LD_A_POSTINC: 3411 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3412 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3413 break; 3414 case OPC1_16_SLR_LD_BU: 3415 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3416 break; 3417 case OPC1_16_SLR_LD_BU_POSTINC: 3418 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3419 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3420 break; 3421 case OPC1_16_SLR_LD_H: 3422 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3423 break; 3424 case OPC1_16_SLR_LD_H_POSTINC: 3425 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3426 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3427 break; 3428 case OPC1_16_SLR_LD_W: 3429 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3430 break; 3431 case OPC1_16_SLR_LD_W_POSTINC: 3432 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3433 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3434 break; 3435 default: 3436 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3437 } 3438 } 3439 3440 static void decode_sro_opc(DisasContext *ctx, int op1) 3441 { 3442 int r2; 3443 int32_t address; 3444 3445 r2 = MASK_OP_SRO_S2(ctx->opcode); 3446 address = MASK_OP_SRO_OFF4(ctx->opcode); 3447 3448 /* SRO-format */ 3449 switch (op1) { 3450 case OPC1_16_SRO_LD_A: 3451 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3452 break; 3453 case OPC1_16_SRO_LD_BU: 3454 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3455 break; 3456 case OPC1_16_SRO_LD_H: 3457 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3458 break; 3459 case OPC1_16_SRO_LD_W: 3460 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3461 break; 3462 case OPC1_16_SRO_ST_A: 3463 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3464 break; 3465 case OPC1_16_SRO_ST_B: 3466 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3467 break; 3468 case OPC1_16_SRO_ST_H: 3469 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3470 break; 3471 case OPC1_16_SRO_ST_W: 3472 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3473 break; 3474 default: 3475 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3476 } 3477 } 3478 3479 static void decode_sr_system(DisasContext *ctx) 3480 { 3481 uint32_t op2; 3482 op2 = MASK_OP_SR_OP2(ctx->opcode); 3483 3484 switch (op2) { 3485 case OPC2_16_SR_NOP: 3486 break; 3487 case OPC2_16_SR_RET: 3488 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 3489 break; 3490 case OPC2_16_SR_RFE: 3491 gen_helper_rfe(cpu_env); 3492 tcg_gen_exit_tb(NULL, 0); 3493 ctx->base.is_jmp = DISAS_NORETURN; 3494 break; 3495 case OPC2_16_SR_DEBUG: 3496 /* raise EXCP_DEBUG */ 3497 break; 3498 case OPC2_16_SR_FRET: 3499 gen_fret(ctx); 3500 break; 3501 default: 3502 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3503 } 3504 } 3505 3506 static void decode_sr_accu(DisasContext *ctx) 3507 { 3508 uint32_t op2; 3509 uint32_t r1; 3510 3511 r1 = MASK_OP_SR_S1D(ctx->opcode); 3512 op2 = MASK_OP_SR_OP2(ctx->opcode); 3513 3514 switch (op2) { 3515 case OPC2_16_SR_RSUB: 3516 /* calc V bit -- overflow only if r1 = -0x80000000 */ 3517 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000); 3518 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 3519 /* calc SV bit */ 3520 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 3521 /* sub */ 3522 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3523 /* calc av */ 3524 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); 3525 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); 3526 /* calc sav */ 3527 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3528 break; 3529 case OPC2_16_SR_SAT_B: 3530 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); 3531 break; 3532 case OPC2_16_SR_SAT_BU: 3533 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); 3534 break; 3535 case OPC2_16_SR_SAT_H: 3536 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); 3537 break; 3538 case OPC2_16_SR_SAT_HU: 3539 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); 3540 break; 3541 default: 3542 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3543 } 3544 } 3545 3546 static void decode_16Bit_opc(DisasContext *ctx) 3547 { 3548 int op1; 3549 int r1, r2; 3550 int32_t const16; 3551 int32_t address; 3552 TCGv temp; 3553 3554 op1 = MASK_OP_MAJOR(ctx->opcode); 3555 3556 /* handle ADDSC.A opcode only being 6 bit long */ 3557 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { 3558 op1 = OPC1_16_SRRS_ADDSC_A; 3559 } 3560 3561 switch (op1) { 3562 case OPC1_16_SRC_ADD: 3563 case OPC1_16_SRC_ADD_A15: 3564 case OPC1_16_SRC_ADD_15A: 3565 case OPC1_16_SRC_ADD_A: 3566 case OPC1_16_SRC_CADD: 3567 case OPC1_16_SRC_CADDN: 3568 case OPC1_16_SRC_CMOV: 3569 case OPC1_16_SRC_CMOVN: 3570 case OPC1_16_SRC_EQ: 3571 case OPC1_16_SRC_LT: 3572 case OPC1_16_SRC_MOV: 3573 case OPC1_16_SRC_MOV_A: 3574 case OPC1_16_SRC_MOV_E: 3575 case OPC1_16_SRC_SH: 3576 case OPC1_16_SRC_SHA: 3577 decode_src_opc(ctx, op1); 3578 break; 3579 /* SRR-format */ 3580 case OPC1_16_SRR_ADD: 3581 case OPC1_16_SRR_ADD_A15: 3582 case OPC1_16_SRR_ADD_15A: 3583 case OPC1_16_SRR_ADD_A: 3584 case OPC1_16_SRR_ADDS: 3585 case OPC1_16_SRR_AND: 3586 case OPC1_16_SRR_CMOV: 3587 case OPC1_16_SRR_CMOVN: 3588 case OPC1_16_SRR_EQ: 3589 case OPC1_16_SRR_LT: 3590 case OPC1_16_SRR_MOV: 3591 case OPC1_16_SRR_MOV_A: 3592 case OPC1_16_SRR_MOV_AA: 3593 case OPC1_16_SRR_MOV_D: 3594 case OPC1_16_SRR_MUL: 3595 case OPC1_16_SRR_OR: 3596 case OPC1_16_SRR_SUB: 3597 case OPC1_16_SRR_SUB_A15B: 3598 case OPC1_16_SRR_SUB_15AB: 3599 case OPC1_16_SRR_SUBS: 3600 case OPC1_16_SRR_XOR: 3601 decode_srr_opc(ctx, op1); 3602 break; 3603 /* SSR-format */ 3604 case OPC1_16_SSR_ST_A: 3605 case OPC1_16_SSR_ST_A_POSTINC: 3606 case OPC1_16_SSR_ST_B: 3607 case OPC1_16_SSR_ST_B_POSTINC: 3608 case OPC1_16_SSR_ST_H: 3609 case OPC1_16_SSR_ST_H_POSTINC: 3610 case OPC1_16_SSR_ST_W: 3611 case OPC1_16_SSR_ST_W_POSTINC: 3612 decode_ssr_opc(ctx, op1); 3613 break; 3614 /* SRRS-format */ 3615 case OPC1_16_SRRS_ADDSC_A: 3616 r2 = MASK_OP_SRRS_S2(ctx->opcode); 3617 r1 = MASK_OP_SRRS_S1D(ctx->opcode); 3618 const16 = MASK_OP_SRRS_N(ctx->opcode); 3619 temp = tcg_temp_new(); 3620 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); 3621 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); 3622 break; 3623 /* SLRO-format */ 3624 case OPC1_16_SLRO_LD_A: 3625 r1 = MASK_OP_SLRO_D(ctx->opcode); 3626 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3627 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3628 break; 3629 case OPC1_16_SLRO_LD_BU: 3630 r1 = MASK_OP_SLRO_D(ctx->opcode); 3631 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3632 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3633 break; 3634 case OPC1_16_SLRO_LD_H: 3635 r1 = MASK_OP_SLRO_D(ctx->opcode); 3636 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3637 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3638 break; 3639 case OPC1_16_SLRO_LD_W: 3640 r1 = MASK_OP_SLRO_D(ctx->opcode); 3641 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3642 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3643 break; 3644 /* SB-format */ 3645 case OPC1_16_SB_CALL: 3646 case OPC1_16_SB_J: 3647 case OPC1_16_SB_JNZ: 3648 case OPC1_16_SB_JZ: 3649 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); 3650 gen_compute_branch(ctx, op1, 0, 0, 0, address); 3651 break; 3652 /* SBC-format */ 3653 case OPC1_16_SBC_JEQ: 3654 case OPC1_16_SBC_JNE: 3655 address = MASK_OP_SBC_DISP4(ctx->opcode); 3656 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3657 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3658 break; 3659 case OPC1_16_SBC_JEQ2: 3660 case OPC1_16_SBC_JNE2: 3661 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3662 address = MASK_OP_SBC_DISP4(ctx->opcode); 3663 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3664 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3665 } else { 3666 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3667 } 3668 break; 3669 /* SBRN-format */ 3670 case OPC1_16_SBRN_JNZ_T: 3671 case OPC1_16_SBRN_JZ_T: 3672 address = MASK_OP_SBRN_DISP4(ctx->opcode); 3673 const16 = MASK_OP_SBRN_N(ctx->opcode); 3674 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3675 break; 3676 /* SBR-format */ 3677 case OPC1_16_SBR_JEQ2: 3678 case OPC1_16_SBR_JNE2: 3679 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3680 r1 = MASK_OP_SBR_S2(ctx->opcode); 3681 address = MASK_OP_SBR_DISP4(ctx->opcode); 3682 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3683 } else { 3684 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3685 } 3686 break; 3687 case OPC1_16_SBR_JEQ: 3688 case OPC1_16_SBR_JGEZ: 3689 case OPC1_16_SBR_JGTZ: 3690 case OPC1_16_SBR_JLEZ: 3691 case OPC1_16_SBR_JLTZ: 3692 case OPC1_16_SBR_JNE: 3693 case OPC1_16_SBR_JNZ: 3694 case OPC1_16_SBR_JNZ_A: 3695 case OPC1_16_SBR_JZ: 3696 case OPC1_16_SBR_JZ_A: 3697 case OPC1_16_SBR_LOOP: 3698 r1 = MASK_OP_SBR_S2(ctx->opcode); 3699 address = MASK_OP_SBR_DISP4(ctx->opcode); 3700 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3701 break; 3702 /* SC-format */ 3703 case OPC1_16_SC_AND: 3704 case OPC1_16_SC_BISR: 3705 case OPC1_16_SC_LD_A: 3706 case OPC1_16_SC_LD_W: 3707 case OPC1_16_SC_MOV: 3708 case OPC1_16_SC_OR: 3709 case OPC1_16_SC_ST_A: 3710 case OPC1_16_SC_ST_W: 3711 case OPC1_16_SC_SUB_A: 3712 decode_sc_opc(ctx, op1); 3713 break; 3714 /* SLR-format */ 3715 case OPC1_16_SLR_LD_A: 3716 case OPC1_16_SLR_LD_A_POSTINC: 3717 case OPC1_16_SLR_LD_BU: 3718 case OPC1_16_SLR_LD_BU_POSTINC: 3719 case OPC1_16_SLR_LD_H: 3720 case OPC1_16_SLR_LD_H_POSTINC: 3721 case OPC1_16_SLR_LD_W: 3722 case OPC1_16_SLR_LD_W_POSTINC: 3723 decode_slr_opc(ctx, op1); 3724 break; 3725 /* SRO-format */ 3726 case OPC1_16_SRO_LD_A: 3727 case OPC1_16_SRO_LD_BU: 3728 case OPC1_16_SRO_LD_H: 3729 case OPC1_16_SRO_LD_W: 3730 case OPC1_16_SRO_ST_A: 3731 case OPC1_16_SRO_ST_B: 3732 case OPC1_16_SRO_ST_H: 3733 case OPC1_16_SRO_ST_W: 3734 decode_sro_opc(ctx, op1); 3735 break; 3736 /* SSRO-format */ 3737 case OPC1_16_SSRO_ST_A: 3738 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3739 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3740 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3741 break; 3742 case OPC1_16_SSRO_ST_B: 3743 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3744 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3745 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3746 break; 3747 case OPC1_16_SSRO_ST_H: 3748 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3749 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3750 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3751 break; 3752 case OPC1_16_SSRO_ST_W: 3753 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3754 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3755 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3756 break; 3757 /* SR-format */ 3758 case OPCM_16_SR_SYSTEM: 3759 decode_sr_system(ctx); 3760 break; 3761 case OPCM_16_SR_ACCU: 3762 decode_sr_accu(ctx); 3763 break; 3764 case OPC1_16_SR_JI: 3765 r1 = MASK_OP_SR_S1D(ctx->opcode); 3766 gen_compute_branch(ctx, op1, r1, 0, 0, 0); 3767 break; 3768 case OPC1_16_SR_NOT: 3769 r1 = MASK_OP_SR_S1D(ctx->opcode); 3770 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3771 break; 3772 default: 3773 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3774 } 3775 } 3776 3777 /* 3778 * 32 bit instructions 3779 */ 3780 3781 /* ABS-format */ 3782 static void decode_abs_ldw(DisasContext *ctx) 3783 { 3784 int32_t op2; 3785 int32_t r1; 3786 uint32_t address; 3787 TCGv temp; 3788 3789 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3790 address = MASK_OP_ABS_OFF18(ctx->opcode); 3791 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3792 3793 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3794 3795 switch (op2) { 3796 case OPC2_32_ABS_LD_A: 3797 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3798 break; 3799 case OPC2_32_ABS_LD_D: 3800 CHECK_REG_PAIR(r1); 3801 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3802 break; 3803 case OPC2_32_ABS_LD_DA: 3804 CHECK_REG_PAIR(r1); 3805 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3806 break; 3807 case OPC2_32_ABS_LD_W: 3808 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3809 break; 3810 default: 3811 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3812 } 3813 } 3814 3815 static void decode_abs_ldb(DisasContext *ctx) 3816 { 3817 int32_t op2; 3818 int32_t r1; 3819 uint32_t address; 3820 TCGv temp; 3821 3822 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3823 address = MASK_OP_ABS_OFF18(ctx->opcode); 3824 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3825 3826 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3827 3828 switch (op2) { 3829 case OPC2_32_ABS_LD_B: 3830 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); 3831 break; 3832 case OPC2_32_ABS_LD_BU: 3833 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3834 break; 3835 case OPC2_32_ABS_LD_H: 3836 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); 3837 break; 3838 case OPC2_32_ABS_LD_HU: 3839 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3840 break; 3841 default: 3842 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3843 } 3844 } 3845 3846 static void decode_abs_ldst_swap(DisasContext *ctx) 3847 { 3848 int32_t op2; 3849 int32_t r1; 3850 uint32_t address; 3851 TCGv temp; 3852 3853 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3854 address = MASK_OP_ABS_OFF18(ctx->opcode); 3855 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3856 3857 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3858 3859 switch (op2) { 3860 case OPC2_32_ABS_LDMST: 3861 gen_ldmst(ctx, r1, temp); 3862 break; 3863 case OPC2_32_ABS_SWAP_W: 3864 gen_swap(ctx, r1, temp); 3865 break; 3866 default: 3867 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3868 } 3869 } 3870 3871 static void decode_abs_ldst_context(DisasContext *ctx) 3872 { 3873 uint32_t op2; 3874 int32_t off18; 3875 3876 off18 = MASK_OP_ABS_OFF18(ctx->opcode); 3877 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3878 3879 switch (op2) { 3880 case OPC2_32_ABS_LDLCX: 3881 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); 3882 break; 3883 case OPC2_32_ABS_LDUCX: 3884 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); 3885 break; 3886 case OPC2_32_ABS_STLCX: 3887 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); 3888 break; 3889 case OPC2_32_ABS_STUCX: 3890 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); 3891 break; 3892 default: 3893 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3894 } 3895 } 3896 3897 static void decode_abs_store(DisasContext *ctx) 3898 { 3899 int32_t op2; 3900 int32_t r1; 3901 uint32_t address; 3902 TCGv temp; 3903 3904 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3905 address = MASK_OP_ABS_OFF18(ctx->opcode); 3906 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3907 3908 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3909 3910 switch (op2) { 3911 case OPC2_32_ABS_ST_A: 3912 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3913 break; 3914 case OPC2_32_ABS_ST_D: 3915 CHECK_REG_PAIR(r1); 3916 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3917 break; 3918 case OPC2_32_ABS_ST_DA: 3919 CHECK_REG_PAIR(r1); 3920 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3921 break; 3922 case OPC2_32_ABS_ST_W: 3923 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3924 break; 3925 default: 3926 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3927 } 3928 } 3929 3930 static void decode_abs_storeb_h(DisasContext *ctx) 3931 { 3932 int32_t op2; 3933 int32_t r1; 3934 uint32_t address; 3935 TCGv temp; 3936 3937 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3938 address = MASK_OP_ABS_OFF18(ctx->opcode); 3939 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3940 3941 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3942 3943 switch (op2) { 3944 case OPC2_32_ABS_ST_B: 3945 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3946 break; 3947 case OPC2_32_ABS_ST_H: 3948 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3949 break; 3950 default: 3951 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3952 } 3953 } 3954 3955 /* Bit-format */ 3956 3957 static void decode_bit_andacc(DisasContext *ctx) 3958 { 3959 uint32_t op2; 3960 int r1, r2, r3; 3961 int pos1, pos2; 3962 3963 r1 = MASK_OP_BIT_S1(ctx->opcode); 3964 r2 = MASK_OP_BIT_S2(ctx->opcode); 3965 r3 = MASK_OP_BIT_D(ctx->opcode); 3966 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 3967 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 3968 op2 = MASK_OP_BIT_OP2(ctx->opcode); 3969 3970 3971 switch (op2) { 3972 case OPC2_32_BIT_AND_AND_T: 3973 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3974 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); 3975 break; 3976 case OPC2_32_BIT_AND_ANDN_T: 3977 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3978 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); 3979 break; 3980 case OPC2_32_BIT_AND_NOR_T: 3981 if (TCG_TARGET_HAS_andc_i32) { 3982 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3983 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); 3984 } else { 3985 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3986 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); 3987 } 3988 break; 3989 case OPC2_32_BIT_AND_OR_T: 3990 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3991 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); 3992 break; 3993 default: 3994 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3995 } 3996 } 3997 3998 static void decode_bit_logical_t(DisasContext *ctx) 3999 { 4000 uint32_t op2; 4001 int r1, r2, r3; 4002 int pos1, pos2; 4003 r1 = MASK_OP_BIT_S1(ctx->opcode); 4004 r2 = MASK_OP_BIT_S2(ctx->opcode); 4005 r3 = MASK_OP_BIT_D(ctx->opcode); 4006 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4007 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4008 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4009 4010 switch (op2) { 4011 case OPC2_32_BIT_AND_T: 4012 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4013 pos1, pos2, &tcg_gen_and_tl); 4014 break; 4015 case OPC2_32_BIT_ANDN_T: 4016 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4017 pos1, pos2, &tcg_gen_andc_tl); 4018 break; 4019 case OPC2_32_BIT_NOR_T: 4020 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4021 pos1, pos2, &tcg_gen_nor_tl); 4022 break; 4023 case OPC2_32_BIT_OR_T: 4024 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4025 pos1, pos2, &tcg_gen_or_tl); 4026 break; 4027 default: 4028 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4029 } 4030 } 4031 4032 static void decode_bit_insert(DisasContext *ctx) 4033 { 4034 uint32_t op2; 4035 int r1, r2, r3; 4036 int pos1, pos2; 4037 TCGv temp; 4038 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4039 r1 = MASK_OP_BIT_S1(ctx->opcode); 4040 r2 = MASK_OP_BIT_S2(ctx->opcode); 4041 r3 = MASK_OP_BIT_D(ctx->opcode); 4042 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4043 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4044 4045 temp = tcg_temp_new(); 4046 4047 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); 4048 if (op2 == OPC2_32_BIT_INSN_T) { 4049 tcg_gen_not_tl(temp, temp); 4050 } 4051 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); 4052 } 4053 4054 static void decode_bit_logical_t2(DisasContext *ctx) 4055 { 4056 uint32_t op2; 4057 4058 int r1, r2, r3; 4059 int pos1, pos2; 4060 4061 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4062 r1 = MASK_OP_BIT_S1(ctx->opcode); 4063 r2 = MASK_OP_BIT_S2(ctx->opcode); 4064 r3 = MASK_OP_BIT_D(ctx->opcode); 4065 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4066 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4067 4068 switch (op2) { 4069 case OPC2_32_BIT_NAND_T: 4070 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4071 pos1, pos2, &tcg_gen_nand_tl); 4072 break; 4073 case OPC2_32_BIT_ORN_T: 4074 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4075 pos1, pos2, &tcg_gen_orc_tl); 4076 break; 4077 case OPC2_32_BIT_XNOR_T: 4078 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4079 pos1, pos2, &tcg_gen_eqv_tl); 4080 break; 4081 case OPC2_32_BIT_XOR_T: 4082 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4083 pos1, pos2, &tcg_gen_xor_tl); 4084 break; 4085 default: 4086 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4087 } 4088 } 4089 4090 static void decode_bit_orand(DisasContext *ctx) 4091 { 4092 uint32_t op2; 4093 4094 int r1, r2, r3; 4095 int pos1, pos2; 4096 4097 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4098 r1 = MASK_OP_BIT_S1(ctx->opcode); 4099 r2 = MASK_OP_BIT_S2(ctx->opcode); 4100 r3 = MASK_OP_BIT_D(ctx->opcode); 4101 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4102 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4103 4104 switch (op2) { 4105 case OPC2_32_BIT_OR_AND_T: 4106 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4107 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); 4108 break; 4109 case OPC2_32_BIT_OR_ANDN_T: 4110 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4111 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); 4112 break; 4113 case OPC2_32_BIT_OR_NOR_T: 4114 if (TCG_TARGET_HAS_orc_i32) { 4115 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4116 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); 4117 } else { 4118 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4119 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); 4120 } 4121 break; 4122 case OPC2_32_BIT_OR_OR_T: 4123 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4124 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); 4125 break; 4126 default: 4127 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4128 } 4129 } 4130 4131 static void decode_bit_sh_logic1(DisasContext *ctx) 4132 { 4133 uint32_t op2; 4134 int r1, r2, r3; 4135 int pos1, pos2; 4136 TCGv temp; 4137 4138 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4139 r1 = MASK_OP_BIT_S1(ctx->opcode); 4140 r2 = MASK_OP_BIT_S2(ctx->opcode); 4141 r3 = MASK_OP_BIT_D(ctx->opcode); 4142 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4143 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4144 4145 temp = tcg_temp_new(); 4146 4147 switch (op2) { 4148 case OPC2_32_BIT_SH_AND_T: 4149 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4150 pos1, pos2, &tcg_gen_and_tl); 4151 break; 4152 case OPC2_32_BIT_SH_ANDN_T: 4153 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4154 pos1, pos2, &tcg_gen_andc_tl); 4155 break; 4156 case OPC2_32_BIT_SH_NOR_T: 4157 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4158 pos1, pos2, &tcg_gen_nor_tl); 4159 break; 4160 case OPC2_32_BIT_SH_OR_T: 4161 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4162 pos1, pos2, &tcg_gen_or_tl); 4163 break; 4164 default: 4165 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4166 } 4167 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4168 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4169 } 4170 4171 static void decode_bit_sh_logic2(DisasContext *ctx) 4172 { 4173 uint32_t op2; 4174 int r1, r2, r3; 4175 int pos1, pos2; 4176 TCGv temp; 4177 4178 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4179 r1 = MASK_OP_BIT_S1(ctx->opcode); 4180 r2 = MASK_OP_BIT_S2(ctx->opcode); 4181 r3 = MASK_OP_BIT_D(ctx->opcode); 4182 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4183 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4184 4185 temp = tcg_temp_new(); 4186 4187 switch (op2) { 4188 case OPC2_32_BIT_SH_NAND_T: 4189 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , 4190 pos1, pos2, &tcg_gen_nand_tl); 4191 break; 4192 case OPC2_32_BIT_SH_ORN_T: 4193 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4194 pos1, pos2, &tcg_gen_orc_tl); 4195 break; 4196 case OPC2_32_BIT_SH_XNOR_T: 4197 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4198 pos1, pos2, &tcg_gen_eqv_tl); 4199 break; 4200 case OPC2_32_BIT_SH_XOR_T: 4201 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4202 pos1, pos2, &tcg_gen_xor_tl); 4203 break; 4204 default: 4205 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4206 } 4207 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4208 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4209 } 4210 4211 /* BO-format */ 4212 4213 4214 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) 4215 { 4216 uint32_t op2; 4217 uint32_t off10; 4218 int32_t r1, r2; 4219 TCGv temp; 4220 4221 r1 = MASK_OP_BO_S1D(ctx->opcode); 4222 r2 = MASK_OP_BO_S2(ctx->opcode); 4223 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4224 op2 = MASK_OP_BO_OP2(ctx->opcode); 4225 4226 switch (op2) { 4227 case OPC2_32_BO_CACHEA_WI_SHORTOFF: 4228 case OPC2_32_BO_CACHEA_W_SHORTOFF: 4229 case OPC2_32_BO_CACHEA_I_SHORTOFF: 4230 /* instruction to access the cache */ 4231 break; 4232 case OPC2_32_BO_CACHEA_WI_POSTINC: 4233 case OPC2_32_BO_CACHEA_W_POSTINC: 4234 case OPC2_32_BO_CACHEA_I_POSTINC: 4235 /* instruction to access the cache, but we still need to handle 4236 the addressing mode */ 4237 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4238 break; 4239 case OPC2_32_BO_CACHEA_WI_PREINC: 4240 case OPC2_32_BO_CACHEA_W_PREINC: 4241 case OPC2_32_BO_CACHEA_I_PREINC: 4242 /* instruction to access the cache, but we still need to handle 4243 the addressing mode */ 4244 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4245 break; 4246 case OPC2_32_BO_CACHEI_WI_SHORTOFF: 4247 case OPC2_32_BO_CACHEI_W_SHORTOFF: 4248 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 4249 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4250 } 4251 break; 4252 case OPC2_32_BO_CACHEI_W_POSTINC: 4253 case OPC2_32_BO_CACHEI_WI_POSTINC: 4254 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4255 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4256 } else { 4257 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4258 } 4259 break; 4260 case OPC2_32_BO_CACHEI_W_PREINC: 4261 case OPC2_32_BO_CACHEI_WI_PREINC: 4262 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4263 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4264 } else { 4265 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4266 } 4267 break; 4268 case OPC2_32_BO_ST_A_SHORTOFF: 4269 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4270 break; 4271 case OPC2_32_BO_ST_A_POSTINC: 4272 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4273 MO_LESL); 4274 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4275 break; 4276 case OPC2_32_BO_ST_A_PREINC: 4277 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4278 break; 4279 case OPC2_32_BO_ST_B_SHORTOFF: 4280 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4281 break; 4282 case OPC2_32_BO_ST_B_POSTINC: 4283 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4284 MO_UB); 4285 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4286 break; 4287 case OPC2_32_BO_ST_B_PREINC: 4288 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4289 break; 4290 case OPC2_32_BO_ST_D_SHORTOFF: 4291 CHECK_REG_PAIR(r1); 4292 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4293 off10, ctx); 4294 break; 4295 case OPC2_32_BO_ST_D_POSTINC: 4296 CHECK_REG_PAIR(r1); 4297 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4298 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4299 break; 4300 case OPC2_32_BO_ST_D_PREINC: 4301 CHECK_REG_PAIR(r1); 4302 temp = tcg_temp_new(); 4303 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4304 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4305 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4306 break; 4307 case OPC2_32_BO_ST_DA_SHORTOFF: 4308 CHECK_REG_PAIR(r1); 4309 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4310 off10, ctx); 4311 break; 4312 case OPC2_32_BO_ST_DA_POSTINC: 4313 CHECK_REG_PAIR(r1); 4314 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4315 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4316 break; 4317 case OPC2_32_BO_ST_DA_PREINC: 4318 CHECK_REG_PAIR(r1); 4319 temp = tcg_temp_new(); 4320 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4321 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4322 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4323 break; 4324 case OPC2_32_BO_ST_H_SHORTOFF: 4325 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4326 break; 4327 case OPC2_32_BO_ST_H_POSTINC: 4328 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4329 MO_LEUW); 4330 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4331 break; 4332 case OPC2_32_BO_ST_H_PREINC: 4333 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4334 break; 4335 case OPC2_32_BO_ST_Q_SHORTOFF: 4336 temp = tcg_temp_new(); 4337 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4338 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4339 break; 4340 case OPC2_32_BO_ST_Q_POSTINC: 4341 temp = tcg_temp_new(); 4342 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4343 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, 4344 MO_LEUW); 4345 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4346 break; 4347 case OPC2_32_BO_ST_Q_PREINC: 4348 temp = tcg_temp_new(); 4349 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4350 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4351 break; 4352 case OPC2_32_BO_ST_W_SHORTOFF: 4353 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4354 break; 4355 case OPC2_32_BO_ST_W_POSTINC: 4356 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4357 MO_LEUL); 4358 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4359 break; 4360 case OPC2_32_BO_ST_W_PREINC: 4361 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4362 break; 4363 default: 4364 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4365 } 4366 } 4367 4368 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) 4369 { 4370 uint32_t op2; 4371 uint32_t off10; 4372 int32_t r1, r2; 4373 TCGv temp, temp2, t_off10; 4374 4375 r1 = MASK_OP_BO_S1D(ctx->opcode); 4376 r2 = MASK_OP_BO_S2(ctx->opcode); 4377 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4378 op2 = MASK_OP_BO_OP2(ctx->opcode); 4379 4380 temp = tcg_temp_new(); 4381 temp2 = tcg_temp_new(); 4382 t_off10 = tcg_constant_i32(off10); 4383 CHECK_REG_PAIR(r2); 4384 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4385 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4386 4387 switch (op2) { 4388 case OPC2_32_BO_CACHEA_WI_BR: 4389 case OPC2_32_BO_CACHEA_W_BR: 4390 case OPC2_32_BO_CACHEA_I_BR: 4391 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4392 break; 4393 case OPC2_32_BO_CACHEA_WI_CIRC: 4394 case OPC2_32_BO_CACHEA_W_CIRC: 4395 case OPC2_32_BO_CACHEA_I_CIRC: 4396 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4397 break; 4398 case OPC2_32_BO_ST_A_BR: 4399 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4400 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4401 break; 4402 case OPC2_32_BO_ST_A_CIRC: 4403 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4404 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4405 break; 4406 case OPC2_32_BO_ST_B_BR: 4407 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4408 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4409 break; 4410 case OPC2_32_BO_ST_B_CIRC: 4411 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4412 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4413 break; 4414 case OPC2_32_BO_ST_D_BR: 4415 CHECK_REG_PAIR(r1); 4416 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4417 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4418 break; 4419 case OPC2_32_BO_ST_D_CIRC: 4420 CHECK_REG_PAIR(r1); 4421 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4422 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4423 tcg_gen_addi_tl(temp, temp, 4); 4424 tcg_gen_rem_tl(temp, temp, temp2); 4425 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4426 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4427 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4428 break; 4429 case OPC2_32_BO_ST_DA_BR: 4430 CHECK_REG_PAIR(r1); 4431 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4432 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4433 break; 4434 case OPC2_32_BO_ST_DA_CIRC: 4435 CHECK_REG_PAIR(r1); 4436 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4437 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4438 tcg_gen_addi_tl(temp, temp, 4); 4439 tcg_gen_rem_tl(temp, temp, temp2); 4440 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4441 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4442 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4443 break; 4444 case OPC2_32_BO_ST_H_BR: 4445 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4446 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4447 break; 4448 case OPC2_32_BO_ST_H_CIRC: 4449 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4450 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4451 break; 4452 case OPC2_32_BO_ST_Q_BR: 4453 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4454 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4455 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4456 break; 4457 case OPC2_32_BO_ST_Q_CIRC: 4458 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4459 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4460 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4461 break; 4462 case OPC2_32_BO_ST_W_BR: 4463 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4464 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4465 break; 4466 case OPC2_32_BO_ST_W_CIRC: 4467 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4468 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4469 break; 4470 default: 4471 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4472 } 4473 } 4474 4475 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) 4476 { 4477 uint32_t op2; 4478 uint32_t off10; 4479 int32_t r1, r2; 4480 TCGv temp; 4481 4482 r1 = MASK_OP_BO_S1D(ctx->opcode); 4483 r2 = MASK_OP_BO_S2(ctx->opcode); 4484 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4485 op2 = MASK_OP_BO_OP2(ctx->opcode); 4486 4487 switch (op2) { 4488 case OPC2_32_BO_LD_A_SHORTOFF: 4489 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4490 break; 4491 case OPC2_32_BO_LD_A_POSTINC: 4492 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4493 MO_LEUL); 4494 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4495 break; 4496 case OPC2_32_BO_LD_A_PREINC: 4497 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4498 break; 4499 case OPC2_32_BO_LD_B_SHORTOFF: 4500 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4501 break; 4502 case OPC2_32_BO_LD_B_POSTINC: 4503 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4504 MO_SB); 4505 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4506 break; 4507 case OPC2_32_BO_LD_B_PREINC: 4508 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4509 break; 4510 case OPC2_32_BO_LD_BU_SHORTOFF: 4511 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4512 break; 4513 case OPC2_32_BO_LD_BU_POSTINC: 4514 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4515 MO_UB); 4516 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4517 break; 4518 case OPC2_32_BO_LD_BU_PREINC: 4519 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4520 break; 4521 case OPC2_32_BO_LD_D_SHORTOFF: 4522 CHECK_REG_PAIR(r1); 4523 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4524 off10, ctx); 4525 break; 4526 case OPC2_32_BO_LD_D_POSTINC: 4527 CHECK_REG_PAIR(r1); 4528 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4529 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4530 break; 4531 case OPC2_32_BO_LD_D_PREINC: 4532 CHECK_REG_PAIR(r1); 4533 temp = tcg_temp_new(); 4534 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4535 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4536 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4537 break; 4538 case OPC2_32_BO_LD_DA_SHORTOFF: 4539 CHECK_REG_PAIR(r1); 4540 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4541 off10, ctx); 4542 break; 4543 case OPC2_32_BO_LD_DA_POSTINC: 4544 CHECK_REG_PAIR(r1); 4545 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4546 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4547 break; 4548 case OPC2_32_BO_LD_DA_PREINC: 4549 CHECK_REG_PAIR(r1); 4550 temp = tcg_temp_new(); 4551 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4552 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4553 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4554 break; 4555 case OPC2_32_BO_LD_H_SHORTOFF: 4556 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4557 break; 4558 case OPC2_32_BO_LD_H_POSTINC: 4559 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4560 MO_LESW); 4561 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4562 break; 4563 case OPC2_32_BO_LD_H_PREINC: 4564 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4565 break; 4566 case OPC2_32_BO_LD_HU_SHORTOFF: 4567 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4568 break; 4569 case OPC2_32_BO_LD_HU_POSTINC: 4570 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4571 MO_LEUW); 4572 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4573 break; 4574 case OPC2_32_BO_LD_HU_PREINC: 4575 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4576 break; 4577 case OPC2_32_BO_LD_Q_SHORTOFF: 4578 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4579 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4580 break; 4581 case OPC2_32_BO_LD_Q_POSTINC: 4582 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4583 MO_LEUW); 4584 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4585 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4586 break; 4587 case OPC2_32_BO_LD_Q_PREINC: 4588 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4589 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4590 break; 4591 case OPC2_32_BO_LD_W_SHORTOFF: 4592 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4593 break; 4594 case OPC2_32_BO_LD_W_POSTINC: 4595 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4596 MO_LEUL); 4597 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4598 break; 4599 case OPC2_32_BO_LD_W_PREINC: 4600 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4601 break; 4602 default: 4603 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4604 } 4605 } 4606 4607 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) 4608 { 4609 uint32_t op2; 4610 uint32_t off10; 4611 int r1, r2; 4612 TCGv temp, temp2, t_off10; 4613 4614 r1 = MASK_OP_BO_S1D(ctx->opcode); 4615 r2 = MASK_OP_BO_S2(ctx->opcode); 4616 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4617 op2 = MASK_OP_BO_OP2(ctx->opcode); 4618 4619 temp = tcg_temp_new(); 4620 temp2 = tcg_temp_new(); 4621 t_off10 = tcg_constant_i32(off10); 4622 CHECK_REG_PAIR(r2); 4623 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4624 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4625 4626 4627 switch (op2) { 4628 case OPC2_32_BO_LD_A_BR: 4629 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4630 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4631 break; 4632 case OPC2_32_BO_LD_A_CIRC: 4633 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4634 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4635 break; 4636 case OPC2_32_BO_LD_B_BR: 4637 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4638 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4639 break; 4640 case OPC2_32_BO_LD_B_CIRC: 4641 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4642 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4643 break; 4644 case OPC2_32_BO_LD_BU_BR: 4645 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4646 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4647 break; 4648 case OPC2_32_BO_LD_BU_CIRC: 4649 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4650 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4651 break; 4652 case OPC2_32_BO_LD_D_BR: 4653 CHECK_REG_PAIR(r1); 4654 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4655 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4656 break; 4657 case OPC2_32_BO_LD_D_CIRC: 4658 CHECK_REG_PAIR(r1); 4659 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4660 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4661 tcg_gen_addi_tl(temp, temp, 4); 4662 tcg_gen_rem_tl(temp, temp, temp2); 4663 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4664 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4665 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4666 break; 4667 case OPC2_32_BO_LD_DA_BR: 4668 CHECK_REG_PAIR(r1); 4669 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4670 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4671 break; 4672 case OPC2_32_BO_LD_DA_CIRC: 4673 CHECK_REG_PAIR(r1); 4674 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4675 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4676 tcg_gen_addi_tl(temp, temp, 4); 4677 tcg_gen_rem_tl(temp, temp, temp2); 4678 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4679 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4680 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4681 break; 4682 case OPC2_32_BO_LD_H_BR: 4683 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4684 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4685 break; 4686 case OPC2_32_BO_LD_H_CIRC: 4687 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4688 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4689 break; 4690 case OPC2_32_BO_LD_HU_BR: 4691 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4692 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4693 break; 4694 case OPC2_32_BO_LD_HU_CIRC: 4695 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4696 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4697 break; 4698 case OPC2_32_BO_LD_Q_BR: 4699 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4700 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4701 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4702 break; 4703 case OPC2_32_BO_LD_Q_CIRC: 4704 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4705 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4706 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4707 break; 4708 case OPC2_32_BO_LD_W_BR: 4709 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4710 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4711 break; 4712 case OPC2_32_BO_LD_W_CIRC: 4713 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4714 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4715 break; 4716 default: 4717 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4718 } 4719 } 4720 4721 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) 4722 { 4723 uint32_t op2; 4724 uint32_t off10; 4725 int r1, r2; 4726 4727 TCGv temp; 4728 4729 r1 = MASK_OP_BO_S1D(ctx->opcode); 4730 r2 = MASK_OP_BO_S2(ctx->opcode); 4731 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4732 op2 = MASK_OP_BO_OP2(ctx->opcode); 4733 4734 4735 temp = tcg_temp_new(); 4736 4737 switch (op2) { 4738 case OPC2_32_BO_LDLCX_SHORTOFF: 4739 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4740 gen_helper_ldlcx(cpu_env, temp); 4741 break; 4742 case OPC2_32_BO_LDMST_SHORTOFF: 4743 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4744 gen_ldmst(ctx, r1, temp); 4745 break; 4746 case OPC2_32_BO_LDMST_POSTINC: 4747 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4748 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4749 break; 4750 case OPC2_32_BO_LDMST_PREINC: 4751 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4752 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4753 break; 4754 case OPC2_32_BO_LDUCX_SHORTOFF: 4755 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4756 gen_helper_lducx(cpu_env, temp); 4757 break; 4758 case OPC2_32_BO_LEA_SHORTOFF: 4759 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); 4760 break; 4761 case OPC2_32_BO_STLCX_SHORTOFF: 4762 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4763 gen_helper_stlcx(cpu_env, temp); 4764 break; 4765 case OPC2_32_BO_STUCX_SHORTOFF: 4766 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4767 gen_helper_stucx(cpu_env, temp); 4768 break; 4769 case OPC2_32_BO_SWAP_W_SHORTOFF: 4770 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4771 gen_swap(ctx, r1, temp); 4772 break; 4773 case OPC2_32_BO_SWAP_W_POSTINC: 4774 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4775 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4776 break; 4777 case OPC2_32_BO_SWAP_W_PREINC: 4778 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4779 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4780 break; 4781 case OPC2_32_BO_CMPSWAP_W_SHORTOFF: 4782 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4783 gen_cmpswap(ctx, r1, temp); 4784 break; 4785 case OPC2_32_BO_CMPSWAP_W_POSTINC: 4786 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4787 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4788 break; 4789 case OPC2_32_BO_CMPSWAP_W_PREINC: 4790 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4791 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4792 break; 4793 case OPC2_32_BO_SWAPMSK_W_SHORTOFF: 4794 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4795 gen_swapmsk(ctx, r1, temp); 4796 break; 4797 case OPC2_32_BO_SWAPMSK_W_POSTINC: 4798 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4799 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4800 break; 4801 case OPC2_32_BO_SWAPMSK_W_PREINC: 4802 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4803 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4804 break; 4805 default: 4806 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4807 } 4808 } 4809 4810 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) 4811 { 4812 uint32_t op2; 4813 uint32_t off10; 4814 int r1, r2; 4815 TCGv temp, temp2, t_off10; 4816 4817 r1 = MASK_OP_BO_S1D(ctx->opcode); 4818 r2 = MASK_OP_BO_S2(ctx->opcode); 4819 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4820 op2 = MASK_OP_BO_OP2(ctx->opcode); 4821 4822 temp = tcg_temp_new(); 4823 temp2 = tcg_temp_new(); 4824 t_off10 = tcg_constant_i32(off10); 4825 CHECK_REG_PAIR(r2); 4826 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4827 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4828 4829 switch (op2) { 4830 case OPC2_32_BO_LDMST_BR: 4831 gen_ldmst(ctx, r1, temp2); 4832 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4833 break; 4834 case OPC2_32_BO_LDMST_CIRC: 4835 gen_ldmst(ctx, r1, temp2); 4836 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4837 break; 4838 case OPC2_32_BO_SWAP_W_BR: 4839 gen_swap(ctx, r1, temp2); 4840 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4841 break; 4842 case OPC2_32_BO_SWAP_W_CIRC: 4843 gen_swap(ctx, r1, temp2); 4844 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4845 break; 4846 case OPC2_32_BO_CMPSWAP_W_BR: 4847 gen_cmpswap(ctx, r1, temp2); 4848 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4849 break; 4850 case OPC2_32_BO_CMPSWAP_W_CIRC: 4851 gen_cmpswap(ctx, r1, temp2); 4852 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4853 break; 4854 case OPC2_32_BO_SWAPMSK_W_BR: 4855 gen_swapmsk(ctx, r1, temp2); 4856 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4857 break; 4858 case OPC2_32_BO_SWAPMSK_W_CIRC: 4859 gen_swapmsk(ctx, r1, temp2); 4860 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4861 break; 4862 default: 4863 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4864 } 4865 } 4866 4867 static void decode_bol_opc(DisasContext *ctx, int32_t op1) 4868 { 4869 int r1, r2; 4870 int32_t address; 4871 TCGv temp; 4872 4873 r1 = MASK_OP_BOL_S1D(ctx->opcode); 4874 r2 = MASK_OP_BOL_S2(ctx->opcode); 4875 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); 4876 4877 switch (op1) { 4878 case OPC1_32_BOL_LD_A_LONGOFF: 4879 temp = tcg_temp_new(); 4880 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4881 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); 4882 break; 4883 case OPC1_32_BOL_LD_W_LONGOFF: 4884 temp = tcg_temp_new(); 4885 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4886 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); 4887 break; 4888 case OPC1_32_BOL_LEA_LONGOFF: 4889 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); 4890 break; 4891 case OPC1_32_BOL_ST_A_LONGOFF: 4892 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4893 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); 4894 } else { 4895 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4896 } 4897 break; 4898 case OPC1_32_BOL_ST_W_LONGOFF: 4899 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); 4900 break; 4901 case OPC1_32_BOL_LD_B_LONGOFF: 4902 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4903 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4904 } else { 4905 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4906 } 4907 break; 4908 case OPC1_32_BOL_LD_BU_LONGOFF: 4909 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4910 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); 4911 } else { 4912 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4913 } 4914 break; 4915 case OPC1_32_BOL_LD_H_LONGOFF: 4916 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4917 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4918 } else { 4919 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4920 } 4921 break; 4922 case OPC1_32_BOL_LD_HU_LONGOFF: 4923 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4924 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); 4925 } else { 4926 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4927 } 4928 break; 4929 case OPC1_32_BOL_ST_B_LONGOFF: 4930 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4931 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4932 } else { 4933 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4934 } 4935 break; 4936 case OPC1_32_BOL_ST_H_LONGOFF: 4937 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4938 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4939 } else { 4940 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4941 } 4942 break; 4943 default: 4944 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4945 } 4946 } 4947 4948 /* RC format */ 4949 static void decode_rc_logical_shift(DisasContext *ctx) 4950 { 4951 uint32_t op2; 4952 int r1, r2; 4953 int32_t const9; 4954 TCGv temp; 4955 4956 r2 = MASK_OP_RC_D(ctx->opcode); 4957 r1 = MASK_OP_RC_S1(ctx->opcode); 4958 const9 = MASK_OP_RC_CONST9(ctx->opcode); 4959 op2 = MASK_OP_RC_OP2(ctx->opcode); 4960 4961 temp = tcg_temp_new(); 4962 4963 switch (op2) { 4964 case OPC2_32_RC_AND: 4965 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4966 break; 4967 case OPC2_32_RC_ANDN: 4968 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4969 break; 4970 case OPC2_32_RC_NAND: 4971 tcg_gen_movi_tl(temp, const9); 4972 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4973 break; 4974 case OPC2_32_RC_NOR: 4975 tcg_gen_movi_tl(temp, const9); 4976 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4977 break; 4978 case OPC2_32_RC_OR: 4979 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4980 break; 4981 case OPC2_32_RC_ORN: 4982 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4983 break; 4984 case OPC2_32_RC_SH: 4985 const9 = sextract32(const9, 0, 6); 4986 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4987 break; 4988 case OPC2_32_RC_SH_H: 4989 const9 = sextract32(const9, 0, 5); 4990 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4991 break; 4992 case OPC2_32_RC_SHA: 4993 const9 = sextract32(const9, 0, 6); 4994 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4995 break; 4996 case OPC2_32_RC_SHA_H: 4997 const9 = sextract32(const9, 0, 5); 4998 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4999 break; 5000 case OPC2_32_RC_SHAS: 5001 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5002 break; 5003 case OPC2_32_RC_XNOR: 5004 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5005 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); 5006 break; 5007 case OPC2_32_RC_XOR: 5008 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5009 break; 5010 default: 5011 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5012 } 5013 } 5014 5015 static void decode_rc_accumulator(DisasContext *ctx) 5016 { 5017 uint32_t op2; 5018 int r1, r2; 5019 int16_t const9; 5020 5021 TCGv temp; 5022 5023 r2 = MASK_OP_RC_D(ctx->opcode); 5024 r1 = MASK_OP_RC_S1(ctx->opcode); 5025 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5026 5027 op2 = MASK_OP_RC_OP2(ctx->opcode); 5028 5029 temp = tcg_temp_new(); 5030 5031 switch (op2) { 5032 case OPC2_32_RC_ABSDIF: 5033 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5034 break; 5035 case OPC2_32_RC_ABSDIFS: 5036 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5037 break; 5038 case OPC2_32_RC_ADD: 5039 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5040 break; 5041 case OPC2_32_RC_ADDC: 5042 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5043 break; 5044 case OPC2_32_RC_ADDS: 5045 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5046 break; 5047 case OPC2_32_RC_ADDS_U: 5048 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5049 break; 5050 case OPC2_32_RC_ADDX: 5051 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5052 break; 5053 case OPC2_32_RC_AND_EQ: 5054 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5055 const9, &tcg_gen_and_tl); 5056 break; 5057 case OPC2_32_RC_AND_GE: 5058 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5059 const9, &tcg_gen_and_tl); 5060 break; 5061 case OPC2_32_RC_AND_GE_U: 5062 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5063 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5064 const9, &tcg_gen_and_tl); 5065 break; 5066 case OPC2_32_RC_AND_LT: 5067 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5068 const9, &tcg_gen_and_tl); 5069 break; 5070 case OPC2_32_RC_AND_LT_U: 5071 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5072 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5073 const9, &tcg_gen_and_tl); 5074 break; 5075 case OPC2_32_RC_AND_NE: 5076 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5077 const9, &tcg_gen_and_tl); 5078 break; 5079 case OPC2_32_RC_EQ: 5080 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5081 break; 5082 case OPC2_32_RC_EQANY_B: 5083 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5084 break; 5085 case OPC2_32_RC_EQANY_H: 5086 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5087 break; 5088 case OPC2_32_RC_GE: 5089 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5090 break; 5091 case OPC2_32_RC_GE_U: 5092 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5093 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5094 break; 5095 case OPC2_32_RC_LT: 5096 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5097 break; 5098 case OPC2_32_RC_LT_U: 5099 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5100 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5101 break; 5102 case OPC2_32_RC_MAX: 5103 tcg_gen_movi_tl(temp, const9); 5104 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5105 cpu_gpr_d[r1], temp); 5106 break; 5107 case OPC2_32_RC_MAX_U: 5108 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5109 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5110 cpu_gpr_d[r1], temp); 5111 break; 5112 case OPC2_32_RC_MIN: 5113 tcg_gen_movi_tl(temp, const9); 5114 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5115 cpu_gpr_d[r1], temp); 5116 break; 5117 case OPC2_32_RC_MIN_U: 5118 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5119 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5120 cpu_gpr_d[r1], temp); 5121 break; 5122 case OPC2_32_RC_NE: 5123 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5124 break; 5125 case OPC2_32_RC_OR_EQ: 5126 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5127 const9, &tcg_gen_or_tl); 5128 break; 5129 case OPC2_32_RC_OR_GE: 5130 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5131 const9, &tcg_gen_or_tl); 5132 break; 5133 case OPC2_32_RC_OR_GE_U: 5134 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5135 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5136 const9, &tcg_gen_or_tl); 5137 break; 5138 case OPC2_32_RC_OR_LT: 5139 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5140 const9, &tcg_gen_or_tl); 5141 break; 5142 case OPC2_32_RC_OR_LT_U: 5143 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5144 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5145 const9, &tcg_gen_or_tl); 5146 break; 5147 case OPC2_32_RC_OR_NE: 5148 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5149 const9, &tcg_gen_or_tl); 5150 break; 5151 case OPC2_32_RC_RSUB: 5152 tcg_gen_movi_tl(temp, const9); 5153 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5154 break; 5155 case OPC2_32_RC_RSUBS: 5156 tcg_gen_movi_tl(temp, const9); 5157 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5158 break; 5159 case OPC2_32_RC_RSUBS_U: 5160 tcg_gen_movi_tl(temp, const9); 5161 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5162 break; 5163 case OPC2_32_RC_SH_EQ: 5164 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5165 break; 5166 case OPC2_32_RC_SH_GE: 5167 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5168 break; 5169 case OPC2_32_RC_SH_GE_U: 5170 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5171 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5172 break; 5173 case OPC2_32_RC_SH_LT: 5174 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5175 break; 5176 case OPC2_32_RC_SH_LT_U: 5177 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5178 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5179 break; 5180 case OPC2_32_RC_SH_NE: 5181 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5182 break; 5183 case OPC2_32_RC_XOR_EQ: 5184 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5185 const9, &tcg_gen_xor_tl); 5186 break; 5187 case OPC2_32_RC_XOR_GE: 5188 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5189 const9, &tcg_gen_xor_tl); 5190 break; 5191 case OPC2_32_RC_XOR_GE_U: 5192 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5193 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5194 const9, &tcg_gen_xor_tl); 5195 break; 5196 case OPC2_32_RC_XOR_LT: 5197 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5198 const9, &tcg_gen_xor_tl); 5199 break; 5200 case OPC2_32_RC_XOR_LT_U: 5201 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5202 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5203 const9, &tcg_gen_xor_tl); 5204 break; 5205 case OPC2_32_RC_XOR_NE: 5206 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5207 const9, &tcg_gen_xor_tl); 5208 break; 5209 default: 5210 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5211 } 5212 } 5213 5214 static void decode_rc_serviceroutine(DisasContext *ctx) 5215 { 5216 uint32_t op2; 5217 uint32_t const9; 5218 5219 op2 = MASK_OP_RC_OP2(ctx->opcode); 5220 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5221 5222 switch (op2) { 5223 case OPC2_32_RC_BISR: 5224 gen_helper_1arg(bisr, const9); 5225 break; 5226 case OPC2_32_RC_SYSCALL: 5227 /* TODO: Add exception generation */ 5228 break; 5229 default: 5230 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5231 } 5232 } 5233 5234 static void decode_rc_mul(DisasContext *ctx) 5235 { 5236 uint32_t op2; 5237 int r1, r2; 5238 int16_t const9; 5239 5240 r2 = MASK_OP_RC_D(ctx->opcode); 5241 r1 = MASK_OP_RC_S1(ctx->opcode); 5242 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5243 5244 op2 = MASK_OP_RC_OP2(ctx->opcode); 5245 5246 switch (op2) { 5247 case OPC2_32_RC_MUL_32: 5248 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5249 break; 5250 case OPC2_32_RC_MUL_64: 5251 CHECK_REG_PAIR(r2); 5252 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5253 break; 5254 case OPC2_32_RC_MULS_32: 5255 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5256 break; 5257 case OPC2_32_RC_MUL_U_64: 5258 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5259 CHECK_REG_PAIR(r2); 5260 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5261 break; 5262 case OPC2_32_RC_MULS_U_32: 5263 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5264 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5265 break; 5266 default: 5267 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5268 } 5269 } 5270 5271 /* RCPW format */ 5272 static void decode_rcpw_insert(DisasContext *ctx) 5273 { 5274 uint32_t op2; 5275 int r1, r2; 5276 int32_t pos, width, const4; 5277 5278 TCGv temp; 5279 5280 op2 = MASK_OP_RCPW_OP2(ctx->opcode); 5281 r1 = MASK_OP_RCPW_S1(ctx->opcode); 5282 r2 = MASK_OP_RCPW_D(ctx->opcode); 5283 const4 = MASK_OP_RCPW_CONST4(ctx->opcode); 5284 width = MASK_OP_RCPW_WIDTH(ctx->opcode); 5285 pos = MASK_OP_RCPW_POS(ctx->opcode); 5286 5287 switch (op2) { 5288 case OPC2_32_RCPW_IMASK: 5289 CHECK_REG_PAIR(r2); 5290 /* if pos + width > 32 undefined result */ 5291 if (pos + width <= 32) { 5292 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); 5293 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); 5294 } 5295 break; 5296 case OPC2_32_RCPW_INSERT: 5297 /* if pos + width > 32 undefined result */ 5298 if (pos + width <= 32) { 5299 temp = tcg_constant_i32(const4); 5300 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); 5301 } 5302 break; 5303 default: 5304 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5305 } 5306 } 5307 5308 /* RCRW format */ 5309 5310 static void decode_rcrw_insert(DisasContext *ctx) 5311 { 5312 uint32_t op2; 5313 int r1, r3, r4; 5314 int32_t width, const4; 5315 5316 TCGv temp, temp2, temp3; 5317 5318 op2 = MASK_OP_RCRW_OP2(ctx->opcode); 5319 r1 = MASK_OP_RCRW_S1(ctx->opcode); 5320 r3 = MASK_OP_RCRW_S3(ctx->opcode); 5321 r4 = MASK_OP_RCRW_D(ctx->opcode); 5322 width = MASK_OP_RCRW_WIDTH(ctx->opcode); 5323 const4 = MASK_OP_RCRW_CONST4(ctx->opcode); 5324 5325 temp = tcg_temp_new(); 5326 temp2 = tcg_temp_new(); 5327 5328 switch (op2) { 5329 case OPC2_32_RCRW_IMASK: 5330 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 5331 tcg_gen_movi_tl(temp2, (1 << width) - 1); 5332 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); 5333 tcg_gen_movi_tl(temp2, const4); 5334 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); 5335 break; 5336 case OPC2_32_RCRW_INSERT: 5337 temp3 = tcg_temp_new(); 5338 5339 tcg_gen_movi_tl(temp, width); 5340 tcg_gen_movi_tl(temp2, const4); 5341 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 5342 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); 5343 break; 5344 default: 5345 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5346 } 5347 } 5348 5349 /* RCR format */ 5350 5351 static void decode_rcr_cond_select(DisasContext *ctx) 5352 { 5353 uint32_t op2; 5354 int r1, r3, r4; 5355 int32_t const9; 5356 5357 TCGv temp, temp2; 5358 5359 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5360 r1 = MASK_OP_RCR_S1(ctx->opcode); 5361 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5362 r3 = MASK_OP_RCR_S3(ctx->opcode); 5363 r4 = MASK_OP_RCR_D(ctx->opcode); 5364 5365 switch (op2) { 5366 case OPC2_32_RCR_CADD: 5367 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5368 cpu_gpr_d[r3]); 5369 break; 5370 case OPC2_32_RCR_CADDN: 5371 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5372 cpu_gpr_d[r3]); 5373 break; 5374 case OPC2_32_RCR_SEL: 5375 temp = tcg_constant_i32(0); 5376 temp2 = tcg_constant_i32(const9); 5377 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5378 cpu_gpr_d[r1], temp2); 5379 break; 5380 case OPC2_32_RCR_SELN: 5381 temp = tcg_constant_i32(0); 5382 temp2 = tcg_constant_i32(const9); 5383 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5384 cpu_gpr_d[r1], temp2); 5385 break; 5386 default: 5387 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5388 } 5389 } 5390 5391 static void decode_rcr_madd(DisasContext *ctx) 5392 { 5393 uint32_t op2; 5394 int r1, r3, r4; 5395 int32_t const9; 5396 5397 5398 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5399 r1 = MASK_OP_RCR_S1(ctx->opcode); 5400 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5401 r3 = MASK_OP_RCR_S3(ctx->opcode); 5402 r4 = MASK_OP_RCR_D(ctx->opcode); 5403 5404 switch (op2) { 5405 case OPC2_32_RCR_MADD_32: 5406 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5407 break; 5408 case OPC2_32_RCR_MADD_64: 5409 CHECK_REG_PAIR(r4); 5410 CHECK_REG_PAIR(r3); 5411 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5412 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5413 break; 5414 case OPC2_32_RCR_MADDS_32: 5415 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5416 break; 5417 case OPC2_32_RCR_MADDS_64: 5418 CHECK_REG_PAIR(r4); 5419 CHECK_REG_PAIR(r3); 5420 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5421 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5422 break; 5423 case OPC2_32_RCR_MADD_U_64: 5424 CHECK_REG_PAIR(r4); 5425 CHECK_REG_PAIR(r3); 5426 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5427 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5428 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5429 break; 5430 case OPC2_32_RCR_MADDS_U_32: 5431 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5432 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5433 break; 5434 case OPC2_32_RCR_MADDS_U_64: 5435 CHECK_REG_PAIR(r4); 5436 CHECK_REG_PAIR(r3); 5437 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5438 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5439 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5440 break; 5441 default: 5442 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5443 } 5444 } 5445 5446 static void decode_rcr_msub(DisasContext *ctx) 5447 { 5448 uint32_t op2; 5449 int r1, r3, r4; 5450 int32_t const9; 5451 5452 5453 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5454 r1 = MASK_OP_RCR_S1(ctx->opcode); 5455 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5456 r3 = MASK_OP_RCR_S3(ctx->opcode); 5457 r4 = MASK_OP_RCR_D(ctx->opcode); 5458 5459 switch (op2) { 5460 case OPC2_32_RCR_MSUB_32: 5461 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5462 break; 5463 case OPC2_32_RCR_MSUB_64: 5464 CHECK_REG_PAIR(r4); 5465 CHECK_REG_PAIR(r3); 5466 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5467 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5468 break; 5469 case OPC2_32_RCR_MSUBS_32: 5470 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5471 break; 5472 case OPC2_32_RCR_MSUBS_64: 5473 CHECK_REG_PAIR(r4); 5474 CHECK_REG_PAIR(r3); 5475 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5476 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5477 break; 5478 case OPC2_32_RCR_MSUB_U_64: 5479 CHECK_REG_PAIR(r4); 5480 CHECK_REG_PAIR(r3); 5481 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5482 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5483 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5484 break; 5485 case OPC2_32_RCR_MSUBS_U_32: 5486 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5487 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5488 break; 5489 case OPC2_32_RCR_MSUBS_U_64: 5490 CHECK_REG_PAIR(r4); 5491 CHECK_REG_PAIR(r3); 5492 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5493 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5494 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5495 break; 5496 default: 5497 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5498 } 5499 } 5500 5501 /* RLC format */ 5502 5503 static void decode_rlc_opc(DisasContext *ctx, 5504 uint32_t op1) 5505 { 5506 int32_t const16; 5507 int r1, r2; 5508 5509 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); 5510 r1 = MASK_OP_RLC_S1(ctx->opcode); 5511 r2 = MASK_OP_RLC_D(ctx->opcode); 5512 5513 switch (op1) { 5514 case OPC1_32_RLC_ADDI: 5515 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); 5516 break; 5517 case OPC1_32_RLC_ADDIH: 5518 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); 5519 break; 5520 case OPC1_32_RLC_ADDIH_A: 5521 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); 5522 break; 5523 case OPC1_32_RLC_MFCR: 5524 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5525 gen_mfcr(ctx, cpu_gpr_d[r2], const16); 5526 break; 5527 case OPC1_32_RLC_MOV: 5528 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5529 break; 5530 case OPC1_32_RLC_MOV_64: 5531 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5532 CHECK_REG_PAIR(r2); 5533 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5534 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); 5535 } else { 5536 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5537 } 5538 break; 5539 case OPC1_32_RLC_MOV_U: 5540 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5541 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5542 break; 5543 case OPC1_32_RLC_MOV_H: 5544 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); 5545 break; 5546 case OPC1_32_RLC_MOVH_A: 5547 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); 5548 break; 5549 case OPC1_32_RLC_MTCR: 5550 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5551 gen_mtcr(ctx, cpu_gpr_d[r1], const16); 5552 break; 5553 default: 5554 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5555 } 5556 } 5557 5558 /* RR format */ 5559 static void decode_rr_accumulator(DisasContext *ctx) 5560 { 5561 uint32_t op2; 5562 int r3, r2, r1; 5563 5564 TCGv temp; 5565 5566 r3 = MASK_OP_RR_D(ctx->opcode); 5567 r2 = MASK_OP_RR_S2(ctx->opcode); 5568 r1 = MASK_OP_RR_S1(ctx->opcode); 5569 op2 = MASK_OP_RR_OP2(ctx->opcode); 5570 5571 switch (op2) { 5572 case OPC2_32_RR_ABS: 5573 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5574 break; 5575 case OPC2_32_RR_ABS_B: 5576 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5577 break; 5578 case OPC2_32_RR_ABS_H: 5579 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5580 break; 5581 case OPC2_32_RR_ABSDIF: 5582 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5583 break; 5584 case OPC2_32_RR_ABSDIF_B: 5585 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5586 cpu_gpr_d[r2]); 5587 break; 5588 case OPC2_32_RR_ABSDIF_H: 5589 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5590 cpu_gpr_d[r2]); 5591 break; 5592 case OPC2_32_RR_ABSDIFS: 5593 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5594 cpu_gpr_d[r2]); 5595 break; 5596 case OPC2_32_RR_ABSDIFS_H: 5597 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5598 cpu_gpr_d[r2]); 5599 break; 5600 case OPC2_32_RR_ABSS: 5601 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5602 break; 5603 case OPC2_32_RR_ABSS_H: 5604 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5605 break; 5606 case OPC2_32_RR_ADD: 5607 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5608 break; 5609 case OPC2_32_RR_ADD_B: 5610 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5611 break; 5612 case OPC2_32_RR_ADD_H: 5613 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5614 break; 5615 case OPC2_32_RR_ADDC: 5616 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5617 break; 5618 case OPC2_32_RR_ADDS: 5619 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5620 break; 5621 case OPC2_32_RR_ADDS_H: 5622 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5623 cpu_gpr_d[r2]); 5624 break; 5625 case OPC2_32_RR_ADDS_HU: 5626 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5627 cpu_gpr_d[r2]); 5628 break; 5629 case OPC2_32_RR_ADDS_U: 5630 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5631 cpu_gpr_d[r2]); 5632 break; 5633 case OPC2_32_RR_ADDX: 5634 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5635 break; 5636 case OPC2_32_RR_AND_EQ: 5637 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5638 cpu_gpr_d[r2], &tcg_gen_and_tl); 5639 break; 5640 case OPC2_32_RR_AND_GE: 5641 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5642 cpu_gpr_d[r2], &tcg_gen_and_tl); 5643 break; 5644 case OPC2_32_RR_AND_GE_U: 5645 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5646 cpu_gpr_d[r2], &tcg_gen_and_tl); 5647 break; 5648 case OPC2_32_RR_AND_LT: 5649 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5650 cpu_gpr_d[r2], &tcg_gen_and_tl); 5651 break; 5652 case OPC2_32_RR_AND_LT_U: 5653 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5654 cpu_gpr_d[r2], &tcg_gen_and_tl); 5655 break; 5656 case OPC2_32_RR_AND_NE: 5657 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5658 cpu_gpr_d[r2], &tcg_gen_and_tl); 5659 break; 5660 case OPC2_32_RR_EQ: 5661 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5662 cpu_gpr_d[r2]); 5663 break; 5664 case OPC2_32_RR_EQ_B: 5665 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5666 break; 5667 case OPC2_32_RR_EQ_H: 5668 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5669 break; 5670 case OPC2_32_RR_EQ_W: 5671 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5672 break; 5673 case OPC2_32_RR_EQANY_B: 5674 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5675 break; 5676 case OPC2_32_RR_EQANY_H: 5677 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5678 break; 5679 case OPC2_32_RR_GE: 5680 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5681 cpu_gpr_d[r2]); 5682 break; 5683 case OPC2_32_RR_GE_U: 5684 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5685 cpu_gpr_d[r2]); 5686 break; 5687 case OPC2_32_RR_LT: 5688 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5689 cpu_gpr_d[r2]); 5690 break; 5691 case OPC2_32_RR_LT_U: 5692 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5693 cpu_gpr_d[r2]); 5694 break; 5695 case OPC2_32_RR_LT_B: 5696 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5697 break; 5698 case OPC2_32_RR_LT_BU: 5699 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5700 break; 5701 case OPC2_32_RR_LT_H: 5702 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5703 break; 5704 case OPC2_32_RR_LT_HU: 5705 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5706 break; 5707 case OPC2_32_RR_LT_W: 5708 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5709 break; 5710 case OPC2_32_RR_LT_WU: 5711 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5712 break; 5713 case OPC2_32_RR_MAX: 5714 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5715 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5716 break; 5717 case OPC2_32_RR_MAX_U: 5718 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5719 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5720 break; 5721 case OPC2_32_RR_MAX_B: 5722 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5723 break; 5724 case OPC2_32_RR_MAX_BU: 5725 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5726 break; 5727 case OPC2_32_RR_MAX_H: 5728 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5729 break; 5730 case OPC2_32_RR_MAX_HU: 5731 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5732 break; 5733 case OPC2_32_RR_MIN: 5734 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5735 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5736 break; 5737 case OPC2_32_RR_MIN_U: 5738 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5739 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5740 break; 5741 case OPC2_32_RR_MIN_B: 5742 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5743 break; 5744 case OPC2_32_RR_MIN_BU: 5745 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5746 break; 5747 case OPC2_32_RR_MIN_H: 5748 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5749 break; 5750 case OPC2_32_RR_MIN_HU: 5751 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5752 break; 5753 case OPC2_32_RR_MOV: 5754 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5755 break; 5756 case OPC2_32_RR_MOV_64: 5757 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5758 temp = tcg_temp_new(); 5759 5760 CHECK_REG_PAIR(r3); 5761 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 5762 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5763 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 5764 } else { 5765 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5766 } 5767 break; 5768 case OPC2_32_RR_MOVS_64: 5769 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5770 CHECK_REG_PAIR(r3); 5771 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5772 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); 5773 } else { 5774 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5775 } 5776 break; 5777 case OPC2_32_RR_NE: 5778 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5779 cpu_gpr_d[r2]); 5780 break; 5781 case OPC2_32_RR_OR_EQ: 5782 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5783 cpu_gpr_d[r2], &tcg_gen_or_tl); 5784 break; 5785 case OPC2_32_RR_OR_GE: 5786 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5787 cpu_gpr_d[r2], &tcg_gen_or_tl); 5788 break; 5789 case OPC2_32_RR_OR_GE_U: 5790 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5791 cpu_gpr_d[r2], &tcg_gen_or_tl); 5792 break; 5793 case OPC2_32_RR_OR_LT: 5794 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5795 cpu_gpr_d[r2], &tcg_gen_or_tl); 5796 break; 5797 case OPC2_32_RR_OR_LT_U: 5798 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5799 cpu_gpr_d[r2], &tcg_gen_or_tl); 5800 break; 5801 case OPC2_32_RR_OR_NE: 5802 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5803 cpu_gpr_d[r2], &tcg_gen_or_tl); 5804 break; 5805 case OPC2_32_RR_SAT_B: 5806 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); 5807 break; 5808 case OPC2_32_RR_SAT_BU: 5809 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); 5810 break; 5811 case OPC2_32_RR_SAT_H: 5812 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); 5813 break; 5814 case OPC2_32_RR_SAT_HU: 5815 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); 5816 break; 5817 case OPC2_32_RR_SH_EQ: 5818 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5819 cpu_gpr_d[r2]); 5820 break; 5821 case OPC2_32_RR_SH_GE: 5822 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5823 cpu_gpr_d[r2]); 5824 break; 5825 case OPC2_32_RR_SH_GE_U: 5826 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5827 cpu_gpr_d[r2]); 5828 break; 5829 case OPC2_32_RR_SH_LT: 5830 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5831 cpu_gpr_d[r2]); 5832 break; 5833 case OPC2_32_RR_SH_LT_U: 5834 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5835 cpu_gpr_d[r2]); 5836 break; 5837 case OPC2_32_RR_SH_NE: 5838 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5839 cpu_gpr_d[r2]); 5840 break; 5841 case OPC2_32_RR_SUB: 5842 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5843 break; 5844 case OPC2_32_RR_SUB_B: 5845 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5846 break; 5847 case OPC2_32_RR_SUB_H: 5848 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5849 break; 5850 case OPC2_32_RR_SUBC: 5851 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5852 break; 5853 case OPC2_32_RR_SUBS: 5854 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5855 break; 5856 case OPC2_32_RR_SUBS_U: 5857 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5858 break; 5859 case OPC2_32_RR_SUBS_H: 5860 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5861 cpu_gpr_d[r2]); 5862 break; 5863 case OPC2_32_RR_SUBS_HU: 5864 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5865 cpu_gpr_d[r2]); 5866 break; 5867 case OPC2_32_RR_SUBX: 5868 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5869 break; 5870 case OPC2_32_RR_XOR_EQ: 5871 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5872 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5873 break; 5874 case OPC2_32_RR_XOR_GE: 5875 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5876 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5877 break; 5878 case OPC2_32_RR_XOR_GE_U: 5879 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5880 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5881 break; 5882 case OPC2_32_RR_XOR_LT: 5883 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5884 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5885 break; 5886 case OPC2_32_RR_XOR_LT_U: 5887 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5888 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5889 break; 5890 case OPC2_32_RR_XOR_NE: 5891 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5892 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5893 break; 5894 default: 5895 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5896 } 5897 } 5898 5899 static void decode_rr_logical_shift(DisasContext *ctx) 5900 { 5901 uint32_t op2; 5902 int r3, r2, r1; 5903 5904 r3 = MASK_OP_RR_D(ctx->opcode); 5905 r2 = MASK_OP_RR_S2(ctx->opcode); 5906 r1 = MASK_OP_RR_S1(ctx->opcode); 5907 op2 = MASK_OP_RR_OP2(ctx->opcode); 5908 5909 switch (op2) { 5910 case OPC2_32_RR_AND: 5911 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5912 break; 5913 case OPC2_32_RR_ANDN: 5914 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5915 break; 5916 case OPC2_32_RR_CLO: 5917 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5918 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); 5919 break; 5920 case OPC2_32_RR_CLO_H: 5921 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5922 break; 5923 case OPC2_32_RR_CLS: 5924 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5925 break; 5926 case OPC2_32_RR_CLS_H: 5927 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5928 break; 5929 case OPC2_32_RR_CLZ: 5930 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); 5931 break; 5932 case OPC2_32_RR_CLZ_H: 5933 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5934 break; 5935 case OPC2_32_RR_NAND: 5936 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5937 break; 5938 case OPC2_32_RR_NOR: 5939 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5940 break; 5941 case OPC2_32_RR_OR: 5942 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5943 break; 5944 case OPC2_32_RR_ORN: 5945 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5946 break; 5947 case OPC2_32_RR_SH: 5948 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5949 break; 5950 case OPC2_32_RR_SH_H: 5951 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5952 break; 5953 case OPC2_32_RR_SHA: 5954 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5955 break; 5956 case OPC2_32_RR_SHA_H: 5957 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5958 break; 5959 case OPC2_32_RR_SHAS: 5960 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5961 break; 5962 case OPC2_32_RR_XNOR: 5963 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5964 break; 5965 case OPC2_32_RR_XOR: 5966 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5967 break; 5968 default: 5969 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5970 } 5971 } 5972 5973 static void decode_rr_address(DisasContext *ctx) 5974 { 5975 uint32_t op2, n; 5976 int r1, r2, r3; 5977 TCGv temp; 5978 5979 op2 = MASK_OP_RR_OP2(ctx->opcode); 5980 r3 = MASK_OP_RR_D(ctx->opcode); 5981 r2 = MASK_OP_RR_S2(ctx->opcode); 5982 r1 = MASK_OP_RR_S1(ctx->opcode); 5983 n = MASK_OP_RR_N(ctx->opcode); 5984 5985 switch (op2) { 5986 case OPC2_32_RR_ADD_A: 5987 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 5988 break; 5989 case OPC2_32_RR_ADDSC_A: 5990 temp = tcg_temp_new(); 5991 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); 5992 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); 5993 break; 5994 case OPC2_32_RR_ADDSC_AT: 5995 temp = tcg_temp_new(); 5996 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); 5997 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); 5998 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); 5999 break; 6000 case OPC2_32_RR_EQ_A: 6001 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 6002 cpu_gpr_a[r2]); 6003 break; 6004 case OPC2_32_RR_EQZ: 6005 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6006 break; 6007 case OPC2_32_RR_GE_A: 6008 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6009 cpu_gpr_a[r2]); 6010 break; 6011 case OPC2_32_RR_LT_A: 6012 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6013 cpu_gpr_a[r2]); 6014 break; 6015 case OPC2_32_RR_MOV_A: 6016 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); 6017 break; 6018 case OPC2_32_RR_MOV_AA: 6019 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); 6020 break; 6021 case OPC2_32_RR_MOV_D: 6022 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); 6023 break; 6024 case OPC2_32_RR_NE_A: 6025 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 6026 cpu_gpr_a[r2]); 6027 break; 6028 case OPC2_32_RR_NEZ_A: 6029 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6030 break; 6031 case OPC2_32_RR_SUB_A: 6032 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6033 break; 6034 default: 6035 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6036 } 6037 } 6038 6039 static void decode_rr_idirect(DisasContext *ctx) 6040 { 6041 uint32_t op2; 6042 int r1; 6043 6044 op2 = MASK_OP_RR_OP2(ctx->opcode); 6045 r1 = MASK_OP_RR_S1(ctx->opcode); 6046 6047 switch (op2) { 6048 case OPC2_32_RR_JI: 6049 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6050 break; 6051 case OPC2_32_RR_JLI: 6052 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 6053 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6054 break; 6055 case OPC2_32_RR_CALLI: 6056 gen_helper_1arg(call, ctx->pc_succ_insn); 6057 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6058 break; 6059 case OPC2_32_RR_FCALLI: 6060 gen_fcall_save_ctx(ctx); 6061 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6062 break; 6063 default: 6064 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6065 } 6066 tcg_gen_exit_tb(NULL, 0); 6067 ctx->base.is_jmp = DISAS_NORETURN; 6068 } 6069 6070 static void decode_rr_divide(DisasContext *ctx) 6071 { 6072 uint32_t op2; 6073 int r1, r2, r3; 6074 6075 TCGv temp, temp2, temp3; 6076 6077 op2 = MASK_OP_RR_OP2(ctx->opcode); 6078 r3 = MASK_OP_RR_D(ctx->opcode); 6079 r2 = MASK_OP_RR_S2(ctx->opcode); 6080 r1 = MASK_OP_RR_S1(ctx->opcode); 6081 6082 switch (op2) { 6083 case OPC2_32_RR_BMERGE: 6084 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6085 break; 6086 case OPC2_32_RR_BSPLIT: 6087 CHECK_REG_PAIR(r3); 6088 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6089 break; 6090 case OPC2_32_RR_DVINIT_B: 6091 CHECK_REG_PAIR(r3); 6092 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6093 cpu_gpr_d[r2]); 6094 break; 6095 case OPC2_32_RR_DVINIT_BU: 6096 temp = tcg_temp_new(); 6097 temp2 = tcg_temp_new(); 6098 temp3 = tcg_temp_new(); 6099 CHECK_REG_PAIR(r3); 6100 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); 6101 /* reset av */ 6102 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6103 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6104 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6105 tcg_gen_abs_tl(temp, temp3); 6106 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6107 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6108 } else { 6109 /* overflow = (D[b] == 0) */ 6110 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6111 } 6112 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6113 /* sv */ 6114 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6115 /* write result */ 6116 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); 6117 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6118 break; 6119 case OPC2_32_RR_DVINIT_H: 6120 CHECK_REG_PAIR(r3); 6121 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6122 cpu_gpr_d[r2]); 6123 break; 6124 case OPC2_32_RR_DVINIT_HU: 6125 temp = tcg_temp_new(); 6126 temp2 = tcg_temp_new(); 6127 temp3 = tcg_temp_new(); 6128 CHECK_REG_PAIR(r3); 6129 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); 6130 /* reset av */ 6131 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6132 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6133 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6134 tcg_gen_abs_tl(temp, temp3); 6135 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6136 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6137 } else { 6138 /* overflow = (D[b] == 0) */ 6139 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6140 } 6141 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6142 /* sv */ 6143 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6144 /* write result */ 6145 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); 6146 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6147 break; 6148 case OPC2_32_RR_DVINIT: 6149 temp = tcg_temp_new(); 6150 temp2 = tcg_temp_new(); 6151 CHECK_REG_PAIR(r3); 6152 /* overflow = ((D[b] == 0) || 6153 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ 6154 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); 6155 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); 6156 tcg_gen_and_tl(temp, temp, temp2); 6157 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); 6158 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 6159 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6160 /* sv */ 6161 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6162 /* reset av */ 6163 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6164 /* write result */ 6165 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6166 /* sign extend to high reg */ 6167 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); 6168 break; 6169 case OPC2_32_RR_DVINIT_U: 6170 /* overflow = (D[b] == 0) */ 6171 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6172 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6173 /* sv */ 6174 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6175 /* reset av */ 6176 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6177 /* write result */ 6178 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6179 /* zero extend to high reg*/ 6180 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); 6181 break; 6182 case OPC2_32_RR_PARITY: 6183 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6184 break; 6185 case OPC2_32_RR_UNPACK: 6186 CHECK_REG_PAIR(r3); 6187 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6188 break; 6189 case OPC2_32_RR_CRC32: 6190 if (has_feature(ctx, TRICORE_FEATURE_161)) { 6191 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6192 } else { 6193 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6194 } 6195 break; 6196 case OPC2_32_RR_DIV: 6197 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6198 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6199 cpu_gpr_d[r2]); 6200 } else { 6201 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6202 } 6203 break; 6204 case OPC2_32_RR_DIV_U: 6205 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6206 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], 6207 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6208 } else { 6209 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6210 } 6211 break; 6212 case OPC2_32_RR_MUL_F: 6213 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6214 break; 6215 case OPC2_32_RR_DIV_F: 6216 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6217 break; 6218 case OPC2_32_RR_CMP_F: 6219 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6220 break; 6221 case OPC2_32_RR_FTOI: 6222 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6223 break; 6224 case OPC2_32_RR_ITOF: 6225 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6226 break; 6227 case OPC2_32_RR_FTOUZ: 6228 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6229 break; 6230 case OPC2_32_RR_UPDFL: 6231 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); 6232 break; 6233 case OPC2_32_RR_UTOF: 6234 gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6235 break; 6236 case OPC2_32_RR_FTOIZ: 6237 gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6238 break; 6239 case OPC2_32_RR_QSEED_F: 6240 gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6241 break; 6242 default: 6243 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6244 } 6245 } 6246 6247 /* RR1 Format */ 6248 static void decode_rr1_mul(DisasContext *ctx) 6249 { 6250 uint32_t op2; 6251 6252 int r1, r2, r3; 6253 TCGv n; 6254 TCGv_i64 temp64; 6255 6256 r1 = MASK_OP_RR1_S1(ctx->opcode); 6257 r2 = MASK_OP_RR1_S2(ctx->opcode); 6258 r3 = MASK_OP_RR1_D(ctx->opcode); 6259 n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode)); 6260 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6261 6262 switch (op2) { 6263 case OPC2_32_RR1_MUL_H_32_LL: 6264 temp64 = tcg_temp_new_i64(); 6265 CHECK_REG_PAIR(r3); 6266 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6267 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6268 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6269 break; 6270 case OPC2_32_RR1_MUL_H_32_LU: 6271 temp64 = tcg_temp_new_i64(); 6272 CHECK_REG_PAIR(r3); 6273 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6274 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6275 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6276 break; 6277 case OPC2_32_RR1_MUL_H_32_UL: 6278 temp64 = tcg_temp_new_i64(); 6279 CHECK_REG_PAIR(r3); 6280 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6281 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6282 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6283 break; 6284 case OPC2_32_RR1_MUL_H_32_UU: 6285 temp64 = tcg_temp_new_i64(); 6286 CHECK_REG_PAIR(r3); 6287 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6288 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6289 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6290 break; 6291 case OPC2_32_RR1_MULM_H_64_LL: 6292 temp64 = tcg_temp_new_i64(); 6293 CHECK_REG_PAIR(r3); 6294 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6295 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6296 /* reset V bit */ 6297 tcg_gen_movi_tl(cpu_PSW_V, 0); 6298 /* reset AV bit */ 6299 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6300 break; 6301 case OPC2_32_RR1_MULM_H_64_LU: 6302 temp64 = tcg_temp_new_i64(); 6303 CHECK_REG_PAIR(r3); 6304 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6305 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6306 /* reset V bit */ 6307 tcg_gen_movi_tl(cpu_PSW_V, 0); 6308 /* reset AV bit */ 6309 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6310 break; 6311 case OPC2_32_RR1_MULM_H_64_UL: 6312 temp64 = tcg_temp_new_i64(); 6313 CHECK_REG_PAIR(r3); 6314 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6315 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6316 /* reset V bit */ 6317 tcg_gen_movi_tl(cpu_PSW_V, 0); 6318 /* reset AV bit */ 6319 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6320 break; 6321 case OPC2_32_RR1_MULM_H_64_UU: 6322 temp64 = tcg_temp_new_i64(); 6323 CHECK_REG_PAIR(r3); 6324 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6325 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6326 /* reset V bit */ 6327 tcg_gen_movi_tl(cpu_PSW_V, 0); 6328 /* reset AV bit */ 6329 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6330 break; 6331 case OPC2_32_RR1_MULR_H_16_LL: 6332 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6333 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6334 break; 6335 case OPC2_32_RR1_MULR_H_16_LU: 6336 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6337 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6338 break; 6339 case OPC2_32_RR1_MULR_H_16_UL: 6340 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6341 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6342 break; 6343 case OPC2_32_RR1_MULR_H_16_UU: 6344 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6345 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6346 break; 6347 default: 6348 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6349 } 6350 } 6351 6352 static void decode_rr1_mulq(DisasContext *ctx) 6353 { 6354 uint32_t op2; 6355 int r1, r2, r3; 6356 uint32_t n; 6357 6358 TCGv temp, temp2; 6359 6360 r1 = MASK_OP_RR1_S1(ctx->opcode); 6361 r2 = MASK_OP_RR1_S2(ctx->opcode); 6362 r3 = MASK_OP_RR1_D(ctx->opcode); 6363 n = MASK_OP_RR1_N(ctx->opcode); 6364 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6365 6366 temp = tcg_temp_new(); 6367 temp2 = tcg_temp_new(); 6368 6369 switch (op2) { 6370 case OPC2_32_RR1_MUL_Q_32: 6371 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); 6372 break; 6373 case OPC2_32_RR1_MUL_Q_64: 6374 CHECK_REG_PAIR(r3); 6375 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6376 n, 0); 6377 break; 6378 case OPC2_32_RR1_MUL_Q_32_L: 6379 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6380 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6381 break; 6382 case OPC2_32_RR1_MUL_Q_64_L: 6383 CHECK_REG_PAIR(r3); 6384 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6385 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6386 break; 6387 case OPC2_32_RR1_MUL_Q_32_U: 6388 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6389 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6390 break; 6391 case OPC2_32_RR1_MUL_Q_64_U: 6392 CHECK_REG_PAIR(r3); 6393 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6394 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6395 break; 6396 case OPC2_32_RR1_MUL_Q_32_LL: 6397 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6398 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6399 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6400 break; 6401 case OPC2_32_RR1_MUL_Q_32_UU: 6402 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6403 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6404 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6405 break; 6406 case OPC2_32_RR1_MULR_Q_32_L: 6407 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6408 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6409 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6410 break; 6411 case OPC2_32_RR1_MULR_Q_32_U: 6412 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6413 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6414 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6415 break; 6416 default: 6417 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6418 } 6419 } 6420 6421 /* RR2 format */ 6422 static void decode_rr2_mul(DisasContext *ctx) 6423 { 6424 uint32_t op2; 6425 int r1, r2, r3; 6426 6427 op2 = MASK_OP_RR2_OP2(ctx->opcode); 6428 r1 = MASK_OP_RR2_S1(ctx->opcode); 6429 r2 = MASK_OP_RR2_S2(ctx->opcode); 6430 r3 = MASK_OP_RR2_D(ctx->opcode); 6431 switch (op2) { 6432 case OPC2_32_RR2_MUL_32: 6433 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6434 break; 6435 case OPC2_32_RR2_MUL_64: 6436 CHECK_REG_PAIR(r3); 6437 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6438 cpu_gpr_d[r2]); 6439 break; 6440 case OPC2_32_RR2_MULS_32: 6441 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6442 cpu_gpr_d[r2]); 6443 break; 6444 case OPC2_32_RR2_MUL_U_64: 6445 CHECK_REG_PAIR(r3); 6446 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6447 cpu_gpr_d[r2]); 6448 break; 6449 case OPC2_32_RR2_MULS_U_32: 6450 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6451 cpu_gpr_d[r2]); 6452 break; 6453 default: 6454 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6455 } 6456 } 6457 6458 /* RRPW format */ 6459 static void decode_rrpw_extract_insert(DisasContext *ctx) 6460 { 6461 uint32_t op2; 6462 int r1, r2, r3; 6463 int32_t pos, width; 6464 TCGv temp; 6465 6466 op2 = MASK_OP_RRPW_OP2(ctx->opcode); 6467 r1 = MASK_OP_RRPW_S1(ctx->opcode); 6468 r2 = MASK_OP_RRPW_S2(ctx->opcode); 6469 r3 = MASK_OP_RRPW_D(ctx->opcode); 6470 pos = MASK_OP_RRPW_POS(ctx->opcode); 6471 width = MASK_OP_RRPW_WIDTH(ctx->opcode); 6472 6473 switch (op2) { 6474 case OPC2_32_RRPW_EXTR: 6475 if (width == 0) { 6476 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6477 break; 6478 } 6479 6480 if (pos + width <= 32) { 6481 /* optimize special cases */ 6482 if ((pos == 0) && (width == 8)) { 6483 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6484 } else if ((pos == 0) && (width == 16)) { 6485 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6486 } else { 6487 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width); 6488 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width); 6489 } 6490 } 6491 break; 6492 case OPC2_32_RRPW_EXTR_U: 6493 if (width == 0) { 6494 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6495 } else { 6496 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); 6497 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width)); 6498 } 6499 break; 6500 case OPC2_32_RRPW_IMASK: 6501 CHECK_REG_PAIR(r3); 6502 6503 if (pos + width <= 32) { 6504 temp = tcg_temp_new(); 6505 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); 6506 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); 6507 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 6508 } 6509 6510 break; 6511 case OPC2_32_RRPW_INSERT: 6512 if (pos + width <= 32) { 6513 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 6514 pos, width); 6515 } 6516 break; 6517 default: 6518 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6519 } 6520 } 6521 6522 /* RRR format */ 6523 static void decode_rrr_cond_select(DisasContext *ctx) 6524 { 6525 uint32_t op2; 6526 int r1, r2, r3, r4; 6527 TCGv temp; 6528 6529 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6530 r1 = MASK_OP_RRR_S1(ctx->opcode); 6531 r2 = MASK_OP_RRR_S2(ctx->opcode); 6532 r3 = MASK_OP_RRR_S3(ctx->opcode); 6533 r4 = MASK_OP_RRR_D(ctx->opcode); 6534 6535 switch (op2) { 6536 case OPC2_32_RRR_CADD: 6537 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 6538 cpu_gpr_d[r4], cpu_gpr_d[r3]); 6539 break; 6540 case OPC2_32_RRR_CADDN: 6541 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6542 cpu_gpr_d[r3]); 6543 break; 6544 case OPC2_32_RRR_CSUB: 6545 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6546 cpu_gpr_d[r3]); 6547 break; 6548 case OPC2_32_RRR_CSUBN: 6549 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6550 cpu_gpr_d[r3]); 6551 break; 6552 case OPC2_32_RRR_SEL: 6553 temp = tcg_constant_i32(0); 6554 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6555 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6556 break; 6557 case OPC2_32_RRR_SELN: 6558 temp = tcg_constant_i32(0); 6559 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6560 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6561 break; 6562 default: 6563 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6564 } 6565 } 6566 6567 static void decode_rrr_divide(DisasContext *ctx) 6568 { 6569 uint32_t op2; 6570 6571 int r1, r2, r3, r4; 6572 6573 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6574 r1 = MASK_OP_RRR_S1(ctx->opcode); 6575 r2 = MASK_OP_RRR_S2(ctx->opcode); 6576 r3 = MASK_OP_RRR_S3(ctx->opcode); 6577 r4 = MASK_OP_RRR_D(ctx->opcode); 6578 6579 switch (op2) { 6580 case OPC2_32_RRR_DVADJ: 6581 CHECK_REG_PAIR(r3); 6582 CHECK_REG_PAIR(r4); 6583 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6584 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6585 break; 6586 case OPC2_32_RRR_DVSTEP: 6587 CHECK_REG_PAIR(r3); 6588 CHECK_REG_PAIR(r4); 6589 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6590 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6591 break; 6592 case OPC2_32_RRR_DVSTEP_U: 6593 CHECK_REG_PAIR(r3); 6594 CHECK_REG_PAIR(r4); 6595 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6596 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6597 break; 6598 case OPC2_32_RRR_IXMAX: 6599 CHECK_REG_PAIR(r3); 6600 CHECK_REG_PAIR(r4); 6601 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6602 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6603 break; 6604 case OPC2_32_RRR_IXMAX_U: 6605 CHECK_REG_PAIR(r3); 6606 CHECK_REG_PAIR(r4); 6607 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6608 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6609 break; 6610 case OPC2_32_RRR_IXMIN: 6611 CHECK_REG_PAIR(r3); 6612 CHECK_REG_PAIR(r4); 6613 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6614 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6615 break; 6616 case OPC2_32_RRR_IXMIN_U: 6617 CHECK_REG_PAIR(r3); 6618 CHECK_REG_PAIR(r4); 6619 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6620 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6621 break; 6622 case OPC2_32_RRR_PACK: 6623 CHECK_REG_PAIR(r3); 6624 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], 6625 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6626 break; 6627 case OPC2_32_RRR_ADD_F: 6628 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6629 break; 6630 case OPC2_32_RRR_SUB_F: 6631 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6632 break; 6633 case OPC2_32_RRR_MADD_F: 6634 gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6635 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6636 break; 6637 case OPC2_32_RRR_MSUB_F: 6638 gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6639 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6640 break; 6641 default: 6642 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6643 } 6644 } 6645 6646 /* RRR2 format */ 6647 static void decode_rrr2_madd(DisasContext *ctx) 6648 { 6649 uint32_t op2; 6650 uint32_t r1, r2, r3, r4; 6651 6652 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6653 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6654 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6655 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6656 r4 = MASK_OP_RRR2_D(ctx->opcode); 6657 switch (op2) { 6658 case OPC2_32_RRR2_MADD_32: 6659 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6660 cpu_gpr_d[r2]); 6661 break; 6662 case OPC2_32_RRR2_MADD_64: 6663 CHECK_REG_PAIR(r4); 6664 CHECK_REG_PAIR(r3); 6665 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6666 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6667 break; 6668 case OPC2_32_RRR2_MADDS_32: 6669 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6670 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6671 break; 6672 case OPC2_32_RRR2_MADDS_64: 6673 CHECK_REG_PAIR(r4); 6674 CHECK_REG_PAIR(r3); 6675 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6676 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6677 break; 6678 case OPC2_32_RRR2_MADD_U_64: 6679 CHECK_REG_PAIR(r4); 6680 CHECK_REG_PAIR(r3); 6681 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6682 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6683 break; 6684 case OPC2_32_RRR2_MADDS_U_32: 6685 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6686 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6687 break; 6688 case OPC2_32_RRR2_MADDS_U_64: 6689 CHECK_REG_PAIR(r4); 6690 CHECK_REG_PAIR(r3); 6691 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6692 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6693 break; 6694 default: 6695 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6696 } 6697 } 6698 6699 static void decode_rrr2_msub(DisasContext *ctx) 6700 { 6701 uint32_t op2; 6702 uint32_t r1, r2, r3, r4; 6703 6704 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6705 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6706 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6707 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6708 r4 = MASK_OP_RRR2_D(ctx->opcode); 6709 6710 switch (op2) { 6711 case OPC2_32_RRR2_MSUB_32: 6712 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6713 cpu_gpr_d[r2]); 6714 break; 6715 case OPC2_32_RRR2_MSUB_64: 6716 CHECK_REG_PAIR(r4); 6717 CHECK_REG_PAIR(r3); 6718 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6719 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6720 break; 6721 case OPC2_32_RRR2_MSUBS_32: 6722 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6723 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6724 break; 6725 case OPC2_32_RRR2_MSUBS_64: 6726 CHECK_REG_PAIR(r4); 6727 CHECK_REG_PAIR(r3); 6728 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6729 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6730 break; 6731 case OPC2_32_RRR2_MSUB_U_64: 6732 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6733 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6734 break; 6735 case OPC2_32_RRR2_MSUBS_U_32: 6736 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6737 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6738 break; 6739 case OPC2_32_RRR2_MSUBS_U_64: 6740 CHECK_REG_PAIR(r4); 6741 CHECK_REG_PAIR(r3); 6742 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6743 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6744 break; 6745 default: 6746 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6747 } 6748 } 6749 6750 /* RRR1 format */ 6751 static void decode_rrr1_madd(DisasContext *ctx) 6752 { 6753 uint32_t op2; 6754 uint32_t r1, r2, r3, r4, n; 6755 6756 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6757 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6758 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6759 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6760 r4 = MASK_OP_RRR1_D(ctx->opcode); 6761 n = MASK_OP_RRR1_N(ctx->opcode); 6762 6763 switch (op2) { 6764 case OPC2_32_RRR1_MADD_H_LL: 6765 CHECK_REG_PAIR(r4); 6766 CHECK_REG_PAIR(r3); 6767 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6768 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6769 break; 6770 case OPC2_32_RRR1_MADD_H_LU: 6771 CHECK_REG_PAIR(r4); 6772 CHECK_REG_PAIR(r3); 6773 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6774 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6775 break; 6776 case OPC2_32_RRR1_MADD_H_UL: 6777 CHECK_REG_PAIR(r4); 6778 CHECK_REG_PAIR(r3); 6779 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6780 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6781 break; 6782 case OPC2_32_RRR1_MADD_H_UU: 6783 CHECK_REG_PAIR(r4); 6784 CHECK_REG_PAIR(r3); 6785 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6786 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6787 break; 6788 case OPC2_32_RRR1_MADDS_H_LL: 6789 CHECK_REG_PAIR(r4); 6790 CHECK_REG_PAIR(r3); 6791 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6792 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6793 break; 6794 case OPC2_32_RRR1_MADDS_H_LU: 6795 CHECK_REG_PAIR(r4); 6796 CHECK_REG_PAIR(r3); 6797 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6798 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6799 break; 6800 case OPC2_32_RRR1_MADDS_H_UL: 6801 CHECK_REG_PAIR(r4); 6802 CHECK_REG_PAIR(r3); 6803 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6804 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6805 break; 6806 case OPC2_32_RRR1_MADDS_H_UU: 6807 CHECK_REG_PAIR(r4); 6808 CHECK_REG_PAIR(r3); 6809 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6810 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6811 break; 6812 case OPC2_32_RRR1_MADDM_H_LL: 6813 CHECK_REG_PAIR(r4); 6814 CHECK_REG_PAIR(r3); 6815 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6816 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6817 break; 6818 case OPC2_32_RRR1_MADDM_H_LU: 6819 CHECK_REG_PAIR(r4); 6820 CHECK_REG_PAIR(r3); 6821 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6822 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6823 break; 6824 case OPC2_32_RRR1_MADDM_H_UL: 6825 CHECK_REG_PAIR(r4); 6826 CHECK_REG_PAIR(r3); 6827 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6828 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6829 break; 6830 case OPC2_32_RRR1_MADDM_H_UU: 6831 CHECK_REG_PAIR(r4); 6832 CHECK_REG_PAIR(r3); 6833 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6834 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6835 break; 6836 case OPC2_32_RRR1_MADDMS_H_LL: 6837 CHECK_REG_PAIR(r4); 6838 CHECK_REG_PAIR(r3); 6839 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6840 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6841 break; 6842 case OPC2_32_RRR1_MADDMS_H_LU: 6843 CHECK_REG_PAIR(r4); 6844 CHECK_REG_PAIR(r3); 6845 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6846 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6847 break; 6848 case OPC2_32_RRR1_MADDMS_H_UL: 6849 CHECK_REG_PAIR(r4); 6850 CHECK_REG_PAIR(r3); 6851 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6852 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6853 break; 6854 case OPC2_32_RRR1_MADDMS_H_UU: 6855 CHECK_REG_PAIR(r4); 6856 CHECK_REG_PAIR(r3); 6857 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6858 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6859 break; 6860 case OPC2_32_RRR1_MADDR_H_LL: 6861 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6862 cpu_gpr_d[r2], n, MODE_LL); 6863 break; 6864 case OPC2_32_RRR1_MADDR_H_LU: 6865 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6866 cpu_gpr_d[r2], n, MODE_LU); 6867 break; 6868 case OPC2_32_RRR1_MADDR_H_UL: 6869 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6870 cpu_gpr_d[r2], n, MODE_UL); 6871 break; 6872 case OPC2_32_RRR1_MADDR_H_UU: 6873 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6874 cpu_gpr_d[r2], n, MODE_UU); 6875 break; 6876 case OPC2_32_RRR1_MADDRS_H_LL: 6877 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6878 cpu_gpr_d[r2], n, MODE_LL); 6879 break; 6880 case OPC2_32_RRR1_MADDRS_H_LU: 6881 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6882 cpu_gpr_d[r2], n, MODE_LU); 6883 break; 6884 case OPC2_32_RRR1_MADDRS_H_UL: 6885 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6886 cpu_gpr_d[r2], n, MODE_UL); 6887 break; 6888 case OPC2_32_RRR1_MADDRS_H_UU: 6889 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6890 cpu_gpr_d[r2], n, MODE_UU); 6891 break; 6892 default: 6893 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6894 } 6895 } 6896 6897 static void decode_rrr1_maddq_h(DisasContext *ctx) 6898 { 6899 uint32_t op2; 6900 uint32_t r1, r2, r3, r4, n; 6901 TCGv temp, temp2; 6902 6903 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6904 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6905 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6906 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6907 r4 = MASK_OP_RRR1_D(ctx->opcode); 6908 n = MASK_OP_RRR1_N(ctx->opcode); 6909 6910 temp = tcg_temp_new(); 6911 temp2 = tcg_temp_new(); 6912 6913 switch (op2) { 6914 case OPC2_32_RRR1_MADD_Q_32: 6915 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6916 cpu_gpr_d[r2], n, 32); 6917 break; 6918 case OPC2_32_RRR1_MADD_Q_64: 6919 CHECK_REG_PAIR(r4); 6920 CHECK_REG_PAIR(r3); 6921 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6922 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6923 n); 6924 break; 6925 case OPC2_32_RRR1_MADD_Q_32_L: 6926 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6927 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6928 temp, n, 16); 6929 break; 6930 case OPC2_32_RRR1_MADD_Q_64_L: 6931 CHECK_REG_PAIR(r4); 6932 CHECK_REG_PAIR(r3); 6933 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6934 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6935 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 6936 n); 6937 break; 6938 case OPC2_32_RRR1_MADD_Q_32_U: 6939 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6940 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6941 temp, n, 16); 6942 break; 6943 case OPC2_32_RRR1_MADD_Q_64_U: 6944 CHECK_REG_PAIR(r4); 6945 CHECK_REG_PAIR(r3); 6946 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6947 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6948 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 6949 n); 6950 break; 6951 case OPC2_32_RRR1_MADD_Q_32_LL: 6952 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6953 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6954 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 6955 break; 6956 case OPC2_32_RRR1_MADD_Q_64_LL: 6957 CHECK_REG_PAIR(r4); 6958 CHECK_REG_PAIR(r3); 6959 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6960 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6961 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6962 cpu_gpr_d[r3+1], temp, temp2, n); 6963 break; 6964 case OPC2_32_RRR1_MADD_Q_32_UU: 6965 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6966 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6967 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 6968 break; 6969 case OPC2_32_RRR1_MADD_Q_64_UU: 6970 CHECK_REG_PAIR(r4); 6971 CHECK_REG_PAIR(r3); 6972 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6973 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6974 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6975 cpu_gpr_d[r3+1], temp, temp2, n); 6976 break; 6977 case OPC2_32_RRR1_MADDS_Q_32: 6978 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6979 cpu_gpr_d[r2], n, 32); 6980 break; 6981 case OPC2_32_RRR1_MADDS_Q_64: 6982 CHECK_REG_PAIR(r4); 6983 CHECK_REG_PAIR(r3); 6984 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6985 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6986 n); 6987 break; 6988 case OPC2_32_RRR1_MADDS_Q_32_L: 6989 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6990 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6991 temp, n, 16); 6992 break; 6993 case OPC2_32_RRR1_MADDS_Q_64_L: 6994 CHECK_REG_PAIR(r4); 6995 CHECK_REG_PAIR(r3); 6996 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6997 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6998 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 6999 n); 7000 break; 7001 case OPC2_32_RRR1_MADDS_Q_32_U: 7002 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7003 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7004 temp, n, 16); 7005 break; 7006 case OPC2_32_RRR1_MADDS_Q_64_U: 7007 CHECK_REG_PAIR(r4); 7008 CHECK_REG_PAIR(r3); 7009 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7010 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7011 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7012 n); 7013 break; 7014 case OPC2_32_RRR1_MADDS_Q_32_LL: 7015 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7016 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7017 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7018 break; 7019 case OPC2_32_RRR1_MADDS_Q_64_LL: 7020 CHECK_REG_PAIR(r4); 7021 CHECK_REG_PAIR(r3); 7022 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7023 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7024 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7025 cpu_gpr_d[r3+1], temp, temp2, n); 7026 break; 7027 case OPC2_32_RRR1_MADDS_Q_32_UU: 7028 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7029 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7030 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7031 break; 7032 case OPC2_32_RRR1_MADDS_Q_64_UU: 7033 CHECK_REG_PAIR(r4); 7034 CHECK_REG_PAIR(r3); 7035 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7036 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7037 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7038 cpu_gpr_d[r3+1], temp, temp2, n); 7039 break; 7040 case OPC2_32_RRR1_MADDR_H_64_UL: 7041 CHECK_REG_PAIR(r3); 7042 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7043 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7044 break; 7045 case OPC2_32_RRR1_MADDRS_H_64_UL: 7046 CHECK_REG_PAIR(r3); 7047 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7048 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7049 break; 7050 case OPC2_32_RRR1_MADDR_Q_32_LL: 7051 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7052 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7053 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7054 break; 7055 case OPC2_32_RRR1_MADDR_Q_32_UU: 7056 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7057 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7058 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7059 break; 7060 case OPC2_32_RRR1_MADDRS_Q_32_LL: 7061 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7062 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7063 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7064 break; 7065 case OPC2_32_RRR1_MADDRS_Q_32_UU: 7066 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7067 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7068 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7069 break; 7070 default: 7071 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7072 } 7073 } 7074 7075 static void decode_rrr1_maddsu_h(DisasContext *ctx) 7076 { 7077 uint32_t op2; 7078 uint32_t r1, r2, r3, r4, n; 7079 7080 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7081 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7082 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7083 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7084 r4 = MASK_OP_RRR1_D(ctx->opcode); 7085 n = MASK_OP_RRR1_N(ctx->opcode); 7086 7087 switch (op2) { 7088 case OPC2_32_RRR1_MADDSU_H_32_LL: 7089 CHECK_REG_PAIR(r4); 7090 CHECK_REG_PAIR(r3); 7091 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7092 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7093 break; 7094 case OPC2_32_RRR1_MADDSU_H_32_LU: 7095 CHECK_REG_PAIR(r4); 7096 CHECK_REG_PAIR(r3); 7097 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7098 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7099 break; 7100 case OPC2_32_RRR1_MADDSU_H_32_UL: 7101 CHECK_REG_PAIR(r4); 7102 CHECK_REG_PAIR(r3); 7103 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7104 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7105 break; 7106 case OPC2_32_RRR1_MADDSU_H_32_UU: 7107 CHECK_REG_PAIR(r4); 7108 CHECK_REG_PAIR(r3); 7109 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7110 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7111 break; 7112 case OPC2_32_RRR1_MADDSUS_H_32_LL: 7113 CHECK_REG_PAIR(r4); 7114 CHECK_REG_PAIR(r3); 7115 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7116 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7117 n, MODE_LL); 7118 break; 7119 case OPC2_32_RRR1_MADDSUS_H_32_LU: 7120 CHECK_REG_PAIR(r4); 7121 CHECK_REG_PAIR(r3); 7122 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7123 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7124 n, MODE_LU); 7125 break; 7126 case OPC2_32_RRR1_MADDSUS_H_32_UL: 7127 CHECK_REG_PAIR(r4); 7128 CHECK_REG_PAIR(r3); 7129 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7130 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7131 n, MODE_UL); 7132 break; 7133 case OPC2_32_RRR1_MADDSUS_H_32_UU: 7134 CHECK_REG_PAIR(r4); 7135 CHECK_REG_PAIR(r3); 7136 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7137 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7138 n, MODE_UU); 7139 break; 7140 case OPC2_32_RRR1_MADDSUM_H_64_LL: 7141 CHECK_REG_PAIR(r4); 7142 CHECK_REG_PAIR(r3); 7143 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7144 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7145 n, MODE_LL); 7146 break; 7147 case OPC2_32_RRR1_MADDSUM_H_64_LU: 7148 CHECK_REG_PAIR(r4); 7149 CHECK_REG_PAIR(r3); 7150 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7151 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7152 n, MODE_LU); 7153 break; 7154 case OPC2_32_RRR1_MADDSUM_H_64_UL: 7155 CHECK_REG_PAIR(r4); 7156 CHECK_REG_PAIR(r3); 7157 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7158 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7159 n, MODE_UL); 7160 break; 7161 case OPC2_32_RRR1_MADDSUM_H_64_UU: 7162 CHECK_REG_PAIR(r4); 7163 CHECK_REG_PAIR(r3); 7164 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7165 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7166 n, MODE_UU); 7167 break; 7168 case OPC2_32_RRR1_MADDSUMS_H_64_LL: 7169 CHECK_REG_PAIR(r4); 7170 CHECK_REG_PAIR(r3); 7171 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7172 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7173 n, MODE_LL); 7174 break; 7175 case OPC2_32_RRR1_MADDSUMS_H_64_LU: 7176 CHECK_REG_PAIR(r4); 7177 CHECK_REG_PAIR(r3); 7178 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7179 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7180 n, MODE_LU); 7181 break; 7182 case OPC2_32_RRR1_MADDSUMS_H_64_UL: 7183 CHECK_REG_PAIR(r4); 7184 CHECK_REG_PAIR(r3); 7185 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7186 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7187 n, MODE_UL); 7188 break; 7189 case OPC2_32_RRR1_MADDSUMS_H_64_UU: 7190 CHECK_REG_PAIR(r4); 7191 CHECK_REG_PAIR(r3); 7192 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7193 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7194 n, MODE_UU); 7195 break; 7196 case OPC2_32_RRR1_MADDSUR_H_16_LL: 7197 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7198 cpu_gpr_d[r2], n, MODE_LL); 7199 break; 7200 case OPC2_32_RRR1_MADDSUR_H_16_LU: 7201 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7202 cpu_gpr_d[r2], n, MODE_LU); 7203 break; 7204 case OPC2_32_RRR1_MADDSUR_H_16_UL: 7205 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7206 cpu_gpr_d[r2], n, MODE_UL); 7207 break; 7208 case OPC2_32_RRR1_MADDSUR_H_16_UU: 7209 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7210 cpu_gpr_d[r2], n, MODE_UU); 7211 break; 7212 case OPC2_32_RRR1_MADDSURS_H_16_LL: 7213 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7214 cpu_gpr_d[r2], n, MODE_LL); 7215 break; 7216 case OPC2_32_RRR1_MADDSURS_H_16_LU: 7217 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7218 cpu_gpr_d[r2], n, MODE_LU); 7219 break; 7220 case OPC2_32_RRR1_MADDSURS_H_16_UL: 7221 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7222 cpu_gpr_d[r2], n, MODE_UL); 7223 break; 7224 case OPC2_32_RRR1_MADDSURS_H_16_UU: 7225 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7226 cpu_gpr_d[r2], n, MODE_UU); 7227 break; 7228 default: 7229 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7230 } 7231 } 7232 7233 static void decode_rrr1_msub(DisasContext *ctx) 7234 { 7235 uint32_t op2; 7236 uint32_t r1, r2, r3, r4, n; 7237 7238 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7239 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7240 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7241 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7242 r4 = MASK_OP_RRR1_D(ctx->opcode); 7243 n = MASK_OP_RRR1_N(ctx->opcode); 7244 7245 switch (op2) { 7246 case OPC2_32_RRR1_MSUB_H_LL: 7247 CHECK_REG_PAIR(r4); 7248 CHECK_REG_PAIR(r3); 7249 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7250 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7251 break; 7252 case OPC2_32_RRR1_MSUB_H_LU: 7253 CHECK_REG_PAIR(r4); 7254 CHECK_REG_PAIR(r3); 7255 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7256 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7257 break; 7258 case OPC2_32_RRR1_MSUB_H_UL: 7259 CHECK_REG_PAIR(r4); 7260 CHECK_REG_PAIR(r3); 7261 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7262 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7263 break; 7264 case OPC2_32_RRR1_MSUB_H_UU: 7265 CHECK_REG_PAIR(r4); 7266 CHECK_REG_PAIR(r3); 7267 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7268 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7269 break; 7270 case OPC2_32_RRR1_MSUBS_H_LL: 7271 CHECK_REG_PAIR(r4); 7272 CHECK_REG_PAIR(r3); 7273 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7274 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7275 break; 7276 case OPC2_32_RRR1_MSUBS_H_LU: 7277 CHECK_REG_PAIR(r4); 7278 CHECK_REG_PAIR(r3); 7279 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7280 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7281 break; 7282 case OPC2_32_RRR1_MSUBS_H_UL: 7283 CHECK_REG_PAIR(r4); 7284 CHECK_REG_PAIR(r3); 7285 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7286 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7287 break; 7288 case OPC2_32_RRR1_MSUBS_H_UU: 7289 CHECK_REG_PAIR(r4); 7290 CHECK_REG_PAIR(r3); 7291 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7292 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7293 break; 7294 case OPC2_32_RRR1_MSUBM_H_LL: 7295 CHECK_REG_PAIR(r4); 7296 CHECK_REG_PAIR(r3); 7297 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7298 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7299 break; 7300 case OPC2_32_RRR1_MSUBM_H_LU: 7301 CHECK_REG_PAIR(r4); 7302 CHECK_REG_PAIR(r3); 7303 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7304 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7305 break; 7306 case OPC2_32_RRR1_MSUBM_H_UL: 7307 CHECK_REG_PAIR(r4); 7308 CHECK_REG_PAIR(r3); 7309 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7310 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7311 break; 7312 case OPC2_32_RRR1_MSUBM_H_UU: 7313 CHECK_REG_PAIR(r4); 7314 CHECK_REG_PAIR(r3); 7315 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7316 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7317 break; 7318 case OPC2_32_RRR1_MSUBMS_H_LL: 7319 CHECK_REG_PAIR(r4); 7320 CHECK_REG_PAIR(r3); 7321 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7322 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7323 break; 7324 case OPC2_32_RRR1_MSUBMS_H_LU: 7325 CHECK_REG_PAIR(r4); 7326 CHECK_REG_PAIR(r3); 7327 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7328 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7329 break; 7330 case OPC2_32_RRR1_MSUBMS_H_UL: 7331 CHECK_REG_PAIR(r4); 7332 CHECK_REG_PAIR(r3); 7333 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7334 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7335 break; 7336 case OPC2_32_RRR1_MSUBMS_H_UU: 7337 CHECK_REG_PAIR(r4); 7338 CHECK_REG_PAIR(r3); 7339 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7340 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7341 break; 7342 case OPC2_32_RRR1_MSUBR_H_LL: 7343 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7344 cpu_gpr_d[r2], n, MODE_LL); 7345 break; 7346 case OPC2_32_RRR1_MSUBR_H_LU: 7347 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7348 cpu_gpr_d[r2], n, MODE_LU); 7349 break; 7350 case OPC2_32_RRR1_MSUBR_H_UL: 7351 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7352 cpu_gpr_d[r2], n, MODE_UL); 7353 break; 7354 case OPC2_32_RRR1_MSUBR_H_UU: 7355 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7356 cpu_gpr_d[r2], n, MODE_UU); 7357 break; 7358 case OPC2_32_RRR1_MSUBRS_H_LL: 7359 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7360 cpu_gpr_d[r2], n, MODE_LL); 7361 break; 7362 case OPC2_32_RRR1_MSUBRS_H_LU: 7363 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7364 cpu_gpr_d[r2], n, MODE_LU); 7365 break; 7366 case OPC2_32_RRR1_MSUBRS_H_UL: 7367 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7368 cpu_gpr_d[r2], n, MODE_UL); 7369 break; 7370 case OPC2_32_RRR1_MSUBRS_H_UU: 7371 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7372 cpu_gpr_d[r2], n, MODE_UU); 7373 break; 7374 default: 7375 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7376 } 7377 } 7378 7379 static void decode_rrr1_msubq_h(DisasContext *ctx) 7380 { 7381 uint32_t op2; 7382 uint32_t r1, r2, r3, r4, n; 7383 TCGv temp, temp2; 7384 7385 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7386 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7387 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7388 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7389 r4 = MASK_OP_RRR1_D(ctx->opcode); 7390 n = MASK_OP_RRR1_N(ctx->opcode); 7391 7392 temp = tcg_temp_new(); 7393 temp2 = tcg_temp_new(); 7394 7395 switch (op2) { 7396 case OPC2_32_RRR1_MSUB_Q_32: 7397 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7398 cpu_gpr_d[r2], n, 32); 7399 break; 7400 case OPC2_32_RRR1_MSUB_Q_64: 7401 CHECK_REG_PAIR(r4); 7402 CHECK_REG_PAIR(r3); 7403 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7404 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7405 n); 7406 break; 7407 case OPC2_32_RRR1_MSUB_Q_32_L: 7408 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7409 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7410 temp, n, 16); 7411 break; 7412 case OPC2_32_RRR1_MSUB_Q_64_L: 7413 CHECK_REG_PAIR(r4); 7414 CHECK_REG_PAIR(r3); 7415 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7416 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7417 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7418 n); 7419 break; 7420 case OPC2_32_RRR1_MSUB_Q_32_U: 7421 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7422 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7423 temp, n, 16); 7424 break; 7425 case OPC2_32_RRR1_MSUB_Q_64_U: 7426 CHECK_REG_PAIR(r4); 7427 CHECK_REG_PAIR(r3); 7428 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7429 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7430 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7431 n); 7432 break; 7433 case OPC2_32_RRR1_MSUB_Q_32_LL: 7434 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7435 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7436 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7437 break; 7438 case OPC2_32_RRR1_MSUB_Q_64_LL: 7439 CHECK_REG_PAIR(r4); 7440 CHECK_REG_PAIR(r3); 7441 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7442 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7443 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7444 cpu_gpr_d[r3+1], temp, temp2, n); 7445 break; 7446 case OPC2_32_RRR1_MSUB_Q_32_UU: 7447 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7448 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7449 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7450 break; 7451 case OPC2_32_RRR1_MSUB_Q_64_UU: 7452 CHECK_REG_PAIR(r4); 7453 CHECK_REG_PAIR(r3); 7454 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7455 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7456 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7457 cpu_gpr_d[r3+1], temp, temp2, n); 7458 break; 7459 case OPC2_32_RRR1_MSUBS_Q_32: 7460 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7461 cpu_gpr_d[r2], n, 32); 7462 break; 7463 case OPC2_32_RRR1_MSUBS_Q_64: 7464 CHECK_REG_PAIR(r4); 7465 CHECK_REG_PAIR(r3); 7466 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7467 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7468 n); 7469 break; 7470 case OPC2_32_RRR1_MSUBS_Q_32_L: 7471 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7472 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7473 temp, n, 16); 7474 break; 7475 case OPC2_32_RRR1_MSUBS_Q_64_L: 7476 CHECK_REG_PAIR(r4); 7477 CHECK_REG_PAIR(r3); 7478 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7479 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7480 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7481 n); 7482 break; 7483 case OPC2_32_RRR1_MSUBS_Q_32_U: 7484 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7485 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7486 temp, n, 16); 7487 break; 7488 case OPC2_32_RRR1_MSUBS_Q_64_U: 7489 CHECK_REG_PAIR(r4); 7490 CHECK_REG_PAIR(r3); 7491 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7492 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7493 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7494 n); 7495 break; 7496 case OPC2_32_RRR1_MSUBS_Q_32_LL: 7497 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7498 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7499 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7500 break; 7501 case OPC2_32_RRR1_MSUBS_Q_64_LL: 7502 CHECK_REG_PAIR(r4); 7503 CHECK_REG_PAIR(r3); 7504 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7505 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7506 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7507 cpu_gpr_d[r3+1], temp, temp2, n); 7508 break; 7509 case OPC2_32_RRR1_MSUBS_Q_32_UU: 7510 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7511 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7512 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7513 break; 7514 case OPC2_32_RRR1_MSUBS_Q_64_UU: 7515 CHECK_REG_PAIR(r4); 7516 CHECK_REG_PAIR(r3); 7517 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7518 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7519 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7520 cpu_gpr_d[r3+1], temp, temp2, n); 7521 break; 7522 case OPC2_32_RRR1_MSUBR_H_64_UL: 7523 CHECK_REG_PAIR(r3); 7524 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7525 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7526 break; 7527 case OPC2_32_RRR1_MSUBRS_H_64_UL: 7528 CHECK_REG_PAIR(r3); 7529 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7530 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7531 break; 7532 case OPC2_32_RRR1_MSUBR_Q_32_LL: 7533 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7534 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7535 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7536 break; 7537 case OPC2_32_RRR1_MSUBR_Q_32_UU: 7538 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7539 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7540 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7541 break; 7542 case OPC2_32_RRR1_MSUBRS_Q_32_LL: 7543 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7544 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7545 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7546 break; 7547 case OPC2_32_RRR1_MSUBRS_Q_32_UU: 7548 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7549 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7550 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7551 break; 7552 default: 7553 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7554 } 7555 } 7556 7557 static void decode_rrr1_msubad_h(DisasContext *ctx) 7558 { 7559 uint32_t op2; 7560 uint32_t r1, r2, r3, r4, n; 7561 7562 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7563 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7564 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7565 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7566 r4 = MASK_OP_RRR1_D(ctx->opcode); 7567 n = MASK_OP_RRR1_N(ctx->opcode); 7568 7569 switch (op2) { 7570 case OPC2_32_RRR1_MSUBAD_H_32_LL: 7571 CHECK_REG_PAIR(r4); 7572 CHECK_REG_PAIR(r3); 7573 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7574 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7575 break; 7576 case OPC2_32_RRR1_MSUBAD_H_32_LU: 7577 CHECK_REG_PAIR(r4); 7578 CHECK_REG_PAIR(r3); 7579 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7580 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7581 break; 7582 case OPC2_32_RRR1_MSUBAD_H_32_UL: 7583 CHECK_REG_PAIR(r4); 7584 CHECK_REG_PAIR(r3); 7585 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7586 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7587 break; 7588 case OPC2_32_RRR1_MSUBAD_H_32_UU: 7589 CHECK_REG_PAIR(r4); 7590 CHECK_REG_PAIR(r3); 7591 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7592 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7593 break; 7594 case OPC2_32_RRR1_MSUBADS_H_32_LL: 7595 CHECK_REG_PAIR(r4); 7596 CHECK_REG_PAIR(r3); 7597 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7598 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7599 n, MODE_LL); 7600 break; 7601 case OPC2_32_RRR1_MSUBADS_H_32_LU: 7602 CHECK_REG_PAIR(r4); 7603 CHECK_REG_PAIR(r3); 7604 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7605 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7606 n, MODE_LU); 7607 break; 7608 case OPC2_32_RRR1_MSUBADS_H_32_UL: 7609 CHECK_REG_PAIR(r4); 7610 CHECK_REG_PAIR(r3); 7611 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7612 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7613 n, MODE_UL); 7614 break; 7615 case OPC2_32_RRR1_MSUBADS_H_32_UU: 7616 CHECK_REG_PAIR(r4); 7617 CHECK_REG_PAIR(r3); 7618 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7619 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7620 n, MODE_UU); 7621 break; 7622 case OPC2_32_RRR1_MSUBADM_H_64_LL: 7623 CHECK_REG_PAIR(r4); 7624 CHECK_REG_PAIR(r3); 7625 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7626 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7627 n, MODE_LL); 7628 break; 7629 case OPC2_32_RRR1_MSUBADM_H_64_LU: 7630 CHECK_REG_PAIR(r4); 7631 CHECK_REG_PAIR(r3); 7632 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7633 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7634 n, MODE_LU); 7635 break; 7636 case OPC2_32_RRR1_MSUBADM_H_64_UL: 7637 CHECK_REG_PAIR(r4); 7638 CHECK_REG_PAIR(r3); 7639 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7640 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7641 n, MODE_UL); 7642 break; 7643 case OPC2_32_RRR1_MSUBADM_H_64_UU: 7644 CHECK_REG_PAIR(r4); 7645 CHECK_REG_PAIR(r3); 7646 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7647 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7648 n, MODE_UU); 7649 break; 7650 case OPC2_32_RRR1_MSUBADMS_H_64_LL: 7651 CHECK_REG_PAIR(r4); 7652 CHECK_REG_PAIR(r3); 7653 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7654 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7655 n, MODE_LL); 7656 break; 7657 case OPC2_32_RRR1_MSUBADMS_H_64_LU: 7658 CHECK_REG_PAIR(r4); 7659 CHECK_REG_PAIR(r3); 7660 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7661 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7662 n, MODE_LU); 7663 break; 7664 case OPC2_32_RRR1_MSUBADMS_H_64_UL: 7665 CHECK_REG_PAIR(r4); 7666 CHECK_REG_PAIR(r3); 7667 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7668 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7669 n, MODE_UL); 7670 break; 7671 case OPC2_32_RRR1_MSUBADMS_H_64_UU: 7672 CHECK_REG_PAIR(r4); 7673 CHECK_REG_PAIR(r3); 7674 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7675 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7676 n, MODE_UU); 7677 break; 7678 case OPC2_32_RRR1_MSUBADR_H_16_LL: 7679 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7680 cpu_gpr_d[r2], n, MODE_LL); 7681 break; 7682 case OPC2_32_RRR1_MSUBADR_H_16_LU: 7683 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7684 cpu_gpr_d[r2], n, MODE_LU); 7685 break; 7686 case OPC2_32_RRR1_MSUBADR_H_16_UL: 7687 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7688 cpu_gpr_d[r2], n, MODE_UL); 7689 break; 7690 case OPC2_32_RRR1_MSUBADR_H_16_UU: 7691 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7692 cpu_gpr_d[r2], n, MODE_UU); 7693 break; 7694 case OPC2_32_RRR1_MSUBADRS_H_16_LL: 7695 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7696 cpu_gpr_d[r2], n, MODE_LL); 7697 break; 7698 case OPC2_32_RRR1_MSUBADRS_H_16_LU: 7699 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7700 cpu_gpr_d[r2], n, MODE_LU); 7701 break; 7702 case OPC2_32_RRR1_MSUBADRS_H_16_UL: 7703 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7704 cpu_gpr_d[r2], n, MODE_UL); 7705 break; 7706 case OPC2_32_RRR1_MSUBADRS_H_16_UU: 7707 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7708 cpu_gpr_d[r2], n, MODE_UU); 7709 break; 7710 default: 7711 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7712 } 7713 } 7714 7715 /* RRRR format */ 7716 static void decode_rrrr_extract_insert(DisasContext *ctx) 7717 { 7718 uint32_t op2; 7719 int r1, r2, r3, r4; 7720 TCGv tmp_width, tmp_pos; 7721 7722 r1 = MASK_OP_RRRR_S1(ctx->opcode); 7723 r2 = MASK_OP_RRRR_S2(ctx->opcode); 7724 r3 = MASK_OP_RRRR_S3(ctx->opcode); 7725 r4 = MASK_OP_RRRR_D(ctx->opcode); 7726 op2 = MASK_OP_RRRR_OP2(ctx->opcode); 7727 7728 tmp_pos = tcg_temp_new(); 7729 tmp_width = tcg_temp_new(); 7730 7731 switch (op2) { 7732 case OPC2_32_RRRR_DEXTR: 7733 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7734 if (r1 == r2) { 7735 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7736 } else { 7737 TCGv msw = tcg_temp_new(); 7738 TCGv zero = tcg_constant_tl(0); 7739 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); 7740 tcg_gen_subfi_tl(msw, 32, tmp_pos); 7741 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw); 7742 /* 7743 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined 7744 * behaviour. So check that case here and set the low bits to zero 7745 * which effectivly returns cpu_gpr_d[r1] 7746 */ 7747 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); 7748 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); 7749 } 7750 break; 7751 case OPC2_32_RRRR_EXTR: 7752 case OPC2_32_RRRR_EXTR_U: 7753 CHECK_REG_PAIR(r3); 7754 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7755 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7756 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); 7757 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 7758 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7759 tcg_gen_subfi_tl(tmp_width, 32, tmp_width); 7760 if (op2 == OPC2_32_RRRR_EXTR) { 7761 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7762 } else { 7763 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7764 } 7765 break; 7766 case OPC2_32_RRRR_INSERT: 7767 CHECK_REG_PAIR(r3); 7768 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7769 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7770 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, 7771 tmp_pos); 7772 break; 7773 default: 7774 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7775 } 7776 } 7777 7778 /* RRRW format */ 7779 static void decode_rrrw_extract_insert(DisasContext *ctx) 7780 { 7781 uint32_t op2; 7782 int r1, r2, r3, r4; 7783 int32_t width; 7784 7785 TCGv temp, temp2; 7786 7787 op2 = MASK_OP_RRRW_OP2(ctx->opcode); 7788 r1 = MASK_OP_RRRW_S1(ctx->opcode); 7789 r2 = MASK_OP_RRRW_S2(ctx->opcode); 7790 r3 = MASK_OP_RRRW_S3(ctx->opcode); 7791 r4 = MASK_OP_RRRW_D(ctx->opcode); 7792 width = MASK_OP_RRRW_WIDTH(ctx->opcode); 7793 7794 temp = tcg_temp_new(); 7795 7796 switch (op2) { 7797 case OPC2_32_RRRW_EXTR: 7798 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7799 tcg_gen_addi_tl(temp, temp, width); 7800 tcg_gen_subfi_tl(temp, 32, temp); 7801 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7802 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); 7803 break; 7804 case OPC2_32_RRRW_EXTR_U: 7805 if (width == 0) { 7806 tcg_gen_movi_tl(cpu_gpr_d[r4], 0); 7807 } else { 7808 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7809 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7810 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); 7811 } 7812 break; 7813 case OPC2_32_RRRW_IMASK: 7814 temp2 = tcg_temp_new(); 7815 7816 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7817 tcg_gen_movi_tl(temp2, (1 << width) - 1); 7818 tcg_gen_shl_tl(temp2, temp2, temp); 7819 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); 7820 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); 7821 break; 7822 case OPC2_32_RRRW_INSERT: 7823 temp2 = tcg_temp_new(); 7824 7825 tcg_gen_movi_tl(temp, width); 7826 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); 7827 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); 7828 break; 7829 default: 7830 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7831 } 7832 } 7833 7834 /* SYS Format*/ 7835 static void decode_sys_interrupts(DisasContext *ctx) 7836 { 7837 uint32_t op2; 7838 uint32_t r1; 7839 TCGLabel *l1; 7840 TCGv tmp; 7841 7842 op2 = MASK_OP_SYS_OP2(ctx->opcode); 7843 r1 = MASK_OP_SYS_S1D(ctx->opcode); 7844 7845 switch (op2) { 7846 case OPC2_32_SYS_DEBUG: 7847 /* raise EXCP_DEBUG */ 7848 break; 7849 case OPC2_32_SYS_DISABLE: 7850 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); 7851 break; 7852 case OPC2_32_SYS_DSYNC: 7853 break; 7854 case OPC2_32_SYS_ENABLE: 7855 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3); 7856 break; 7857 case OPC2_32_SYS_ISYNC: 7858 break; 7859 case OPC2_32_SYS_NOP: 7860 break; 7861 case OPC2_32_SYS_RET: 7862 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 7863 break; 7864 case OPC2_32_SYS_FRET: 7865 gen_fret(ctx); 7866 break; 7867 case OPC2_32_SYS_RFE: 7868 gen_helper_rfe(cpu_env); 7869 tcg_gen_exit_tb(NULL, 0); 7870 ctx->base.is_jmp = DISAS_NORETURN; 7871 break; 7872 case OPC2_32_SYS_RFM: 7873 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 7874 tmp = tcg_temp_new(); 7875 l1 = gen_new_label(); 7876 7877 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR)); 7878 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); 7879 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); 7880 gen_helper_rfm(cpu_env); 7881 gen_set_label(l1); 7882 tcg_gen_exit_tb(NULL, 0); 7883 ctx->base.is_jmp = DISAS_NORETURN; 7884 } else { 7885 /* generate privilege trap */ 7886 } 7887 break; 7888 case OPC2_32_SYS_RSLCX: 7889 gen_helper_rslcx(cpu_env); 7890 break; 7891 case OPC2_32_SYS_SVLCX: 7892 gen_helper_svlcx(cpu_env); 7893 break; 7894 case OPC2_32_SYS_RESTORE: 7895 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7896 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM || 7897 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) { 7898 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); 7899 } /* else raise privilege trap */ 7900 } else { 7901 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7902 } 7903 break; 7904 case OPC2_32_SYS_TRAPSV: 7905 l1 = gen_new_label(); 7906 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); 7907 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); 7908 gen_set_label(l1); 7909 break; 7910 case OPC2_32_SYS_TRAPV: 7911 l1 = gen_new_label(); 7912 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); 7913 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); 7914 gen_set_label(l1); 7915 break; 7916 default: 7917 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7918 } 7919 } 7920 7921 static void decode_32Bit_opc(DisasContext *ctx) 7922 { 7923 int op1; 7924 int32_t r1, r2, r3; 7925 int32_t address, const16; 7926 int8_t b, const4; 7927 int32_t bpos; 7928 TCGv temp, temp2, temp3; 7929 7930 op1 = MASK_OP_MAJOR(ctx->opcode); 7931 7932 /* handle JNZ.T opcode only being 7 bit long */ 7933 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { 7934 op1 = OPCM_32_BRN_JTT; 7935 } 7936 7937 switch (op1) { 7938 /* ABS-format */ 7939 case OPCM_32_ABS_LDW: 7940 decode_abs_ldw(ctx); 7941 break; 7942 case OPCM_32_ABS_LDB: 7943 decode_abs_ldb(ctx); 7944 break; 7945 case OPCM_32_ABS_LDMST_SWAP: 7946 decode_abs_ldst_swap(ctx); 7947 break; 7948 case OPCM_32_ABS_LDST_CONTEXT: 7949 decode_abs_ldst_context(ctx); 7950 break; 7951 case OPCM_32_ABS_STORE: 7952 decode_abs_store(ctx); 7953 break; 7954 case OPCM_32_ABS_STOREB_H: 7955 decode_abs_storeb_h(ctx); 7956 break; 7957 case OPC1_32_ABS_STOREQ: 7958 address = MASK_OP_ABS_OFF18(ctx->opcode); 7959 r1 = MASK_OP_ABS_S1D(ctx->opcode); 7960 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 7961 temp2 = tcg_temp_new(); 7962 7963 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); 7964 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); 7965 break; 7966 case OPC1_32_ABS_LD_Q: 7967 address = MASK_OP_ABS_OFF18(ctx->opcode); 7968 r1 = MASK_OP_ABS_S1D(ctx->opcode); 7969 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 7970 7971 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 7972 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 7973 break; 7974 case OPC1_32_ABS_LEA: 7975 address = MASK_OP_ABS_OFF18(ctx->opcode); 7976 r1 = MASK_OP_ABS_S1D(ctx->opcode); 7977 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); 7978 break; 7979 /* ABSB-format */ 7980 case OPC1_32_ABSB_ST_T: 7981 address = MASK_OP_ABS_OFF18(ctx->opcode); 7982 b = MASK_OP_ABSB_B(ctx->opcode); 7983 bpos = MASK_OP_ABSB_BPOS(ctx->opcode); 7984 7985 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 7986 temp2 = tcg_temp_new(); 7987 7988 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); 7989 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); 7990 tcg_gen_ori_tl(temp2, temp2, (b << bpos)); 7991 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); 7992 break; 7993 /* B-format */ 7994 case OPC1_32_B_CALL: 7995 case OPC1_32_B_CALLA: 7996 case OPC1_32_B_FCALL: 7997 case OPC1_32_B_FCALLA: 7998 case OPC1_32_B_J: 7999 case OPC1_32_B_JA: 8000 case OPC1_32_B_JL: 8001 case OPC1_32_B_JLA: 8002 address = MASK_OP_B_DISP24_SEXT(ctx->opcode); 8003 gen_compute_branch(ctx, op1, 0, 0, 0, address); 8004 break; 8005 /* Bit-format */ 8006 case OPCM_32_BIT_ANDACC: 8007 decode_bit_andacc(ctx); 8008 break; 8009 case OPCM_32_BIT_LOGICAL_T1: 8010 decode_bit_logical_t(ctx); 8011 break; 8012 case OPCM_32_BIT_INSERT: 8013 decode_bit_insert(ctx); 8014 break; 8015 case OPCM_32_BIT_LOGICAL_T2: 8016 decode_bit_logical_t2(ctx); 8017 break; 8018 case OPCM_32_BIT_ORAND: 8019 decode_bit_orand(ctx); 8020 break; 8021 case OPCM_32_BIT_SH_LOGIC1: 8022 decode_bit_sh_logic1(ctx); 8023 break; 8024 case OPCM_32_BIT_SH_LOGIC2: 8025 decode_bit_sh_logic2(ctx); 8026 break; 8027 /* BO Format */ 8028 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: 8029 decode_bo_addrmode_post_pre_base(ctx); 8030 break; 8031 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: 8032 decode_bo_addrmode_bitreverse_circular(ctx); 8033 break; 8034 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: 8035 decode_bo_addrmode_ld_post_pre_base(ctx); 8036 break; 8037 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: 8038 decode_bo_addrmode_ld_bitreverse_circular(ctx); 8039 break; 8040 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: 8041 decode_bo_addrmode_stctx_post_pre_base(ctx); 8042 break; 8043 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: 8044 decode_bo_addrmode_ldmst_bitreverse_circular(ctx); 8045 break; 8046 /* BOL-format */ 8047 case OPC1_32_BOL_LD_A_LONGOFF: 8048 case OPC1_32_BOL_LD_W_LONGOFF: 8049 case OPC1_32_BOL_LEA_LONGOFF: 8050 case OPC1_32_BOL_ST_W_LONGOFF: 8051 case OPC1_32_BOL_ST_A_LONGOFF: 8052 case OPC1_32_BOL_LD_B_LONGOFF: 8053 case OPC1_32_BOL_LD_BU_LONGOFF: 8054 case OPC1_32_BOL_LD_H_LONGOFF: 8055 case OPC1_32_BOL_LD_HU_LONGOFF: 8056 case OPC1_32_BOL_ST_B_LONGOFF: 8057 case OPC1_32_BOL_ST_H_LONGOFF: 8058 decode_bol_opc(ctx, op1); 8059 break; 8060 /* BRC Format */ 8061 case OPCM_32_BRC_EQ_NEQ: 8062 case OPCM_32_BRC_GE: 8063 case OPCM_32_BRC_JLT: 8064 case OPCM_32_BRC_JNE: 8065 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); 8066 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); 8067 r1 = MASK_OP_BRC_S1(ctx->opcode); 8068 gen_compute_branch(ctx, op1, r1, 0, const4, address); 8069 break; 8070 /* BRN Format */ 8071 case OPCM_32_BRN_JTT: 8072 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); 8073 r1 = MASK_OP_BRN_S1(ctx->opcode); 8074 gen_compute_branch(ctx, op1, r1, 0, 0, address); 8075 break; 8076 /* BRR Format */ 8077 case OPCM_32_BRR_EQ_NEQ: 8078 case OPCM_32_BRR_ADDR_EQ_NEQ: 8079 case OPCM_32_BRR_GE: 8080 case OPCM_32_BRR_JLT: 8081 case OPCM_32_BRR_JNE: 8082 case OPCM_32_BRR_JNZ: 8083 case OPCM_32_BRR_LOOP: 8084 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); 8085 r2 = MASK_OP_BRR_S2(ctx->opcode); 8086 r1 = MASK_OP_BRR_S1(ctx->opcode); 8087 gen_compute_branch(ctx, op1, r1, r2, 0, address); 8088 break; 8089 /* RC Format */ 8090 case OPCM_32_RC_LOGICAL_SHIFT: 8091 decode_rc_logical_shift(ctx); 8092 break; 8093 case OPCM_32_RC_ACCUMULATOR: 8094 decode_rc_accumulator(ctx); 8095 break; 8096 case OPCM_32_RC_SERVICEROUTINE: 8097 decode_rc_serviceroutine(ctx); 8098 break; 8099 case OPCM_32_RC_MUL: 8100 decode_rc_mul(ctx); 8101 break; 8102 /* RCPW Format */ 8103 case OPCM_32_RCPW_MASK_INSERT: 8104 decode_rcpw_insert(ctx); 8105 break; 8106 /* RCRR Format */ 8107 case OPC1_32_RCRR_INSERT: 8108 r1 = MASK_OP_RCRR_S1(ctx->opcode); 8109 r2 = MASK_OP_RCRR_S3(ctx->opcode); 8110 r3 = MASK_OP_RCRR_D(ctx->opcode); 8111 const16 = MASK_OP_RCRR_CONST4(ctx->opcode); 8112 temp = tcg_constant_i32(const16); 8113 temp2 = tcg_temp_new(); /* width*/ 8114 temp3 = tcg_temp_new(); /* pos */ 8115 8116 CHECK_REG_PAIR(r3); 8117 8118 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f); 8119 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 8120 8121 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); 8122 break; 8123 /* RCRW Format */ 8124 case OPCM_32_RCRW_MASK_INSERT: 8125 decode_rcrw_insert(ctx); 8126 break; 8127 /* RCR Format */ 8128 case OPCM_32_RCR_COND_SELECT: 8129 decode_rcr_cond_select(ctx); 8130 break; 8131 case OPCM_32_RCR_MADD: 8132 decode_rcr_madd(ctx); 8133 break; 8134 case OPCM_32_RCR_MSUB: 8135 decode_rcr_msub(ctx); 8136 break; 8137 /* RLC Format */ 8138 case OPC1_32_RLC_ADDI: 8139 case OPC1_32_RLC_ADDIH: 8140 case OPC1_32_RLC_ADDIH_A: 8141 case OPC1_32_RLC_MFCR: 8142 case OPC1_32_RLC_MOV: 8143 case OPC1_32_RLC_MOV_64: 8144 case OPC1_32_RLC_MOV_U: 8145 case OPC1_32_RLC_MOV_H: 8146 case OPC1_32_RLC_MOVH_A: 8147 case OPC1_32_RLC_MTCR: 8148 decode_rlc_opc(ctx, op1); 8149 break; 8150 /* RR Format */ 8151 case OPCM_32_RR_ACCUMULATOR: 8152 decode_rr_accumulator(ctx); 8153 break; 8154 case OPCM_32_RR_LOGICAL_SHIFT: 8155 decode_rr_logical_shift(ctx); 8156 break; 8157 case OPCM_32_RR_ADDRESS: 8158 decode_rr_address(ctx); 8159 break; 8160 case OPCM_32_RR_IDIRECT: 8161 decode_rr_idirect(ctx); 8162 break; 8163 case OPCM_32_RR_DIVIDE: 8164 decode_rr_divide(ctx); 8165 break; 8166 /* RR1 Format */ 8167 case OPCM_32_RR1_MUL: 8168 decode_rr1_mul(ctx); 8169 break; 8170 case OPCM_32_RR1_MULQ: 8171 decode_rr1_mulq(ctx); 8172 break; 8173 /* RR2 format */ 8174 case OPCM_32_RR2_MUL: 8175 decode_rr2_mul(ctx); 8176 break; 8177 /* RRPW format */ 8178 case OPCM_32_RRPW_EXTRACT_INSERT: 8179 decode_rrpw_extract_insert(ctx); 8180 break; 8181 case OPC1_32_RRPW_DEXTR: 8182 r1 = MASK_OP_RRPW_S1(ctx->opcode); 8183 r2 = MASK_OP_RRPW_S2(ctx->opcode); 8184 r3 = MASK_OP_RRPW_D(ctx->opcode); 8185 const16 = MASK_OP_RRPW_POS(ctx->opcode); 8186 8187 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1], 8188 32 - const16); 8189 break; 8190 /* RRR Format */ 8191 case OPCM_32_RRR_COND_SELECT: 8192 decode_rrr_cond_select(ctx); 8193 break; 8194 case OPCM_32_RRR_DIVIDE: 8195 decode_rrr_divide(ctx); 8196 break; 8197 /* RRR2 Format */ 8198 case OPCM_32_RRR2_MADD: 8199 decode_rrr2_madd(ctx); 8200 break; 8201 case OPCM_32_RRR2_MSUB: 8202 decode_rrr2_msub(ctx); 8203 break; 8204 /* RRR1 format */ 8205 case OPCM_32_RRR1_MADD: 8206 decode_rrr1_madd(ctx); 8207 break; 8208 case OPCM_32_RRR1_MADDQ_H: 8209 decode_rrr1_maddq_h(ctx); 8210 break; 8211 case OPCM_32_RRR1_MADDSU_H: 8212 decode_rrr1_maddsu_h(ctx); 8213 break; 8214 case OPCM_32_RRR1_MSUB_H: 8215 decode_rrr1_msub(ctx); 8216 break; 8217 case OPCM_32_RRR1_MSUB_Q: 8218 decode_rrr1_msubq_h(ctx); 8219 break; 8220 case OPCM_32_RRR1_MSUBAD_H: 8221 decode_rrr1_msubad_h(ctx); 8222 break; 8223 /* RRRR format */ 8224 case OPCM_32_RRRR_EXTRACT_INSERT: 8225 decode_rrrr_extract_insert(ctx); 8226 break; 8227 /* RRRW format */ 8228 case OPCM_32_RRRW_EXTRACT_INSERT: 8229 decode_rrrw_extract_insert(ctx); 8230 break; 8231 /* SYS format */ 8232 case OPCM_32_SYS_INTERRUPTS: 8233 decode_sys_interrupts(ctx); 8234 break; 8235 case OPC1_32_SYS_RSTV: 8236 tcg_gen_movi_tl(cpu_PSW_V, 0); 8237 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); 8238 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 8239 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); 8240 break; 8241 default: 8242 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8243 } 8244 } 8245 8246 static bool tricore_insn_is_16bit(uint32_t insn) 8247 { 8248 return (insn & 0x1) == 0; 8249 } 8250 8251 static void tricore_tr_init_disas_context(DisasContextBase *dcbase, 8252 CPUState *cs) 8253 { 8254 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8255 CPUTriCoreState *env = cs->env_ptr; 8256 ctx->mem_idx = cpu_mmu_index(env, false); 8257 ctx->hflags = (uint32_t)ctx->base.tb->flags; 8258 ctx->features = env->features; 8259 } 8260 8261 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) 8262 { 8263 } 8264 8265 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 8266 { 8267 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8268 8269 tcg_gen_insn_start(ctx->base.pc_next); 8270 } 8271 8272 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) 8273 { 8274 /* 8275 * Return true if the insn at ctx->base.pc_next might cross a page boundary. 8276 * (False positives are OK, false negatives are not.) 8277 * Our caller ensures we are only called if dc->base.pc_next is less than 8278 * 4 bytes from the page boundary, so we cross the page if the first 8279 * 16 bits indicate that this is a 32 bit insn. 8280 */ 8281 uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next); 8282 8283 return !tricore_insn_is_16bit(insn); 8284 } 8285 8286 8287 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 8288 { 8289 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8290 CPUTriCoreState *env = cpu->env_ptr; 8291 uint16_t insn_lo; 8292 bool is_16bit; 8293 8294 insn_lo = cpu_lduw_code(env, ctx->base.pc_next); 8295 is_16bit = tricore_insn_is_16bit(insn_lo); 8296 if (is_16bit) { 8297 ctx->opcode = insn_lo; 8298 ctx->pc_succ_insn = ctx->base.pc_next + 2; 8299 decode_16Bit_opc(ctx); 8300 } else { 8301 uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2); 8302 ctx->opcode = insn_hi << 16 | insn_lo; 8303 ctx->pc_succ_insn = ctx->base.pc_next + 4; 8304 decode_32Bit_opc(ctx); 8305 } 8306 ctx->base.pc_next = ctx->pc_succ_insn; 8307 8308 if (ctx->base.is_jmp == DISAS_NEXT) { 8309 target_ulong page_start; 8310 8311 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 8312 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE 8313 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 8314 && insn_crosses_page(env, ctx))) { 8315 ctx->base.is_jmp = DISAS_TOO_MANY; 8316 } 8317 } 8318 } 8319 8320 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 8321 { 8322 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8323 8324 switch (ctx->base.is_jmp) { 8325 case DISAS_TOO_MANY: 8326 gen_goto_tb(ctx, 0, ctx->base.pc_next); 8327 break; 8328 case DISAS_NORETURN: 8329 break; 8330 default: 8331 g_assert_not_reached(); 8332 } 8333 } 8334 8335 static void tricore_tr_disas_log(const DisasContextBase *dcbase, 8336 CPUState *cpu, FILE *logfile) 8337 { 8338 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 8339 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 8340 } 8341 8342 static const TranslatorOps tricore_tr_ops = { 8343 .init_disas_context = tricore_tr_init_disas_context, 8344 .tb_start = tricore_tr_tb_start, 8345 .insn_start = tricore_tr_insn_start, 8346 .translate_insn = tricore_tr_translate_insn, 8347 .tb_stop = tricore_tr_tb_stop, 8348 .disas_log = tricore_tr_disas_log, 8349 }; 8350 8351 8352 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 8353 target_ulong pc, void *host_pc) 8354 { 8355 DisasContext ctx; 8356 translator_loop(cs, tb, max_insns, pc, host_pc, 8357 &tricore_tr_ops, &ctx.base); 8358 } 8359 8360 /* 8361 * 8362 * Initialization 8363 * 8364 */ 8365 8366 void cpu_state_reset(CPUTriCoreState *env) 8367 { 8368 /* Reset Regs to Default Value */ 8369 env->PSW = 0xb80; 8370 fpu_set_state(env); 8371 } 8372 8373 static void tricore_tcg_init_csfr(void) 8374 { 8375 cpu_PCXI = tcg_global_mem_new(cpu_env, 8376 offsetof(CPUTriCoreState, PCXI), "PCXI"); 8377 cpu_PSW = tcg_global_mem_new(cpu_env, 8378 offsetof(CPUTriCoreState, PSW), "PSW"); 8379 cpu_PC = tcg_global_mem_new(cpu_env, 8380 offsetof(CPUTriCoreState, PC), "PC"); 8381 cpu_ICR = tcg_global_mem_new(cpu_env, 8382 offsetof(CPUTriCoreState, ICR), "ICR"); 8383 } 8384 8385 void tricore_tcg_init(void) 8386 { 8387 int i; 8388 8389 /* reg init */ 8390 for (i = 0 ; i < 16 ; i++) { 8391 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, 8392 offsetof(CPUTriCoreState, gpr_a[i]), 8393 regnames_a[i]); 8394 } 8395 for (i = 0 ; i < 16 ; i++) { 8396 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env, 8397 offsetof(CPUTriCoreState, gpr_d[i]), 8398 regnames_d[i]); 8399 } 8400 tricore_tcg_init_csfr(); 8401 /* init PSW flag cache */ 8402 cpu_PSW_C = tcg_global_mem_new(cpu_env, 8403 offsetof(CPUTriCoreState, PSW_USB_C), 8404 "PSW_C"); 8405 cpu_PSW_V = tcg_global_mem_new(cpu_env, 8406 offsetof(CPUTriCoreState, PSW_USB_V), 8407 "PSW_V"); 8408 cpu_PSW_SV = tcg_global_mem_new(cpu_env, 8409 offsetof(CPUTriCoreState, PSW_USB_SV), 8410 "PSW_SV"); 8411 cpu_PSW_AV = tcg_global_mem_new(cpu_env, 8412 offsetof(CPUTriCoreState, PSW_USB_AV), 8413 "PSW_AV"); 8414 cpu_PSW_SAV = tcg_global_mem_new(cpu_env, 8415 offsetof(CPUTriCoreState, PSW_USB_SAV), 8416 "PSW_SAV"); 8417 } 8418