1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "disas/disas.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "exec/cpu_ldst.h" 27 #include "qemu/qemu-print.h" 28 29 #include "exec/helper-proto.h" 30 #include "exec/helper-gen.h" 31 32 #include "tricore-opcodes.h" 33 #include "exec/translator.h" 34 #include "exec/log.h" 35 36 /* 37 * TCG registers 38 */ 39 static TCGv cpu_PC; 40 static TCGv cpu_PCXI; 41 static TCGv cpu_PSW; 42 static TCGv cpu_ICR; 43 /* GPR registers */ 44 static TCGv cpu_gpr_a[16]; 45 static TCGv cpu_gpr_d[16]; 46 /* PSW Flag cache */ 47 static TCGv cpu_PSW_C; 48 static TCGv cpu_PSW_V; 49 static TCGv cpu_PSW_SV; 50 static TCGv cpu_PSW_AV; 51 static TCGv cpu_PSW_SAV; 52 53 #include "exec/gen-icount.h" 54 55 static const char *regnames_a[] = { 56 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , 57 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , 58 "a12" , "a13" , "a14" , "a15", 59 }; 60 61 static const char *regnames_d[] = { 62 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , 63 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , 64 "d12" , "d13" , "d14" , "d15", 65 }; 66 67 typedef struct DisasContext { 68 DisasContextBase base; 69 target_ulong pc_succ_insn; 70 uint32_t opcode; 71 /* Routine used to access memory */ 72 int mem_idx; 73 uint32_t hflags, saved_hflags; 74 uint64_t features; 75 } DisasContext; 76 77 static int has_feature(DisasContext *ctx, int feature) 78 { 79 return (ctx->features & (1ULL << feature)) != 0; 80 } 81 82 enum { 83 MODE_LL = 0, 84 MODE_LU = 1, 85 MODE_UL = 2, 86 MODE_UU = 3, 87 }; 88 89 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) 90 { 91 TriCoreCPU *cpu = TRICORE_CPU(cs); 92 CPUTriCoreState *env = &cpu->env; 93 uint32_t psw; 94 int i; 95 96 psw = psw_read(env); 97 98 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); 99 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); 100 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); 101 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); 102 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); 103 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); 104 105 for (i = 0; i < 16; ++i) { 106 if ((i & 3) == 0) { 107 qemu_fprintf(f, "\nGPR A%02d:", i); 108 } 109 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); 110 } 111 for (i = 0; i < 16; ++i) { 112 if ((i & 3) == 0) { 113 qemu_fprintf(f, "\nGPR D%02d:", i); 114 } 115 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); 116 } 117 qemu_fprintf(f, "\n"); 118 } 119 120 /* 121 * Functions to generate micro-ops 122 */ 123 124 /* Makros for generating helpers */ 125 126 #define gen_helper_1arg(name, arg) do { \ 127 TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ 128 gen_helper_##name(cpu_env, helper_tmp); \ 129 } while (0) 130 131 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ 132 TCGv arg00 = tcg_temp_new(); \ 133 TCGv arg01 = tcg_temp_new(); \ 134 TCGv arg11 = tcg_temp_new(); \ 135 tcg_gen_sari_tl(arg00, arg0, 16); \ 136 tcg_gen_ext16s_tl(arg01, arg0); \ 137 tcg_gen_ext16s_tl(arg11, arg1); \ 138 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 139 } while (0) 140 141 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ 142 TCGv arg00 = tcg_temp_new(); \ 143 TCGv arg01 = tcg_temp_new(); \ 144 TCGv arg10 = tcg_temp_new(); \ 145 TCGv arg11 = tcg_temp_new(); \ 146 tcg_gen_sari_tl(arg00, arg0, 16); \ 147 tcg_gen_ext16s_tl(arg01, arg0); \ 148 tcg_gen_sari_tl(arg11, arg1, 16); \ 149 tcg_gen_ext16s_tl(arg10, arg1); \ 150 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 151 } while (0) 152 153 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ 154 TCGv arg00 = tcg_temp_new(); \ 155 TCGv arg01 = tcg_temp_new(); \ 156 TCGv arg10 = tcg_temp_new(); \ 157 TCGv arg11 = tcg_temp_new(); \ 158 tcg_gen_sari_tl(arg00, arg0, 16); \ 159 tcg_gen_ext16s_tl(arg01, arg0); \ 160 tcg_gen_sari_tl(arg10, arg1, 16); \ 161 tcg_gen_ext16s_tl(arg11, arg1); \ 162 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 163 } while (0) 164 165 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ 166 TCGv arg00 = tcg_temp_new(); \ 167 TCGv arg01 = tcg_temp_new(); \ 168 TCGv arg11 = tcg_temp_new(); \ 169 tcg_gen_sari_tl(arg01, arg0, 16); \ 170 tcg_gen_ext16s_tl(arg00, arg0); \ 171 tcg_gen_sari_tl(arg11, arg1, 16); \ 172 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 173 } while (0) 174 175 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ 176 TCGv_i64 ret = tcg_temp_new_i64(); \ 177 TCGv_i64 arg1 = tcg_temp_new_i64(); \ 178 \ 179 tcg_gen_concat_i32_i64(arg1, al1, ah1); \ 180 gen_helper_##name(ret, arg1, arg2); \ 181 tcg_gen_extr_i64_i32(rl, rh, ret); \ 182 } while (0) 183 184 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ 185 TCGv_i64 ret = tcg_temp_new_i64(); \ 186 \ 187 gen_helper_##name(ret, cpu_env, arg1, arg2); \ 188 tcg_gen_extr_i64_i32(rl, rh, ret); \ 189 } while (0) 190 191 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) 192 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ 193 ((offset & 0x0fffff) << 1)) 194 195 /* For two 32-bit registers used a 64-bit register, the first 196 registernumber needs to be even. Otherwise we trap. */ 197 static inline void generate_trap(DisasContext *ctx, int class, int tin); 198 #define CHECK_REG_PAIR(reg) do { \ 199 if (reg & 0x1) { \ 200 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ 201 } \ 202 } while (0) 203 204 /* Functions for load/save to/from memory */ 205 206 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, 207 int16_t con, MemOp mop) 208 { 209 TCGv temp = tcg_temp_new(); 210 tcg_gen_addi_tl(temp, r2, con); 211 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 212 } 213 214 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, 215 int16_t con, MemOp mop) 216 { 217 TCGv temp = tcg_temp_new(); 218 tcg_gen_addi_tl(temp, r2, con); 219 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 220 } 221 222 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 223 { 224 TCGv_i64 temp = tcg_temp_new_i64(); 225 226 tcg_gen_concat_i32_i64(temp, rl, rh); 227 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); 228 } 229 230 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 231 DisasContext *ctx) 232 { 233 TCGv temp = tcg_temp_new(); 234 tcg_gen_addi_tl(temp, base, con); 235 gen_st_2regs_64(rh, rl, temp, ctx); 236 } 237 238 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 239 { 240 TCGv_i64 temp = tcg_temp_new_i64(); 241 242 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ); 243 /* write back to two 32 bit regs */ 244 tcg_gen_extr_i64_i32(rl, rh, temp); 245 } 246 247 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 248 DisasContext *ctx) 249 { 250 TCGv temp = tcg_temp_new(); 251 tcg_gen_addi_tl(temp, base, con); 252 gen_ld_2regs_64(rh, rl, temp, ctx); 253 } 254 255 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 256 MemOp mop) 257 { 258 TCGv temp = tcg_temp_new(); 259 tcg_gen_addi_tl(temp, r2, off); 260 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 261 tcg_gen_mov_tl(r2, temp); 262 } 263 264 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 265 MemOp mop) 266 { 267 TCGv temp = tcg_temp_new(); 268 tcg_gen_addi_tl(temp, r2, off); 269 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 270 tcg_gen_mov_tl(r2, temp); 271 } 272 273 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ 274 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) 275 { 276 TCGv temp = tcg_temp_new(); 277 TCGv temp2 = tcg_temp_new(); 278 279 CHECK_REG_PAIR(ereg); 280 /* temp = (M(EA, word) */ 281 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 282 /* temp = temp & ~E[a][63:32]) */ 283 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); 284 /* temp2 = (E[a][31:0] & E[a][63:32]); */ 285 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); 286 /* temp = temp | temp2; */ 287 tcg_gen_or_tl(temp, temp, temp2); 288 /* M(EA, word) = temp; */ 289 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); 290 } 291 292 /* tmp = M(EA, word); 293 M(EA, word) = D[a]; 294 D[a] = tmp[31:0];*/ 295 static void gen_swap(DisasContext *ctx, int reg, TCGv ea) 296 { 297 TCGv temp = tcg_temp_new(); 298 299 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 300 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); 301 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 302 } 303 304 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) 305 { 306 TCGv temp = tcg_temp_new(); 307 TCGv temp2 = tcg_temp_new(); 308 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 309 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, 310 cpu_gpr_d[reg], temp); 311 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 312 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 313 } 314 315 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) 316 { 317 TCGv temp = tcg_temp_new(); 318 TCGv temp2 = tcg_temp_new(); 319 TCGv temp3 = tcg_temp_new(); 320 321 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 322 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); 323 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); 324 tcg_gen_or_tl(temp2, temp2, temp3); 325 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 326 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 327 } 328 329 330 /* We generate loads and store to core special function register (csfr) through 331 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 332 makros R, A and E, which allow read-only, all and endinit protected access. 333 These makros also specify in which ISA version the csfr was introduced. */ 334 #define R(ADDRESS, REG, FEATURE) \ 335 case ADDRESS: \ 336 if (has_feature(ctx, FEATURE)) { \ 337 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ 338 } \ 339 break; 340 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 341 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 342 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) 343 { 344 /* since we're caching PSW make this a special case */ 345 if (offset == 0xfe04) { 346 gen_helper_psw_read(ret, cpu_env); 347 } else { 348 switch (offset) { 349 #include "csfr.h.inc" 350 } 351 } 352 } 353 #undef R 354 #undef A 355 #undef E 356 357 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, 358 since no execption occurs */ 359 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ 360 case ADDRESS: \ 361 if (has_feature(ctx, FEATURE)) { \ 362 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ 363 } \ 364 break; 365 /* Endinit protected registers 366 TODO: Since the endinit bit is in a register of a not yet implemented 367 watchdog device, we handle endinit protected registers like 368 all-access registers for now. */ 369 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) 370 static inline void gen_mtcr(DisasContext *ctx, TCGv r1, 371 int32_t offset) 372 { 373 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 374 /* since we're caching PSW make this a special case */ 375 if (offset == 0xfe04) { 376 gen_helper_psw_write(cpu_env, r1); 377 } else { 378 switch (offset) { 379 #include "csfr.h.inc" 380 } 381 } 382 } else { 383 /* generate privilege trap */ 384 } 385 } 386 387 /* Functions for arithmetic instructions */ 388 389 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) 390 { 391 TCGv t0 = tcg_temp_new_i32(); 392 TCGv result = tcg_temp_new_i32(); 393 /* Addition and set V/SV bits */ 394 tcg_gen_add_tl(result, r1, r2); 395 /* calc V bit */ 396 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 397 tcg_gen_xor_tl(t0, r1, r2); 398 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 399 /* Calc SV bit */ 400 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 401 /* Calc AV/SAV bits */ 402 tcg_gen_add_tl(cpu_PSW_AV, result, result); 403 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 404 /* calc SAV */ 405 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 406 /* write back result */ 407 tcg_gen_mov_tl(ret, result); 408 } 409 410 static inline void 411 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 412 { 413 TCGv temp = tcg_temp_new(); 414 TCGv_i64 t0 = tcg_temp_new_i64(); 415 TCGv_i64 t1 = tcg_temp_new_i64(); 416 TCGv_i64 result = tcg_temp_new_i64(); 417 418 tcg_gen_add_i64(result, r1, r2); 419 /* calc v bit */ 420 tcg_gen_xor_i64(t1, result, r1); 421 tcg_gen_xor_i64(t0, r1, r2); 422 tcg_gen_andc_i64(t1, t1, t0); 423 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 424 /* calc SV bit */ 425 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 426 /* calc AV/SAV bits */ 427 tcg_gen_extrh_i64_i32(temp, result); 428 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 429 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 430 /* calc SAV */ 431 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 432 /* write back result */ 433 tcg_gen_mov_i64(ret, result); 434 } 435 436 static inline void 437 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 438 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), 439 void(*op2)(TCGv, TCGv, TCGv)) 440 { 441 TCGv temp = tcg_temp_new(); 442 TCGv temp2 = tcg_temp_new(); 443 TCGv temp3 = tcg_temp_new(); 444 TCGv temp4 = tcg_temp_new(); 445 446 (*op1)(temp, r1_low, r2); 447 /* calc V0 bit */ 448 tcg_gen_xor_tl(temp2, temp, r1_low); 449 tcg_gen_xor_tl(temp3, r1_low, r2); 450 if (op1 == tcg_gen_add_tl) { 451 tcg_gen_andc_tl(temp2, temp2, temp3); 452 } else { 453 tcg_gen_and_tl(temp2, temp2, temp3); 454 } 455 456 (*op2)(temp3, r1_high, r3); 457 /* calc V1 bit */ 458 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); 459 tcg_gen_xor_tl(temp4, r1_high, r3); 460 if (op2 == tcg_gen_add_tl) { 461 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); 462 } else { 463 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); 464 } 465 /* combine V0/V1 bits */ 466 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); 467 /* calc sv bit */ 468 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 469 /* write result */ 470 tcg_gen_mov_tl(ret_low, temp); 471 tcg_gen_mov_tl(ret_high, temp3); 472 /* calc AV bit */ 473 tcg_gen_add_tl(temp, ret_low, ret_low); 474 tcg_gen_xor_tl(temp, temp, ret_low); 475 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 476 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); 477 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 478 /* calc SAV bit */ 479 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 480 } 481 482 /* ret = r2 + (r1 * r3); */ 483 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 484 { 485 TCGv_i64 t1 = tcg_temp_new_i64(); 486 TCGv_i64 t2 = tcg_temp_new_i64(); 487 TCGv_i64 t3 = tcg_temp_new_i64(); 488 489 tcg_gen_ext_i32_i64(t1, r1); 490 tcg_gen_ext_i32_i64(t2, r2); 491 tcg_gen_ext_i32_i64(t3, r3); 492 493 tcg_gen_mul_i64(t1, t1, t3); 494 tcg_gen_add_i64(t1, t2, t1); 495 496 tcg_gen_extrl_i64_i32(ret, t1); 497 /* calc V 498 t1 > 0x7fffffff */ 499 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 500 /* t1 < -0x80000000 */ 501 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 502 tcg_gen_or_i64(t2, t2, t3); 503 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 504 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 505 /* Calc SV bit */ 506 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 507 /* Calc AV/SAV bits */ 508 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 509 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 510 /* calc SAV */ 511 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 512 } 513 514 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 515 { 516 TCGv temp = tcg_constant_i32(con); 517 gen_madd32_d(ret, r1, r2, temp); 518 } 519 520 static inline void 521 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 522 TCGv r3) 523 { 524 TCGv t1 = tcg_temp_new(); 525 TCGv t2 = tcg_temp_new(); 526 TCGv t3 = tcg_temp_new(); 527 TCGv t4 = tcg_temp_new(); 528 529 tcg_gen_muls2_tl(t1, t2, r1, r3); 530 /* only the add can overflow */ 531 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); 532 /* calc V bit */ 533 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 534 tcg_gen_xor_tl(t1, r2_high, t2); 535 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); 536 /* Calc SV bit */ 537 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 538 /* Calc AV/SAV bits */ 539 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 540 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 541 /* calc SAV */ 542 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 543 /* write back the result */ 544 tcg_gen_mov_tl(ret_low, t3); 545 tcg_gen_mov_tl(ret_high, t4); 546 } 547 548 static inline void 549 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 550 TCGv r3) 551 { 552 TCGv_i64 t1 = tcg_temp_new_i64(); 553 TCGv_i64 t2 = tcg_temp_new_i64(); 554 TCGv_i64 t3 = tcg_temp_new_i64(); 555 556 tcg_gen_extu_i32_i64(t1, r1); 557 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 558 tcg_gen_extu_i32_i64(t3, r3); 559 560 tcg_gen_mul_i64(t1, t1, t3); 561 tcg_gen_add_i64(t2, t2, t1); 562 /* write back result */ 563 tcg_gen_extr_i64_i32(ret_low, ret_high, t2); 564 /* only the add overflows, if t2 < t1 565 calc V bit */ 566 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); 567 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 568 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 569 /* Calc SV bit */ 570 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 571 /* Calc AV/SAV bits */ 572 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 573 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 574 /* calc SAV */ 575 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 576 } 577 578 static inline void 579 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 580 int32_t con) 581 { 582 TCGv temp = tcg_constant_i32(con); 583 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 584 } 585 586 static inline void 587 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 588 int32_t con) 589 { 590 TCGv temp = tcg_constant_i32(con); 591 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 592 } 593 594 static inline void 595 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 596 TCGv r3, uint32_t n, uint32_t mode) 597 { 598 TCGv t_n = tcg_constant_i32(n); 599 TCGv temp = tcg_temp_new(); 600 TCGv temp2 = tcg_temp_new(); 601 TCGv_i64 temp64 = tcg_temp_new_i64(); 602 switch (mode) { 603 case MODE_LL: 604 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 605 break; 606 case MODE_LU: 607 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 608 break; 609 case MODE_UL: 610 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 611 break; 612 case MODE_UU: 613 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 614 break; 615 } 616 tcg_gen_extr_i64_i32(temp, temp2, temp64); 617 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 618 tcg_gen_add_tl, tcg_gen_add_tl); 619 } 620 621 static inline void 622 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 623 TCGv r3, uint32_t n, uint32_t mode) 624 { 625 TCGv t_n = tcg_constant_i32(n); 626 TCGv temp = tcg_temp_new(); 627 TCGv temp2 = tcg_temp_new(); 628 TCGv_i64 temp64 = tcg_temp_new_i64(); 629 switch (mode) { 630 case MODE_LL: 631 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 632 break; 633 case MODE_LU: 634 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 635 break; 636 case MODE_UL: 637 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 638 break; 639 case MODE_UU: 640 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 641 break; 642 } 643 tcg_gen_extr_i64_i32(temp, temp2, temp64); 644 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 645 tcg_gen_sub_tl, tcg_gen_add_tl); 646 } 647 648 static inline void 649 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 650 TCGv r3, uint32_t n, uint32_t mode) 651 { 652 TCGv t_n = tcg_constant_i32(n); 653 TCGv_i64 temp64 = tcg_temp_new_i64(); 654 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 655 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 656 switch (mode) { 657 case MODE_LL: 658 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 659 break; 660 case MODE_LU: 661 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 662 break; 663 case MODE_UL: 664 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 665 break; 666 case MODE_UU: 667 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 668 break; 669 } 670 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 671 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 672 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 673 tcg_gen_sub_i64(temp64, temp64_2, temp64); 674 tcg_gen_shli_i64(temp64, temp64, 16); 675 676 gen_add64_d(temp64_2, temp64_3, temp64); 677 /* write back result */ 678 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 679 } 680 681 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); 682 683 static inline void 684 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 685 TCGv r3, uint32_t n, uint32_t mode) 686 { 687 TCGv t_n = tcg_constant_i32(n); 688 TCGv temp = tcg_temp_new(); 689 TCGv temp2 = tcg_temp_new(); 690 TCGv temp3 = tcg_temp_new(); 691 TCGv_i64 temp64 = tcg_temp_new_i64(); 692 693 switch (mode) { 694 case MODE_LL: 695 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 696 break; 697 case MODE_LU: 698 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 699 break; 700 case MODE_UL: 701 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 702 break; 703 case MODE_UU: 704 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 705 break; 706 } 707 tcg_gen_extr_i64_i32(temp, temp2, temp64); 708 gen_adds(ret_low, r1_low, temp); 709 tcg_gen_mov_tl(temp, cpu_PSW_V); 710 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 711 gen_adds(ret_high, r1_high, temp2); 712 /* combine v bits */ 713 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 714 /* combine av bits */ 715 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 716 } 717 718 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); 719 720 static inline void 721 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 722 TCGv r3, uint32_t n, uint32_t mode) 723 { 724 TCGv t_n = tcg_constant_i32(n); 725 TCGv temp = tcg_temp_new(); 726 TCGv temp2 = tcg_temp_new(); 727 TCGv temp3 = tcg_temp_new(); 728 TCGv_i64 temp64 = tcg_temp_new_i64(); 729 730 switch (mode) { 731 case MODE_LL: 732 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 733 break; 734 case MODE_LU: 735 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 736 break; 737 case MODE_UL: 738 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 739 break; 740 case MODE_UU: 741 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 742 break; 743 } 744 tcg_gen_extr_i64_i32(temp, temp2, temp64); 745 gen_subs(ret_low, r1_low, temp); 746 tcg_gen_mov_tl(temp, cpu_PSW_V); 747 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 748 gen_adds(ret_high, r1_high, temp2); 749 /* combine v bits */ 750 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 751 /* combine av bits */ 752 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 753 } 754 755 static inline void 756 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 757 TCGv r3, uint32_t n, uint32_t mode) 758 { 759 TCGv t_n = tcg_constant_i32(n); 760 TCGv_i64 temp64 = tcg_temp_new_i64(); 761 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 762 763 switch (mode) { 764 case MODE_LL: 765 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 766 break; 767 case MODE_LU: 768 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 769 break; 770 case MODE_UL: 771 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 772 break; 773 case MODE_UU: 774 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 775 break; 776 } 777 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 778 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 779 tcg_gen_sub_i64(temp64, temp64_2, temp64); 780 tcg_gen_shli_i64(temp64, temp64, 16); 781 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 782 783 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 784 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 785 } 786 787 788 static inline void 789 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 790 TCGv r3, uint32_t n, uint32_t mode) 791 { 792 TCGv t_n = tcg_constant_i32(n); 793 TCGv_i64 temp64 = tcg_temp_new_i64(); 794 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 795 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 796 switch (mode) { 797 case MODE_LL: 798 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 799 break; 800 case MODE_LU: 801 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 802 break; 803 case MODE_UL: 804 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 805 break; 806 case MODE_UU: 807 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 808 break; 809 } 810 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 811 gen_add64_d(temp64_3, temp64_2, temp64); 812 /* write back result */ 813 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 814 } 815 816 static inline void 817 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 818 TCGv r3, uint32_t n, uint32_t mode) 819 { 820 TCGv t_n = tcg_constant_i32(n); 821 TCGv_i64 temp64 = tcg_temp_new_i64(); 822 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 823 switch (mode) { 824 case MODE_LL: 825 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 826 break; 827 case MODE_LU: 828 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 829 break; 830 case MODE_UL: 831 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 832 break; 833 case MODE_UU: 834 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 835 break; 836 } 837 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 838 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 839 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 840 } 841 842 static inline void 843 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 844 uint32_t mode) 845 { 846 TCGv t_n = tcg_constant_i32(n); 847 TCGv_i64 temp64 = tcg_temp_new_i64(); 848 switch (mode) { 849 case MODE_LL: 850 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 851 break; 852 case MODE_LU: 853 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 854 break; 855 case MODE_UL: 856 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 857 break; 858 case MODE_UU: 859 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 860 break; 861 } 862 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); 863 } 864 865 static inline void 866 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 867 { 868 TCGv temp = tcg_temp_new(); 869 TCGv temp2 = tcg_temp_new(); 870 871 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 872 tcg_gen_shli_tl(temp, r1, 16); 873 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); 874 } 875 876 static inline void 877 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 878 { 879 TCGv t_n = tcg_constant_i32(n); 880 TCGv temp = tcg_temp_new(); 881 TCGv temp2 = tcg_temp_new(); 882 TCGv_i64 temp64 = tcg_temp_new_i64(); 883 switch (mode) { 884 case MODE_LL: 885 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 886 break; 887 case MODE_LU: 888 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 889 break; 890 case MODE_UL: 891 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 892 break; 893 case MODE_UU: 894 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 895 break; 896 } 897 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 898 tcg_gen_shli_tl(temp, r1, 16); 899 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); 900 } 901 902 903 static inline void 904 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 905 uint32_t n, uint32_t mode) 906 { 907 TCGv t_n = tcg_constant_i32(n); 908 TCGv_i64 temp64 = tcg_temp_new_i64(); 909 switch (mode) { 910 case MODE_LL: 911 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 912 break; 913 case MODE_LU: 914 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 915 break; 916 case MODE_UL: 917 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 918 break; 919 case MODE_UU: 920 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 921 break; 922 } 923 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 924 } 925 926 static inline void 927 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 928 { 929 TCGv temp = tcg_temp_new(); 930 TCGv temp2 = tcg_temp_new(); 931 932 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 933 tcg_gen_shli_tl(temp, r1, 16); 934 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); 935 } 936 937 static inline void 938 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 939 { 940 TCGv t_n = tcg_constant_i32(n); 941 TCGv temp = tcg_temp_new(); 942 TCGv temp2 = tcg_temp_new(); 943 TCGv_i64 temp64 = tcg_temp_new_i64(); 944 switch (mode) { 945 case MODE_LL: 946 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 947 break; 948 case MODE_LU: 949 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 950 break; 951 case MODE_UL: 952 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 953 break; 954 case MODE_UU: 955 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 956 break; 957 } 958 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 959 tcg_gen_shli_tl(temp, r1, 16); 960 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); 961 } 962 963 static inline void 964 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 965 { 966 TCGv t_n = tcg_constant_i32(n); 967 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n); 968 } 969 970 static inline void 971 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 972 { 973 TCGv t_n = tcg_constant_i32(n); 974 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n); 975 } 976 977 static inline void 978 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 979 uint32_t up_shift) 980 { 981 TCGv temp = tcg_temp_new(); 982 TCGv temp2 = tcg_temp_new(); 983 TCGv temp3 = tcg_temp_new(); 984 TCGv_i64 t1 = tcg_temp_new_i64(); 985 TCGv_i64 t2 = tcg_temp_new_i64(); 986 TCGv_i64 t3 = tcg_temp_new_i64(); 987 988 tcg_gen_ext_i32_i64(t2, arg2); 989 tcg_gen_ext_i32_i64(t3, arg3); 990 991 tcg_gen_mul_i64(t2, t2, t3); 992 tcg_gen_shli_i64(t2, t2, n); 993 994 tcg_gen_ext_i32_i64(t1, arg1); 995 tcg_gen_sari_i64(t2, t2, up_shift); 996 997 tcg_gen_add_i64(t3, t1, t2); 998 tcg_gen_extrl_i64_i32(temp3, t3); 999 /* calc v bit */ 1000 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1001 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1002 tcg_gen_or_i64(t1, t1, t2); 1003 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1004 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1005 /* We produce an overflow on the host if the mul before was 1006 (0x80000000 * 0x80000000) << 1). If this is the 1007 case, we negate the ovf. */ 1008 if (n == 1) { 1009 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1010 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1011 tcg_gen_and_tl(temp, temp, temp2); 1012 tcg_gen_shli_tl(temp, temp, 31); 1013 /* negate v bit, if special condition */ 1014 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1015 } 1016 /* Calc SV bit */ 1017 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1018 /* Calc AV/SAV bits */ 1019 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1020 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1021 /* calc SAV */ 1022 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1023 /* write back result */ 1024 tcg_gen_mov_tl(ret, temp3); 1025 } 1026 1027 static inline void 1028 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1029 { 1030 TCGv temp = tcg_temp_new(); 1031 TCGv temp2 = tcg_temp_new(); 1032 if (n == 0) { 1033 tcg_gen_mul_tl(temp, arg2, arg3); 1034 } else { /* n is expected to be 1 */ 1035 tcg_gen_mul_tl(temp, arg2, arg3); 1036 tcg_gen_shli_tl(temp, temp, 1); 1037 /* catch special case r1 = r2 = 0x8000 */ 1038 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1039 tcg_gen_sub_tl(temp, temp, temp2); 1040 } 1041 gen_add_d(ret, arg1, temp); 1042 } 1043 1044 static inline void 1045 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1046 { 1047 TCGv temp = tcg_temp_new(); 1048 TCGv temp2 = tcg_temp_new(); 1049 if (n == 0) { 1050 tcg_gen_mul_tl(temp, arg2, arg3); 1051 } else { /* n is expected to be 1 */ 1052 tcg_gen_mul_tl(temp, arg2, arg3); 1053 tcg_gen_shli_tl(temp, temp, 1); 1054 /* catch special case r1 = r2 = 0x8000 */ 1055 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1056 tcg_gen_sub_tl(temp, temp, temp2); 1057 } 1058 gen_adds(ret, arg1, temp); 1059 } 1060 1061 static inline void 1062 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1063 TCGv arg3, uint32_t n) 1064 { 1065 TCGv temp = tcg_temp_new(); 1066 TCGv temp2 = tcg_temp_new(); 1067 TCGv_i64 t1 = tcg_temp_new_i64(); 1068 TCGv_i64 t2 = tcg_temp_new_i64(); 1069 TCGv_i64 t3 = tcg_temp_new_i64(); 1070 1071 if (n == 0) { 1072 tcg_gen_mul_tl(temp, arg2, arg3); 1073 } else { /* n is expected to be 1 */ 1074 tcg_gen_mul_tl(temp, arg2, arg3); 1075 tcg_gen_shli_tl(temp, temp, 1); 1076 /* catch special case r1 = r2 = 0x8000 */ 1077 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1078 tcg_gen_sub_tl(temp, temp, temp2); 1079 } 1080 tcg_gen_ext_i32_i64(t2, temp); 1081 tcg_gen_shli_i64(t2, t2, 16); 1082 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1083 gen_add64_d(t3, t1, t2); 1084 /* write back result */ 1085 tcg_gen_extr_i64_i32(rl, rh, t3); 1086 } 1087 1088 static inline void 1089 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1090 TCGv arg3, uint32_t n) 1091 { 1092 TCGv temp = tcg_temp_new(); 1093 TCGv temp2 = tcg_temp_new(); 1094 TCGv_i64 t1 = tcg_temp_new_i64(); 1095 TCGv_i64 t2 = tcg_temp_new_i64(); 1096 1097 if (n == 0) { 1098 tcg_gen_mul_tl(temp, arg2, arg3); 1099 } else { /* n is expected to be 1 */ 1100 tcg_gen_mul_tl(temp, arg2, arg3); 1101 tcg_gen_shli_tl(temp, temp, 1); 1102 /* catch special case r1 = r2 = 0x8000 */ 1103 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1104 tcg_gen_sub_tl(temp, temp, temp2); 1105 } 1106 tcg_gen_ext_i32_i64(t2, temp); 1107 tcg_gen_shli_i64(t2, t2, 16); 1108 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1109 1110 gen_helper_add64_ssov(t1, cpu_env, t1, t2); 1111 tcg_gen_extr_i64_i32(rl, rh, t1); 1112 } 1113 1114 static inline void 1115 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1116 TCGv arg3, uint32_t n) 1117 { 1118 TCGv_i64 t1 = tcg_temp_new_i64(); 1119 TCGv_i64 t2 = tcg_temp_new_i64(); 1120 TCGv_i64 t3 = tcg_temp_new_i64(); 1121 TCGv_i64 t4 = tcg_temp_new_i64(); 1122 TCGv temp, temp2; 1123 1124 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1125 tcg_gen_ext_i32_i64(t2, arg2); 1126 tcg_gen_ext_i32_i64(t3, arg3); 1127 1128 tcg_gen_mul_i64(t2, t2, t3); 1129 if (n != 0) { 1130 tcg_gen_shli_i64(t2, t2, 1); 1131 } 1132 tcg_gen_add_i64(t4, t1, t2); 1133 /* calc v bit */ 1134 tcg_gen_xor_i64(t3, t4, t1); 1135 tcg_gen_xor_i64(t2, t1, t2); 1136 tcg_gen_andc_i64(t3, t3, t2); 1137 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1138 /* We produce an overflow on the host if the mul before was 1139 (0x80000000 * 0x80000000) << 1). If this is the 1140 case, we negate the ovf. */ 1141 if (n == 1) { 1142 temp = tcg_temp_new(); 1143 temp2 = tcg_temp_new(); 1144 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1145 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1146 tcg_gen_and_tl(temp, temp, temp2); 1147 tcg_gen_shli_tl(temp, temp, 31); 1148 /* negate v bit, if special condition */ 1149 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1150 } 1151 /* write back result */ 1152 tcg_gen_extr_i64_i32(rl, rh, t4); 1153 /* Calc SV bit */ 1154 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1155 /* Calc AV/SAV bits */ 1156 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1157 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1158 /* calc SAV */ 1159 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1160 } 1161 1162 static inline void 1163 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1164 uint32_t up_shift) 1165 { 1166 TCGv_i64 t1 = tcg_temp_new_i64(); 1167 TCGv_i64 t2 = tcg_temp_new_i64(); 1168 TCGv_i64 t3 = tcg_temp_new_i64(); 1169 1170 tcg_gen_ext_i32_i64(t1, arg1); 1171 tcg_gen_ext_i32_i64(t2, arg2); 1172 tcg_gen_ext_i32_i64(t3, arg3); 1173 1174 tcg_gen_mul_i64(t2, t2, t3); 1175 tcg_gen_sari_i64(t2, t2, up_shift - n); 1176 1177 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); 1178 } 1179 1180 static inline void 1181 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1182 TCGv arg3, uint32_t n) 1183 { 1184 TCGv_i64 r1 = tcg_temp_new_i64(); 1185 TCGv t_n = tcg_constant_i32(n); 1186 1187 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1188 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); 1189 tcg_gen_extr_i64_i32(rl, rh, r1); 1190 } 1191 1192 /* ret = r2 - (r1 * r3); */ 1193 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 1194 { 1195 TCGv_i64 t1 = tcg_temp_new_i64(); 1196 TCGv_i64 t2 = tcg_temp_new_i64(); 1197 TCGv_i64 t3 = tcg_temp_new_i64(); 1198 1199 tcg_gen_ext_i32_i64(t1, r1); 1200 tcg_gen_ext_i32_i64(t2, r2); 1201 tcg_gen_ext_i32_i64(t3, r3); 1202 1203 tcg_gen_mul_i64(t1, t1, t3); 1204 tcg_gen_sub_i64(t1, t2, t1); 1205 1206 tcg_gen_extrl_i64_i32(ret, t1); 1207 /* calc V 1208 t2 > 0x7fffffff */ 1209 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 1210 /* result < -0x80000000 */ 1211 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 1212 tcg_gen_or_i64(t2, t2, t3); 1213 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 1214 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1215 1216 /* Calc SV bit */ 1217 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1218 /* Calc AV/SAV bits */ 1219 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 1220 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 1221 /* calc SAV */ 1222 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1223 } 1224 1225 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 1226 { 1227 TCGv temp = tcg_constant_i32(con); 1228 gen_msub32_d(ret, r1, r2, temp); 1229 } 1230 1231 static inline void 1232 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1233 TCGv r3) 1234 { 1235 TCGv t1 = tcg_temp_new(); 1236 TCGv t2 = tcg_temp_new(); 1237 TCGv t3 = tcg_temp_new(); 1238 TCGv t4 = tcg_temp_new(); 1239 1240 tcg_gen_muls2_tl(t1, t2, r1, r3); 1241 /* only the sub can overflow */ 1242 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); 1243 /* calc V bit */ 1244 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 1245 tcg_gen_xor_tl(t1, r2_high, t2); 1246 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); 1247 /* Calc SV bit */ 1248 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1249 /* Calc AV/SAV bits */ 1250 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 1251 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 1252 /* calc SAV */ 1253 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1254 /* write back the result */ 1255 tcg_gen_mov_tl(ret_low, t3); 1256 tcg_gen_mov_tl(ret_high, t4); 1257 } 1258 1259 static inline void 1260 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1261 int32_t con) 1262 { 1263 TCGv temp = tcg_constant_i32(con); 1264 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1265 } 1266 1267 static inline void 1268 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1269 TCGv r3) 1270 { 1271 TCGv_i64 t1 = tcg_temp_new_i64(); 1272 TCGv_i64 t2 = tcg_temp_new_i64(); 1273 TCGv_i64 t3 = tcg_temp_new_i64(); 1274 1275 tcg_gen_extu_i32_i64(t1, r1); 1276 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 1277 tcg_gen_extu_i32_i64(t3, r3); 1278 1279 tcg_gen_mul_i64(t1, t1, t3); 1280 tcg_gen_sub_i64(t3, t2, t1); 1281 tcg_gen_extr_i64_i32(ret_low, ret_high, t3); 1282 /* calc V bit, only the sub can overflow, if t1 > t2 */ 1283 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); 1284 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1285 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1286 /* Calc SV bit */ 1287 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1288 /* Calc AV/SAV bits */ 1289 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 1290 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 1291 /* calc SAV */ 1292 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1293 } 1294 1295 static inline void 1296 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1297 int32_t con) 1298 { 1299 TCGv temp = tcg_constant_i32(con); 1300 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1301 } 1302 1303 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) 1304 { 1305 TCGv temp = tcg_constant_i32(r2); 1306 gen_add_d(ret, r1, temp); 1307 } 1308 1309 /* calculate the carry bit too */ 1310 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) 1311 { 1312 TCGv t0 = tcg_temp_new_i32(); 1313 TCGv result = tcg_temp_new_i32(); 1314 1315 tcg_gen_movi_tl(t0, 0); 1316 /* Addition and set C/V/SV bits */ 1317 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); 1318 /* calc V bit */ 1319 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1320 tcg_gen_xor_tl(t0, r1, r2); 1321 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1322 /* Calc SV bit */ 1323 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1324 /* Calc AV/SAV bits */ 1325 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1326 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1327 /* calc SAV */ 1328 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1329 /* write back result */ 1330 tcg_gen_mov_tl(ret, result); 1331 } 1332 1333 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) 1334 { 1335 TCGv temp = tcg_constant_i32(con); 1336 gen_add_CC(ret, r1, temp); 1337 } 1338 1339 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) 1340 { 1341 TCGv carry = tcg_temp_new_i32(); 1342 TCGv t0 = tcg_temp_new_i32(); 1343 TCGv result = tcg_temp_new_i32(); 1344 1345 tcg_gen_movi_tl(t0, 0); 1346 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); 1347 /* Addition, carry and set C/V/SV bits */ 1348 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); 1349 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); 1350 /* calc V bit */ 1351 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1352 tcg_gen_xor_tl(t0, r1, r2); 1353 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1354 /* Calc SV bit */ 1355 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1356 /* Calc AV/SAV bits */ 1357 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1358 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1359 /* calc SAV */ 1360 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1361 /* write back result */ 1362 tcg_gen_mov_tl(ret, result); 1363 } 1364 1365 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) 1366 { 1367 TCGv temp = tcg_constant_i32(con); 1368 gen_addc_CC(ret, r1, temp); 1369 } 1370 1371 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1372 TCGv r4) 1373 { 1374 TCGv temp = tcg_temp_new(); 1375 TCGv temp2 = tcg_temp_new(); 1376 TCGv result = tcg_temp_new(); 1377 TCGv mask = tcg_temp_new(); 1378 TCGv t0 = tcg_constant_i32(0); 1379 1380 /* create mask for sticky bits */ 1381 tcg_gen_setcond_tl(cond, mask, r4, t0); 1382 tcg_gen_shli_tl(mask, mask, 31); 1383 1384 tcg_gen_add_tl(result, r1, r2); 1385 /* Calc PSW_V */ 1386 tcg_gen_xor_tl(temp, result, r1); 1387 tcg_gen_xor_tl(temp2, r1, r2); 1388 tcg_gen_andc_tl(temp, temp, temp2); 1389 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1390 /* Set PSW_SV */ 1391 tcg_gen_and_tl(temp, temp, mask); 1392 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1393 /* calc AV bit */ 1394 tcg_gen_add_tl(temp, result, result); 1395 tcg_gen_xor_tl(temp, temp, result); 1396 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1397 /* calc SAV bit */ 1398 tcg_gen_and_tl(temp, temp, mask); 1399 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1400 /* write back result */ 1401 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1402 } 1403 1404 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, 1405 TCGv r3, TCGv r4) 1406 { 1407 TCGv temp = tcg_constant_i32(r2); 1408 gen_cond_add(cond, r1, temp, r3, r4); 1409 } 1410 1411 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) 1412 { 1413 TCGv temp = tcg_temp_new_i32(); 1414 TCGv result = tcg_temp_new_i32(); 1415 1416 tcg_gen_sub_tl(result, r1, r2); 1417 /* calc V bit */ 1418 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1419 tcg_gen_xor_tl(temp, r1, r2); 1420 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1421 /* calc SV bit */ 1422 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1423 /* Calc AV bit */ 1424 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1425 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1426 /* calc SAV bit */ 1427 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1428 /* write back result */ 1429 tcg_gen_mov_tl(ret, result); 1430 } 1431 1432 static inline void 1433 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 1434 { 1435 TCGv temp = tcg_temp_new(); 1436 TCGv_i64 t0 = tcg_temp_new_i64(); 1437 TCGv_i64 t1 = tcg_temp_new_i64(); 1438 TCGv_i64 result = tcg_temp_new_i64(); 1439 1440 tcg_gen_sub_i64(result, r1, r2); 1441 /* calc v bit */ 1442 tcg_gen_xor_i64(t1, result, r1); 1443 tcg_gen_xor_i64(t0, r1, r2); 1444 tcg_gen_and_i64(t1, t1, t0); 1445 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 1446 /* calc SV bit */ 1447 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1448 /* calc AV/SAV bits */ 1449 tcg_gen_extrh_i64_i32(temp, result); 1450 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 1451 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 1452 /* calc SAV */ 1453 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1454 /* write back result */ 1455 tcg_gen_mov_i64(ret, result); 1456 } 1457 1458 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) 1459 { 1460 TCGv result = tcg_temp_new(); 1461 TCGv temp = tcg_temp_new(); 1462 1463 tcg_gen_sub_tl(result, r1, r2); 1464 /* calc C bit */ 1465 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); 1466 /* calc V bit */ 1467 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1468 tcg_gen_xor_tl(temp, r1, r2); 1469 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1470 /* calc SV bit */ 1471 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1472 /* Calc AV bit */ 1473 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1474 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1475 /* calc SAV bit */ 1476 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1477 /* write back result */ 1478 tcg_gen_mov_tl(ret, result); 1479 } 1480 1481 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) 1482 { 1483 TCGv temp = tcg_temp_new(); 1484 tcg_gen_not_tl(temp, r2); 1485 gen_addc_CC(ret, r1, temp); 1486 } 1487 1488 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1489 TCGv r4) 1490 { 1491 TCGv temp = tcg_temp_new(); 1492 TCGv temp2 = tcg_temp_new(); 1493 TCGv result = tcg_temp_new(); 1494 TCGv mask = tcg_temp_new(); 1495 TCGv t0 = tcg_constant_i32(0); 1496 1497 /* create mask for sticky bits */ 1498 tcg_gen_setcond_tl(cond, mask, r4, t0); 1499 tcg_gen_shli_tl(mask, mask, 31); 1500 1501 tcg_gen_sub_tl(result, r1, r2); 1502 /* Calc PSW_V */ 1503 tcg_gen_xor_tl(temp, result, r1); 1504 tcg_gen_xor_tl(temp2, r1, r2); 1505 tcg_gen_and_tl(temp, temp, temp2); 1506 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1507 /* Set PSW_SV */ 1508 tcg_gen_and_tl(temp, temp, mask); 1509 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1510 /* calc AV bit */ 1511 tcg_gen_add_tl(temp, result, result); 1512 tcg_gen_xor_tl(temp, temp, result); 1513 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1514 /* calc SAV bit */ 1515 tcg_gen_and_tl(temp, temp, mask); 1516 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1517 /* write back result */ 1518 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1519 } 1520 1521 static inline void 1522 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1523 TCGv r3, uint32_t n, uint32_t mode) 1524 { 1525 TCGv t_n = tcg_constant_i32(n); 1526 TCGv temp = tcg_temp_new(); 1527 TCGv temp2 = tcg_temp_new(); 1528 TCGv_i64 temp64 = tcg_temp_new_i64(); 1529 switch (mode) { 1530 case MODE_LL: 1531 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1532 break; 1533 case MODE_LU: 1534 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1535 break; 1536 case MODE_UL: 1537 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1538 break; 1539 case MODE_UU: 1540 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1541 break; 1542 } 1543 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1544 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1545 tcg_gen_sub_tl, tcg_gen_sub_tl); 1546 } 1547 1548 static inline void 1549 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1550 TCGv r3, uint32_t n, uint32_t mode) 1551 { 1552 TCGv t_n = tcg_constant_i32(n); 1553 TCGv temp = tcg_temp_new(); 1554 TCGv temp2 = tcg_temp_new(); 1555 TCGv temp3 = tcg_temp_new(); 1556 TCGv_i64 temp64 = tcg_temp_new_i64(); 1557 1558 switch (mode) { 1559 case MODE_LL: 1560 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1561 break; 1562 case MODE_LU: 1563 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1564 break; 1565 case MODE_UL: 1566 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1567 break; 1568 case MODE_UU: 1569 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1570 break; 1571 } 1572 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1573 gen_subs(ret_low, r1_low, temp); 1574 tcg_gen_mov_tl(temp, cpu_PSW_V); 1575 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 1576 gen_subs(ret_high, r1_high, temp2); 1577 /* combine v bits */ 1578 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 1579 /* combine av bits */ 1580 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 1581 } 1582 1583 static inline void 1584 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1585 TCGv r3, uint32_t n, uint32_t mode) 1586 { 1587 TCGv t_n = tcg_constant_i32(n); 1588 TCGv_i64 temp64 = tcg_temp_new_i64(); 1589 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1590 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1591 switch (mode) { 1592 case MODE_LL: 1593 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1594 break; 1595 case MODE_LU: 1596 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1597 break; 1598 case MODE_UL: 1599 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1600 break; 1601 case MODE_UU: 1602 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1603 break; 1604 } 1605 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1606 gen_sub64_d(temp64_3, temp64_2, temp64); 1607 /* write back result */ 1608 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 1609 } 1610 1611 static inline void 1612 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1613 TCGv r3, uint32_t n, uint32_t mode) 1614 { 1615 TCGv t_n = tcg_constant_i32(n); 1616 TCGv_i64 temp64 = tcg_temp_new_i64(); 1617 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1618 switch (mode) { 1619 case MODE_LL: 1620 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); 1621 break; 1622 case MODE_LU: 1623 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); 1624 break; 1625 case MODE_UL: 1626 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); 1627 break; 1628 case MODE_UU: 1629 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); 1630 break; 1631 } 1632 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1633 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 1634 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 1635 } 1636 1637 static inline void 1638 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 1639 uint32_t mode) 1640 { 1641 TCGv t_n = tcg_constant_i32(n); 1642 TCGv_i64 temp64 = tcg_temp_new_i64(); 1643 switch (mode) { 1644 case MODE_LL: 1645 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1646 break; 1647 case MODE_LU: 1648 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1649 break; 1650 case MODE_UL: 1651 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1652 break; 1653 case MODE_UU: 1654 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1655 break; 1656 } 1657 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); 1658 } 1659 1660 static inline void 1661 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1662 { 1663 TCGv temp = tcg_temp_new(); 1664 TCGv temp2 = tcg_temp_new(); 1665 1666 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1667 tcg_gen_shli_tl(temp, r1, 16); 1668 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); 1669 } 1670 1671 static inline void 1672 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1673 uint32_t n, uint32_t mode) 1674 { 1675 TCGv t_n = tcg_constant_i32(n); 1676 TCGv_i64 temp64 = tcg_temp_new_i64(); 1677 switch (mode) { 1678 case MODE_LL: 1679 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1680 break; 1681 case MODE_LU: 1682 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1683 break; 1684 case MODE_UL: 1685 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1686 break; 1687 case MODE_UU: 1688 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1689 break; 1690 } 1691 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 1692 } 1693 1694 static inline void 1695 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1696 { 1697 TCGv temp = tcg_temp_new(); 1698 TCGv temp2 = tcg_temp_new(); 1699 1700 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1701 tcg_gen_shli_tl(temp, r1, 16); 1702 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); 1703 } 1704 1705 static inline void 1706 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1707 { 1708 TCGv temp = tcg_constant_i32(n); 1709 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); 1710 } 1711 1712 static inline void 1713 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1714 { 1715 TCGv temp = tcg_constant_i32(n); 1716 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); 1717 } 1718 1719 static inline void 1720 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1721 uint32_t up_shift) 1722 { 1723 TCGv temp3 = tcg_temp_new(); 1724 TCGv_i64 t1 = tcg_temp_new_i64(); 1725 TCGv_i64 t2 = tcg_temp_new_i64(); 1726 TCGv_i64 t3 = tcg_temp_new_i64(); 1727 TCGv_i64 t4 = tcg_temp_new_i64(); 1728 1729 tcg_gen_ext_i32_i64(t2, arg2); 1730 tcg_gen_ext_i32_i64(t3, arg3); 1731 1732 tcg_gen_mul_i64(t2, t2, t3); 1733 1734 tcg_gen_ext_i32_i64(t1, arg1); 1735 /* if we shift part of the fraction out, we need to round up */ 1736 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1737 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1738 tcg_gen_sari_i64(t2, t2, up_shift - n); 1739 tcg_gen_add_i64(t2, t2, t4); 1740 1741 tcg_gen_sub_i64(t3, t1, t2); 1742 tcg_gen_extrl_i64_i32(temp3, t3); 1743 /* calc v bit */ 1744 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1745 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1746 tcg_gen_or_i64(t1, t1, t2); 1747 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1748 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1749 /* Calc SV bit */ 1750 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1751 /* Calc AV/SAV bits */ 1752 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1753 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1754 /* calc SAV */ 1755 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1756 /* write back result */ 1757 tcg_gen_mov_tl(ret, temp3); 1758 } 1759 1760 static inline void 1761 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1762 { 1763 TCGv temp = tcg_temp_new(); 1764 TCGv temp2 = tcg_temp_new(); 1765 if (n == 0) { 1766 tcg_gen_mul_tl(temp, arg2, arg3); 1767 } else { /* n is expected to be 1 */ 1768 tcg_gen_mul_tl(temp, arg2, arg3); 1769 tcg_gen_shli_tl(temp, temp, 1); 1770 /* catch special case r1 = r2 = 0x8000 */ 1771 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1772 tcg_gen_sub_tl(temp, temp, temp2); 1773 } 1774 gen_sub_d(ret, arg1, temp); 1775 } 1776 1777 static inline void 1778 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1779 { 1780 TCGv temp = tcg_temp_new(); 1781 TCGv temp2 = tcg_temp_new(); 1782 if (n == 0) { 1783 tcg_gen_mul_tl(temp, arg2, arg3); 1784 } else { /* n is expected to be 1 */ 1785 tcg_gen_mul_tl(temp, arg2, arg3); 1786 tcg_gen_shli_tl(temp, temp, 1); 1787 /* catch special case r1 = r2 = 0x8000 */ 1788 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1789 tcg_gen_sub_tl(temp, temp, temp2); 1790 } 1791 gen_subs(ret, arg1, temp); 1792 } 1793 1794 static inline void 1795 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1796 TCGv arg3, uint32_t n) 1797 { 1798 TCGv temp = tcg_temp_new(); 1799 TCGv temp2 = tcg_temp_new(); 1800 TCGv_i64 t1 = tcg_temp_new_i64(); 1801 TCGv_i64 t2 = tcg_temp_new_i64(); 1802 TCGv_i64 t3 = tcg_temp_new_i64(); 1803 1804 if (n == 0) { 1805 tcg_gen_mul_tl(temp, arg2, arg3); 1806 } else { /* n is expected to be 1 */ 1807 tcg_gen_mul_tl(temp, arg2, arg3); 1808 tcg_gen_shli_tl(temp, temp, 1); 1809 /* catch special case r1 = r2 = 0x8000 */ 1810 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1811 tcg_gen_sub_tl(temp, temp, temp2); 1812 } 1813 tcg_gen_ext_i32_i64(t2, temp); 1814 tcg_gen_shli_i64(t2, t2, 16); 1815 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1816 gen_sub64_d(t3, t1, t2); 1817 /* write back result */ 1818 tcg_gen_extr_i64_i32(rl, rh, t3); 1819 } 1820 1821 static inline void 1822 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1823 TCGv arg3, uint32_t n) 1824 { 1825 TCGv temp = tcg_temp_new(); 1826 TCGv temp2 = tcg_temp_new(); 1827 TCGv_i64 t1 = tcg_temp_new_i64(); 1828 TCGv_i64 t2 = tcg_temp_new_i64(); 1829 1830 if (n == 0) { 1831 tcg_gen_mul_tl(temp, arg2, arg3); 1832 } else { /* n is expected to be 1 */ 1833 tcg_gen_mul_tl(temp, arg2, arg3); 1834 tcg_gen_shli_tl(temp, temp, 1); 1835 /* catch special case r1 = r2 = 0x8000 */ 1836 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1837 tcg_gen_sub_tl(temp, temp, temp2); 1838 } 1839 tcg_gen_ext_i32_i64(t2, temp); 1840 tcg_gen_shli_i64(t2, t2, 16); 1841 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1842 1843 gen_helper_sub64_ssov(t1, cpu_env, t1, t2); 1844 tcg_gen_extr_i64_i32(rl, rh, t1); 1845 } 1846 1847 static inline void 1848 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1849 TCGv arg3, uint32_t n) 1850 { 1851 TCGv_i64 t1 = tcg_temp_new_i64(); 1852 TCGv_i64 t2 = tcg_temp_new_i64(); 1853 TCGv_i64 t3 = tcg_temp_new_i64(); 1854 TCGv_i64 t4 = tcg_temp_new_i64(); 1855 TCGv temp, temp2; 1856 1857 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1858 tcg_gen_ext_i32_i64(t2, arg2); 1859 tcg_gen_ext_i32_i64(t3, arg3); 1860 1861 tcg_gen_mul_i64(t2, t2, t3); 1862 if (n != 0) { 1863 tcg_gen_shli_i64(t2, t2, 1); 1864 } 1865 tcg_gen_sub_i64(t4, t1, t2); 1866 /* calc v bit */ 1867 tcg_gen_xor_i64(t3, t4, t1); 1868 tcg_gen_xor_i64(t2, t1, t2); 1869 tcg_gen_and_i64(t3, t3, t2); 1870 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1871 /* We produce an overflow on the host if the mul before was 1872 (0x80000000 * 0x80000000) << 1). If this is the 1873 case, we negate the ovf. */ 1874 if (n == 1) { 1875 temp = tcg_temp_new(); 1876 temp2 = tcg_temp_new(); 1877 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1878 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1879 tcg_gen_and_tl(temp, temp, temp2); 1880 tcg_gen_shli_tl(temp, temp, 31); 1881 /* negate v bit, if special condition */ 1882 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1883 } 1884 /* write back result */ 1885 tcg_gen_extr_i64_i32(rl, rh, t4); 1886 /* Calc SV bit */ 1887 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1888 /* Calc AV/SAV bits */ 1889 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1890 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1891 /* calc SAV */ 1892 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1893 } 1894 1895 static inline void 1896 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1897 uint32_t up_shift) 1898 { 1899 TCGv_i64 t1 = tcg_temp_new_i64(); 1900 TCGv_i64 t2 = tcg_temp_new_i64(); 1901 TCGv_i64 t3 = tcg_temp_new_i64(); 1902 TCGv_i64 t4 = tcg_temp_new_i64(); 1903 1904 tcg_gen_ext_i32_i64(t1, arg1); 1905 tcg_gen_ext_i32_i64(t2, arg2); 1906 tcg_gen_ext_i32_i64(t3, arg3); 1907 1908 tcg_gen_mul_i64(t2, t2, t3); 1909 /* if we shift part of the fraction out, we need to round up */ 1910 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1911 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1912 tcg_gen_sari_i64(t3, t2, up_shift - n); 1913 tcg_gen_add_i64(t3, t3, t4); 1914 1915 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); 1916 } 1917 1918 static inline void 1919 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1920 TCGv arg3, uint32_t n) 1921 { 1922 TCGv_i64 r1 = tcg_temp_new_i64(); 1923 TCGv t_n = tcg_constant_i32(n); 1924 1925 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1926 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); 1927 tcg_gen_extr_i64_i32(rl, rh, r1); 1928 } 1929 1930 static inline void 1931 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1932 TCGv r3, uint32_t n, uint32_t mode) 1933 { 1934 TCGv t_n = tcg_constant_i32(n); 1935 TCGv temp = tcg_temp_new(); 1936 TCGv temp2 = tcg_temp_new(); 1937 TCGv_i64 temp64 = tcg_temp_new_i64(); 1938 switch (mode) { 1939 case MODE_LL: 1940 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1941 break; 1942 case MODE_LU: 1943 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1944 break; 1945 case MODE_UL: 1946 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1947 break; 1948 case MODE_UU: 1949 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1950 break; 1951 } 1952 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1953 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1954 tcg_gen_add_tl, tcg_gen_sub_tl); 1955 } 1956 1957 static inline void 1958 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1959 TCGv r3, uint32_t n, uint32_t mode) 1960 { 1961 TCGv t_n = tcg_constant_i32(n); 1962 TCGv_i64 temp64 = tcg_temp_new_i64(); 1963 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1964 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1965 switch (mode) { 1966 case MODE_LL: 1967 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 1968 break; 1969 case MODE_LU: 1970 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 1971 break; 1972 case MODE_UL: 1973 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 1974 break; 1975 case MODE_UU: 1976 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 1977 break; 1978 } 1979 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 1980 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 1981 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 1982 tcg_gen_sub_i64(temp64, temp64_2, temp64); 1983 tcg_gen_shli_i64(temp64, temp64, 16); 1984 1985 gen_sub64_d(temp64_2, temp64_3, temp64); 1986 /* write back result */ 1987 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 1988 } 1989 1990 static inline void 1991 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1992 { 1993 TCGv t_n = tcg_constant_i32(n); 1994 TCGv temp = tcg_temp_new(); 1995 TCGv temp2 = tcg_temp_new(); 1996 TCGv_i64 temp64 = tcg_temp_new_i64(); 1997 switch (mode) { 1998 case MODE_LL: 1999 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2000 break; 2001 case MODE_LU: 2002 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2003 break; 2004 case MODE_UL: 2005 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2006 break; 2007 case MODE_UU: 2008 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2009 break; 2010 } 2011 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2012 tcg_gen_shli_tl(temp, r1, 16); 2013 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); 2014 } 2015 2016 static inline void 2017 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2018 TCGv r3, uint32_t n, uint32_t mode) 2019 { 2020 TCGv t_n = tcg_constant_i32(n); 2021 TCGv temp = tcg_temp_new(); 2022 TCGv temp2 = tcg_temp_new(); 2023 TCGv temp3 = tcg_temp_new(); 2024 TCGv_i64 temp64 = tcg_temp_new_i64(); 2025 2026 switch (mode) { 2027 case MODE_LL: 2028 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2029 break; 2030 case MODE_LU: 2031 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2032 break; 2033 case MODE_UL: 2034 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2035 break; 2036 case MODE_UU: 2037 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2038 break; 2039 } 2040 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2041 gen_adds(ret_low, r1_low, temp); 2042 tcg_gen_mov_tl(temp, cpu_PSW_V); 2043 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 2044 gen_subs(ret_high, r1_high, temp2); 2045 /* combine v bits */ 2046 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 2047 /* combine av bits */ 2048 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 2049 } 2050 2051 static inline void 2052 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2053 TCGv r3, uint32_t n, uint32_t mode) 2054 { 2055 TCGv t_n = tcg_constant_i32(n); 2056 TCGv_i64 temp64 = tcg_temp_new_i64(); 2057 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2058 2059 switch (mode) { 2060 case MODE_LL: 2061 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2062 break; 2063 case MODE_LU: 2064 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2065 break; 2066 case MODE_UL: 2067 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2068 break; 2069 case MODE_UU: 2070 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2071 break; 2072 } 2073 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2074 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2075 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2076 tcg_gen_shli_i64(temp64, temp64, 16); 2077 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 2078 2079 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 2080 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2081 } 2082 2083 static inline void 2084 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2085 { 2086 TCGv t_n = tcg_constant_i32(n); 2087 TCGv temp = tcg_temp_new(); 2088 TCGv temp2 = tcg_temp_new(); 2089 TCGv_i64 temp64 = tcg_temp_new_i64(); 2090 switch (mode) { 2091 case MODE_LL: 2092 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); 2093 break; 2094 case MODE_LU: 2095 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); 2096 break; 2097 case MODE_UL: 2098 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); 2099 break; 2100 case MODE_UU: 2101 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); 2102 break; 2103 } 2104 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2105 tcg_gen_shli_tl(temp, r1, 16); 2106 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); 2107 } 2108 2109 static inline void gen_abs(TCGv ret, TCGv r1) 2110 { 2111 tcg_gen_abs_tl(ret, r1); 2112 /* overflow can only happen, if r1 = 0x80000000 */ 2113 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); 2114 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2115 /* calc SV bit */ 2116 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2117 /* Calc AV bit */ 2118 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2119 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2120 /* calc SAV bit */ 2121 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2122 } 2123 2124 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) 2125 { 2126 TCGv temp = tcg_temp_new_i32(); 2127 TCGv result = tcg_temp_new_i32(); 2128 2129 tcg_gen_sub_tl(result, r1, r2); 2130 tcg_gen_sub_tl(temp, r2, r1); 2131 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); 2132 2133 /* calc V bit */ 2134 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 2135 tcg_gen_xor_tl(temp, result, r2); 2136 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); 2137 tcg_gen_xor_tl(temp, r1, r2); 2138 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 2139 /* calc SV bit */ 2140 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2141 /* Calc AV bit */ 2142 tcg_gen_add_tl(cpu_PSW_AV, result, result); 2143 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 2144 /* calc SAV bit */ 2145 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2146 /* write back result */ 2147 tcg_gen_mov_tl(ret, result); 2148 } 2149 2150 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) 2151 { 2152 TCGv temp = tcg_constant_i32(con); 2153 gen_absdif(ret, r1, temp); 2154 } 2155 2156 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) 2157 { 2158 TCGv temp = tcg_constant_i32(con); 2159 gen_helper_absdif_ssov(ret, cpu_env, r1, temp); 2160 } 2161 2162 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) 2163 { 2164 TCGv high = tcg_temp_new(); 2165 TCGv low = tcg_temp_new(); 2166 2167 tcg_gen_muls2_tl(low, high, r1, r2); 2168 tcg_gen_mov_tl(ret, low); 2169 /* calc V bit */ 2170 tcg_gen_sari_tl(low, low, 31); 2171 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); 2172 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2173 /* calc SV bit */ 2174 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2175 /* Calc AV bit */ 2176 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2177 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2178 /* calc SAV bit */ 2179 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2180 } 2181 2182 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) 2183 { 2184 TCGv temp = tcg_constant_i32(con); 2185 gen_mul_i32s(ret, r1, temp); 2186 } 2187 2188 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2189 { 2190 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); 2191 /* clear V bit */ 2192 tcg_gen_movi_tl(cpu_PSW_V, 0); 2193 /* calc SV bit */ 2194 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2195 /* Calc AV bit */ 2196 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2197 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2198 /* calc SAV bit */ 2199 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2200 } 2201 2202 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, 2203 int32_t con) 2204 { 2205 TCGv temp = tcg_constant_i32(con); 2206 gen_mul_i64s(ret_low, ret_high, r1, temp); 2207 } 2208 2209 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2210 { 2211 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); 2212 /* clear V bit */ 2213 tcg_gen_movi_tl(cpu_PSW_V, 0); 2214 /* calc SV bit */ 2215 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2216 /* Calc AV bit */ 2217 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2218 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2219 /* calc SAV bit */ 2220 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2221 } 2222 2223 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, 2224 int32_t con) 2225 { 2226 TCGv temp = tcg_constant_i32(con); 2227 gen_mul_i64u(ret_low, ret_high, r1, temp); 2228 } 2229 2230 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) 2231 { 2232 TCGv temp = tcg_constant_i32(con); 2233 gen_helper_mul_ssov(ret, cpu_env, r1, temp); 2234 } 2235 2236 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) 2237 { 2238 TCGv temp = tcg_constant_i32(con); 2239 gen_helper_mul_suov(ret, cpu_env, r1, temp); 2240 } 2241 2242 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ 2243 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2244 { 2245 TCGv temp = tcg_constant_i32(con); 2246 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); 2247 } 2248 2249 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2250 { 2251 TCGv temp = tcg_constant_i32(con); 2252 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); 2253 } 2254 2255 static void 2256 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) 2257 { 2258 TCGv_i64 temp_64 = tcg_temp_new_i64(); 2259 TCGv_i64 temp2_64 = tcg_temp_new_i64(); 2260 2261 if (n == 0) { 2262 if (up_shift == 32) { 2263 tcg_gen_muls2_tl(rh, rl, arg1, arg2); 2264 } else if (up_shift == 16) { 2265 tcg_gen_ext_i32_i64(temp_64, arg1); 2266 tcg_gen_ext_i32_i64(temp2_64, arg2); 2267 2268 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2269 tcg_gen_shri_i64(temp_64, temp_64, up_shift); 2270 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2271 } else { 2272 tcg_gen_muls2_tl(rl, rh, arg1, arg2); 2273 } 2274 /* reset v bit */ 2275 tcg_gen_movi_tl(cpu_PSW_V, 0); 2276 } else { /* n is expected to be 1 */ 2277 tcg_gen_ext_i32_i64(temp_64, arg1); 2278 tcg_gen_ext_i32_i64(temp2_64, arg2); 2279 2280 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2281 2282 if (up_shift == 0) { 2283 tcg_gen_shli_i64(temp_64, temp_64, 1); 2284 } else { 2285 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); 2286 } 2287 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2288 /* overflow only occurs if r1 = r2 = 0x8000 */ 2289 if (up_shift == 0) {/* result is 64 bit */ 2290 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, 2291 0x80000000); 2292 } else { /* result is 32 bit */ 2293 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, 2294 0x80000000); 2295 } 2296 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2297 /* calc sv overflow bit */ 2298 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2299 } 2300 /* calc av overflow bit */ 2301 if (up_shift == 0) { 2302 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2303 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2304 } else { 2305 tcg_gen_add_tl(cpu_PSW_AV, rl, rl); 2306 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); 2307 } 2308 /* calc sav overflow bit */ 2309 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2310 } 2311 2312 static void 2313 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2314 { 2315 TCGv temp = tcg_temp_new(); 2316 if (n == 0) { 2317 tcg_gen_mul_tl(ret, arg1, arg2); 2318 } else { /* n is expected to be 1 */ 2319 tcg_gen_mul_tl(ret, arg1, arg2); 2320 tcg_gen_shli_tl(ret, ret, 1); 2321 /* catch special case r1 = r2 = 0x8000 */ 2322 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); 2323 tcg_gen_sub_tl(ret, ret, temp); 2324 } 2325 /* reset v bit */ 2326 tcg_gen_movi_tl(cpu_PSW_V, 0); 2327 /* calc av overflow bit */ 2328 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2329 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2330 /* calc sav overflow bit */ 2331 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2332 } 2333 2334 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2335 { 2336 TCGv temp = tcg_temp_new(); 2337 if (n == 0) { 2338 tcg_gen_mul_tl(ret, arg1, arg2); 2339 tcg_gen_addi_tl(ret, ret, 0x8000); 2340 } else { 2341 tcg_gen_mul_tl(ret, arg1, arg2); 2342 tcg_gen_shli_tl(ret, ret, 1); 2343 tcg_gen_addi_tl(ret, ret, 0x8000); 2344 /* catch special case r1 = r2 = 0x8000 */ 2345 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); 2346 tcg_gen_muli_tl(temp, temp, 0x8001); 2347 tcg_gen_sub_tl(ret, ret, temp); 2348 } 2349 /* reset v bit */ 2350 tcg_gen_movi_tl(cpu_PSW_V, 0); 2351 /* calc av overflow bit */ 2352 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2353 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2354 /* calc sav overflow bit */ 2355 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2356 /* cut halfword off */ 2357 tcg_gen_andi_tl(ret, ret, 0xffff0000); 2358 } 2359 2360 static inline void 2361 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2362 TCGv r3) 2363 { 2364 TCGv_i64 temp64 = tcg_temp_new_i64(); 2365 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2366 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); 2367 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2368 } 2369 2370 static inline void 2371 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2372 int32_t con) 2373 { 2374 TCGv temp = tcg_constant_i32(con); 2375 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2376 } 2377 2378 static inline void 2379 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2380 TCGv r3) 2381 { 2382 TCGv_i64 temp64 = tcg_temp_new_i64(); 2383 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2384 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); 2385 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2386 } 2387 2388 static inline void 2389 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2390 int32_t con) 2391 { 2392 TCGv temp = tcg_constant_i32(con); 2393 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2394 } 2395 2396 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2397 { 2398 TCGv temp = tcg_constant_i32(con); 2399 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); 2400 } 2401 2402 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2403 { 2404 TCGv temp = tcg_constant_i32(con); 2405 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); 2406 } 2407 2408 static inline void 2409 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2410 TCGv r3) 2411 { 2412 TCGv_i64 temp64 = tcg_temp_new_i64(); 2413 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2414 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); 2415 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2416 } 2417 2418 static inline void 2419 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2420 int32_t con) 2421 { 2422 TCGv temp = tcg_constant_i32(con); 2423 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2424 } 2425 2426 static inline void 2427 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2428 TCGv r3) 2429 { 2430 TCGv_i64 temp64 = tcg_temp_new_i64(); 2431 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2432 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); 2433 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2434 } 2435 2436 static inline void 2437 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2438 int32_t con) 2439 { 2440 TCGv temp = tcg_constant_i32(con); 2441 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2442 } 2443 2444 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) 2445 { 2446 TCGv sat_neg = tcg_const_i32(low); 2447 TCGv temp = tcg_const_i32(up); 2448 2449 /* sat_neg = (arg < low ) ? low : arg; */ 2450 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg); 2451 2452 /* ret = (sat_neg > up ) ? up : sat_neg; */ 2453 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg); 2454 } 2455 2456 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) 2457 { 2458 TCGv temp = tcg_const_i32(up); 2459 /* sat_neg = (arg > up ) ? up : arg; */ 2460 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg); 2461 } 2462 2463 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) 2464 { 2465 if (shift_count == -32) { 2466 tcg_gen_movi_tl(ret, 0); 2467 } else if (shift_count >= 0) { 2468 tcg_gen_shli_tl(ret, r1, shift_count); 2469 } else { 2470 tcg_gen_shri_tl(ret, r1, -shift_count); 2471 } 2472 } 2473 2474 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) 2475 { 2476 TCGv temp_low, temp_high; 2477 2478 if (shiftcount == -16) { 2479 tcg_gen_movi_tl(ret, 0); 2480 } else { 2481 temp_high = tcg_temp_new(); 2482 temp_low = tcg_temp_new(); 2483 2484 tcg_gen_andi_tl(temp_low, r1, 0xffff); 2485 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); 2486 gen_shi(temp_low, temp_low, shiftcount); 2487 gen_shi(ret, temp_high, shiftcount); 2488 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); 2489 } 2490 } 2491 2492 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) 2493 { 2494 uint32_t msk, msk_start; 2495 TCGv temp = tcg_temp_new(); 2496 TCGv temp2 = tcg_temp_new(); 2497 2498 if (shift_count == 0) { 2499 /* Clear PSW.C and PSW.V */ 2500 tcg_gen_movi_tl(cpu_PSW_C, 0); 2501 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); 2502 tcg_gen_mov_tl(ret, r1); 2503 } else if (shift_count == -32) { 2504 /* set PSW.C */ 2505 tcg_gen_mov_tl(cpu_PSW_C, r1); 2506 /* fill ret completely with sign bit */ 2507 tcg_gen_sari_tl(ret, r1, 31); 2508 /* clear PSW.V */ 2509 tcg_gen_movi_tl(cpu_PSW_V, 0); 2510 } else if (shift_count > 0) { 2511 TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count); 2512 TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count); 2513 2514 /* calc carry */ 2515 msk_start = 32 - shift_count; 2516 msk = ((1 << shift_count) - 1) << msk_start; 2517 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2518 /* calc v/sv bits */ 2519 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); 2520 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); 2521 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 2522 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2523 /* calc sv */ 2524 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); 2525 /* do shift */ 2526 tcg_gen_shli_tl(ret, r1, shift_count); 2527 } else { 2528 /* clear PSW.V */ 2529 tcg_gen_movi_tl(cpu_PSW_V, 0); 2530 /* calc carry */ 2531 msk = (1 << -shift_count) - 1; 2532 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2533 /* do shift */ 2534 tcg_gen_sari_tl(ret, r1, -shift_count); 2535 } 2536 /* calc av overflow bit */ 2537 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2538 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2539 /* calc sav overflow bit */ 2540 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2541 } 2542 2543 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) 2544 { 2545 gen_helper_sha_ssov(ret, cpu_env, r1, r2); 2546 } 2547 2548 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) 2549 { 2550 TCGv temp = tcg_constant_i32(con); 2551 gen_shas(ret, r1, temp); 2552 } 2553 2554 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) 2555 { 2556 TCGv low, high; 2557 2558 if (shift_count == 0) { 2559 tcg_gen_mov_tl(ret, r1); 2560 } else if (shift_count > 0) { 2561 low = tcg_temp_new(); 2562 high = tcg_temp_new(); 2563 2564 tcg_gen_andi_tl(high, r1, 0xffff0000); 2565 tcg_gen_shli_tl(low, r1, shift_count); 2566 tcg_gen_shli_tl(ret, high, shift_count); 2567 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2568 } else { 2569 low = tcg_temp_new(); 2570 high = tcg_temp_new(); 2571 2572 tcg_gen_ext16s_tl(low, r1); 2573 tcg_gen_sari_tl(low, low, -shift_count); 2574 tcg_gen_sari_tl(ret, r1, -shift_count); 2575 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2576 } 2577 } 2578 2579 /* ret = {ret[30:0], (r1 cond r2)}; */ 2580 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) 2581 { 2582 TCGv temp = tcg_temp_new(); 2583 TCGv temp2 = tcg_temp_new(); 2584 2585 tcg_gen_shli_tl(temp, ret, 1); 2586 tcg_gen_setcond_tl(cond, temp2, r1, r2); 2587 tcg_gen_or_tl(ret, temp, temp2); 2588 } 2589 2590 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) 2591 { 2592 TCGv temp = tcg_constant_i32(con); 2593 gen_sh_cond(cond, ret, r1, temp); 2594 } 2595 2596 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) 2597 { 2598 gen_helper_add_ssov(ret, cpu_env, r1, r2); 2599 } 2600 2601 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) 2602 { 2603 TCGv temp = tcg_constant_i32(con); 2604 gen_helper_add_ssov(ret, cpu_env, r1, temp); 2605 } 2606 2607 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) 2608 { 2609 TCGv temp = tcg_constant_i32(con); 2610 gen_helper_add_suov(ret, cpu_env, r1, temp); 2611 } 2612 2613 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) 2614 { 2615 gen_helper_sub_ssov(ret, cpu_env, r1, r2); 2616 } 2617 2618 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) 2619 { 2620 gen_helper_sub_suov(ret, cpu_env, r1, r2); 2621 } 2622 2623 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, 2624 int pos1, int pos2, 2625 void(*op1)(TCGv, TCGv, TCGv), 2626 void(*op2)(TCGv, TCGv, TCGv)) 2627 { 2628 TCGv temp1, temp2; 2629 2630 temp1 = tcg_temp_new(); 2631 temp2 = tcg_temp_new(); 2632 2633 tcg_gen_shri_tl(temp2, r2, pos2); 2634 tcg_gen_shri_tl(temp1, r1, pos1); 2635 2636 (*op1)(temp1, temp1, temp2); 2637 (*op2)(temp1 , ret, temp1); 2638 2639 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); 2640 } 2641 2642 /* ret = r1[pos1] op1 r2[pos2]; */ 2643 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, 2644 int pos1, int pos2, 2645 void(*op1)(TCGv, TCGv, TCGv)) 2646 { 2647 TCGv temp1, temp2; 2648 2649 temp1 = tcg_temp_new(); 2650 temp2 = tcg_temp_new(); 2651 2652 tcg_gen_shri_tl(temp2, r2, pos2); 2653 tcg_gen_shri_tl(temp1, r1, pos1); 2654 2655 (*op1)(ret, temp1, temp2); 2656 2657 tcg_gen_andi_tl(ret, ret, 0x1); 2658 } 2659 2660 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, 2661 void(*op)(TCGv, TCGv, TCGv)) 2662 { 2663 TCGv temp = tcg_temp_new(); 2664 TCGv temp2 = tcg_temp_new(); 2665 /* temp = (arg1 cond arg2 )*/ 2666 tcg_gen_setcond_tl(cond, temp, r1, r2); 2667 /* temp2 = ret[0]*/ 2668 tcg_gen_andi_tl(temp2, ret, 0x1); 2669 /* temp = temp insn temp2 */ 2670 (*op)(temp, temp, temp2); 2671 /* ret = {ret[31:1], temp} */ 2672 tcg_gen_deposit_tl(ret, ret, temp, 0, 1); 2673 } 2674 2675 static inline void 2676 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, 2677 void(*op)(TCGv, TCGv, TCGv)) 2678 { 2679 TCGv temp = tcg_constant_i32(con); 2680 gen_accumulating_cond(cond, ret, r1, temp, op); 2681 } 2682 2683 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ 2684 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2) 2685 { 2686 tcg_gen_setcond_tl(cond, ret, r1, r2); 2687 tcg_gen_neg_tl(ret, ret); 2688 } 2689 2690 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) 2691 { 2692 TCGv b0 = tcg_temp_new(); 2693 TCGv b1 = tcg_temp_new(); 2694 TCGv b2 = tcg_temp_new(); 2695 TCGv b3 = tcg_temp_new(); 2696 2697 /* byte 0 */ 2698 tcg_gen_andi_tl(b0, r1, 0xff); 2699 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); 2700 2701 /* byte 1 */ 2702 tcg_gen_andi_tl(b1, r1, 0xff00); 2703 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); 2704 2705 /* byte 2 */ 2706 tcg_gen_andi_tl(b2, r1, 0xff0000); 2707 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); 2708 2709 /* byte 3 */ 2710 tcg_gen_andi_tl(b3, r1, 0xff000000); 2711 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); 2712 2713 /* combine them */ 2714 tcg_gen_or_tl(ret, b0, b1); 2715 tcg_gen_or_tl(ret, ret, b2); 2716 tcg_gen_or_tl(ret, ret, b3); 2717 } 2718 2719 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) 2720 { 2721 TCGv h0 = tcg_temp_new(); 2722 TCGv h1 = tcg_temp_new(); 2723 2724 /* halfword 0 */ 2725 tcg_gen_andi_tl(h0, r1, 0xffff); 2726 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); 2727 2728 /* halfword 1 */ 2729 tcg_gen_andi_tl(h1, r1, 0xffff0000); 2730 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); 2731 2732 /* combine them */ 2733 tcg_gen_or_tl(ret, h0, h1); 2734 } 2735 2736 /* mask = ((1 << width) -1) << pos; 2737 ret = (r1 & ~mask) | (r2 << pos) & mask); */ 2738 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) 2739 { 2740 TCGv mask = tcg_temp_new(); 2741 TCGv temp = tcg_temp_new(); 2742 TCGv temp2 = tcg_temp_new(); 2743 2744 tcg_gen_movi_tl(mask, 1); 2745 tcg_gen_shl_tl(mask, mask, width); 2746 tcg_gen_subi_tl(mask, mask, 1); 2747 tcg_gen_shl_tl(mask, mask, pos); 2748 2749 tcg_gen_shl_tl(temp, r2, pos); 2750 tcg_gen_and_tl(temp, temp, mask); 2751 tcg_gen_andc_tl(temp2, r1, mask); 2752 tcg_gen_or_tl(ret, temp, temp2); 2753 } 2754 2755 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) 2756 { 2757 TCGv_i64 temp = tcg_temp_new_i64(); 2758 2759 gen_helper_bsplit(temp, r1); 2760 tcg_gen_extr_i64_i32(rl, rh, temp); 2761 } 2762 2763 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) 2764 { 2765 TCGv_i64 temp = tcg_temp_new_i64(); 2766 2767 gen_helper_unpack(temp, r1); 2768 tcg_gen_extr_i64_i32(rl, rh, temp); 2769 } 2770 2771 static inline void 2772 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2773 { 2774 TCGv_i64 ret = tcg_temp_new_i64(); 2775 2776 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2777 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); 2778 } else { 2779 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); 2780 } 2781 tcg_gen_extr_i64_i32(rl, rh, ret); 2782 } 2783 2784 static inline void 2785 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 2786 { 2787 TCGv_i64 ret = tcg_temp_new_i64(); 2788 2789 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 2790 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); 2791 } else { 2792 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); 2793 } 2794 tcg_gen_extr_i64_i32(rl, rh, ret); 2795 } 2796 2797 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) 2798 { 2799 TCGv temp = tcg_temp_new(); 2800 /* calc AV bit */ 2801 tcg_gen_add_tl(temp, arg_low, arg_low); 2802 tcg_gen_xor_tl(temp, temp, arg_low); 2803 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); 2804 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); 2805 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2806 /* calc SAV bit */ 2807 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2808 tcg_gen_movi_tl(cpu_PSW_V, 0); 2809 } 2810 2811 static void gen_calc_usb_mulr_h(TCGv arg) 2812 { 2813 TCGv temp = tcg_temp_new(); 2814 /* calc AV bit */ 2815 tcg_gen_add_tl(temp, arg, arg); 2816 tcg_gen_xor_tl(temp, temp, arg); 2817 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); 2818 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 2819 /* calc SAV bit */ 2820 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2821 /* clear V bit */ 2822 tcg_gen_movi_tl(cpu_PSW_V, 0); 2823 } 2824 2825 /* helpers for generating program flow micro-ops */ 2826 2827 static inline void gen_save_pc(target_ulong pc) 2828 { 2829 tcg_gen_movi_tl(cpu_PC, pc); 2830 } 2831 2832 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 2833 { 2834 if (translator_use_goto_tb(&ctx->base, dest)) { 2835 tcg_gen_goto_tb(n); 2836 gen_save_pc(dest); 2837 tcg_gen_exit_tb(ctx->base.tb, n); 2838 } else { 2839 gen_save_pc(dest); 2840 tcg_gen_lookup_and_goto_ptr(); 2841 } 2842 } 2843 2844 static void generate_trap(DisasContext *ctx, int class, int tin) 2845 { 2846 TCGv_i32 classtemp = tcg_constant_i32(class); 2847 TCGv_i32 tintemp = tcg_constant_i32(tin); 2848 2849 gen_save_pc(ctx->base.pc_next); 2850 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); 2851 ctx->base.is_jmp = DISAS_NORETURN; 2852 } 2853 2854 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, 2855 TCGv r2, int16_t address) 2856 { 2857 TCGLabel *jumpLabel = gen_new_label(); 2858 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); 2859 2860 gen_goto_tb(ctx, 1, ctx->pc_succ_insn); 2861 2862 gen_set_label(jumpLabel); 2863 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); 2864 } 2865 2866 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, 2867 int r2, int16_t address) 2868 { 2869 TCGv temp = tcg_constant_i32(r2); 2870 gen_branch_cond(ctx, cond, r1, temp, address); 2871 } 2872 2873 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) 2874 { 2875 TCGLabel *l1 = gen_new_label(); 2876 2877 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); 2878 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); 2879 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); 2880 gen_set_label(l1); 2881 gen_goto_tb(ctx, 0, ctx->pc_succ_insn); 2882 } 2883 2884 static void gen_fcall_save_ctx(DisasContext *ctx) 2885 { 2886 TCGv temp = tcg_temp_new(); 2887 2888 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); 2889 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); 2890 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 2891 tcg_gen_mov_tl(cpu_gpr_a[10], temp); 2892 } 2893 2894 static void gen_fret(DisasContext *ctx) 2895 { 2896 TCGv temp = tcg_temp_new(); 2897 2898 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); 2899 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); 2900 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); 2901 tcg_gen_mov_tl(cpu_PC, temp); 2902 tcg_gen_exit_tb(NULL, 0); 2903 ctx->base.is_jmp = DISAS_NORETURN; 2904 } 2905 2906 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 2907 int r2 , int32_t constant , int32_t offset) 2908 { 2909 TCGv temp, temp2; 2910 int n; 2911 2912 switch (opc) { 2913 /* SB-format jumps */ 2914 case OPC1_16_SB_J: 2915 case OPC1_32_B_J: 2916 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2917 break; 2918 case OPC1_32_B_CALL: 2919 case OPC1_16_SB_CALL: 2920 gen_helper_1arg(call, ctx->pc_succ_insn); 2921 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 2922 break; 2923 case OPC1_16_SB_JZ: 2924 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); 2925 break; 2926 case OPC1_16_SB_JNZ: 2927 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); 2928 break; 2929 /* SBC-format jumps */ 2930 case OPC1_16_SBC_JEQ: 2931 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); 2932 break; 2933 case OPC1_16_SBC_JEQ2: 2934 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, 2935 offset + 16); 2936 break; 2937 case OPC1_16_SBC_JNE: 2938 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); 2939 break; 2940 case OPC1_16_SBC_JNE2: 2941 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 2942 constant, offset + 16); 2943 break; 2944 /* SBRN-format jumps */ 2945 case OPC1_16_SBRN_JZ_T: 2946 temp = tcg_temp_new(); 2947 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2948 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 2949 break; 2950 case OPC1_16_SBRN_JNZ_T: 2951 temp = tcg_temp_new(); 2952 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 2953 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 2954 break; 2955 /* SBR-format jumps */ 2956 case OPC1_16_SBR_JEQ: 2957 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2958 offset); 2959 break; 2960 case OPC1_16_SBR_JEQ2: 2961 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 2962 offset + 16); 2963 break; 2964 case OPC1_16_SBR_JNE: 2965 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2966 offset); 2967 break; 2968 case OPC1_16_SBR_JNE2: 2969 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 2970 offset + 16); 2971 break; 2972 case OPC1_16_SBR_JNZ: 2973 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); 2974 break; 2975 case OPC1_16_SBR_JNZ_A: 2976 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 2977 break; 2978 case OPC1_16_SBR_JGEZ: 2979 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); 2980 break; 2981 case OPC1_16_SBR_JGTZ: 2982 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); 2983 break; 2984 case OPC1_16_SBR_JLEZ: 2985 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); 2986 break; 2987 case OPC1_16_SBR_JLTZ: 2988 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); 2989 break; 2990 case OPC1_16_SBR_JZ: 2991 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); 2992 break; 2993 case OPC1_16_SBR_JZ_A: 2994 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 2995 break; 2996 case OPC1_16_SBR_LOOP: 2997 gen_loop(ctx, r1, offset * 2 - 32); 2998 break; 2999 /* SR-format jumps */ 3000 case OPC1_16_SR_JI: 3001 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); 3002 tcg_gen_exit_tb(NULL, 0); 3003 break; 3004 case OPC2_32_SYS_RET: 3005 case OPC2_16_SR_RET: 3006 gen_helper_ret(cpu_env); 3007 tcg_gen_exit_tb(NULL, 0); 3008 break; 3009 /* B-format */ 3010 case OPC1_32_B_CALLA: 3011 gen_helper_1arg(call, ctx->pc_succ_insn); 3012 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3013 break; 3014 case OPC1_32_B_FCALL: 3015 gen_fcall_save_ctx(ctx); 3016 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3017 break; 3018 case OPC1_32_B_FCALLA: 3019 gen_fcall_save_ctx(ctx); 3020 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3021 break; 3022 case OPC1_32_B_JLA: 3023 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3024 /* fall through */ 3025 case OPC1_32_B_JA: 3026 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3027 break; 3028 case OPC1_32_B_JL: 3029 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 3030 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3031 break; 3032 /* BOL format */ 3033 case OPCM_32_BRC_EQ_NEQ: 3034 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { 3035 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); 3036 } else { 3037 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); 3038 } 3039 break; 3040 case OPCM_32_BRC_GE: 3041 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { 3042 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); 3043 } else { 3044 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3045 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, 3046 offset); 3047 } 3048 break; 3049 case OPCM_32_BRC_JLT: 3050 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { 3051 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); 3052 } else { 3053 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3054 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, 3055 offset); 3056 } 3057 break; 3058 case OPCM_32_BRC_JNE: 3059 temp = tcg_temp_new(); 3060 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { 3061 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3062 /* subi is unconditional */ 3063 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3064 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3065 } else { 3066 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3067 /* addi is unconditional */ 3068 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3069 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3070 } 3071 break; 3072 /* BRN format */ 3073 case OPCM_32_BRN_JTT: 3074 n = MASK_OP_BRN_N(ctx->opcode); 3075 3076 temp = tcg_temp_new(); 3077 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); 3078 3079 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { 3080 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3081 } else { 3082 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3083 } 3084 break; 3085 /* BRR Format */ 3086 case OPCM_32_BRR_EQ_NEQ: 3087 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { 3088 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], 3089 offset); 3090 } else { 3091 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3092 offset); 3093 } 3094 break; 3095 case OPCM_32_BRR_ADDR_EQ_NEQ: 3096 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { 3097 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], 3098 offset); 3099 } else { 3100 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], 3101 offset); 3102 } 3103 break; 3104 case OPCM_32_BRR_GE: 3105 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { 3106 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3107 offset); 3108 } else { 3109 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3110 offset); 3111 } 3112 break; 3113 case OPCM_32_BRR_JLT: 3114 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { 3115 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], 3116 offset); 3117 } else { 3118 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3119 offset); 3120 } 3121 break; 3122 case OPCM_32_BRR_LOOP: 3123 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { 3124 gen_loop(ctx, r2, offset * 2); 3125 } else { 3126 /* OPC2_32_BRR_LOOPU */ 3127 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); 3128 } 3129 break; 3130 case OPCM_32_BRR_JNE: 3131 temp = tcg_temp_new(); 3132 temp2 = tcg_temp_new(); 3133 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { 3134 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3135 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3136 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3137 /* subi is unconditional */ 3138 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3139 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3140 } else { 3141 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3142 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3143 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3144 /* addi is unconditional */ 3145 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3146 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3147 } 3148 break; 3149 case OPCM_32_BRR_JNZ: 3150 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { 3151 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3152 } else { 3153 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3154 } 3155 break; 3156 default: 3157 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3158 } 3159 ctx->base.is_jmp = DISAS_NORETURN; 3160 } 3161 3162 3163 /* 3164 * Functions for decoding instructions 3165 */ 3166 3167 static void decode_src_opc(DisasContext *ctx, int op1) 3168 { 3169 int r1; 3170 int32_t const4; 3171 TCGv temp, temp2; 3172 3173 r1 = MASK_OP_SRC_S1D(ctx->opcode); 3174 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); 3175 3176 switch (op1) { 3177 case OPC1_16_SRC_ADD: 3178 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3179 break; 3180 case OPC1_16_SRC_ADD_A15: 3181 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); 3182 break; 3183 case OPC1_16_SRC_ADD_15A: 3184 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); 3185 break; 3186 case OPC1_16_SRC_ADD_A: 3187 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); 3188 break; 3189 case OPC1_16_SRC_CADD: 3190 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3191 cpu_gpr_d[15]); 3192 break; 3193 case OPC1_16_SRC_CADDN: 3194 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3195 cpu_gpr_d[15]); 3196 break; 3197 case OPC1_16_SRC_CMOV: 3198 temp = tcg_constant_tl(0); 3199 temp2 = tcg_constant_tl(const4); 3200 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3201 temp2, cpu_gpr_d[r1]); 3202 break; 3203 case OPC1_16_SRC_CMOVN: 3204 temp = tcg_constant_tl(0); 3205 temp2 = tcg_constant_tl(const4); 3206 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3207 temp2, cpu_gpr_d[r1]); 3208 break; 3209 case OPC1_16_SRC_EQ: 3210 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3211 const4); 3212 break; 3213 case OPC1_16_SRC_LT: 3214 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3215 const4); 3216 break; 3217 case OPC1_16_SRC_MOV: 3218 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3219 break; 3220 case OPC1_16_SRC_MOV_A: 3221 const4 = MASK_OP_SRC_CONST4(ctx->opcode); 3222 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); 3223 break; 3224 case OPC1_16_SRC_MOV_E: 3225 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3226 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3227 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); 3228 } else { 3229 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3230 } 3231 break; 3232 case OPC1_16_SRC_SH: 3233 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3234 break; 3235 case OPC1_16_SRC_SHA: 3236 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3237 break; 3238 default: 3239 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3240 } 3241 } 3242 3243 static void decode_srr_opc(DisasContext *ctx, int op1) 3244 { 3245 int r1, r2; 3246 TCGv temp; 3247 3248 r1 = MASK_OP_SRR_S1D(ctx->opcode); 3249 r2 = MASK_OP_SRR_S2(ctx->opcode); 3250 3251 switch (op1) { 3252 case OPC1_16_SRR_ADD: 3253 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3254 break; 3255 case OPC1_16_SRR_ADD_A15: 3256 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3257 break; 3258 case OPC1_16_SRR_ADD_15A: 3259 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3260 break; 3261 case OPC1_16_SRR_ADD_A: 3262 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); 3263 break; 3264 case OPC1_16_SRR_ADDS: 3265 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3266 break; 3267 case OPC1_16_SRR_AND: 3268 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3269 break; 3270 case OPC1_16_SRR_CMOV: 3271 temp = tcg_constant_tl(0); 3272 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3273 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3274 break; 3275 case OPC1_16_SRR_CMOVN: 3276 temp = tcg_constant_tl(0); 3277 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3278 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3279 break; 3280 case OPC1_16_SRR_EQ: 3281 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3282 cpu_gpr_d[r2]); 3283 break; 3284 case OPC1_16_SRR_LT: 3285 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3286 cpu_gpr_d[r2]); 3287 break; 3288 case OPC1_16_SRR_MOV: 3289 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); 3290 break; 3291 case OPC1_16_SRR_MOV_A: 3292 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); 3293 break; 3294 case OPC1_16_SRR_MOV_AA: 3295 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); 3296 break; 3297 case OPC1_16_SRR_MOV_D: 3298 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); 3299 break; 3300 case OPC1_16_SRR_MUL: 3301 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3302 break; 3303 case OPC1_16_SRR_OR: 3304 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3305 break; 3306 case OPC1_16_SRR_SUB: 3307 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3308 break; 3309 case OPC1_16_SRR_SUB_A15B: 3310 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3311 break; 3312 case OPC1_16_SRR_SUB_15AB: 3313 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3314 break; 3315 case OPC1_16_SRR_SUBS: 3316 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3317 break; 3318 case OPC1_16_SRR_XOR: 3319 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3320 break; 3321 default: 3322 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3323 } 3324 } 3325 3326 static void decode_ssr_opc(DisasContext *ctx, int op1) 3327 { 3328 int r1, r2; 3329 3330 r1 = MASK_OP_SSR_S1(ctx->opcode); 3331 r2 = MASK_OP_SSR_S2(ctx->opcode); 3332 3333 switch (op1) { 3334 case OPC1_16_SSR_ST_A: 3335 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3336 break; 3337 case OPC1_16_SSR_ST_A_POSTINC: 3338 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3339 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3340 break; 3341 case OPC1_16_SSR_ST_B: 3342 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3343 break; 3344 case OPC1_16_SSR_ST_B_POSTINC: 3345 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3346 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3347 break; 3348 case OPC1_16_SSR_ST_H: 3349 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3350 break; 3351 case OPC1_16_SSR_ST_H_POSTINC: 3352 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3353 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3354 break; 3355 case OPC1_16_SSR_ST_W: 3356 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3357 break; 3358 case OPC1_16_SSR_ST_W_POSTINC: 3359 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3360 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3361 break; 3362 default: 3363 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3364 } 3365 } 3366 3367 static void decode_sc_opc(DisasContext *ctx, int op1) 3368 { 3369 int32_t const16; 3370 3371 const16 = MASK_OP_SC_CONST8(ctx->opcode); 3372 3373 switch (op1) { 3374 case OPC1_16_SC_AND: 3375 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3376 break; 3377 case OPC1_16_SC_BISR: 3378 gen_helper_1arg(bisr, const16 & 0xff); 3379 break; 3380 case OPC1_16_SC_LD_A: 3381 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3382 break; 3383 case OPC1_16_SC_LD_W: 3384 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3385 break; 3386 case OPC1_16_SC_MOV: 3387 tcg_gen_movi_tl(cpu_gpr_d[15], const16); 3388 break; 3389 case OPC1_16_SC_OR: 3390 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3391 break; 3392 case OPC1_16_SC_ST_A: 3393 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3394 break; 3395 case OPC1_16_SC_ST_W: 3396 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3397 break; 3398 case OPC1_16_SC_SUB_A: 3399 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); 3400 break; 3401 default: 3402 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3403 } 3404 } 3405 3406 static void decode_slr_opc(DisasContext *ctx, int op1) 3407 { 3408 int r1, r2; 3409 3410 r1 = MASK_OP_SLR_D(ctx->opcode); 3411 r2 = MASK_OP_SLR_S2(ctx->opcode); 3412 3413 switch (op1) { 3414 /* SLR-format */ 3415 case OPC1_16_SLR_LD_A: 3416 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3417 break; 3418 case OPC1_16_SLR_LD_A_POSTINC: 3419 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3420 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3421 break; 3422 case OPC1_16_SLR_LD_BU: 3423 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3424 break; 3425 case OPC1_16_SLR_LD_BU_POSTINC: 3426 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3427 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3428 break; 3429 case OPC1_16_SLR_LD_H: 3430 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3431 break; 3432 case OPC1_16_SLR_LD_H_POSTINC: 3433 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3434 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3435 break; 3436 case OPC1_16_SLR_LD_W: 3437 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3438 break; 3439 case OPC1_16_SLR_LD_W_POSTINC: 3440 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3441 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3442 break; 3443 default: 3444 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3445 } 3446 } 3447 3448 static void decode_sro_opc(DisasContext *ctx, int op1) 3449 { 3450 int r2; 3451 int32_t address; 3452 3453 r2 = MASK_OP_SRO_S2(ctx->opcode); 3454 address = MASK_OP_SRO_OFF4(ctx->opcode); 3455 3456 /* SRO-format */ 3457 switch (op1) { 3458 case OPC1_16_SRO_LD_A: 3459 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3460 break; 3461 case OPC1_16_SRO_LD_BU: 3462 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3463 break; 3464 case OPC1_16_SRO_LD_H: 3465 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3466 break; 3467 case OPC1_16_SRO_LD_W: 3468 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3469 break; 3470 case OPC1_16_SRO_ST_A: 3471 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3472 break; 3473 case OPC1_16_SRO_ST_B: 3474 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3475 break; 3476 case OPC1_16_SRO_ST_H: 3477 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3478 break; 3479 case OPC1_16_SRO_ST_W: 3480 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3481 break; 3482 default: 3483 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3484 } 3485 } 3486 3487 static void decode_sr_system(DisasContext *ctx) 3488 { 3489 uint32_t op2; 3490 op2 = MASK_OP_SR_OP2(ctx->opcode); 3491 3492 switch (op2) { 3493 case OPC2_16_SR_NOP: 3494 break; 3495 case OPC2_16_SR_RET: 3496 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 3497 break; 3498 case OPC2_16_SR_RFE: 3499 gen_helper_rfe(cpu_env); 3500 tcg_gen_exit_tb(NULL, 0); 3501 ctx->base.is_jmp = DISAS_NORETURN; 3502 break; 3503 case OPC2_16_SR_DEBUG: 3504 /* raise EXCP_DEBUG */ 3505 break; 3506 case OPC2_16_SR_FRET: 3507 gen_fret(ctx); 3508 break; 3509 default: 3510 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3511 } 3512 } 3513 3514 static void decode_sr_accu(DisasContext *ctx) 3515 { 3516 uint32_t op2; 3517 uint32_t r1; 3518 3519 r1 = MASK_OP_SR_S1D(ctx->opcode); 3520 op2 = MASK_OP_SR_OP2(ctx->opcode); 3521 3522 switch (op2) { 3523 case OPC2_16_SR_RSUB: 3524 /* calc V bit -- overflow only if r1 = -0x80000000 */ 3525 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000); 3526 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 3527 /* calc SV bit */ 3528 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 3529 /* sub */ 3530 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3531 /* calc av */ 3532 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); 3533 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); 3534 /* calc sav */ 3535 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3536 break; 3537 case OPC2_16_SR_SAT_B: 3538 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); 3539 break; 3540 case OPC2_16_SR_SAT_BU: 3541 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); 3542 break; 3543 case OPC2_16_SR_SAT_H: 3544 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); 3545 break; 3546 case OPC2_16_SR_SAT_HU: 3547 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); 3548 break; 3549 default: 3550 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3551 } 3552 } 3553 3554 static void decode_16Bit_opc(DisasContext *ctx) 3555 { 3556 int op1; 3557 int r1, r2; 3558 int32_t const16; 3559 int32_t address; 3560 TCGv temp; 3561 3562 op1 = MASK_OP_MAJOR(ctx->opcode); 3563 3564 /* handle ADDSC.A opcode only being 6 bit long */ 3565 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { 3566 op1 = OPC1_16_SRRS_ADDSC_A; 3567 } 3568 3569 switch (op1) { 3570 case OPC1_16_SRC_ADD: 3571 case OPC1_16_SRC_ADD_A15: 3572 case OPC1_16_SRC_ADD_15A: 3573 case OPC1_16_SRC_ADD_A: 3574 case OPC1_16_SRC_CADD: 3575 case OPC1_16_SRC_CADDN: 3576 case OPC1_16_SRC_CMOV: 3577 case OPC1_16_SRC_CMOVN: 3578 case OPC1_16_SRC_EQ: 3579 case OPC1_16_SRC_LT: 3580 case OPC1_16_SRC_MOV: 3581 case OPC1_16_SRC_MOV_A: 3582 case OPC1_16_SRC_MOV_E: 3583 case OPC1_16_SRC_SH: 3584 case OPC1_16_SRC_SHA: 3585 decode_src_opc(ctx, op1); 3586 break; 3587 /* SRR-format */ 3588 case OPC1_16_SRR_ADD: 3589 case OPC1_16_SRR_ADD_A15: 3590 case OPC1_16_SRR_ADD_15A: 3591 case OPC1_16_SRR_ADD_A: 3592 case OPC1_16_SRR_ADDS: 3593 case OPC1_16_SRR_AND: 3594 case OPC1_16_SRR_CMOV: 3595 case OPC1_16_SRR_CMOVN: 3596 case OPC1_16_SRR_EQ: 3597 case OPC1_16_SRR_LT: 3598 case OPC1_16_SRR_MOV: 3599 case OPC1_16_SRR_MOV_A: 3600 case OPC1_16_SRR_MOV_AA: 3601 case OPC1_16_SRR_MOV_D: 3602 case OPC1_16_SRR_MUL: 3603 case OPC1_16_SRR_OR: 3604 case OPC1_16_SRR_SUB: 3605 case OPC1_16_SRR_SUB_A15B: 3606 case OPC1_16_SRR_SUB_15AB: 3607 case OPC1_16_SRR_SUBS: 3608 case OPC1_16_SRR_XOR: 3609 decode_srr_opc(ctx, op1); 3610 break; 3611 /* SSR-format */ 3612 case OPC1_16_SSR_ST_A: 3613 case OPC1_16_SSR_ST_A_POSTINC: 3614 case OPC1_16_SSR_ST_B: 3615 case OPC1_16_SSR_ST_B_POSTINC: 3616 case OPC1_16_SSR_ST_H: 3617 case OPC1_16_SSR_ST_H_POSTINC: 3618 case OPC1_16_SSR_ST_W: 3619 case OPC1_16_SSR_ST_W_POSTINC: 3620 decode_ssr_opc(ctx, op1); 3621 break; 3622 /* SRRS-format */ 3623 case OPC1_16_SRRS_ADDSC_A: 3624 r2 = MASK_OP_SRRS_S2(ctx->opcode); 3625 r1 = MASK_OP_SRRS_S1D(ctx->opcode); 3626 const16 = MASK_OP_SRRS_N(ctx->opcode); 3627 temp = tcg_temp_new(); 3628 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); 3629 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); 3630 break; 3631 /* SLRO-format */ 3632 case OPC1_16_SLRO_LD_A: 3633 r1 = MASK_OP_SLRO_D(ctx->opcode); 3634 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3635 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3636 break; 3637 case OPC1_16_SLRO_LD_BU: 3638 r1 = MASK_OP_SLRO_D(ctx->opcode); 3639 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3640 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3641 break; 3642 case OPC1_16_SLRO_LD_H: 3643 r1 = MASK_OP_SLRO_D(ctx->opcode); 3644 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3645 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3646 break; 3647 case OPC1_16_SLRO_LD_W: 3648 r1 = MASK_OP_SLRO_D(ctx->opcode); 3649 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 3650 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3651 break; 3652 /* SB-format */ 3653 case OPC1_16_SB_CALL: 3654 case OPC1_16_SB_J: 3655 case OPC1_16_SB_JNZ: 3656 case OPC1_16_SB_JZ: 3657 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); 3658 gen_compute_branch(ctx, op1, 0, 0, 0, address); 3659 break; 3660 /* SBC-format */ 3661 case OPC1_16_SBC_JEQ: 3662 case OPC1_16_SBC_JNE: 3663 address = MASK_OP_SBC_DISP4(ctx->opcode); 3664 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3665 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3666 break; 3667 case OPC1_16_SBC_JEQ2: 3668 case OPC1_16_SBC_JNE2: 3669 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3670 address = MASK_OP_SBC_DISP4(ctx->opcode); 3671 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 3672 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3673 } else { 3674 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3675 } 3676 break; 3677 /* SBRN-format */ 3678 case OPC1_16_SBRN_JNZ_T: 3679 case OPC1_16_SBRN_JZ_T: 3680 address = MASK_OP_SBRN_DISP4(ctx->opcode); 3681 const16 = MASK_OP_SBRN_N(ctx->opcode); 3682 gen_compute_branch(ctx, op1, 0, 0, const16, address); 3683 break; 3684 /* SBR-format */ 3685 case OPC1_16_SBR_JEQ2: 3686 case OPC1_16_SBR_JNE2: 3687 if (has_feature(ctx, TRICORE_FEATURE_16)) { 3688 r1 = MASK_OP_SBR_S2(ctx->opcode); 3689 address = MASK_OP_SBR_DISP4(ctx->opcode); 3690 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3691 } else { 3692 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3693 } 3694 break; 3695 case OPC1_16_SBR_JEQ: 3696 case OPC1_16_SBR_JGEZ: 3697 case OPC1_16_SBR_JGTZ: 3698 case OPC1_16_SBR_JLEZ: 3699 case OPC1_16_SBR_JLTZ: 3700 case OPC1_16_SBR_JNE: 3701 case OPC1_16_SBR_JNZ: 3702 case OPC1_16_SBR_JNZ_A: 3703 case OPC1_16_SBR_JZ: 3704 case OPC1_16_SBR_JZ_A: 3705 case OPC1_16_SBR_LOOP: 3706 r1 = MASK_OP_SBR_S2(ctx->opcode); 3707 address = MASK_OP_SBR_DISP4(ctx->opcode); 3708 gen_compute_branch(ctx, op1, r1, 0, 0, address); 3709 break; 3710 /* SC-format */ 3711 case OPC1_16_SC_AND: 3712 case OPC1_16_SC_BISR: 3713 case OPC1_16_SC_LD_A: 3714 case OPC1_16_SC_LD_W: 3715 case OPC1_16_SC_MOV: 3716 case OPC1_16_SC_OR: 3717 case OPC1_16_SC_ST_A: 3718 case OPC1_16_SC_ST_W: 3719 case OPC1_16_SC_SUB_A: 3720 decode_sc_opc(ctx, op1); 3721 break; 3722 /* SLR-format */ 3723 case OPC1_16_SLR_LD_A: 3724 case OPC1_16_SLR_LD_A_POSTINC: 3725 case OPC1_16_SLR_LD_BU: 3726 case OPC1_16_SLR_LD_BU_POSTINC: 3727 case OPC1_16_SLR_LD_H: 3728 case OPC1_16_SLR_LD_H_POSTINC: 3729 case OPC1_16_SLR_LD_W: 3730 case OPC1_16_SLR_LD_W_POSTINC: 3731 decode_slr_opc(ctx, op1); 3732 break; 3733 /* SRO-format */ 3734 case OPC1_16_SRO_LD_A: 3735 case OPC1_16_SRO_LD_BU: 3736 case OPC1_16_SRO_LD_H: 3737 case OPC1_16_SRO_LD_W: 3738 case OPC1_16_SRO_ST_A: 3739 case OPC1_16_SRO_ST_B: 3740 case OPC1_16_SRO_ST_H: 3741 case OPC1_16_SRO_ST_W: 3742 decode_sro_opc(ctx, op1); 3743 break; 3744 /* SSRO-format */ 3745 case OPC1_16_SSRO_ST_A: 3746 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3747 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3748 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3749 break; 3750 case OPC1_16_SSRO_ST_B: 3751 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3752 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3753 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 3754 break; 3755 case OPC1_16_SSRO_ST_H: 3756 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3757 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3758 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 3759 break; 3760 case OPC1_16_SSRO_ST_W: 3761 r1 = MASK_OP_SSRO_S1(ctx->opcode); 3762 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 3763 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 3764 break; 3765 /* SR-format */ 3766 case OPCM_16_SR_SYSTEM: 3767 decode_sr_system(ctx); 3768 break; 3769 case OPCM_16_SR_ACCU: 3770 decode_sr_accu(ctx); 3771 break; 3772 case OPC1_16_SR_JI: 3773 r1 = MASK_OP_SR_S1D(ctx->opcode); 3774 gen_compute_branch(ctx, op1, r1, 0, 0, 0); 3775 break; 3776 case OPC1_16_SR_NOT: 3777 r1 = MASK_OP_SR_S1D(ctx->opcode); 3778 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3779 break; 3780 default: 3781 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3782 } 3783 } 3784 3785 /* 3786 * 32 bit instructions 3787 */ 3788 3789 /* ABS-format */ 3790 static void decode_abs_ldw(DisasContext *ctx) 3791 { 3792 int32_t op2; 3793 int32_t r1; 3794 uint32_t address; 3795 TCGv temp; 3796 3797 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3798 address = MASK_OP_ABS_OFF18(ctx->opcode); 3799 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3800 3801 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3802 3803 switch (op2) { 3804 case OPC2_32_ABS_LD_A: 3805 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3806 break; 3807 case OPC2_32_ABS_LD_D: 3808 CHECK_REG_PAIR(r1); 3809 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3810 break; 3811 case OPC2_32_ABS_LD_DA: 3812 CHECK_REG_PAIR(r1); 3813 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3814 break; 3815 case OPC2_32_ABS_LD_W: 3816 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3817 break; 3818 default: 3819 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3820 } 3821 } 3822 3823 static void decode_abs_ldb(DisasContext *ctx) 3824 { 3825 int32_t op2; 3826 int32_t r1; 3827 uint32_t address; 3828 TCGv temp; 3829 3830 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3831 address = MASK_OP_ABS_OFF18(ctx->opcode); 3832 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3833 3834 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3835 3836 switch (op2) { 3837 case OPC2_32_ABS_LD_B: 3838 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); 3839 break; 3840 case OPC2_32_ABS_LD_BU: 3841 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3842 break; 3843 case OPC2_32_ABS_LD_H: 3844 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); 3845 break; 3846 case OPC2_32_ABS_LD_HU: 3847 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3848 break; 3849 default: 3850 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3851 } 3852 } 3853 3854 static void decode_abs_ldst_swap(DisasContext *ctx) 3855 { 3856 int32_t op2; 3857 int32_t r1; 3858 uint32_t address; 3859 TCGv temp; 3860 3861 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3862 address = MASK_OP_ABS_OFF18(ctx->opcode); 3863 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3864 3865 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3866 3867 switch (op2) { 3868 case OPC2_32_ABS_LDMST: 3869 gen_ldmst(ctx, r1, temp); 3870 break; 3871 case OPC2_32_ABS_SWAP_W: 3872 gen_swap(ctx, r1, temp); 3873 break; 3874 default: 3875 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3876 } 3877 } 3878 3879 static void decode_abs_ldst_context(DisasContext *ctx) 3880 { 3881 uint32_t op2; 3882 int32_t off18; 3883 3884 off18 = MASK_OP_ABS_OFF18(ctx->opcode); 3885 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3886 3887 switch (op2) { 3888 case OPC2_32_ABS_LDLCX: 3889 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); 3890 break; 3891 case OPC2_32_ABS_LDUCX: 3892 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); 3893 break; 3894 case OPC2_32_ABS_STLCX: 3895 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); 3896 break; 3897 case OPC2_32_ABS_STUCX: 3898 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); 3899 break; 3900 default: 3901 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3902 } 3903 } 3904 3905 static void decode_abs_store(DisasContext *ctx) 3906 { 3907 int32_t op2; 3908 int32_t r1; 3909 uint32_t address; 3910 TCGv temp; 3911 3912 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3913 address = MASK_OP_ABS_OFF18(ctx->opcode); 3914 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3915 3916 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3917 3918 switch (op2) { 3919 case OPC2_32_ABS_ST_A: 3920 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 3921 break; 3922 case OPC2_32_ABS_ST_D: 3923 CHECK_REG_PAIR(r1); 3924 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 3925 break; 3926 case OPC2_32_ABS_ST_DA: 3927 CHECK_REG_PAIR(r1); 3928 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 3929 break; 3930 case OPC2_32_ABS_ST_W: 3931 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 3932 break; 3933 default: 3934 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3935 } 3936 } 3937 3938 static void decode_abs_storeb_h(DisasContext *ctx) 3939 { 3940 int32_t op2; 3941 int32_t r1; 3942 uint32_t address; 3943 TCGv temp; 3944 3945 r1 = MASK_OP_ABS_S1D(ctx->opcode); 3946 address = MASK_OP_ABS_OFF18(ctx->opcode); 3947 op2 = MASK_OP_ABS_OP2(ctx->opcode); 3948 3949 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 3950 3951 switch (op2) { 3952 case OPC2_32_ABS_ST_B: 3953 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 3954 break; 3955 case OPC2_32_ABS_ST_H: 3956 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 3957 break; 3958 default: 3959 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3960 } 3961 } 3962 3963 /* Bit-format */ 3964 3965 static void decode_bit_andacc(DisasContext *ctx) 3966 { 3967 uint32_t op2; 3968 int r1, r2, r3; 3969 int pos1, pos2; 3970 3971 r1 = MASK_OP_BIT_S1(ctx->opcode); 3972 r2 = MASK_OP_BIT_S2(ctx->opcode); 3973 r3 = MASK_OP_BIT_D(ctx->opcode); 3974 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 3975 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 3976 op2 = MASK_OP_BIT_OP2(ctx->opcode); 3977 3978 3979 switch (op2) { 3980 case OPC2_32_BIT_AND_AND_T: 3981 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3982 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); 3983 break; 3984 case OPC2_32_BIT_AND_ANDN_T: 3985 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3986 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); 3987 break; 3988 case OPC2_32_BIT_AND_NOR_T: 3989 if (TCG_TARGET_HAS_andc_i32) { 3990 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3991 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); 3992 } else { 3993 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3994 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); 3995 } 3996 break; 3997 case OPC2_32_BIT_AND_OR_T: 3998 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 3999 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); 4000 break; 4001 default: 4002 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4003 } 4004 } 4005 4006 static void decode_bit_logical_t(DisasContext *ctx) 4007 { 4008 uint32_t op2; 4009 int r1, r2, r3; 4010 int pos1, pos2; 4011 r1 = MASK_OP_BIT_S1(ctx->opcode); 4012 r2 = MASK_OP_BIT_S2(ctx->opcode); 4013 r3 = MASK_OP_BIT_D(ctx->opcode); 4014 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4015 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4016 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4017 4018 switch (op2) { 4019 case OPC2_32_BIT_AND_T: 4020 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4021 pos1, pos2, &tcg_gen_and_tl); 4022 break; 4023 case OPC2_32_BIT_ANDN_T: 4024 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4025 pos1, pos2, &tcg_gen_andc_tl); 4026 break; 4027 case OPC2_32_BIT_NOR_T: 4028 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4029 pos1, pos2, &tcg_gen_nor_tl); 4030 break; 4031 case OPC2_32_BIT_OR_T: 4032 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4033 pos1, pos2, &tcg_gen_or_tl); 4034 break; 4035 default: 4036 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4037 } 4038 } 4039 4040 static void decode_bit_insert(DisasContext *ctx) 4041 { 4042 uint32_t op2; 4043 int r1, r2, r3; 4044 int pos1, pos2; 4045 TCGv temp; 4046 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4047 r1 = MASK_OP_BIT_S1(ctx->opcode); 4048 r2 = MASK_OP_BIT_S2(ctx->opcode); 4049 r3 = MASK_OP_BIT_D(ctx->opcode); 4050 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4051 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4052 4053 temp = tcg_temp_new(); 4054 4055 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); 4056 if (op2 == OPC2_32_BIT_INSN_T) { 4057 tcg_gen_not_tl(temp, temp); 4058 } 4059 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); 4060 } 4061 4062 static void decode_bit_logical_t2(DisasContext *ctx) 4063 { 4064 uint32_t op2; 4065 4066 int r1, r2, r3; 4067 int pos1, pos2; 4068 4069 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4070 r1 = MASK_OP_BIT_S1(ctx->opcode); 4071 r2 = MASK_OP_BIT_S2(ctx->opcode); 4072 r3 = MASK_OP_BIT_D(ctx->opcode); 4073 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4074 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4075 4076 switch (op2) { 4077 case OPC2_32_BIT_NAND_T: 4078 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4079 pos1, pos2, &tcg_gen_nand_tl); 4080 break; 4081 case OPC2_32_BIT_ORN_T: 4082 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4083 pos1, pos2, &tcg_gen_orc_tl); 4084 break; 4085 case OPC2_32_BIT_XNOR_T: 4086 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4087 pos1, pos2, &tcg_gen_eqv_tl); 4088 break; 4089 case OPC2_32_BIT_XOR_T: 4090 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4091 pos1, pos2, &tcg_gen_xor_tl); 4092 break; 4093 default: 4094 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4095 } 4096 } 4097 4098 static void decode_bit_orand(DisasContext *ctx) 4099 { 4100 uint32_t op2; 4101 4102 int r1, r2, r3; 4103 int pos1, pos2; 4104 4105 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4106 r1 = MASK_OP_BIT_S1(ctx->opcode); 4107 r2 = MASK_OP_BIT_S2(ctx->opcode); 4108 r3 = MASK_OP_BIT_D(ctx->opcode); 4109 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4110 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4111 4112 switch (op2) { 4113 case OPC2_32_BIT_OR_AND_T: 4114 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4115 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); 4116 break; 4117 case OPC2_32_BIT_OR_ANDN_T: 4118 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4119 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); 4120 break; 4121 case OPC2_32_BIT_OR_NOR_T: 4122 if (TCG_TARGET_HAS_orc_i32) { 4123 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4124 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); 4125 } else { 4126 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4127 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); 4128 } 4129 break; 4130 case OPC2_32_BIT_OR_OR_T: 4131 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4132 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); 4133 break; 4134 default: 4135 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4136 } 4137 } 4138 4139 static void decode_bit_sh_logic1(DisasContext *ctx) 4140 { 4141 uint32_t op2; 4142 int r1, r2, r3; 4143 int pos1, pos2; 4144 TCGv temp; 4145 4146 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4147 r1 = MASK_OP_BIT_S1(ctx->opcode); 4148 r2 = MASK_OP_BIT_S2(ctx->opcode); 4149 r3 = MASK_OP_BIT_D(ctx->opcode); 4150 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4151 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4152 4153 temp = tcg_temp_new(); 4154 4155 switch (op2) { 4156 case OPC2_32_BIT_SH_AND_T: 4157 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4158 pos1, pos2, &tcg_gen_and_tl); 4159 break; 4160 case OPC2_32_BIT_SH_ANDN_T: 4161 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4162 pos1, pos2, &tcg_gen_andc_tl); 4163 break; 4164 case OPC2_32_BIT_SH_NOR_T: 4165 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4166 pos1, pos2, &tcg_gen_nor_tl); 4167 break; 4168 case OPC2_32_BIT_SH_OR_T: 4169 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4170 pos1, pos2, &tcg_gen_or_tl); 4171 break; 4172 default: 4173 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4174 } 4175 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4176 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4177 } 4178 4179 static void decode_bit_sh_logic2(DisasContext *ctx) 4180 { 4181 uint32_t op2; 4182 int r1, r2, r3; 4183 int pos1, pos2; 4184 TCGv temp; 4185 4186 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4187 r1 = MASK_OP_BIT_S1(ctx->opcode); 4188 r2 = MASK_OP_BIT_S2(ctx->opcode); 4189 r3 = MASK_OP_BIT_D(ctx->opcode); 4190 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4191 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4192 4193 temp = tcg_temp_new(); 4194 4195 switch (op2) { 4196 case OPC2_32_BIT_SH_NAND_T: 4197 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , 4198 pos1, pos2, &tcg_gen_nand_tl); 4199 break; 4200 case OPC2_32_BIT_SH_ORN_T: 4201 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4202 pos1, pos2, &tcg_gen_orc_tl); 4203 break; 4204 case OPC2_32_BIT_SH_XNOR_T: 4205 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4206 pos1, pos2, &tcg_gen_eqv_tl); 4207 break; 4208 case OPC2_32_BIT_SH_XOR_T: 4209 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4210 pos1, pos2, &tcg_gen_xor_tl); 4211 break; 4212 default: 4213 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4214 } 4215 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4216 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4217 } 4218 4219 /* BO-format */ 4220 4221 4222 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) 4223 { 4224 uint32_t op2; 4225 uint32_t off10; 4226 int32_t r1, r2; 4227 TCGv temp; 4228 4229 r1 = MASK_OP_BO_S1D(ctx->opcode); 4230 r2 = MASK_OP_BO_S2(ctx->opcode); 4231 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4232 op2 = MASK_OP_BO_OP2(ctx->opcode); 4233 4234 switch (op2) { 4235 case OPC2_32_BO_CACHEA_WI_SHORTOFF: 4236 case OPC2_32_BO_CACHEA_W_SHORTOFF: 4237 case OPC2_32_BO_CACHEA_I_SHORTOFF: 4238 /* instruction to access the cache */ 4239 break; 4240 case OPC2_32_BO_CACHEA_WI_POSTINC: 4241 case OPC2_32_BO_CACHEA_W_POSTINC: 4242 case OPC2_32_BO_CACHEA_I_POSTINC: 4243 /* instruction to access the cache, but we still need to handle 4244 the addressing mode */ 4245 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4246 break; 4247 case OPC2_32_BO_CACHEA_WI_PREINC: 4248 case OPC2_32_BO_CACHEA_W_PREINC: 4249 case OPC2_32_BO_CACHEA_I_PREINC: 4250 /* instruction to access the cache, but we still need to handle 4251 the addressing mode */ 4252 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4253 break; 4254 case OPC2_32_BO_CACHEI_WI_SHORTOFF: 4255 case OPC2_32_BO_CACHEI_W_SHORTOFF: 4256 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 4257 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4258 } 4259 break; 4260 case OPC2_32_BO_CACHEI_W_POSTINC: 4261 case OPC2_32_BO_CACHEI_WI_POSTINC: 4262 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4263 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4264 } else { 4265 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4266 } 4267 break; 4268 case OPC2_32_BO_CACHEI_W_PREINC: 4269 case OPC2_32_BO_CACHEI_WI_PREINC: 4270 if (has_feature(ctx, TRICORE_FEATURE_131)) { 4271 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4272 } else { 4273 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4274 } 4275 break; 4276 case OPC2_32_BO_ST_A_SHORTOFF: 4277 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4278 break; 4279 case OPC2_32_BO_ST_A_POSTINC: 4280 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4281 MO_LESL); 4282 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4283 break; 4284 case OPC2_32_BO_ST_A_PREINC: 4285 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4286 break; 4287 case OPC2_32_BO_ST_B_SHORTOFF: 4288 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4289 break; 4290 case OPC2_32_BO_ST_B_POSTINC: 4291 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4292 MO_UB); 4293 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4294 break; 4295 case OPC2_32_BO_ST_B_PREINC: 4296 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4297 break; 4298 case OPC2_32_BO_ST_D_SHORTOFF: 4299 CHECK_REG_PAIR(r1); 4300 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4301 off10, ctx); 4302 break; 4303 case OPC2_32_BO_ST_D_POSTINC: 4304 CHECK_REG_PAIR(r1); 4305 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4306 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4307 break; 4308 case OPC2_32_BO_ST_D_PREINC: 4309 CHECK_REG_PAIR(r1); 4310 temp = tcg_temp_new(); 4311 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4312 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4313 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4314 break; 4315 case OPC2_32_BO_ST_DA_SHORTOFF: 4316 CHECK_REG_PAIR(r1); 4317 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4318 off10, ctx); 4319 break; 4320 case OPC2_32_BO_ST_DA_POSTINC: 4321 CHECK_REG_PAIR(r1); 4322 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4323 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4324 break; 4325 case OPC2_32_BO_ST_DA_PREINC: 4326 CHECK_REG_PAIR(r1); 4327 temp = tcg_temp_new(); 4328 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4329 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4330 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4331 break; 4332 case OPC2_32_BO_ST_H_SHORTOFF: 4333 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4334 break; 4335 case OPC2_32_BO_ST_H_POSTINC: 4336 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4337 MO_LEUW); 4338 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4339 break; 4340 case OPC2_32_BO_ST_H_PREINC: 4341 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4342 break; 4343 case OPC2_32_BO_ST_Q_SHORTOFF: 4344 temp = tcg_temp_new(); 4345 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4346 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4347 break; 4348 case OPC2_32_BO_ST_Q_POSTINC: 4349 temp = tcg_temp_new(); 4350 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4351 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, 4352 MO_LEUW); 4353 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4354 break; 4355 case OPC2_32_BO_ST_Q_PREINC: 4356 temp = tcg_temp_new(); 4357 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4358 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4359 break; 4360 case OPC2_32_BO_ST_W_SHORTOFF: 4361 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4362 break; 4363 case OPC2_32_BO_ST_W_POSTINC: 4364 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4365 MO_LEUL); 4366 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4367 break; 4368 case OPC2_32_BO_ST_W_PREINC: 4369 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4370 break; 4371 default: 4372 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4373 } 4374 } 4375 4376 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) 4377 { 4378 uint32_t op2; 4379 uint32_t off10; 4380 int32_t r1, r2; 4381 TCGv temp, temp2, t_off10; 4382 4383 r1 = MASK_OP_BO_S1D(ctx->opcode); 4384 r2 = MASK_OP_BO_S2(ctx->opcode); 4385 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4386 op2 = MASK_OP_BO_OP2(ctx->opcode); 4387 4388 temp = tcg_temp_new(); 4389 temp2 = tcg_temp_new(); 4390 t_off10 = tcg_constant_i32(off10); 4391 CHECK_REG_PAIR(r2); 4392 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4393 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4394 4395 switch (op2) { 4396 case OPC2_32_BO_CACHEA_WI_BR: 4397 case OPC2_32_BO_CACHEA_W_BR: 4398 case OPC2_32_BO_CACHEA_I_BR: 4399 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4400 break; 4401 case OPC2_32_BO_CACHEA_WI_CIRC: 4402 case OPC2_32_BO_CACHEA_W_CIRC: 4403 case OPC2_32_BO_CACHEA_I_CIRC: 4404 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4405 break; 4406 case OPC2_32_BO_ST_A_BR: 4407 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4408 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4409 break; 4410 case OPC2_32_BO_ST_A_CIRC: 4411 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4412 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4413 break; 4414 case OPC2_32_BO_ST_B_BR: 4415 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4416 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4417 break; 4418 case OPC2_32_BO_ST_B_CIRC: 4419 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4420 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4421 break; 4422 case OPC2_32_BO_ST_D_BR: 4423 CHECK_REG_PAIR(r1); 4424 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4425 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4426 break; 4427 case OPC2_32_BO_ST_D_CIRC: 4428 CHECK_REG_PAIR(r1); 4429 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4430 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4431 tcg_gen_addi_tl(temp, temp, 4); 4432 tcg_gen_rem_tl(temp, temp, temp2); 4433 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4434 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4435 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4436 break; 4437 case OPC2_32_BO_ST_DA_BR: 4438 CHECK_REG_PAIR(r1); 4439 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4440 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4441 break; 4442 case OPC2_32_BO_ST_DA_CIRC: 4443 CHECK_REG_PAIR(r1); 4444 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4445 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4446 tcg_gen_addi_tl(temp, temp, 4); 4447 tcg_gen_rem_tl(temp, temp, temp2); 4448 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4449 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4450 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4451 break; 4452 case OPC2_32_BO_ST_H_BR: 4453 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4454 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4455 break; 4456 case OPC2_32_BO_ST_H_CIRC: 4457 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4458 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4459 break; 4460 case OPC2_32_BO_ST_Q_BR: 4461 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4462 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4463 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4464 break; 4465 case OPC2_32_BO_ST_Q_CIRC: 4466 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4467 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4468 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4469 break; 4470 case OPC2_32_BO_ST_W_BR: 4471 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4472 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4473 break; 4474 case OPC2_32_BO_ST_W_CIRC: 4475 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4476 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4477 break; 4478 default: 4479 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4480 } 4481 } 4482 4483 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) 4484 { 4485 uint32_t op2; 4486 uint32_t off10; 4487 int32_t r1, r2; 4488 TCGv temp; 4489 4490 r1 = MASK_OP_BO_S1D(ctx->opcode); 4491 r2 = MASK_OP_BO_S2(ctx->opcode); 4492 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4493 op2 = MASK_OP_BO_OP2(ctx->opcode); 4494 4495 switch (op2) { 4496 case OPC2_32_BO_LD_A_SHORTOFF: 4497 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4498 break; 4499 case OPC2_32_BO_LD_A_POSTINC: 4500 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4501 MO_LEUL); 4502 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4503 break; 4504 case OPC2_32_BO_LD_A_PREINC: 4505 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4506 break; 4507 case OPC2_32_BO_LD_B_SHORTOFF: 4508 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4509 break; 4510 case OPC2_32_BO_LD_B_POSTINC: 4511 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4512 MO_SB); 4513 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4514 break; 4515 case OPC2_32_BO_LD_B_PREINC: 4516 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4517 break; 4518 case OPC2_32_BO_LD_BU_SHORTOFF: 4519 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4520 break; 4521 case OPC2_32_BO_LD_BU_POSTINC: 4522 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4523 MO_UB); 4524 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4525 break; 4526 case OPC2_32_BO_LD_BU_PREINC: 4527 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4528 break; 4529 case OPC2_32_BO_LD_D_SHORTOFF: 4530 CHECK_REG_PAIR(r1); 4531 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4532 off10, ctx); 4533 break; 4534 case OPC2_32_BO_LD_D_POSTINC: 4535 CHECK_REG_PAIR(r1); 4536 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4537 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4538 break; 4539 case OPC2_32_BO_LD_D_PREINC: 4540 CHECK_REG_PAIR(r1); 4541 temp = tcg_temp_new(); 4542 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4543 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4544 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4545 break; 4546 case OPC2_32_BO_LD_DA_SHORTOFF: 4547 CHECK_REG_PAIR(r1); 4548 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4549 off10, ctx); 4550 break; 4551 case OPC2_32_BO_LD_DA_POSTINC: 4552 CHECK_REG_PAIR(r1); 4553 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4554 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4555 break; 4556 case OPC2_32_BO_LD_DA_PREINC: 4557 CHECK_REG_PAIR(r1); 4558 temp = tcg_temp_new(); 4559 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4560 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4561 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4562 break; 4563 case OPC2_32_BO_LD_H_SHORTOFF: 4564 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4565 break; 4566 case OPC2_32_BO_LD_H_POSTINC: 4567 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4568 MO_LESW); 4569 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4570 break; 4571 case OPC2_32_BO_LD_H_PREINC: 4572 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 4573 break; 4574 case OPC2_32_BO_LD_HU_SHORTOFF: 4575 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4576 break; 4577 case OPC2_32_BO_LD_HU_POSTINC: 4578 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4579 MO_LEUW); 4580 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4581 break; 4582 case OPC2_32_BO_LD_HU_PREINC: 4583 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4584 break; 4585 case OPC2_32_BO_LD_Q_SHORTOFF: 4586 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4587 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4588 break; 4589 case OPC2_32_BO_LD_Q_POSTINC: 4590 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4591 MO_LEUW); 4592 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4593 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4594 break; 4595 case OPC2_32_BO_LD_Q_PREINC: 4596 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4597 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4598 break; 4599 case OPC2_32_BO_LD_W_SHORTOFF: 4600 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4601 break; 4602 case OPC2_32_BO_LD_W_POSTINC: 4603 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4604 MO_LEUL); 4605 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4606 break; 4607 case OPC2_32_BO_LD_W_PREINC: 4608 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4609 break; 4610 default: 4611 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4612 } 4613 } 4614 4615 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) 4616 { 4617 uint32_t op2; 4618 uint32_t off10; 4619 int r1, r2; 4620 TCGv temp, temp2, t_off10; 4621 4622 r1 = MASK_OP_BO_S1D(ctx->opcode); 4623 r2 = MASK_OP_BO_S2(ctx->opcode); 4624 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4625 op2 = MASK_OP_BO_OP2(ctx->opcode); 4626 4627 temp = tcg_temp_new(); 4628 temp2 = tcg_temp_new(); 4629 t_off10 = tcg_constant_i32(off10); 4630 CHECK_REG_PAIR(r2); 4631 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4632 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4633 4634 4635 switch (op2) { 4636 case OPC2_32_BO_LD_A_BR: 4637 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4638 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4639 break; 4640 case OPC2_32_BO_LD_A_CIRC: 4641 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4642 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4643 break; 4644 case OPC2_32_BO_LD_B_BR: 4645 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4646 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4647 break; 4648 case OPC2_32_BO_LD_B_CIRC: 4649 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 4650 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4651 break; 4652 case OPC2_32_BO_LD_BU_BR: 4653 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4654 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4655 break; 4656 case OPC2_32_BO_LD_BU_CIRC: 4657 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4658 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4659 break; 4660 case OPC2_32_BO_LD_D_BR: 4661 CHECK_REG_PAIR(r1); 4662 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4663 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4664 break; 4665 case OPC2_32_BO_LD_D_CIRC: 4666 CHECK_REG_PAIR(r1); 4667 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4668 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4669 tcg_gen_addi_tl(temp, temp, 4); 4670 tcg_gen_rem_tl(temp, temp, temp2); 4671 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4672 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4673 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4674 break; 4675 case OPC2_32_BO_LD_DA_BR: 4676 CHECK_REG_PAIR(r1); 4677 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4678 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4679 break; 4680 case OPC2_32_BO_LD_DA_CIRC: 4681 CHECK_REG_PAIR(r1); 4682 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4683 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4684 tcg_gen_addi_tl(temp, temp, 4); 4685 tcg_gen_rem_tl(temp, temp, temp2); 4686 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4687 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4688 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4689 break; 4690 case OPC2_32_BO_LD_H_BR: 4691 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4692 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4693 break; 4694 case OPC2_32_BO_LD_H_CIRC: 4695 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 4696 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4697 break; 4698 case OPC2_32_BO_LD_HU_BR: 4699 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4700 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4701 break; 4702 case OPC2_32_BO_LD_HU_CIRC: 4703 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4704 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4705 break; 4706 case OPC2_32_BO_LD_Q_BR: 4707 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4708 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4709 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4710 break; 4711 case OPC2_32_BO_LD_Q_CIRC: 4712 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4713 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 4714 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4715 break; 4716 case OPC2_32_BO_LD_W_BR: 4717 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4718 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4719 break; 4720 case OPC2_32_BO_LD_W_CIRC: 4721 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4722 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4723 break; 4724 default: 4725 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4726 } 4727 } 4728 4729 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) 4730 { 4731 uint32_t op2; 4732 uint32_t off10; 4733 int r1, r2; 4734 4735 TCGv temp; 4736 4737 r1 = MASK_OP_BO_S1D(ctx->opcode); 4738 r2 = MASK_OP_BO_S2(ctx->opcode); 4739 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4740 op2 = MASK_OP_BO_OP2(ctx->opcode); 4741 4742 4743 temp = tcg_temp_new(); 4744 4745 switch (op2) { 4746 case OPC2_32_BO_LDLCX_SHORTOFF: 4747 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4748 gen_helper_ldlcx(cpu_env, temp); 4749 break; 4750 case OPC2_32_BO_LDMST_SHORTOFF: 4751 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4752 gen_ldmst(ctx, r1, temp); 4753 break; 4754 case OPC2_32_BO_LDMST_POSTINC: 4755 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4756 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4757 break; 4758 case OPC2_32_BO_LDMST_PREINC: 4759 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4760 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 4761 break; 4762 case OPC2_32_BO_LDUCX_SHORTOFF: 4763 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4764 gen_helper_lducx(cpu_env, temp); 4765 break; 4766 case OPC2_32_BO_LEA_SHORTOFF: 4767 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); 4768 break; 4769 case OPC2_32_BO_STLCX_SHORTOFF: 4770 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4771 gen_helper_stlcx(cpu_env, temp); 4772 break; 4773 case OPC2_32_BO_STUCX_SHORTOFF: 4774 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4775 gen_helper_stucx(cpu_env, temp); 4776 break; 4777 case OPC2_32_BO_SWAP_W_SHORTOFF: 4778 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4779 gen_swap(ctx, r1, temp); 4780 break; 4781 case OPC2_32_BO_SWAP_W_POSTINC: 4782 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4783 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4784 break; 4785 case OPC2_32_BO_SWAP_W_PREINC: 4786 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4787 gen_swap(ctx, r1, cpu_gpr_a[r2]); 4788 break; 4789 case OPC2_32_BO_CMPSWAP_W_SHORTOFF: 4790 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4791 gen_cmpswap(ctx, r1, temp); 4792 break; 4793 case OPC2_32_BO_CMPSWAP_W_POSTINC: 4794 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4795 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4796 break; 4797 case OPC2_32_BO_CMPSWAP_W_PREINC: 4798 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4799 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 4800 break; 4801 case OPC2_32_BO_SWAPMSK_W_SHORTOFF: 4802 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4803 gen_swapmsk(ctx, r1, temp); 4804 break; 4805 case OPC2_32_BO_SWAPMSK_W_POSTINC: 4806 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4807 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4808 break; 4809 case OPC2_32_BO_SWAPMSK_W_PREINC: 4810 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4811 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 4812 break; 4813 default: 4814 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4815 } 4816 } 4817 4818 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) 4819 { 4820 uint32_t op2; 4821 uint32_t off10; 4822 int r1, r2; 4823 TCGv temp, temp2, t_off10; 4824 4825 r1 = MASK_OP_BO_S1D(ctx->opcode); 4826 r2 = MASK_OP_BO_S2(ctx->opcode); 4827 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4828 op2 = MASK_OP_BO_OP2(ctx->opcode); 4829 4830 temp = tcg_temp_new(); 4831 temp2 = tcg_temp_new(); 4832 t_off10 = tcg_constant_i32(off10); 4833 CHECK_REG_PAIR(r2); 4834 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4835 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4836 4837 switch (op2) { 4838 case OPC2_32_BO_LDMST_BR: 4839 gen_ldmst(ctx, r1, temp2); 4840 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4841 break; 4842 case OPC2_32_BO_LDMST_CIRC: 4843 gen_ldmst(ctx, r1, temp2); 4844 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4845 break; 4846 case OPC2_32_BO_SWAP_W_BR: 4847 gen_swap(ctx, r1, temp2); 4848 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4849 break; 4850 case OPC2_32_BO_SWAP_W_CIRC: 4851 gen_swap(ctx, r1, temp2); 4852 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4853 break; 4854 case OPC2_32_BO_CMPSWAP_W_BR: 4855 gen_cmpswap(ctx, r1, temp2); 4856 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4857 break; 4858 case OPC2_32_BO_CMPSWAP_W_CIRC: 4859 gen_cmpswap(ctx, r1, temp2); 4860 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4861 break; 4862 case OPC2_32_BO_SWAPMSK_W_BR: 4863 gen_swapmsk(ctx, r1, temp2); 4864 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4865 break; 4866 case OPC2_32_BO_SWAPMSK_W_CIRC: 4867 gen_swapmsk(ctx, r1, temp2); 4868 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); 4869 break; 4870 default: 4871 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4872 } 4873 } 4874 4875 static void decode_bol_opc(DisasContext *ctx, int32_t op1) 4876 { 4877 int r1, r2; 4878 int32_t address; 4879 TCGv temp; 4880 4881 r1 = MASK_OP_BOL_S1D(ctx->opcode); 4882 r2 = MASK_OP_BOL_S2(ctx->opcode); 4883 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); 4884 4885 switch (op1) { 4886 case OPC1_32_BOL_LD_A_LONGOFF: 4887 temp = tcg_temp_new(); 4888 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4889 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); 4890 break; 4891 case OPC1_32_BOL_LD_W_LONGOFF: 4892 temp = tcg_temp_new(); 4893 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 4894 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); 4895 break; 4896 case OPC1_32_BOL_LEA_LONGOFF: 4897 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); 4898 break; 4899 case OPC1_32_BOL_ST_A_LONGOFF: 4900 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4901 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); 4902 } else { 4903 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4904 } 4905 break; 4906 case OPC1_32_BOL_ST_W_LONGOFF: 4907 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); 4908 break; 4909 case OPC1_32_BOL_LD_B_LONGOFF: 4910 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4911 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4912 } else { 4913 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4914 } 4915 break; 4916 case OPC1_32_BOL_LD_BU_LONGOFF: 4917 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4918 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); 4919 } else { 4920 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4921 } 4922 break; 4923 case OPC1_32_BOL_LD_H_LONGOFF: 4924 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4925 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4926 } else { 4927 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4928 } 4929 break; 4930 case OPC1_32_BOL_LD_HU_LONGOFF: 4931 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4932 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); 4933 } else { 4934 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4935 } 4936 break; 4937 case OPC1_32_BOL_ST_B_LONGOFF: 4938 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4939 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 4940 } else { 4941 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4942 } 4943 break; 4944 case OPC1_32_BOL_ST_H_LONGOFF: 4945 if (has_feature(ctx, TRICORE_FEATURE_16)) { 4946 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 4947 } else { 4948 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4949 } 4950 break; 4951 default: 4952 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4953 } 4954 } 4955 4956 /* RC format */ 4957 static void decode_rc_logical_shift(DisasContext *ctx) 4958 { 4959 uint32_t op2; 4960 int r1, r2; 4961 int32_t const9; 4962 TCGv temp; 4963 4964 r2 = MASK_OP_RC_D(ctx->opcode); 4965 r1 = MASK_OP_RC_S1(ctx->opcode); 4966 const9 = MASK_OP_RC_CONST9(ctx->opcode); 4967 op2 = MASK_OP_RC_OP2(ctx->opcode); 4968 4969 temp = tcg_temp_new(); 4970 4971 switch (op2) { 4972 case OPC2_32_RC_AND: 4973 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4974 break; 4975 case OPC2_32_RC_ANDN: 4976 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4977 break; 4978 case OPC2_32_RC_NAND: 4979 tcg_gen_movi_tl(temp, const9); 4980 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4981 break; 4982 case OPC2_32_RC_NOR: 4983 tcg_gen_movi_tl(temp, const9); 4984 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 4985 break; 4986 case OPC2_32_RC_OR: 4987 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4988 break; 4989 case OPC2_32_RC_ORN: 4990 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 4991 break; 4992 case OPC2_32_RC_SH: 4993 const9 = sextract32(const9, 0, 6); 4994 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4995 break; 4996 case OPC2_32_RC_SH_H: 4997 const9 = sextract32(const9, 0, 5); 4998 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 4999 break; 5000 case OPC2_32_RC_SHA: 5001 const9 = sextract32(const9, 0, 6); 5002 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5003 break; 5004 case OPC2_32_RC_SHA_H: 5005 const9 = sextract32(const9, 0, 5); 5006 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5007 break; 5008 case OPC2_32_RC_SHAS: 5009 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5010 break; 5011 case OPC2_32_RC_XNOR: 5012 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5013 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); 5014 break; 5015 case OPC2_32_RC_XOR: 5016 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5017 break; 5018 default: 5019 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5020 } 5021 } 5022 5023 static void decode_rc_accumulator(DisasContext *ctx) 5024 { 5025 uint32_t op2; 5026 int r1, r2; 5027 int16_t const9; 5028 5029 TCGv temp; 5030 5031 r2 = MASK_OP_RC_D(ctx->opcode); 5032 r1 = MASK_OP_RC_S1(ctx->opcode); 5033 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5034 5035 op2 = MASK_OP_RC_OP2(ctx->opcode); 5036 5037 temp = tcg_temp_new(); 5038 5039 switch (op2) { 5040 case OPC2_32_RC_ABSDIF: 5041 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5042 break; 5043 case OPC2_32_RC_ABSDIFS: 5044 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5045 break; 5046 case OPC2_32_RC_ADD: 5047 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5048 break; 5049 case OPC2_32_RC_ADDC: 5050 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5051 break; 5052 case OPC2_32_RC_ADDS: 5053 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5054 break; 5055 case OPC2_32_RC_ADDS_U: 5056 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5057 break; 5058 case OPC2_32_RC_ADDX: 5059 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5060 break; 5061 case OPC2_32_RC_AND_EQ: 5062 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5063 const9, &tcg_gen_and_tl); 5064 break; 5065 case OPC2_32_RC_AND_GE: 5066 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5067 const9, &tcg_gen_and_tl); 5068 break; 5069 case OPC2_32_RC_AND_GE_U: 5070 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5071 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5072 const9, &tcg_gen_and_tl); 5073 break; 5074 case OPC2_32_RC_AND_LT: 5075 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5076 const9, &tcg_gen_and_tl); 5077 break; 5078 case OPC2_32_RC_AND_LT_U: 5079 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5080 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5081 const9, &tcg_gen_and_tl); 5082 break; 5083 case OPC2_32_RC_AND_NE: 5084 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5085 const9, &tcg_gen_and_tl); 5086 break; 5087 case OPC2_32_RC_EQ: 5088 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5089 break; 5090 case OPC2_32_RC_EQANY_B: 5091 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5092 break; 5093 case OPC2_32_RC_EQANY_H: 5094 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5095 break; 5096 case OPC2_32_RC_GE: 5097 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5098 break; 5099 case OPC2_32_RC_GE_U: 5100 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5101 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5102 break; 5103 case OPC2_32_RC_LT: 5104 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5105 break; 5106 case OPC2_32_RC_LT_U: 5107 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5108 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5109 break; 5110 case OPC2_32_RC_MAX: 5111 tcg_gen_movi_tl(temp, const9); 5112 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5113 cpu_gpr_d[r1], temp); 5114 break; 5115 case OPC2_32_RC_MAX_U: 5116 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5117 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5118 cpu_gpr_d[r1], temp); 5119 break; 5120 case OPC2_32_RC_MIN: 5121 tcg_gen_movi_tl(temp, const9); 5122 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5123 cpu_gpr_d[r1], temp); 5124 break; 5125 case OPC2_32_RC_MIN_U: 5126 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5127 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5128 cpu_gpr_d[r1], temp); 5129 break; 5130 case OPC2_32_RC_NE: 5131 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5132 break; 5133 case OPC2_32_RC_OR_EQ: 5134 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5135 const9, &tcg_gen_or_tl); 5136 break; 5137 case OPC2_32_RC_OR_GE: 5138 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5139 const9, &tcg_gen_or_tl); 5140 break; 5141 case OPC2_32_RC_OR_GE_U: 5142 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5143 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5144 const9, &tcg_gen_or_tl); 5145 break; 5146 case OPC2_32_RC_OR_LT: 5147 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5148 const9, &tcg_gen_or_tl); 5149 break; 5150 case OPC2_32_RC_OR_LT_U: 5151 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5152 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5153 const9, &tcg_gen_or_tl); 5154 break; 5155 case OPC2_32_RC_OR_NE: 5156 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5157 const9, &tcg_gen_or_tl); 5158 break; 5159 case OPC2_32_RC_RSUB: 5160 tcg_gen_movi_tl(temp, const9); 5161 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5162 break; 5163 case OPC2_32_RC_RSUBS: 5164 tcg_gen_movi_tl(temp, const9); 5165 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5166 break; 5167 case OPC2_32_RC_RSUBS_U: 5168 tcg_gen_movi_tl(temp, const9); 5169 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5170 break; 5171 case OPC2_32_RC_SH_EQ: 5172 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5173 break; 5174 case OPC2_32_RC_SH_GE: 5175 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5176 break; 5177 case OPC2_32_RC_SH_GE_U: 5178 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5179 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5180 break; 5181 case OPC2_32_RC_SH_LT: 5182 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5183 break; 5184 case OPC2_32_RC_SH_LT_U: 5185 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5186 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5187 break; 5188 case OPC2_32_RC_SH_NE: 5189 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5190 break; 5191 case OPC2_32_RC_XOR_EQ: 5192 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5193 const9, &tcg_gen_xor_tl); 5194 break; 5195 case OPC2_32_RC_XOR_GE: 5196 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5197 const9, &tcg_gen_xor_tl); 5198 break; 5199 case OPC2_32_RC_XOR_GE_U: 5200 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5201 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5202 const9, &tcg_gen_xor_tl); 5203 break; 5204 case OPC2_32_RC_XOR_LT: 5205 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5206 const9, &tcg_gen_xor_tl); 5207 break; 5208 case OPC2_32_RC_XOR_LT_U: 5209 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5210 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5211 const9, &tcg_gen_xor_tl); 5212 break; 5213 case OPC2_32_RC_XOR_NE: 5214 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5215 const9, &tcg_gen_xor_tl); 5216 break; 5217 default: 5218 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5219 } 5220 } 5221 5222 static void decode_rc_serviceroutine(DisasContext *ctx) 5223 { 5224 uint32_t op2; 5225 uint32_t const9; 5226 5227 op2 = MASK_OP_RC_OP2(ctx->opcode); 5228 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5229 5230 switch (op2) { 5231 case OPC2_32_RC_BISR: 5232 gen_helper_1arg(bisr, const9); 5233 break; 5234 case OPC2_32_RC_SYSCALL: 5235 /* TODO: Add exception generation */ 5236 break; 5237 default: 5238 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5239 } 5240 } 5241 5242 static void decode_rc_mul(DisasContext *ctx) 5243 { 5244 uint32_t op2; 5245 int r1, r2; 5246 int16_t const9; 5247 5248 r2 = MASK_OP_RC_D(ctx->opcode); 5249 r1 = MASK_OP_RC_S1(ctx->opcode); 5250 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5251 5252 op2 = MASK_OP_RC_OP2(ctx->opcode); 5253 5254 switch (op2) { 5255 case OPC2_32_RC_MUL_32: 5256 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5257 break; 5258 case OPC2_32_RC_MUL_64: 5259 CHECK_REG_PAIR(r2); 5260 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5261 break; 5262 case OPC2_32_RC_MULS_32: 5263 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5264 break; 5265 case OPC2_32_RC_MUL_U_64: 5266 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5267 CHECK_REG_PAIR(r2); 5268 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5269 break; 5270 case OPC2_32_RC_MULS_U_32: 5271 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5272 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5273 break; 5274 default: 5275 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5276 } 5277 } 5278 5279 /* RCPW format */ 5280 static void decode_rcpw_insert(DisasContext *ctx) 5281 { 5282 uint32_t op2; 5283 int r1, r2; 5284 int32_t pos, width, const4; 5285 5286 TCGv temp; 5287 5288 op2 = MASK_OP_RCPW_OP2(ctx->opcode); 5289 r1 = MASK_OP_RCPW_S1(ctx->opcode); 5290 r2 = MASK_OP_RCPW_D(ctx->opcode); 5291 const4 = MASK_OP_RCPW_CONST4(ctx->opcode); 5292 width = MASK_OP_RCPW_WIDTH(ctx->opcode); 5293 pos = MASK_OP_RCPW_POS(ctx->opcode); 5294 5295 switch (op2) { 5296 case OPC2_32_RCPW_IMASK: 5297 CHECK_REG_PAIR(r2); 5298 /* if pos + width > 32 undefined result */ 5299 if (pos + width <= 32) { 5300 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); 5301 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); 5302 } 5303 break; 5304 case OPC2_32_RCPW_INSERT: 5305 /* if pos + width > 32 undefined result */ 5306 if (pos + width <= 32) { 5307 temp = tcg_constant_i32(const4); 5308 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); 5309 } 5310 break; 5311 default: 5312 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5313 } 5314 } 5315 5316 /* RCRW format */ 5317 5318 static void decode_rcrw_insert(DisasContext *ctx) 5319 { 5320 uint32_t op2; 5321 int r1, r3, r4; 5322 int32_t width, const4; 5323 5324 TCGv temp, temp2, temp3; 5325 5326 op2 = MASK_OP_RCRW_OP2(ctx->opcode); 5327 r1 = MASK_OP_RCRW_S1(ctx->opcode); 5328 r3 = MASK_OP_RCRW_S3(ctx->opcode); 5329 r4 = MASK_OP_RCRW_D(ctx->opcode); 5330 width = MASK_OP_RCRW_WIDTH(ctx->opcode); 5331 const4 = MASK_OP_RCRW_CONST4(ctx->opcode); 5332 5333 temp = tcg_temp_new(); 5334 temp2 = tcg_temp_new(); 5335 5336 switch (op2) { 5337 case OPC2_32_RCRW_IMASK: 5338 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 5339 tcg_gen_movi_tl(temp2, (1 << width) - 1); 5340 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); 5341 tcg_gen_movi_tl(temp2, const4); 5342 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); 5343 break; 5344 case OPC2_32_RCRW_INSERT: 5345 temp3 = tcg_temp_new(); 5346 5347 tcg_gen_movi_tl(temp, width); 5348 tcg_gen_movi_tl(temp2, const4); 5349 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 5350 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); 5351 break; 5352 default: 5353 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5354 } 5355 } 5356 5357 /* RCR format */ 5358 5359 static void decode_rcr_cond_select(DisasContext *ctx) 5360 { 5361 uint32_t op2; 5362 int r1, r3, r4; 5363 int32_t const9; 5364 5365 TCGv temp, temp2; 5366 5367 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5368 r1 = MASK_OP_RCR_S1(ctx->opcode); 5369 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5370 r3 = MASK_OP_RCR_S3(ctx->opcode); 5371 r4 = MASK_OP_RCR_D(ctx->opcode); 5372 5373 switch (op2) { 5374 case OPC2_32_RCR_CADD: 5375 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5376 cpu_gpr_d[r3]); 5377 break; 5378 case OPC2_32_RCR_CADDN: 5379 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5380 cpu_gpr_d[r3]); 5381 break; 5382 case OPC2_32_RCR_SEL: 5383 temp = tcg_constant_i32(0); 5384 temp2 = tcg_constant_i32(const9); 5385 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5386 cpu_gpr_d[r1], temp2); 5387 break; 5388 case OPC2_32_RCR_SELN: 5389 temp = tcg_constant_i32(0); 5390 temp2 = tcg_constant_i32(const9); 5391 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5392 cpu_gpr_d[r1], temp2); 5393 break; 5394 default: 5395 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5396 } 5397 } 5398 5399 static void decode_rcr_madd(DisasContext *ctx) 5400 { 5401 uint32_t op2; 5402 int r1, r3, r4; 5403 int32_t const9; 5404 5405 5406 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5407 r1 = MASK_OP_RCR_S1(ctx->opcode); 5408 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5409 r3 = MASK_OP_RCR_S3(ctx->opcode); 5410 r4 = MASK_OP_RCR_D(ctx->opcode); 5411 5412 switch (op2) { 5413 case OPC2_32_RCR_MADD_32: 5414 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5415 break; 5416 case OPC2_32_RCR_MADD_64: 5417 CHECK_REG_PAIR(r4); 5418 CHECK_REG_PAIR(r3); 5419 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5420 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5421 break; 5422 case OPC2_32_RCR_MADDS_32: 5423 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5424 break; 5425 case OPC2_32_RCR_MADDS_64: 5426 CHECK_REG_PAIR(r4); 5427 CHECK_REG_PAIR(r3); 5428 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5429 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5430 break; 5431 case OPC2_32_RCR_MADD_U_64: 5432 CHECK_REG_PAIR(r4); 5433 CHECK_REG_PAIR(r3); 5434 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5435 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5436 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5437 break; 5438 case OPC2_32_RCR_MADDS_U_32: 5439 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5440 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5441 break; 5442 case OPC2_32_RCR_MADDS_U_64: 5443 CHECK_REG_PAIR(r4); 5444 CHECK_REG_PAIR(r3); 5445 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5446 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5447 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5448 break; 5449 default: 5450 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5451 } 5452 } 5453 5454 static void decode_rcr_msub(DisasContext *ctx) 5455 { 5456 uint32_t op2; 5457 int r1, r3, r4; 5458 int32_t const9; 5459 5460 5461 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5462 r1 = MASK_OP_RCR_S1(ctx->opcode); 5463 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5464 r3 = MASK_OP_RCR_S3(ctx->opcode); 5465 r4 = MASK_OP_RCR_D(ctx->opcode); 5466 5467 switch (op2) { 5468 case OPC2_32_RCR_MSUB_32: 5469 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5470 break; 5471 case OPC2_32_RCR_MSUB_64: 5472 CHECK_REG_PAIR(r4); 5473 CHECK_REG_PAIR(r3); 5474 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5475 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5476 break; 5477 case OPC2_32_RCR_MSUBS_32: 5478 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5479 break; 5480 case OPC2_32_RCR_MSUBS_64: 5481 CHECK_REG_PAIR(r4); 5482 CHECK_REG_PAIR(r3); 5483 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5484 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5485 break; 5486 case OPC2_32_RCR_MSUB_U_64: 5487 CHECK_REG_PAIR(r4); 5488 CHECK_REG_PAIR(r3); 5489 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5490 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5491 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5492 break; 5493 case OPC2_32_RCR_MSUBS_U_32: 5494 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5495 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5496 break; 5497 case OPC2_32_RCR_MSUBS_U_64: 5498 CHECK_REG_PAIR(r4); 5499 CHECK_REG_PAIR(r3); 5500 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5501 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5502 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5503 break; 5504 default: 5505 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5506 } 5507 } 5508 5509 /* RLC format */ 5510 5511 static void decode_rlc_opc(DisasContext *ctx, 5512 uint32_t op1) 5513 { 5514 int32_t const16; 5515 int r1, r2; 5516 5517 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); 5518 r1 = MASK_OP_RLC_S1(ctx->opcode); 5519 r2 = MASK_OP_RLC_D(ctx->opcode); 5520 5521 switch (op1) { 5522 case OPC1_32_RLC_ADDI: 5523 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); 5524 break; 5525 case OPC1_32_RLC_ADDIH: 5526 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); 5527 break; 5528 case OPC1_32_RLC_ADDIH_A: 5529 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); 5530 break; 5531 case OPC1_32_RLC_MFCR: 5532 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5533 gen_mfcr(ctx, cpu_gpr_d[r2], const16); 5534 break; 5535 case OPC1_32_RLC_MOV: 5536 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5537 break; 5538 case OPC1_32_RLC_MOV_64: 5539 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5540 CHECK_REG_PAIR(r2); 5541 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5542 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); 5543 } else { 5544 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5545 } 5546 break; 5547 case OPC1_32_RLC_MOV_U: 5548 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5549 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 5550 break; 5551 case OPC1_32_RLC_MOV_H: 5552 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); 5553 break; 5554 case OPC1_32_RLC_MOVH_A: 5555 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); 5556 break; 5557 case OPC1_32_RLC_MTCR: 5558 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 5559 gen_mtcr(ctx, cpu_gpr_d[r1], const16); 5560 break; 5561 default: 5562 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5563 } 5564 } 5565 5566 /* RR format */ 5567 static void decode_rr_accumulator(DisasContext *ctx) 5568 { 5569 uint32_t op2; 5570 int r3, r2, r1; 5571 5572 TCGv temp; 5573 5574 r3 = MASK_OP_RR_D(ctx->opcode); 5575 r2 = MASK_OP_RR_S2(ctx->opcode); 5576 r1 = MASK_OP_RR_S1(ctx->opcode); 5577 op2 = MASK_OP_RR_OP2(ctx->opcode); 5578 5579 switch (op2) { 5580 case OPC2_32_RR_ABS: 5581 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5582 break; 5583 case OPC2_32_RR_ABS_B: 5584 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5585 break; 5586 case OPC2_32_RR_ABS_H: 5587 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5588 break; 5589 case OPC2_32_RR_ABSDIF: 5590 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5591 break; 5592 case OPC2_32_RR_ABSDIF_B: 5593 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5594 cpu_gpr_d[r2]); 5595 break; 5596 case OPC2_32_RR_ABSDIF_H: 5597 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5598 cpu_gpr_d[r2]); 5599 break; 5600 case OPC2_32_RR_ABSDIFS: 5601 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5602 cpu_gpr_d[r2]); 5603 break; 5604 case OPC2_32_RR_ABSDIFS_H: 5605 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5606 cpu_gpr_d[r2]); 5607 break; 5608 case OPC2_32_RR_ABSS: 5609 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5610 break; 5611 case OPC2_32_RR_ABSS_H: 5612 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 5613 break; 5614 case OPC2_32_RR_ADD: 5615 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5616 break; 5617 case OPC2_32_RR_ADD_B: 5618 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5619 break; 5620 case OPC2_32_RR_ADD_H: 5621 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5622 break; 5623 case OPC2_32_RR_ADDC: 5624 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5625 break; 5626 case OPC2_32_RR_ADDS: 5627 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5628 break; 5629 case OPC2_32_RR_ADDS_H: 5630 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5631 cpu_gpr_d[r2]); 5632 break; 5633 case OPC2_32_RR_ADDS_HU: 5634 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5635 cpu_gpr_d[r2]); 5636 break; 5637 case OPC2_32_RR_ADDS_U: 5638 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5639 cpu_gpr_d[r2]); 5640 break; 5641 case OPC2_32_RR_ADDX: 5642 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5643 break; 5644 case OPC2_32_RR_AND_EQ: 5645 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5646 cpu_gpr_d[r2], &tcg_gen_and_tl); 5647 break; 5648 case OPC2_32_RR_AND_GE: 5649 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5650 cpu_gpr_d[r2], &tcg_gen_and_tl); 5651 break; 5652 case OPC2_32_RR_AND_GE_U: 5653 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5654 cpu_gpr_d[r2], &tcg_gen_and_tl); 5655 break; 5656 case OPC2_32_RR_AND_LT: 5657 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5658 cpu_gpr_d[r2], &tcg_gen_and_tl); 5659 break; 5660 case OPC2_32_RR_AND_LT_U: 5661 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5662 cpu_gpr_d[r2], &tcg_gen_and_tl); 5663 break; 5664 case OPC2_32_RR_AND_NE: 5665 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5666 cpu_gpr_d[r2], &tcg_gen_and_tl); 5667 break; 5668 case OPC2_32_RR_EQ: 5669 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5670 cpu_gpr_d[r2]); 5671 break; 5672 case OPC2_32_RR_EQ_B: 5673 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5674 break; 5675 case OPC2_32_RR_EQ_H: 5676 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5677 break; 5678 case OPC2_32_RR_EQ_W: 5679 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5680 break; 5681 case OPC2_32_RR_EQANY_B: 5682 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5683 break; 5684 case OPC2_32_RR_EQANY_H: 5685 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5686 break; 5687 case OPC2_32_RR_GE: 5688 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5689 cpu_gpr_d[r2]); 5690 break; 5691 case OPC2_32_RR_GE_U: 5692 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5693 cpu_gpr_d[r2]); 5694 break; 5695 case OPC2_32_RR_LT: 5696 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5697 cpu_gpr_d[r2]); 5698 break; 5699 case OPC2_32_RR_LT_U: 5700 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5701 cpu_gpr_d[r2]); 5702 break; 5703 case OPC2_32_RR_LT_B: 5704 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5705 break; 5706 case OPC2_32_RR_LT_BU: 5707 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5708 break; 5709 case OPC2_32_RR_LT_H: 5710 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5711 break; 5712 case OPC2_32_RR_LT_HU: 5713 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5714 break; 5715 case OPC2_32_RR_LT_W: 5716 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5717 break; 5718 case OPC2_32_RR_LT_WU: 5719 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5720 break; 5721 case OPC2_32_RR_MAX: 5722 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5723 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5724 break; 5725 case OPC2_32_RR_MAX_U: 5726 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5727 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5728 break; 5729 case OPC2_32_RR_MAX_B: 5730 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5731 break; 5732 case OPC2_32_RR_MAX_BU: 5733 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5734 break; 5735 case OPC2_32_RR_MAX_H: 5736 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5737 break; 5738 case OPC2_32_RR_MAX_HU: 5739 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5740 break; 5741 case OPC2_32_RR_MIN: 5742 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5743 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5744 break; 5745 case OPC2_32_RR_MIN_U: 5746 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5747 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5748 break; 5749 case OPC2_32_RR_MIN_B: 5750 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5751 break; 5752 case OPC2_32_RR_MIN_BU: 5753 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5754 break; 5755 case OPC2_32_RR_MIN_H: 5756 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5757 break; 5758 case OPC2_32_RR_MIN_HU: 5759 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5760 break; 5761 case OPC2_32_RR_MOV: 5762 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5763 break; 5764 case OPC2_32_RR_MOV_64: 5765 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5766 temp = tcg_temp_new(); 5767 5768 CHECK_REG_PAIR(r3); 5769 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 5770 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5771 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 5772 } else { 5773 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5774 } 5775 break; 5776 case OPC2_32_RR_MOVS_64: 5777 if (has_feature(ctx, TRICORE_FEATURE_16)) { 5778 CHECK_REG_PAIR(r3); 5779 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 5780 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); 5781 } else { 5782 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5783 } 5784 break; 5785 case OPC2_32_RR_NE: 5786 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5787 cpu_gpr_d[r2]); 5788 break; 5789 case OPC2_32_RR_OR_EQ: 5790 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5791 cpu_gpr_d[r2], &tcg_gen_or_tl); 5792 break; 5793 case OPC2_32_RR_OR_GE: 5794 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5795 cpu_gpr_d[r2], &tcg_gen_or_tl); 5796 break; 5797 case OPC2_32_RR_OR_GE_U: 5798 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5799 cpu_gpr_d[r2], &tcg_gen_or_tl); 5800 break; 5801 case OPC2_32_RR_OR_LT: 5802 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5803 cpu_gpr_d[r2], &tcg_gen_or_tl); 5804 break; 5805 case OPC2_32_RR_OR_LT_U: 5806 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5807 cpu_gpr_d[r2], &tcg_gen_or_tl); 5808 break; 5809 case OPC2_32_RR_OR_NE: 5810 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5811 cpu_gpr_d[r2], &tcg_gen_or_tl); 5812 break; 5813 case OPC2_32_RR_SAT_B: 5814 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); 5815 break; 5816 case OPC2_32_RR_SAT_BU: 5817 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); 5818 break; 5819 case OPC2_32_RR_SAT_H: 5820 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); 5821 break; 5822 case OPC2_32_RR_SAT_HU: 5823 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); 5824 break; 5825 case OPC2_32_RR_SH_EQ: 5826 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5827 cpu_gpr_d[r2]); 5828 break; 5829 case OPC2_32_RR_SH_GE: 5830 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5831 cpu_gpr_d[r2]); 5832 break; 5833 case OPC2_32_RR_SH_GE_U: 5834 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5835 cpu_gpr_d[r2]); 5836 break; 5837 case OPC2_32_RR_SH_LT: 5838 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5839 cpu_gpr_d[r2]); 5840 break; 5841 case OPC2_32_RR_SH_LT_U: 5842 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5843 cpu_gpr_d[r2]); 5844 break; 5845 case OPC2_32_RR_SH_NE: 5846 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5847 cpu_gpr_d[r2]); 5848 break; 5849 case OPC2_32_RR_SUB: 5850 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5851 break; 5852 case OPC2_32_RR_SUB_B: 5853 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5854 break; 5855 case OPC2_32_RR_SUB_H: 5856 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5857 break; 5858 case OPC2_32_RR_SUBC: 5859 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5860 break; 5861 case OPC2_32_RR_SUBS: 5862 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5863 break; 5864 case OPC2_32_RR_SUBS_U: 5865 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5866 break; 5867 case OPC2_32_RR_SUBS_H: 5868 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5869 cpu_gpr_d[r2]); 5870 break; 5871 case OPC2_32_RR_SUBS_HU: 5872 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 5873 cpu_gpr_d[r2]); 5874 break; 5875 case OPC2_32_RR_SUBX: 5876 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5877 break; 5878 case OPC2_32_RR_XOR_EQ: 5879 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 5880 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5881 break; 5882 case OPC2_32_RR_XOR_GE: 5883 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5884 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5885 break; 5886 case OPC2_32_RR_XOR_GE_U: 5887 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5888 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5889 break; 5890 case OPC2_32_RR_XOR_LT: 5891 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 5892 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5893 break; 5894 case OPC2_32_RR_XOR_LT_U: 5895 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 5896 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5897 break; 5898 case OPC2_32_RR_XOR_NE: 5899 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 5900 cpu_gpr_d[r2], &tcg_gen_xor_tl); 5901 break; 5902 default: 5903 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5904 } 5905 } 5906 5907 static void decode_rr_logical_shift(DisasContext *ctx) 5908 { 5909 uint32_t op2; 5910 int r3, r2, r1; 5911 5912 r3 = MASK_OP_RR_D(ctx->opcode); 5913 r2 = MASK_OP_RR_S2(ctx->opcode); 5914 r1 = MASK_OP_RR_S1(ctx->opcode); 5915 op2 = MASK_OP_RR_OP2(ctx->opcode); 5916 5917 switch (op2) { 5918 case OPC2_32_RR_AND: 5919 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5920 break; 5921 case OPC2_32_RR_ANDN: 5922 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5923 break; 5924 case OPC2_32_RR_CLO: 5925 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5926 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); 5927 break; 5928 case OPC2_32_RR_CLO_H: 5929 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5930 break; 5931 case OPC2_32_RR_CLS: 5932 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5933 break; 5934 case OPC2_32_RR_CLS_H: 5935 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5936 break; 5937 case OPC2_32_RR_CLZ: 5938 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); 5939 break; 5940 case OPC2_32_RR_CLZ_H: 5941 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 5942 break; 5943 case OPC2_32_RR_NAND: 5944 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5945 break; 5946 case OPC2_32_RR_NOR: 5947 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5948 break; 5949 case OPC2_32_RR_OR: 5950 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5951 break; 5952 case OPC2_32_RR_ORN: 5953 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5954 break; 5955 case OPC2_32_RR_SH: 5956 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5957 break; 5958 case OPC2_32_RR_SH_H: 5959 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5960 break; 5961 case OPC2_32_RR_SHA: 5962 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 5963 break; 5964 case OPC2_32_RR_SHA_H: 5965 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5966 break; 5967 case OPC2_32_RR_SHAS: 5968 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5969 break; 5970 case OPC2_32_RR_XNOR: 5971 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5972 break; 5973 case OPC2_32_RR_XOR: 5974 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 5975 break; 5976 default: 5977 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5978 } 5979 } 5980 5981 static void decode_rr_address(DisasContext *ctx) 5982 { 5983 uint32_t op2, n; 5984 int r1, r2, r3; 5985 TCGv temp; 5986 5987 op2 = MASK_OP_RR_OP2(ctx->opcode); 5988 r3 = MASK_OP_RR_D(ctx->opcode); 5989 r2 = MASK_OP_RR_S2(ctx->opcode); 5990 r1 = MASK_OP_RR_S1(ctx->opcode); 5991 n = MASK_OP_RR_N(ctx->opcode); 5992 5993 switch (op2) { 5994 case OPC2_32_RR_ADD_A: 5995 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 5996 break; 5997 case OPC2_32_RR_ADDSC_A: 5998 temp = tcg_temp_new(); 5999 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); 6000 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); 6001 break; 6002 case OPC2_32_RR_ADDSC_AT: 6003 temp = tcg_temp_new(); 6004 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); 6005 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); 6006 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); 6007 break; 6008 case OPC2_32_RR_EQ_A: 6009 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 6010 cpu_gpr_a[r2]); 6011 break; 6012 case OPC2_32_RR_EQZ: 6013 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6014 break; 6015 case OPC2_32_RR_GE_A: 6016 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6017 cpu_gpr_a[r2]); 6018 break; 6019 case OPC2_32_RR_LT_A: 6020 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6021 cpu_gpr_a[r2]); 6022 break; 6023 case OPC2_32_RR_MOV_A: 6024 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); 6025 break; 6026 case OPC2_32_RR_MOV_AA: 6027 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); 6028 break; 6029 case OPC2_32_RR_MOV_D: 6030 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); 6031 break; 6032 case OPC2_32_RR_NE_A: 6033 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 6034 cpu_gpr_a[r2]); 6035 break; 6036 case OPC2_32_RR_NEZ_A: 6037 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6038 break; 6039 case OPC2_32_RR_SUB_A: 6040 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6041 break; 6042 default: 6043 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6044 } 6045 } 6046 6047 static void decode_rr_idirect(DisasContext *ctx) 6048 { 6049 uint32_t op2; 6050 int r1; 6051 6052 op2 = MASK_OP_RR_OP2(ctx->opcode); 6053 r1 = MASK_OP_RR_S1(ctx->opcode); 6054 6055 switch (op2) { 6056 case OPC2_32_RR_JI: 6057 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6058 break; 6059 case OPC2_32_RR_JLI: 6060 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); 6061 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6062 break; 6063 case OPC2_32_RR_CALLI: 6064 gen_helper_1arg(call, ctx->pc_succ_insn); 6065 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6066 break; 6067 case OPC2_32_RR_FCALLI: 6068 gen_fcall_save_ctx(ctx); 6069 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6070 break; 6071 default: 6072 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6073 } 6074 tcg_gen_exit_tb(NULL, 0); 6075 ctx->base.is_jmp = DISAS_NORETURN; 6076 } 6077 6078 static void decode_rr_divide(DisasContext *ctx) 6079 { 6080 uint32_t op2; 6081 int r1, r2, r3; 6082 6083 TCGv temp, temp2, temp3; 6084 6085 op2 = MASK_OP_RR_OP2(ctx->opcode); 6086 r3 = MASK_OP_RR_D(ctx->opcode); 6087 r2 = MASK_OP_RR_S2(ctx->opcode); 6088 r1 = MASK_OP_RR_S1(ctx->opcode); 6089 6090 switch (op2) { 6091 case OPC2_32_RR_BMERGE: 6092 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6093 break; 6094 case OPC2_32_RR_BSPLIT: 6095 CHECK_REG_PAIR(r3); 6096 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6097 break; 6098 case OPC2_32_RR_DVINIT_B: 6099 CHECK_REG_PAIR(r3); 6100 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6101 cpu_gpr_d[r2]); 6102 break; 6103 case OPC2_32_RR_DVINIT_BU: 6104 temp = tcg_temp_new(); 6105 temp2 = tcg_temp_new(); 6106 temp3 = tcg_temp_new(); 6107 CHECK_REG_PAIR(r3); 6108 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); 6109 /* reset av */ 6110 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6111 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6112 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6113 tcg_gen_abs_tl(temp, temp3); 6114 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6115 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6116 } else { 6117 /* overflow = (D[b] == 0) */ 6118 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6119 } 6120 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6121 /* sv */ 6122 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6123 /* write result */ 6124 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); 6125 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6126 break; 6127 case OPC2_32_RR_DVINIT_H: 6128 CHECK_REG_PAIR(r3); 6129 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6130 cpu_gpr_d[r2]); 6131 break; 6132 case OPC2_32_RR_DVINIT_HU: 6133 temp = tcg_temp_new(); 6134 temp2 = tcg_temp_new(); 6135 temp3 = tcg_temp_new(); 6136 CHECK_REG_PAIR(r3); 6137 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); 6138 /* reset av */ 6139 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6140 if (!has_feature(ctx, TRICORE_FEATURE_131)) { 6141 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6142 tcg_gen_abs_tl(temp, temp3); 6143 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6144 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6145 } else { 6146 /* overflow = (D[b] == 0) */ 6147 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6148 } 6149 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6150 /* sv */ 6151 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6152 /* write result */ 6153 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); 6154 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6155 break; 6156 case OPC2_32_RR_DVINIT: 6157 temp = tcg_temp_new(); 6158 temp2 = tcg_temp_new(); 6159 CHECK_REG_PAIR(r3); 6160 /* overflow = ((D[b] == 0) || 6161 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ 6162 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); 6163 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); 6164 tcg_gen_and_tl(temp, temp, temp2); 6165 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); 6166 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 6167 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6168 /* sv */ 6169 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6170 /* reset av */ 6171 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6172 /* write result */ 6173 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6174 /* sign extend to high reg */ 6175 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); 6176 break; 6177 case OPC2_32_RR_DVINIT_U: 6178 /* overflow = (D[b] == 0) */ 6179 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6180 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6181 /* sv */ 6182 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6183 /* reset av */ 6184 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6185 /* write result */ 6186 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6187 /* zero extend to high reg*/ 6188 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); 6189 break; 6190 case OPC2_32_RR_PARITY: 6191 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6192 break; 6193 case OPC2_32_RR_UNPACK: 6194 CHECK_REG_PAIR(r3); 6195 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6196 break; 6197 case OPC2_32_RR_CRC32: 6198 if (has_feature(ctx, TRICORE_FEATURE_161)) { 6199 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6200 } else { 6201 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6202 } 6203 break; 6204 case OPC2_32_RR_DIV: 6205 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6206 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6207 cpu_gpr_d[r2]); 6208 } else { 6209 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6210 } 6211 break; 6212 case OPC2_32_RR_DIV_U: 6213 if (has_feature(ctx, TRICORE_FEATURE_16)) { 6214 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], 6215 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6216 } else { 6217 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6218 } 6219 break; 6220 case OPC2_32_RR_MUL_F: 6221 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6222 break; 6223 case OPC2_32_RR_DIV_F: 6224 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6225 break; 6226 case OPC2_32_RR_CMP_F: 6227 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6228 break; 6229 case OPC2_32_RR_FTOI: 6230 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6231 break; 6232 case OPC2_32_RR_ITOF: 6233 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6234 break; 6235 case OPC2_32_RR_FTOUZ: 6236 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6237 break; 6238 case OPC2_32_RR_UPDFL: 6239 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); 6240 break; 6241 case OPC2_32_RR_UTOF: 6242 gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6243 break; 6244 case OPC2_32_RR_FTOIZ: 6245 gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6246 break; 6247 case OPC2_32_RR_QSEED_F: 6248 gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6249 break; 6250 default: 6251 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6252 } 6253 } 6254 6255 /* RR1 Format */ 6256 static void decode_rr1_mul(DisasContext *ctx) 6257 { 6258 uint32_t op2; 6259 6260 int r1, r2, r3; 6261 TCGv n; 6262 TCGv_i64 temp64; 6263 6264 r1 = MASK_OP_RR1_S1(ctx->opcode); 6265 r2 = MASK_OP_RR1_S2(ctx->opcode); 6266 r3 = MASK_OP_RR1_D(ctx->opcode); 6267 n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode)); 6268 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6269 6270 switch (op2) { 6271 case OPC2_32_RR1_MUL_H_32_LL: 6272 temp64 = tcg_temp_new_i64(); 6273 CHECK_REG_PAIR(r3); 6274 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6275 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6276 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6277 break; 6278 case OPC2_32_RR1_MUL_H_32_LU: 6279 temp64 = tcg_temp_new_i64(); 6280 CHECK_REG_PAIR(r3); 6281 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6282 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6283 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6284 break; 6285 case OPC2_32_RR1_MUL_H_32_UL: 6286 temp64 = tcg_temp_new_i64(); 6287 CHECK_REG_PAIR(r3); 6288 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6289 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6290 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6291 break; 6292 case OPC2_32_RR1_MUL_H_32_UU: 6293 temp64 = tcg_temp_new_i64(); 6294 CHECK_REG_PAIR(r3); 6295 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6296 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6297 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6298 break; 6299 case OPC2_32_RR1_MULM_H_64_LL: 6300 temp64 = tcg_temp_new_i64(); 6301 CHECK_REG_PAIR(r3); 6302 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6303 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6304 /* reset V bit */ 6305 tcg_gen_movi_tl(cpu_PSW_V, 0); 6306 /* reset AV bit */ 6307 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6308 break; 6309 case OPC2_32_RR1_MULM_H_64_LU: 6310 temp64 = tcg_temp_new_i64(); 6311 CHECK_REG_PAIR(r3); 6312 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6313 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6314 /* reset V bit */ 6315 tcg_gen_movi_tl(cpu_PSW_V, 0); 6316 /* reset AV bit */ 6317 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6318 break; 6319 case OPC2_32_RR1_MULM_H_64_UL: 6320 temp64 = tcg_temp_new_i64(); 6321 CHECK_REG_PAIR(r3); 6322 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6323 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6324 /* reset V bit */ 6325 tcg_gen_movi_tl(cpu_PSW_V, 0); 6326 /* reset AV bit */ 6327 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6328 break; 6329 case OPC2_32_RR1_MULM_H_64_UU: 6330 temp64 = tcg_temp_new_i64(); 6331 CHECK_REG_PAIR(r3); 6332 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6333 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6334 /* reset V bit */ 6335 tcg_gen_movi_tl(cpu_PSW_V, 0); 6336 /* reset AV bit */ 6337 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6338 break; 6339 case OPC2_32_RR1_MULR_H_16_LL: 6340 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6341 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6342 break; 6343 case OPC2_32_RR1_MULR_H_16_LU: 6344 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6345 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6346 break; 6347 case OPC2_32_RR1_MULR_H_16_UL: 6348 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6349 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6350 break; 6351 case OPC2_32_RR1_MULR_H_16_UU: 6352 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6353 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6354 break; 6355 default: 6356 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6357 } 6358 } 6359 6360 static void decode_rr1_mulq(DisasContext *ctx) 6361 { 6362 uint32_t op2; 6363 int r1, r2, r3; 6364 uint32_t n; 6365 6366 TCGv temp, temp2; 6367 6368 r1 = MASK_OP_RR1_S1(ctx->opcode); 6369 r2 = MASK_OP_RR1_S2(ctx->opcode); 6370 r3 = MASK_OP_RR1_D(ctx->opcode); 6371 n = MASK_OP_RR1_N(ctx->opcode); 6372 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6373 6374 temp = tcg_temp_new(); 6375 temp2 = tcg_temp_new(); 6376 6377 switch (op2) { 6378 case OPC2_32_RR1_MUL_Q_32: 6379 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); 6380 break; 6381 case OPC2_32_RR1_MUL_Q_64: 6382 CHECK_REG_PAIR(r3); 6383 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6384 n, 0); 6385 break; 6386 case OPC2_32_RR1_MUL_Q_32_L: 6387 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6388 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6389 break; 6390 case OPC2_32_RR1_MUL_Q_64_L: 6391 CHECK_REG_PAIR(r3); 6392 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6393 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6394 break; 6395 case OPC2_32_RR1_MUL_Q_32_U: 6396 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6397 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6398 break; 6399 case OPC2_32_RR1_MUL_Q_64_U: 6400 CHECK_REG_PAIR(r3); 6401 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6402 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6403 break; 6404 case OPC2_32_RR1_MUL_Q_32_LL: 6405 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6406 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6407 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6408 break; 6409 case OPC2_32_RR1_MUL_Q_32_UU: 6410 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6411 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6412 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6413 break; 6414 case OPC2_32_RR1_MULR_Q_32_L: 6415 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6416 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6417 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6418 break; 6419 case OPC2_32_RR1_MULR_Q_32_U: 6420 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6421 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6422 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6423 break; 6424 default: 6425 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6426 } 6427 } 6428 6429 /* RR2 format */ 6430 static void decode_rr2_mul(DisasContext *ctx) 6431 { 6432 uint32_t op2; 6433 int r1, r2, r3; 6434 6435 op2 = MASK_OP_RR2_OP2(ctx->opcode); 6436 r1 = MASK_OP_RR2_S1(ctx->opcode); 6437 r2 = MASK_OP_RR2_S2(ctx->opcode); 6438 r3 = MASK_OP_RR2_D(ctx->opcode); 6439 switch (op2) { 6440 case OPC2_32_RR2_MUL_32: 6441 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6442 break; 6443 case OPC2_32_RR2_MUL_64: 6444 CHECK_REG_PAIR(r3); 6445 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6446 cpu_gpr_d[r2]); 6447 break; 6448 case OPC2_32_RR2_MULS_32: 6449 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6450 cpu_gpr_d[r2]); 6451 break; 6452 case OPC2_32_RR2_MUL_U_64: 6453 CHECK_REG_PAIR(r3); 6454 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6455 cpu_gpr_d[r2]); 6456 break; 6457 case OPC2_32_RR2_MULS_U_32: 6458 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6459 cpu_gpr_d[r2]); 6460 break; 6461 default: 6462 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6463 } 6464 } 6465 6466 /* RRPW format */ 6467 static void decode_rrpw_extract_insert(DisasContext *ctx) 6468 { 6469 uint32_t op2; 6470 int r1, r2, r3; 6471 int32_t pos, width; 6472 TCGv temp; 6473 6474 op2 = MASK_OP_RRPW_OP2(ctx->opcode); 6475 r1 = MASK_OP_RRPW_S1(ctx->opcode); 6476 r2 = MASK_OP_RRPW_S2(ctx->opcode); 6477 r3 = MASK_OP_RRPW_D(ctx->opcode); 6478 pos = MASK_OP_RRPW_POS(ctx->opcode); 6479 width = MASK_OP_RRPW_WIDTH(ctx->opcode); 6480 6481 switch (op2) { 6482 case OPC2_32_RRPW_EXTR: 6483 if (width == 0) { 6484 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6485 break; 6486 } 6487 6488 if (pos + width <= 32) { 6489 /* optimize special cases */ 6490 if ((pos == 0) && (width == 8)) { 6491 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6492 } else if ((pos == 0) && (width == 16)) { 6493 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6494 } else { 6495 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width); 6496 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width); 6497 } 6498 } 6499 break; 6500 case OPC2_32_RRPW_EXTR_U: 6501 if (width == 0) { 6502 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 6503 } else { 6504 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); 6505 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width)); 6506 } 6507 break; 6508 case OPC2_32_RRPW_IMASK: 6509 CHECK_REG_PAIR(r3); 6510 6511 if (pos + width <= 32) { 6512 temp = tcg_temp_new(); 6513 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); 6514 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); 6515 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 6516 } 6517 6518 break; 6519 case OPC2_32_RRPW_INSERT: 6520 if (pos + width <= 32) { 6521 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 6522 pos, width); 6523 } 6524 break; 6525 default: 6526 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6527 } 6528 } 6529 6530 /* RRR format */ 6531 static void decode_rrr_cond_select(DisasContext *ctx) 6532 { 6533 uint32_t op2; 6534 int r1, r2, r3, r4; 6535 TCGv temp; 6536 6537 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6538 r1 = MASK_OP_RRR_S1(ctx->opcode); 6539 r2 = MASK_OP_RRR_S2(ctx->opcode); 6540 r3 = MASK_OP_RRR_S3(ctx->opcode); 6541 r4 = MASK_OP_RRR_D(ctx->opcode); 6542 6543 switch (op2) { 6544 case OPC2_32_RRR_CADD: 6545 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 6546 cpu_gpr_d[r4], cpu_gpr_d[r3]); 6547 break; 6548 case OPC2_32_RRR_CADDN: 6549 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6550 cpu_gpr_d[r3]); 6551 break; 6552 case OPC2_32_RRR_CSUB: 6553 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6554 cpu_gpr_d[r3]); 6555 break; 6556 case OPC2_32_RRR_CSUBN: 6557 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 6558 cpu_gpr_d[r3]); 6559 break; 6560 case OPC2_32_RRR_SEL: 6561 temp = tcg_constant_i32(0); 6562 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6563 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6564 break; 6565 case OPC2_32_RRR_SELN: 6566 temp = tcg_constant_i32(0); 6567 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 6568 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6569 break; 6570 default: 6571 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6572 } 6573 } 6574 6575 static void decode_rrr_divide(DisasContext *ctx) 6576 { 6577 uint32_t op2; 6578 6579 int r1, r2, r3, r4; 6580 6581 op2 = MASK_OP_RRR_OP2(ctx->opcode); 6582 r1 = MASK_OP_RRR_S1(ctx->opcode); 6583 r2 = MASK_OP_RRR_S2(ctx->opcode); 6584 r3 = MASK_OP_RRR_S3(ctx->opcode); 6585 r4 = MASK_OP_RRR_D(ctx->opcode); 6586 6587 switch (op2) { 6588 case OPC2_32_RRR_DVADJ: 6589 CHECK_REG_PAIR(r3); 6590 CHECK_REG_PAIR(r4); 6591 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6592 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6593 break; 6594 case OPC2_32_RRR_DVSTEP: 6595 CHECK_REG_PAIR(r3); 6596 CHECK_REG_PAIR(r4); 6597 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6598 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6599 break; 6600 case OPC2_32_RRR_DVSTEP_U: 6601 CHECK_REG_PAIR(r3); 6602 CHECK_REG_PAIR(r4); 6603 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6604 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6605 break; 6606 case OPC2_32_RRR_IXMAX: 6607 CHECK_REG_PAIR(r3); 6608 CHECK_REG_PAIR(r4); 6609 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6610 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6611 break; 6612 case OPC2_32_RRR_IXMAX_U: 6613 CHECK_REG_PAIR(r3); 6614 CHECK_REG_PAIR(r4); 6615 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6616 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6617 break; 6618 case OPC2_32_RRR_IXMIN: 6619 CHECK_REG_PAIR(r3); 6620 CHECK_REG_PAIR(r4); 6621 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6622 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6623 break; 6624 case OPC2_32_RRR_IXMIN_U: 6625 CHECK_REG_PAIR(r3); 6626 CHECK_REG_PAIR(r4); 6627 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6628 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6629 break; 6630 case OPC2_32_RRR_PACK: 6631 CHECK_REG_PAIR(r3); 6632 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], 6633 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6634 break; 6635 case OPC2_32_RRR_ADD_F: 6636 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6637 break; 6638 case OPC2_32_RRR_SUB_F: 6639 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 6640 break; 6641 case OPC2_32_RRR_MADD_F: 6642 gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6643 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6644 break; 6645 case OPC2_32_RRR_MSUB_F: 6646 gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6647 cpu_gpr_d[r2], cpu_gpr_d[r3]); 6648 break; 6649 default: 6650 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6651 } 6652 } 6653 6654 /* RRR2 format */ 6655 static void decode_rrr2_madd(DisasContext *ctx) 6656 { 6657 uint32_t op2; 6658 uint32_t r1, r2, r3, r4; 6659 6660 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6661 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6662 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6663 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6664 r4 = MASK_OP_RRR2_D(ctx->opcode); 6665 switch (op2) { 6666 case OPC2_32_RRR2_MADD_32: 6667 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6668 cpu_gpr_d[r2]); 6669 break; 6670 case OPC2_32_RRR2_MADD_64: 6671 CHECK_REG_PAIR(r4); 6672 CHECK_REG_PAIR(r3); 6673 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6674 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6675 break; 6676 case OPC2_32_RRR2_MADDS_32: 6677 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6678 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6679 break; 6680 case OPC2_32_RRR2_MADDS_64: 6681 CHECK_REG_PAIR(r4); 6682 CHECK_REG_PAIR(r3); 6683 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6684 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6685 break; 6686 case OPC2_32_RRR2_MADD_U_64: 6687 CHECK_REG_PAIR(r4); 6688 CHECK_REG_PAIR(r3); 6689 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6690 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6691 break; 6692 case OPC2_32_RRR2_MADDS_U_32: 6693 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6694 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6695 break; 6696 case OPC2_32_RRR2_MADDS_U_64: 6697 CHECK_REG_PAIR(r4); 6698 CHECK_REG_PAIR(r3); 6699 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6700 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6701 break; 6702 default: 6703 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6704 } 6705 } 6706 6707 static void decode_rrr2_msub(DisasContext *ctx) 6708 { 6709 uint32_t op2; 6710 uint32_t r1, r2, r3, r4; 6711 6712 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 6713 r1 = MASK_OP_RRR2_S1(ctx->opcode); 6714 r2 = MASK_OP_RRR2_S2(ctx->opcode); 6715 r3 = MASK_OP_RRR2_S3(ctx->opcode); 6716 r4 = MASK_OP_RRR2_D(ctx->opcode); 6717 6718 switch (op2) { 6719 case OPC2_32_RRR2_MSUB_32: 6720 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 6721 cpu_gpr_d[r2]); 6722 break; 6723 case OPC2_32_RRR2_MSUB_64: 6724 CHECK_REG_PAIR(r4); 6725 CHECK_REG_PAIR(r3); 6726 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6727 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6728 break; 6729 case OPC2_32_RRR2_MSUBS_32: 6730 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6731 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6732 break; 6733 case OPC2_32_RRR2_MSUBS_64: 6734 CHECK_REG_PAIR(r4); 6735 CHECK_REG_PAIR(r3); 6736 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6737 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6738 break; 6739 case OPC2_32_RRR2_MSUB_U_64: 6740 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6741 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6742 break; 6743 case OPC2_32_RRR2_MSUBS_U_32: 6744 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 6745 cpu_gpr_d[r3], cpu_gpr_d[r2]); 6746 break; 6747 case OPC2_32_RRR2_MSUBS_U_64: 6748 CHECK_REG_PAIR(r4); 6749 CHECK_REG_PAIR(r3); 6750 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6751 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 6752 break; 6753 default: 6754 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6755 } 6756 } 6757 6758 /* RRR1 format */ 6759 static void decode_rrr1_madd(DisasContext *ctx) 6760 { 6761 uint32_t op2; 6762 uint32_t r1, r2, r3, r4, n; 6763 6764 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6765 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6766 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6767 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6768 r4 = MASK_OP_RRR1_D(ctx->opcode); 6769 n = MASK_OP_RRR1_N(ctx->opcode); 6770 6771 switch (op2) { 6772 case OPC2_32_RRR1_MADD_H_LL: 6773 CHECK_REG_PAIR(r4); 6774 CHECK_REG_PAIR(r3); 6775 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6776 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6777 break; 6778 case OPC2_32_RRR1_MADD_H_LU: 6779 CHECK_REG_PAIR(r4); 6780 CHECK_REG_PAIR(r3); 6781 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6782 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6783 break; 6784 case OPC2_32_RRR1_MADD_H_UL: 6785 CHECK_REG_PAIR(r4); 6786 CHECK_REG_PAIR(r3); 6787 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6788 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6789 break; 6790 case OPC2_32_RRR1_MADD_H_UU: 6791 CHECK_REG_PAIR(r4); 6792 CHECK_REG_PAIR(r3); 6793 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6794 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6795 break; 6796 case OPC2_32_RRR1_MADDS_H_LL: 6797 CHECK_REG_PAIR(r4); 6798 CHECK_REG_PAIR(r3); 6799 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6800 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6801 break; 6802 case OPC2_32_RRR1_MADDS_H_LU: 6803 CHECK_REG_PAIR(r4); 6804 CHECK_REG_PAIR(r3); 6805 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6806 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6807 break; 6808 case OPC2_32_RRR1_MADDS_H_UL: 6809 CHECK_REG_PAIR(r4); 6810 CHECK_REG_PAIR(r3); 6811 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6812 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6813 break; 6814 case OPC2_32_RRR1_MADDS_H_UU: 6815 CHECK_REG_PAIR(r4); 6816 CHECK_REG_PAIR(r3); 6817 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6818 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6819 break; 6820 case OPC2_32_RRR1_MADDM_H_LL: 6821 CHECK_REG_PAIR(r4); 6822 CHECK_REG_PAIR(r3); 6823 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6824 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6825 break; 6826 case OPC2_32_RRR1_MADDM_H_LU: 6827 CHECK_REG_PAIR(r4); 6828 CHECK_REG_PAIR(r3); 6829 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6830 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6831 break; 6832 case OPC2_32_RRR1_MADDM_H_UL: 6833 CHECK_REG_PAIR(r4); 6834 CHECK_REG_PAIR(r3); 6835 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6836 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6837 break; 6838 case OPC2_32_RRR1_MADDM_H_UU: 6839 CHECK_REG_PAIR(r4); 6840 CHECK_REG_PAIR(r3); 6841 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6842 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6843 break; 6844 case OPC2_32_RRR1_MADDMS_H_LL: 6845 CHECK_REG_PAIR(r4); 6846 CHECK_REG_PAIR(r3); 6847 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6848 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 6849 break; 6850 case OPC2_32_RRR1_MADDMS_H_LU: 6851 CHECK_REG_PAIR(r4); 6852 CHECK_REG_PAIR(r3); 6853 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6854 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 6855 break; 6856 case OPC2_32_RRR1_MADDMS_H_UL: 6857 CHECK_REG_PAIR(r4); 6858 CHECK_REG_PAIR(r3); 6859 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6860 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 6861 break; 6862 case OPC2_32_RRR1_MADDMS_H_UU: 6863 CHECK_REG_PAIR(r4); 6864 CHECK_REG_PAIR(r3); 6865 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6866 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 6867 break; 6868 case OPC2_32_RRR1_MADDR_H_LL: 6869 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6870 cpu_gpr_d[r2], n, MODE_LL); 6871 break; 6872 case OPC2_32_RRR1_MADDR_H_LU: 6873 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6874 cpu_gpr_d[r2], n, MODE_LU); 6875 break; 6876 case OPC2_32_RRR1_MADDR_H_UL: 6877 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6878 cpu_gpr_d[r2], n, MODE_UL); 6879 break; 6880 case OPC2_32_RRR1_MADDR_H_UU: 6881 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6882 cpu_gpr_d[r2], n, MODE_UU); 6883 break; 6884 case OPC2_32_RRR1_MADDRS_H_LL: 6885 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6886 cpu_gpr_d[r2], n, MODE_LL); 6887 break; 6888 case OPC2_32_RRR1_MADDRS_H_LU: 6889 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6890 cpu_gpr_d[r2], n, MODE_LU); 6891 break; 6892 case OPC2_32_RRR1_MADDRS_H_UL: 6893 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6894 cpu_gpr_d[r2], n, MODE_UL); 6895 break; 6896 case OPC2_32_RRR1_MADDRS_H_UU: 6897 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6898 cpu_gpr_d[r2], n, MODE_UU); 6899 break; 6900 default: 6901 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6902 } 6903 } 6904 6905 static void decode_rrr1_maddq_h(DisasContext *ctx) 6906 { 6907 uint32_t op2; 6908 uint32_t r1, r2, r3, r4, n; 6909 TCGv temp, temp2; 6910 6911 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 6912 r1 = MASK_OP_RRR1_S1(ctx->opcode); 6913 r2 = MASK_OP_RRR1_S2(ctx->opcode); 6914 r3 = MASK_OP_RRR1_S3(ctx->opcode); 6915 r4 = MASK_OP_RRR1_D(ctx->opcode); 6916 n = MASK_OP_RRR1_N(ctx->opcode); 6917 6918 temp = tcg_temp_new(); 6919 temp2 = tcg_temp_new(); 6920 6921 switch (op2) { 6922 case OPC2_32_RRR1_MADD_Q_32: 6923 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6924 cpu_gpr_d[r2], n, 32); 6925 break; 6926 case OPC2_32_RRR1_MADD_Q_64: 6927 CHECK_REG_PAIR(r4); 6928 CHECK_REG_PAIR(r3); 6929 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6930 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6931 n); 6932 break; 6933 case OPC2_32_RRR1_MADD_Q_32_L: 6934 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6935 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6936 temp, n, 16); 6937 break; 6938 case OPC2_32_RRR1_MADD_Q_64_L: 6939 CHECK_REG_PAIR(r4); 6940 CHECK_REG_PAIR(r3); 6941 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6942 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6943 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 6944 n); 6945 break; 6946 case OPC2_32_RRR1_MADD_Q_32_U: 6947 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6948 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6949 temp, n, 16); 6950 break; 6951 case OPC2_32_RRR1_MADD_Q_64_U: 6952 CHECK_REG_PAIR(r4); 6953 CHECK_REG_PAIR(r3); 6954 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6955 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6956 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 6957 n); 6958 break; 6959 case OPC2_32_RRR1_MADD_Q_32_LL: 6960 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6961 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6962 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 6963 break; 6964 case OPC2_32_RRR1_MADD_Q_64_LL: 6965 CHECK_REG_PAIR(r4); 6966 CHECK_REG_PAIR(r3); 6967 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6968 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6969 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6970 cpu_gpr_d[r3+1], temp, temp2, n); 6971 break; 6972 case OPC2_32_RRR1_MADD_Q_32_UU: 6973 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6974 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6975 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 6976 break; 6977 case OPC2_32_RRR1_MADD_Q_64_UU: 6978 CHECK_REG_PAIR(r4); 6979 CHECK_REG_PAIR(r3); 6980 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6981 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6982 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6983 cpu_gpr_d[r3+1], temp, temp2, n); 6984 break; 6985 case OPC2_32_RRR1_MADDS_Q_32: 6986 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6987 cpu_gpr_d[r2], n, 32); 6988 break; 6989 case OPC2_32_RRR1_MADDS_Q_64: 6990 CHECK_REG_PAIR(r4); 6991 CHECK_REG_PAIR(r3); 6992 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 6993 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6994 n); 6995 break; 6996 case OPC2_32_RRR1_MADDS_Q_32_L: 6997 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6998 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 6999 temp, n, 16); 7000 break; 7001 case OPC2_32_RRR1_MADDS_Q_64_L: 7002 CHECK_REG_PAIR(r4); 7003 CHECK_REG_PAIR(r3); 7004 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7005 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7006 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7007 n); 7008 break; 7009 case OPC2_32_RRR1_MADDS_Q_32_U: 7010 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7011 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7012 temp, n, 16); 7013 break; 7014 case OPC2_32_RRR1_MADDS_Q_64_U: 7015 CHECK_REG_PAIR(r4); 7016 CHECK_REG_PAIR(r3); 7017 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7018 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7019 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7020 n); 7021 break; 7022 case OPC2_32_RRR1_MADDS_Q_32_LL: 7023 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7024 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7025 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7026 break; 7027 case OPC2_32_RRR1_MADDS_Q_64_LL: 7028 CHECK_REG_PAIR(r4); 7029 CHECK_REG_PAIR(r3); 7030 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7031 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7032 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7033 cpu_gpr_d[r3+1], temp, temp2, n); 7034 break; 7035 case OPC2_32_RRR1_MADDS_Q_32_UU: 7036 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7037 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7038 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7039 break; 7040 case OPC2_32_RRR1_MADDS_Q_64_UU: 7041 CHECK_REG_PAIR(r4); 7042 CHECK_REG_PAIR(r3); 7043 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7044 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7045 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7046 cpu_gpr_d[r3+1], temp, temp2, n); 7047 break; 7048 case OPC2_32_RRR1_MADDR_H_64_UL: 7049 CHECK_REG_PAIR(r3); 7050 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7051 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7052 break; 7053 case OPC2_32_RRR1_MADDRS_H_64_UL: 7054 CHECK_REG_PAIR(r3); 7055 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7056 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7057 break; 7058 case OPC2_32_RRR1_MADDR_Q_32_LL: 7059 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7060 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7061 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7062 break; 7063 case OPC2_32_RRR1_MADDR_Q_32_UU: 7064 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7065 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7066 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7067 break; 7068 case OPC2_32_RRR1_MADDRS_Q_32_LL: 7069 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7070 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7071 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7072 break; 7073 case OPC2_32_RRR1_MADDRS_Q_32_UU: 7074 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7075 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7076 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7077 break; 7078 default: 7079 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7080 } 7081 } 7082 7083 static void decode_rrr1_maddsu_h(DisasContext *ctx) 7084 { 7085 uint32_t op2; 7086 uint32_t r1, r2, r3, r4, n; 7087 7088 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7089 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7090 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7091 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7092 r4 = MASK_OP_RRR1_D(ctx->opcode); 7093 n = MASK_OP_RRR1_N(ctx->opcode); 7094 7095 switch (op2) { 7096 case OPC2_32_RRR1_MADDSU_H_32_LL: 7097 CHECK_REG_PAIR(r4); 7098 CHECK_REG_PAIR(r3); 7099 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7100 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7101 break; 7102 case OPC2_32_RRR1_MADDSU_H_32_LU: 7103 CHECK_REG_PAIR(r4); 7104 CHECK_REG_PAIR(r3); 7105 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7106 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7107 break; 7108 case OPC2_32_RRR1_MADDSU_H_32_UL: 7109 CHECK_REG_PAIR(r4); 7110 CHECK_REG_PAIR(r3); 7111 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7112 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7113 break; 7114 case OPC2_32_RRR1_MADDSU_H_32_UU: 7115 CHECK_REG_PAIR(r4); 7116 CHECK_REG_PAIR(r3); 7117 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7118 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7119 break; 7120 case OPC2_32_RRR1_MADDSUS_H_32_LL: 7121 CHECK_REG_PAIR(r4); 7122 CHECK_REG_PAIR(r3); 7123 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7124 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7125 n, MODE_LL); 7126 break; 7127 case OPC2_32_RRR1_MADDSUS_H_32_LU: 7128 CHECK_REG_PAIR(r4); 7129 CHECK_REG_PAIR(r3); 7130 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7131 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7132 n, MODE_LU); 7133 break; 7134 case OPC2_32_RRR1_MADDSUS_H_32_UL: 7135 CHECK_REG_PAIR(r4); 7136 CHECK_REG_PAIR(r3); 7137 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7138 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7139 n, MODE_UL); 7140 break; 7141 case OPC2_32_RRR1_MADDSUS_H_32_UU: 7142 CHECK_REG_PAIR(r4); 7143 CHECK_REG_PAIR(r3); 7144 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7145 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7146 n, MODE_UU); 7147 break; 7148 case OPC2_32_RRR1_MADDSUM_H_64_LL: 7149 CHECK_REG_PAIR(r4); 7150 CHECK_REG_PAIR(r3); 7151 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7152 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7153 n, MODE_LL); 7154 break; 7155 case OPC2_32_RRR1_MADDSUM_H_64_LU: 7156 CHECK_REG_PAIR(r4); 7157 CHECK_REG_PAIR(r3); 7158 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7159 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7160 n, MODE_LU); 7161 break; 7162 case OPC2_32_RRR1_MADDSUM_H_64_UL: 7163 CHECK_REG_PAIR(r4); 7164 CHECK_REG_PAIR(r3); 7165 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7166 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7167 n, MODE_UL); 7168 break; 7169 case OPC2_32_RRR1_MADDSUM_H_64_UU: 7170 CHECK_REG_PAIR(r4); 7171 CHECK_REG_PAIR(r3); 7172 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7173 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7174 n, MODE_UU); 7175 break; 7176 case OPC2_32_RRR1_MADDSUMS_H_64_LL: 7177 CHECK_REG_PAIR(r4); 7178 CHECK_REG_PAIR(r3); 7179 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7180 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7181 n, MODE_LL); 7182 break; 7183 case OPC2_32_RRR1_MADDSUMS_H_64_LU: 7184 CHECK_REG_PAIR(r4); 7185 CHECK_REG_PAIR(r3); 7186 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7187 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7188 n, MODE_LU); 7189 break; 7190 case OPC2_32_RRR1_MADDSUMS_H_64_UL: 7191 CHECK_REG_PAIR(r4); 7192 CHECK_REG_PAIR(r3); 7193 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7194 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7195 n, MODE_UL); 7196 break; 7197 case OPC2_32_RRR1_MADDSUMS_H_64_UU: 7198 CHECK_REG_PAIR(r4); 7199 CHECK_REG_PAIR(r3); 7200 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7201 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7202 n, MODE_UU); 7203 break; 7204 case OPC2_32_RRR1_MADDSUR_H_16_LL: 7205 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7206 cpu_gpr_d[r2], n, MODE_LL); 7207 break; 7208 case OPC2_32_RRR1_MADDSUR_H_16_LU: 7209 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7210 cpu_gpr_d[r2], n, MODE_LU); 7211 break; 7212 case OPC2_32_RRR1_MADDSUR_H_16_UL: 7213 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7214 cpu_gpr_d[r2], n, MODE_UL); 7215 break; 7216 case OPC2_32_RRR1_MADDSUR_H_16_UU: 7217 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7218 cpu_gpr_d[r2], n, MODE_UU); 7219 break; 7220 case OPC2_32_RRR1_MADDSURS_H_16_LL: 7221 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7222 cpu_gpr_d[r2], n, MODE_LL); 7223 break; 7224 case OPC2_32_RRR1_MADDSURS_H_16_LU: 7225 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7226 cpu_gpr_d[r2], n, MODE_LU); 7227 break; 7228 case OPC2_32_RRR1_MADDSURS_H_16_UL: 7229 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7230 cpu_gpr_d[r2], n, MODE_UL); 7231 break; 7232 case OPC2_32_RRR1_MADDSURS_H_16_UU: 7233 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7234 cpu_gpr_d[r2], n, MODE_UU); 7235 break; 7236 default: 7237 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7238 } 7239 } 7240 7241 static void decode_rrr1_msub(DisasContext *ctx) 7242 { 7243 uint32_t op2; 7244 uint32_t r1, r2, r3, r4, n; 7245 7246 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7247 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7248 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7249 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7250 r4 = MASK_OP_RRR1_D(ctx->opcode); 7251 n = MASK_OP_RRR1_N(ctx->opcode); 7252 7253 switch (op2) { 7254 case OPC2_32_RRR1_MSUB_H_LL: 7255 CHECK_REG_PAIR(r4); 7256 CHECK_REG_PAIR(r3); 7257 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7258 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7259 break; 7260 case OPC2_32_RRR1_MSUB_H_LU: 7261 CHECK_REG_PAIR(r4); 7262 CHECK_REG_PAIR(r3); 7263 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7264 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7265 break; 7266 case OPC2_32_RRR1_MSUB_H_UL: 7267 CHECK_REG_PAIR(r4); 7268 CHECK_REG_PAIR(r3); 7269 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7270 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7271 break; 7272 case OPC2_32_RRR1_MSUB_H_UU: 7273 CHECK_REG_PAIR(r4); 7274 CHECK_REG_PAIR(r3); 7275 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7276 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7277 break; 7278 case OPC2_32_RRR1_MSUBS_H_LL: 7279 CHECK_REG_PAIR(r4); 7280 CHECK_REG_PAIR(r3); 7281 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7282 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7283 break; 7284 case OPC2_32_RRR1_MSUBS_H_LU: 7285 CHECK_REG_PAIR(r4); 7286 CHECK_REG_PAIR(r3); 7287 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7288 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7289 break; 7290 case OPC2_32_RRR1_MSUBS_H_UL: 7291 CHECK_REG_PAIR(r4); 7292 CHECK_REG_PAIR(r3); 7293 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7294 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7295 break; 7296 case OPC2_32_RRR1_MSUBS_H_UU: 7297 CHECK_REG_PAIR(r4); 7298 CHECK_REG_PAIR(r3); 7299 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7300 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7301 break; 7302 case OPC2_32_RRR1_MSUBM_H_LL: 7303 CHECK_REG_PAIR(r4); 7304 CHECK_REG_PAIR(r3); 7305 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7306 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7307 break; 7308 case OPC2_32_RRR1_MSUBM_H_LU: 7309 CHECK_REG_PAIR(r4); 7310 CHECK_REG_PAIR(r3); 7311 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7312 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7313 break; 7314 case OPC2_32_RRR1_MSUBM_H_UL: 7315 CHECK_REG_PAIR(r4); 7316 CHECK_REG_PAIR(r3); 7317 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7318 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7319 break; 7320 case OPC2_32_RRR1_MSUBM_H_UU: 7321 CHECK_REG_PAIR(r4); 7322 CHECK_REG_PAIR(r3); 7323 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7324 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7325 break; 7326 case OPC2_32_RRR1_MSUBMS_H_LL: 7327 CHECK_REG_PAIR(r4); 7328 CHECK_REG_PAIR(r3); 7329 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7330 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7331 break; 7332 case OPC2_32_RRR1_MSUBMS_H_LU: 7333 CHECK_REG_PAIR(r4); 7334 CHECK_REG_PAIR(r3); 7335 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7336 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7337 break; 7338 case OPC2_32_RRR1_MSUBMS_H_UL: 7339 CHECK_REG_PAIR(r4); 7340 CHECK_REG_PAIR(r3); 7341 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7342 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7343 break; 7344 case OPC2_32_RRR1_MSUBMS_H_UU: 7345 CHECK_REG_PAIR(r4); 7346 CHECK_REG_PAIR(r3); 7347 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7348 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7349 break; 7350 case OPC2_32_RRR1_MSUBR_H_LL: 7351 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7352 cpu_gpr_d[r2], n, MODE_LL); 7353 break; 7354 case OPC2_32_RRR1_MSUBR_H_LU: 7355 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7356 cpu_gpr_d[r2], n, MODE_LU); 7357 break; 7358 case OPC2_32_RRR1_MSUBR_H_UL: 7359 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7360 cpu_gpr_d[r2], n, MODE_UL); 7361 break; 7362 case OPC2_32_RRR1_MSUBR_H_UU: 7363 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7364 cpu_gpr_d[r2], n, MODE_UU); 7365 break; 7366 case OPC2_32_RRR1_MSUBRS_H_LL: 7367 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7368 cpu_gpr_d[r2], n, MODE_LL); 7369 break; 7370 case OPC2_32_RRR1_MSUBRS_H_LU: 7371 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7372 cpu_gpr_d[r2], n, MODE_LU); 7373 break; 7374 case OPC2_32_RRR1_MSUBRS_H_UL: 7375 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7376 cpu_gpr_d[r2], n, MODE_UL); 7377 break; 7378 case OPC2_32_RRR1_MSUBRS_H_UU: 7379 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7380 cpu_gpr_d[r2], n, MODE_UU); 7381 break; 7382 default: 7383 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7384 } 7385 } 7386 7387 static void decode_rrr1_msubq_h(DisasContext *ctx) 7388 { 7389 uint32_t op2; 7390 uint32_t r1, r2, r3, r4, n; 7391 TCGv temp, temp2; 7392 7393 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7394 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7395 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7396 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7397 r4 = MASK_OP_RRR1_D(ctx->opcode); 7398 n = MASK_OP_RRR1_N(ctx->opcode); 7399 7400 temp = tcg_temp_new(); 7401 temp2 = tcg_temp_new(); 7402 7403 switch (op2) { 7404 case OPC2_32_RRR1_MSUB_Q_32: 7405 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7406 cpu_gpr_d[r2], n, 32); 7407 break; 7408 case OPC2_32_RRR1_MSUB_Q_64: 7409 CHECK_REG_PAIR(r4); 7410 CHECK_REG_PAIR(r3); 7411 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7412 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7413 n); 7414 break; 7415 case OPC2_32_RRR1_MSUB_Q_32_L: 7416 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7417 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7418 temp, n, 16); 7419 break; 7420 case OPC2_32_RRR1_MSUB_Q_64_L: 7421 CHECK_REG_PAIR(r4); 7422 CHECK_REG_PAIR(r3); 7423 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7424 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7425 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7426 n); 7427 break; 7428 case OPC2_32_RRR1_MSUB_Q_32_U: 7429 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7430 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7431 temp, n, 16); 7432 break; 7433 case OPC2_32_RRR1_MSUB_Q_64_U: 7434 CHECK_REG_PAIR(r4); 7435 CHECK_REG_PAIR(r3); 7436 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7437 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7438 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7439 n); 7440 break; 7441 case OPC2_32_RRR1_MSUB_Q_32_LL: 7442 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7443 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7444 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7445 break; 7446 case OPC2_32_RRR1_MSUB_Q_64_LL: 7447 CHECK_REG_PAIR(r4); 7448 CHECK_REG_PAIR(r3); 7449 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7450 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7451 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7452 cpu_gpr_d[r3+1], temp, temp2, n); 7453 break; 7454 case OPC2_32_RRR1_MSUB_Q_32_UU: 7455 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7456 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7457 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7458 break; 7459 case OPC2_32_RRR1_MSUB_Q_64_UU: 7460 CHECK_REG_PAIR(r4); 7461 CHECK_REG_PAIR(r3); 7462 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7463 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7464 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7465 cpu_gpr_d[r3+1], temp, temp2, n); 7466 break; 7467 case OPC2_32_RRR1_MSUBS_Q_32: 7468 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7469 cpu_gpr_d[r2], n, 32); 7470 break; 7471 case OPC2_32_RRR1_MSUBS_Q_64: 7472 CHECK_REG_PAIR(r4); 7473 CHECK_REG_PAIR(r3); 7474 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7475 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7476 n); 7477 break; 7478 case OPC2_32_RRR1_MSUBS_Q_32_L: 7479 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7480 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7481 temp, n, 16); 7482 break; 7483 case OPC2_32_RRR1_MSUBS_Q_64_L: 7484 CHECK_REG_PAIR(r4); 7485 CHECK_REG_PAIR(r3); 7486 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7487 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7488 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7489 n); 7490 break; 7491 case OPC2_32_RRR1_MSUBS_Q_32_U: 7492 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7493 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7494 temp, n, 16); 7495 break; 7496 case OPC2_32_RRR1_MSUBS_Q_64_U: 7497 CHECK_REG_PAIR(r4); 7498 CHECK_REG_PAIR(r3); 7499 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7500 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7501 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7502 n); 7503 break; 7504 case OPC2_32_RRR1_MSUBS_Q_32_LL: 7505 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7506 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7507 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7508 break; 7509 case OPC2_32_RRR1_MSUBS_Q_64_LL: 7510 CHECK_REG_PAIR(r4); 7511 CHECK_REG_PAIR(r3); 7512 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7513 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7514 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7515 cpu_gpr_d[r3+1], temp, temp2, n); 7516 break; 7517 case OPC2_32_RRR1_MSUBS_Q_32_UU: 7518 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7519 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7520 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7521 break; 7522 case OPC2_32_RRR1_MSUBS_Q_64_UU: 7523 CHECK_REG_PAIR(r4); 7524 CHECK_REG_PAIR(r3); 7525 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7526 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7527 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7528 cpu_gpr_d[r3+1], temp, temp2, n); 7529 break; 7530 case OPC2_32_RRR1_MSUBR_H_64_UL: 7531 CHECK_REG_PAIR(r3); 7532 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7533 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7534 break; 7535 case OPC2_32_RRR1_MSUBRS_H_64_UL: 7536 CHECK_REG_PAIR(r3); 7537 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7538 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7539 break; 7540 case OPC2_32_RRR1_MSUBR_Q_32_LL: 7541 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7542 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7543 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7544 break; 7545 case OPC2_32_RRR1_MSUBR_Q_32_UU: 7546 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7547 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7548 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7549 break; 7550 case OPC2_32_RRR1_MSUBRS_Q_32_LL: 7551 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7552 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7553 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7554 break; 7555 case OPC2_32_RRR1_MSUBRS_Q_32_UU: 7556 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7557 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7558 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7559 break; 7560 default: 7561 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7562 } 7563 } 7564 7565 static void decode_rrr1_msubad_h(DisasContext *ctx) 7566 { 7567 uint32_t op2; 7568 uint32_t r1, r2, r3, r4, n; 7569 7570 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7571 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7572 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7573 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7574 r4 = MASK_OP_RRR1_D(ctx->opcode); 7575 n = MASK_OP_RRR1_N(ctx->opcode); 7576 7577 switch (op2) { 7578 case OPC2_32_RRR1_MSUBAD_H_32_LL: 7579 CHECK_REG_PAIR(r4); 7580 CHECK_REG_PAIR(r3); 7581 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7582 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7583 break; 7584 case OPC2_32_RRR1_MSUBAD_H_32_LU: 7585 CHECK_REG_PAIR(r4); 7586 CHECK_REG_PAIR(r3); 7587 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7588 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7589 break; 7590 case OPC2_32_RRR1_MSUBAD_H_32_UL: 7591 CHECK_REG_PAIR(r4); 7592 CHECK_REG_PAIR(r3); 7593 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7594 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7595 break; 7596 case OPC2_32_RRR1_MSUBAD_H_32_UU: 7597 CHECK_REG_PAIR(r4); 7598 CHECK_REG_PAIR(r3); 7599 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7600 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7601 break; 7602 case OPC2_32_RRR1_MSUBADS_H_32_LL: 7603 CHECK_REG_PAIR(r4); 7604 CHECK_REG_PAIR(r3); 7605 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7606 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7607 n, MODE_LL); 7608 break; 7609 case OPC2_32_RRR1_MSUBADS_H_32_LU: 7610 CHECK_REG_PAIR(r4); 7611 CHECK_REG_PAIR(r3); 7612 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7613 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7614 n, MODE_LU); 7615 break; 7616 case OPC2_32_RRR1_MSUBADS_H_32_UL: 7617 CHECK_REG_PAIR(r4); 7618 CHECK_REG_PAIR(r3); 7619 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7620 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7621 n, MODE_UL); 7622 break; 7623 case OPC2_32_RRR1_MSUBADS_H_32_UU: 7624 CHECK_REG_PAIR(r4); 7625 CHECK_REG_PAIR(r3); 7626 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7627 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7628 n, MODE_UU); 7629 break; 7630 case OPC2_32_RRR1_MSUBADM_H_64_LL: 7631 CHECK_REG_PAIR(r4); 7632 CHECK_REG_PAIR(r3); 7633 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7634 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7635 n, MODE_LL); 7636 break; 7637 case OPC2_32_RRR1_MSUBADM_H_64_LU: 7638 CHECK_REG_PAIR(r4); 7639 CHECK_REG_PAIR(r3); 7640 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7641 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7642 n, MODE_LU); 7643 break; 7644 case OPC2_32_RRR1_MSUBADM_H_64_UL: 7645 CHECK_REG_PAIR(r4); 7646 CHECK_REG_PAIR(r3); 7647 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7648 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7649 n, MODE_UL); 7650 break; 7651 case OPC2_32_RRR1_MSUBADM_H_64_UU: 7652 CHECK_REG_PAIR(r4); 7653 CHECK_REG_PAIR(r3); 7654 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7655 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7656 n, MODE_UU); 7657 break; 7658 case OPC2_32_RRR1_MSUBADMS_H_64_LL: 7659 CHECK_REG_PAIR(r4); 7660 CHECK_REG_PAIR(r3); 7661 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7662 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7663 n, MODE_LL); 7664 break; 7665 case OPC2_32_RRR1_MSUBADMS_H_64_LU: 7666 CHECK_REG_PAIR(r4); 7667 CHECK_REG_PAIR(r3); 7668 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7669 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7670 n, MODE_LU); 7671 break; 7672 case OPC2_32_RRR1_MSUBADMS_H_64_UL: 7673 CHECK_REG_PAIR(r4); 7674 CHECK_REG_PAIR(r3); 7675 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7676 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7677 n, MODE_UL); 7678 break; 7679 case OPC2_32_RRR1_MSUBADMS_H_64_UU: 7680 CHECK_REG_PAIR(r4); 7681 CHECK_REG_PAIR(r3); 7682 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7683 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7684 n, MODE_UU); 7685 break; 7686 case OPC2_32_RRR1_MSUBADR_H_16_LL: 7687 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7688 cpu_gpr_d[r2], n, MODE_LL); 7689 break; 7690 case OPC2_32_RRR1_MSUBADR_H_16_LU: 7691 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7692 cpu_gpr_d[r2], n, MODE_LU); 7693 break; 7694 case OPC2_32_RRR1_MSUBADR_H_16_UL: 7695 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7696 cpu_gpr_d[r2], n, MODE_UL); 7697 break; 7698 case OPC2_32_RRR1_MSUBADR_H_16_UU: 7699 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7700 cpu_gpr_d[r2], n, MODE_UU); 7701 break; 7702 case OPC2_32_RRR1_MSUBADRS_H_16_LL: 7703 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7704 cpu_gpr_d[r2], n, MODE_LL); 7705 break; 7706 case OPC2_32_RRR1_MSUBADRS_H_16_LU: 7707 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7708 cpu_gpr_d[r2], n, MODE_LU); 7709 break; 7710 case OPC2_32_RRR1_MSUBADRS_H_16_UL: 7711 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7712 cpu_gpr_d[r2], n, MODE_UL); 7713 break; 7714 case OPC2_32_RRR1_MSUBADRS_H_16_UU: 7715 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7716 cpu_gpr_d[r2], n, MODE_UU); 7717 break; 7718 default: 7719 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7720 } 7721 } 7722 7723 /* RRRR format */ 7724 static void decode_rrrr_extract_insert(DisasContext *ctx) 7725 { 7726 uint32_t op2; 7727 int r1, r2, r3, r4; 7728 TCGv tmp_width, tmp_pos; 7729 7730 r1 = MASK_OP_RRRR_S1(ctx->opcode); 7731 r2 = MASK_OP_RRRR_S2(ctx->opcode); 7732 r3 = MASK_OP_RRRR_S3(ctx->opcode); 7733 r4 = MASK_OP_RRRR_D(ctx->opcode); 7734 op2 = MASK_OP_RRRR_OP2(ctx->opcode); 7735 7736 tmp_pos = tcg_temp_new(); 7737 tmp_width = tcg_temp_new(); 7738 7739 switch (op2) { 7740 case OPC2_32_RRRR_DEXTR: 7741 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7742 if (r1 == r2) { 7743 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7744 } else { 7745 TCGv msw = tcg_temp_new(); 7746 TCGv zero = tcg_constant_tl(0); 7747 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); 7748 tcg_gen_subfi_tl(msw, 32, tmp_pos); 7749 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw); 7750 /* 7751 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined 7752 * behaviour. So check that case here and set the low bits to zero 7753 * which effectivly returns cpu_gpr_d[r1] 7754 */ 7755 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); 7756 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); 7757 } 7758 break; 7759 case OPC2_32_RRRR_EXTR: 7760 case OPC2_32_RRRR_EXTR_U: 7761 CHECK_REG_PAIR(r3); 7762 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7763 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7764 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); 7765 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 7766 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 7767 tcg_gen_subfi_tl(tmp_width, 32, tmp_width); 7768 if (op2 == OPC2_32_RRRR_EXTR) { 7769 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7770 } else { 7771 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 7772 } 7773 break; 7774 case OPC2_32_RRRR_INSERT: 7775 CHECK_REG_PAIR(r3); 7776 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 7777 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 7778 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, 7779 tmp_pos); 7780 break; 7781 default: 7782 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7783 } 7784 } 7785 7786 /* RRRW format */ 7787 static void decode_rrrw_extract_insert(DisasContext *ctx) 7788 { 7789 uint32_t op2; 7790 int r1, r2, r3, r4; 7791 int32_t width; 7792 7793 TCGv temp, temp2; 7794 7795 op2 = MASK_OP_RRRW_OP2(ctx->opcode); 7796 r1 = MASK_OP_RRRW_S1(ctx->opcode); 7797 r2 = MASK_OP_RRRW_S2(ctx->opcode); 7798 r3 = MASK_OP_RRRW_S3(ctx->opcode); 7799 r4 = MASK_OP_RRRW_D(ctx->opcode); 7800 width = MASK_OP_RRRW_WIDTH(ctx->opcode); 7801 7802 temp = tcg_temp_new(); 7803 7804 switch (op2) { 7805 case OPC2_32_RRRW_EXTR: 7806 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7807 tcg_gen_addi_tl(temp, temp, width); 7808 tcg_gen_subfi_tl(temp, 32, temp); 7809 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7810 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); 7811 break; 7812 case OPC2_32_RRRW_EXTR_U: 7813 if (width == 0) { 7814 tcg_gen_movi_tl(cpu_gpr_d[r4], 0); 7815 } else { 7816 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7817 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 7818 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); 7819 } 7820 break; 7821 case OPC2_32_RRRW_IMASK: 7822 temp2 = tcg_temp_new(); 7823 7824 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 7825 tcg_gen_movi_tl(temp2, (1 << width) - 1); 7826 tcg_gen_shl_tl(temp2, temp2, temp); 7827 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); 7828 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); 7829 break; 7830 case OPC2_32_RRRW_INSERT: 7831 temp2 = tcg_temp_new(); 7832 7833 tcg_gen_movi_tl(temp, width); 7834 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); 7835 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); 7836 break; 7837 default: 7838 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7839 } 7840 } 7841 7842 /* SYS Format*/ 7843 static void decode_sys_interrupts(DisasContext *ctx) 7844 { 7845 uint32_t op2; 7846 uint32_t r1; 7847 TCGLabel *l1; 7848 TCGv tmp; 7849 7850 op2 = MASK_OP_SYS_OP2(ctx->opcode); 7851 r1 = MASK_OP_SYS_S1D(ctx->opcode); 7852 7853 switch (op2) { 7854 case OPC2_32_SYS_DEBUG: 7855 /* raise EXCP_DEBUG */ 7856 break; 7857 case OPC2_32_SYS_DISABLE: 7858 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); 7859 break; 7860 case OPC2_32_SYS_DSYNC: 7861 break; 7862 case OPC2_32_SYS_ENABLE: 7863 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3); 7864 break; 7865 case OPC2_32_SYS_ISYNC: 7866 break; 7867 case OPC2_32_SYS_NOP: 7868 break; 7869 case OPC2_32_SYS_RET: 7870 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 7871 break; 7872 case OPC2_32_SYS_FRET: 7873 gen_fret(ctx); 7874 break; 7875 case OPC2_32_SYS_RFE: 7876 gen_helper_rfe(cpu_env); 7877 tcg_gen_exit_tb(NULL, 0); 7878 ctx->base.is_jmp = DISAS_NORETURN; 7879 break; 7880 case OPC2_32_SYS_RFM: 7881 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 7882 tmp = tcg_temp_new(); 7883 l1 = gen_new_label(); 7884 7885 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR)); 7886 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); 7887 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); 7888 gen_helper_rfm(cpu_env); 7889 gen_set_label(l1); 7890 tcg_gen_exit_tb(NULL, 0); 7891 ctx->base.is_jmp = DISAS_NORETURN; 7892 } else { 7893 /* generate privilege trap */ 7894 } 7895 break; 7896 case OPC2_32_SYS_RSLCX: 7897 gen_helper_rslcx(cpu_env); 7898 break; 7899 case OPC2_32_SYS_SVLCX: 7900 gen_helper_svlcx(cpu_env); 7901 break; 7902 case OPC2_32_SYS_RESTORE: 7903 if (has_feature(ctx, TRICORE_FEATURE_16)) { 7904 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM || 7905 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) { 7906 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); 7907 } /* else raise privilege trap */ 7908 } else { 7909 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7910 } 7911 break; 7912 case OPC2_32_SYS_TRAPSV: 7913 l1 = gen_new_label(); 7914 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); 7915 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); 7916 gen_set_label(l1); 7917 break; 7918 case OPC2_32_SYS_TRAPV: 7919 l1 = gen_new_label(); 7920 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); 7921 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); 7922 gen_set_label(l1); 7923 break; 7924 default: 7925 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7926 } 7927 } 7928 7929 static void decode_32Bit_opc(DisasContext *ctx) 7930 { 7931 int op1; 7932 int32_t r1, r2, r3; 7933 int32_t address, const16; 7934 int8_t b, const4; 7935 int32_t bpos; 7936 TCGv temp, temp2, temp3; 7937 7938 op1 = MASK_OP_MAJOR(ctx->opcode); 7939 7940 /* handle JNZ.T opcode only being 7 bit long */ 7941 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { 7942 op1 = OPCM_32_BRN_JTT; 7943 } 7944 7945 switch (op1) { 7946 /* ABS-format */ 7947 case OPCM_32_ABS_LDW: 7948 decode_abs_ldw(ctx); 7949 break; 7950 case OPCM_32_ABS_LDB: 7951 decode_abs_ldb(ctx); 7952 break; 7953 case OPCM_32_ABS_LDMST_SWAP: 7954 decode_abs_ldst_swap(ctx); 7955 break; 7956 case OPCM_32_ABS_LDST_CONTEXT: 7957 decode_abs_ldst_context(ctx); 7958 break; 7959 case OPCM_32_ABS_STORE: 7960 decode_abs_store(ctx); 7961 break; 7962 case OPCM_32_ABS_STOREB_H: 7963 decode_abs_storeb_h(ctx); 7964 break; 7965 case OPC1_32_ABS_STOREQ: 7966 address = MASK_OP_ABS_OFF18(ctx->opcode); 7967 r1 = MASK_OP_ABS_S1D(ctx->opcode); 7968 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 7969 temp2 = tcg_temp_new(); 7970 7971 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); 7972 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); 7973 break; 7974 case OPC1_32_ABS_LD_Q: 7975 address = MASK_OP_ABS_OFF18(ctx->opcode); 7976 r1 = MASK_OP_ABS_S1D(ctx->opcode); 7977 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 7978 7979 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 7980 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 7981 break; 7982 case OPC1_32_ABS_LEA: 7983 address = MASK_OP_ABS_OFF18(ctx->opcode); 7984 r1 = MASK_OP_ABS_S1D(ctx->opcode); 7985 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); 7986 break; 7987 /* ABSB-format */ 7988 case OPC1_32_ABSB_ST_T: 7989 address = MASK_OP_ABS_OFF18(ctx->opcode); 7990 b = MASK_OP_ABSB_B(ctx->opcode); 7991 bpos = MASK_OP_ABSB_BPOS(ctx->opcode); 7992 7993 temp = tcg_constant_i32(EA_ABS_FORMAT(address)); 7994 temp2 = tcg_temp_new(); 7995 7996 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); 7997 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); 7998 tcg_gen_ori_tl(temp2, temp2, (b << bpos)); 7999 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); 8000 break; 8001 /* B-format */ 8002 case OPC1_32_B_CALL: 8003 case OPC1_32_B_CALLA: 8004 case OPC1_32_B_FCALL: 8005 case OPC1_32_B_FCALLA: 8006 case OPC1_32_B_J: 8007 case OPC1_32_B_JA: 8008 case OPC1_32_B_JL: 8009 case OPC1_32_B_JLA: 8010 address = MASK_OP_B_DISP24_SEXT(ctx->opcode); 8011 gen_compute_branch(ctx, op1, 0, 0, 0, address); 8012 break; 8013 /* Bit-format */ 8014 case OPCM_32_BIT_ANDACC: 8015 decode_bit_andacc(ctx); 8016 break; 8017 case OPCM_32_BIT_LOGICAL_T1: 8018 decode_bit_logical_t(ctx); 8019 break; 8020 case OPCM_32_BIT_INSERT: 8021 decode_bit_insert(ctx); 8022 break; 8023 case OPCM_32_BIT_LOGICAL_T2: 8024 decode_bit_logical_t2(ctx); 8025 break; 8026 case OPCM_32_BIT_ORAND: 8027 decode_bit_orand(ctx); 8028 break; 8029 case OPCM_32_BIT_SH_LOGIC1: 8030 decode_bit_sh_logic1(ctx); 8031 break; 8032 case OPCM_32_BIT_SH_LOGIC2: 8033 decode_bit_sh_logic2(ctx); 8034 break; 8035 /* BO Format */ 8036 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: 8037 decode_bo_addrmode_post_pre_base(ctx); 8038 break; 8039 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: 8040 decode_bo_addrmode_bitreverse_circular(ctx); 8041 break; 8042 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: 8043 decode_bo_addrmode_ld_post_pre_base(ctx); 8044 break; 8045 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: 8046 decode_bo_addrmode_ld_bitreverse_circular(ctx); 8047 break; 8048 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: 8049 decode_bo_addrmode_stctx_post_pre_base(ctx); 8050 break; 8051 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: 8052 decode_bo_addrmode_ldmst_bitreverse_circular(ctx); 8053 break; 8054 /* BOL-format */ 8055 case OPC1_32_BOL_LD_A_LONGOFF: 8056 case OPC1_32_BOL_LD_W_LONGOFF: 8057 case OPC1_32_BOL_LEA_LONGOFF: 8058 case OPC1_32_BOL_ST_W_LONGOFF: 8059 case OPC1_32_BOL_ST_A_LONGOFF: 8060 case OPC1_32_BOL_LD_B_LONGOFF: 8061 case OPC1_32_BOL_LD_BU_LONGOFF: 8062 case OPC1_32_BOL_LD_H_LONGOFF: 8063 case OPC1_32_BOL_LD_HU_LONGOFF: 8064 case OPC1_32_BOL_ST_B_LONGOFF: 8065 case OPC1_32_BOL_ST_H_LONGOFF: 8066 decode_bol_opc(ctx, op1); 8067 break; 8068 /* BRC Format */ 8069 case OPCM_32_BRC_EQ_NEQ: 8070 case OPCM_32_BRC_GE: 8071 case OPCM_32_BRC_JLT: 8072 case OPCM_32_BRC_JNE: 8073 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); 8074 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); 8075 r1 = MASK_OP_BRC_S1(ctx->opcode); 8076 gen_compute_branch(ctx, op1, r1, 0, const4, address); 8077 break; 8078 /* BRN Format */ 8079 case OPCM_32_BRN_JTT: 8080 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); 8081 r1 = MASK_OP_BRN_S1(ctx->opcode); 8082 gen_compute_branch(ctx, op1, r1, 0, 0, address); 8083 break; 8084 /* BRR Format */ 8085 case OPCM_32_BRR_EQ_NEQ: 8086 case OPCM_32_BRR_ADDR_EQ_NEQ: 8087 case OPCM_32_BRR_GE: 8088 case OPCM_32_BRR_JLT: 8089 case OPCM_32_BRR_JNE: 8090 case OPCM_32_BRR_JNZ: 8091 case OPCM_32_BRR_LOOP: 8092 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); 8093 r2 = MASK_OP_BRR_S2(ctx->opcode); 8094 r1 = MASK_OP_BRR_S1(ctx->opcode); 8095 gen_compute_branch(ctx, op1, r1, r2, 0, address); 8096 break; 8097 /* RC Format */ 8098 case OPCM_32_RC_LOGICAL_SHIFT: 8099 decode_rc_logical_shift(ctx); 8100 break; 8101 case OPCM_32_RC_ACCUMULATOR: 8102 decode_rc_accumulator(ctx); 8103 break; 8104 case OPCM_32_RC_SERVICEROUTINE: 8105 decode_rc_serviceroutine(ctx); 8106 break; 8107 case OPCM_32_RC_MUL: 8108 decode_rc_mul(ctx); 8109 break; 8110 /* RCPW Format */ 8111 case OPCM_32_RCPW_MASK_INSERT: 8112 decode_rcpw_insert(ctx); 8113 break; 8114 /* RCRR Format */ 8115 case OPC1_32_RCRR_INSERT: 8116 r1 = MASK_OP_RCRR_S1(ctx->opcode); 8117 r2 = MASK_OP_RCRR_S3(ctx->opcode); 8118 r3 = MASK_OP_RCRR_D(ctx->opcode); 8119 const16 = MASK_OP_RCRR_CONST4(ctx->opcode); 8120 temp = tcg_constant_i32(const16); 8121 temp2 = tcg_temp_new(); /* width*/ 8122 temp3 = tcg_temp_new(); /* pos */ 8123 8124 CHECK_REG_PAIR(r3); 8125 8126 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f); 8127 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 8128 8129 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); 8130 break; 8131 /* RCRW Format */ 8132 case OPCM_32_RCRW_MASK_INSERT: 8133 decode_rcrw_insert(ctx); 8134 break; 8135 /* RCR Format */ 8136 case OPCM_32_RCR_COND_SELECT: 8137 decode_rcr_cond_select(ctx); 8138 break; 8139 case OPCM_32_RCR_MADD: 8140 decode_rcr_madd(ctx); 8141 break; 8142 case OPCM_32_RCR_MSUB: 8143 decode_rcr_msub(ctx); 8144 break; 8145 /* RLC Format */ 8146 case OPC1_32_RLC_ADDI: 8147 case OPC1_32_RLC_ADDIH: 8148 case OPC1_32_RLC_ADDIH_A: 8149 case OPC1_32_RLC_MFCR: 8150 case OPC1_32_RLC_MOV: 8151 case OPC1_32_RLC_MOV_64: 8152 case OPC1_32_RLC_MOV_U: 8153 case OPC1_32_RLC_MOV_H: 8154 case OPC1_32_RLC_MOVH_A: 8155 case OPC1_32_RLC_MTCR: 8156 decode_rlc_opc(ctx, op1); 8157 break; 8158 /* RR Format */ 8159 case OPCM_32_RR_ACCUMULATOR: 8160 decode_rr_accumulator(ctx); 8161 break; 8162 case OPCM_32_RR_LOGICAL_SHIFT: 8163 decode_rr_logical_shift(ctx); 8164 break; 8165 case OPCM_32_RR_ADDRESS: 8166 decode_rr_address(ctx); 8167 break; 8168 case OPCM_32_RR_IDIRECT: 8169 decode_rr_idirect(ctx); 8170 break; 8171 case OPCM_32_RR_DIVIDE: 8172 decode_rr_divide(ctx); 8173 break; 8174 /* RR1 Format */ 8175 case OPCM_32_RR1_MUL: 8176 decode_rr1_mul(ctx); 8177 break; 8178 case OPCM_32_RR1_MULQ: 8179 decode_rr1_mulq(ctx); 8180 break; 8181 /* RR2 format */ 8182 case OPCM_32_RR2_MUL: 8183 decode_rr2_mul(ctx); 8184 break; 8185 /* RRPW format */ 8186 case OPCM_32_RRPW_EXTRACT_INSERT: 8187 decode_rrpw_extract_insert(ctx); 8188 break; 8189 case OPC1_32_RRPW_DEXTR: 8190 r1 = MASK_OP_RRPW_S1(ctx->opcode); 8191 r2 = MASK_OP_RRPW_S2(ctx->opcode); 8192 r3 = MASK_OP_RRPW_D(ctx->opcode); 8193 const16 = MASK_OP_RRPW_POS(ctx->opcode); 8194 8195 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1], 8196 32 - const16); 8197 break; 8198 /* RRR Format */ 8199 case OPCM_32_RRR_COND_SELECT: 8200 decode_rrr_cond_select(ctx); 8201 break; 8202 case OPCM_32_RRR_DIVIDE: 8203 decode_rrr_divide(ctx); 8204 break; 8205 /* RRR2 Format */ 8206 case OPCM_32_RRR2_MADD: 8207 decode_rrr2_madd(ctx); 8208 break; 8209 case OPCM_32_RRR2_MSUB: 8210 decode_rrr2_msub(ctx); 8211 break; 8212 /* RRR1 format */ 8213 case OPCM_32_RRR1_MADD: 8214 decode_rrr1_madd(ctx); 8215 break; 8216 case OPCM_32_RRR1_MADDQ_H: 8217 decode_rrr1_maddq_h(ctx); 8218 break; 8219 case OPCM_32_RRR1_MADDSU_H: 8220 decode_rrr1_maddsu_h(ctx); 8221 break; 8222 case OPCM_32_RRR1_MSUB_H: 8223 decode_rrr1_msub(ctx); 8224 break; 8225 case OPCM_32_RRR1_MSUB_Q: 8226 decode_rrr1_msubq_h(ctx); 8227 break; 8228 case OPCM_32_RRR1_MSUBAD_H: 8229 decode_rrr1_msubad_h(ctx); 8230 break; 8231 /* RRRR format */ 8232 case OPCM_32_RRRR_EXTRACT_INSERT: 8233 decode_rrrr_extract_insert(ctx); 8234 break; 8235 /* RRRW format */ 8236 case OPCM_32_RRRW_EXTRACT_INSERT: 8237 decode_rrrw_extract_insert(ctx); 8238 break; 8239 /* SYS format */ 8240 case OPCM_32_SYS_INTERRUPTS: 8241 decode_sys_interrupts(ctx); 8242 break; 8243 case OPC1_32_SYS_RSTV: 8244 tcg_gen_movi_tl(cpu_PSW_V, 0); 8245 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); 8246 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 8247 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); 8248 break; 8249 default: 8250 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8251 } 8252 } 8253 8254 static bool tricore_insn_is_16bit(uint32_t insn) 8255 { 8256 return (insn & 0x1) == 0; 8257 } 8258 8259 static void tricore_tr_init_disas_context(DisasContextBase *dcbase, 8260 CPUState *cs) 8261 { 8262 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8263 CPUTriCoreState *env = cs->env_ptr; 8264 ctx->mem_idx = cpu_mmu_index(env, false); 8265 ctx->hflags = (uint32_t)ctx->base.tb->flags; 8266 ctx->features = env->features; 8267 } 8268 8269 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) 8270 { 8271 } 8272 8273 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 8274 { 8275 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8276 8277 tcg_gen_insn_start(ctx->base.pc_next); 8278 } 8279 8280 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) 8281 { 8282 /* 8283 * Return true if the insn at ctx->base.pc_next might cross a page boundary. 8284 * (False positives are OK, false negatives are not.) 8285 * Our caller ensures we are only called if dc->base.pc_next is less than 8286 * 4 bytes from the page boundary, so we cross the page if the first 8287 * 16 bits indicate that this is a 32 bit insn. 8288 */ 8289 uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next); 8290 8291 return !tricore_insn_is_16bit(insn); 8292 } 8293 8294 8295 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 8296 { 8297 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8298 CPUTriCoreState *env = cpu->env_ptr; 8299 uint16_t insn_lo; 8300 bool is_16bit; 8301 8302 insn_lo = cpu_lduw_code(env, ctx->base.pc_next); 8303 is_16bit = tricore_insn_is_16bit(insn_lo); 8304 if (is_16bit) { 8305 ctx->opcode = insn_lo; 8306 ctx->pc_succ_insn = ctx->base.pc_next + 2; 8307 decode_16Bit_opc(ctx); 8308 } else { 8309 uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2); 8310 ctx->opcode = insn_hi << 16 | insn_lo; 8311 ctx->pc_succ_insn = ctx->base.pc_next + 4; 8312 decode_32Bit_opc(ctx); 8313 } 8314 ctx->base.pc_next = ctx->pc_succ_insn; 8315 8316 if (ctx->base.is_jmp == DISAS_NEXT) { 8317 target_ulong page_start; 8318 8319 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 8320 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE 8321 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 8322 && insn_crosses_page(env, ctx))) { 8323 ctx->base.is_jmp = DISAS_TOO_MANY; 8324 } 8325 } 8326 } 8327 8328 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 8329 { 8330 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8331 8332 switch (ctx->base.is_jmp) { 8333 case DISAS_TOO_MANY: 8334 gen_goto_tb(ctx, 0, ctx->base.pc_next); 8335 break; 8336 case DISAS_NORETURN: 8337 break; 8338 default: 8339 g_assert_not_reached(); 8340 } 8341 } 8342 8343 static void tricore_tr_disas_log(const DisasContextBase *dcbase, 8344 CPUState *cpu, FILE *logfile) 8345 { 8346 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 8347 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 8348 } 8349 8350 static const TranslatorOps tricore_tr_ops = { 8351 .init_disas_context = tricore_tr_init_disas_context, 8352 .tb_start = tricore_tr_tb_start, 8353 .insn_start = tricore_tr_insn_start, 8354 .translate_insn = tricore_tr_translate_insn, 8355 .tb_stop = tricore_tr_tb_stop, 8356 .disas_log = tricore_tr_disas_log, 8357 }; 8358 8359 8360 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 8361 target_ulong pc, void *host_pc) 8362 { 8363 DisasContext ctx; 8364 translator_loop(cs, tb, max_insns, pc, host_pc, 8365 &tricore_tr_ops, &ctx.base); 8366 } 8367 8368 /* 8369 * 8370 * Initialization 8371 * 8372 */ 8373 8374 void cpu_state_reset(CPUTriCoreState *env) 8375 { 8376 /* Reset Regs to Default Value */ 8377 env->PSW = 0xb80; 8378 fpu_set_state(env); 8379 } 8380 8381 static void tricore_tcg_init_csfr(void) 8382 { 8383 cpu_PCXI = tcg_global_mem_new(cpu_env, 8384 offsetof(CPUTriCoreState, PCXI), "PCXI"); 8385 cpu_PSW = tcg_global_mem_new(cpu_env, 8386 offsetof(CPUTriCoreState, PSW), "PSW"); 8387 cpu_PC = tcg_global_mem_new(cpu_env, 8388 offsetof(CPUTriCoreState, PC), "PC"); 8389 cpu_ICR = tcg_global_mem_new(cpu_env, 8390 offsetof(CPUTriCoreState, ICR), "ICR"); 8391 } 8392 8393 void tricore_tcg_init(void) 8394 { 8395 int i; 8396 8397 /* reg init */ 8398 for (i = 0 ; i < 16 ; i++) { 8399 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, 8400 offsetof(CPUTriCoreState, gpr_a[i]), 8401 regnames_a[i]); 8402 } 8403 for (i = 0 ; i < 16 ; i++) { 8404 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env, 8405 offsetof(CPUTriCoreState, gpr_d[i]), 8406 regnames_d[i]); 8407 } 8408 tricore_tcg_init_csfr(); 8409 /* init PSW flag cache */ 8410 cpu_PSW_C = tcg_global_mem_new(cpu_env, 8411 offsetof(CPUTriCoreState, PSW_USB_C), 8412 "PSW_C"); 8413 cpu_PSW_V = tcg_global_mem_new(cpu_env, 8414 offsetof(CPUTriCoreState, PSW_USB_V), 8415 "PSW_V"); 8416 cpu_PSW_SV = tcg_global_mem_new(cpu_env, 8417 offsetof(CPUTriCoreState, PSW_USB_SV), 8418 "PSW_SV"); 8419 cpu_PSW_AV = tcg_global_mem_new(cpu_env, 8420 offsetof(CPUTriCoreState, PSW_USB_AV), 8421 "PSW_AV"); 8422 cpu_PSW_SAV = tcg_global_mem_new(cpu_env, 8423 offsetof(CPUTriCoreState, PSW_USB_SAV), 8424 "PSW_SAV"); 8425 } 8426