1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "disas/disas.h" 24 #include "exec/exec-all.h" 25 #include "tcg-op.h" 26 #include "exec/cpu_ldst.h" 27 #include "qemu/qemu-print.h" 28 29 #include "exec/helper-proto.h" 30 #include "exec/helper-gen.h" 31 32 #include "tricore-opcodes.h" 33 #include "exec/log.h" 34 35 /* 36 * TCG registers 37 */ 38 static TCGv cpu_PC; 39 static TCGv cpu_PCXI; 40 static TCGv cpu_PSW; 41 static TCGv cpu_ICR; 42 /* GPR registers */ 43 static TCGv cpu_gpr_a[16]; 44 static TCGv cpu_gpr_d[16]; 45 /* PSW Flag cache */ 46 static TCGv cpu_PSW_C; 47 static TCGv cpu_PSW_V; 48 static TCGv cpu_PSW_SV; 49 static TCGv cpu_PSW_AV; 50 static TCGv cpu_PSW_SAV; 51 52 #include "exec/gen-icount.h" 53 54 static const char *regnames_a[] = { 55 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , 56 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , 57 "a12" , "a13" , "a14" , "a15", 58 }; 59 60 static const char *regnames_d[] = { 61 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , 62 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , 63 "d12" , "d13" , "d14" , "d15", 64 }; 65 66 typedef struct DisasContext { 67 struct TranslationBlock *tb; 68 target_ulong pc, saved_pc, next_pc; 69 uint32_t opcode; 70 int singlestep_enabled; 71 /* Routine used to access memory */ 72 int mem_idx; 73 uint32_t hflags, saved_hflags; 74 int bstate; 75 } DisasContext; 76 77 enum { 78 79 BS_NONE = 0, 80 BS_STOP = 1, 81 BS_BRANCH = 2, 82 BS_EXCP = 3, 83 }; 84 85 enum { 86 MODE_LL = 0, 87 MODE_LU = 1, 88 MODE_UL = 2, 89 MODE_UU = 3, 90 }; 91 92 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) 93 { 94 TriCoreCPU *cpu = TRICORE_CPU(cs); 95 CPUTriCoreState *env = &cpu->env; 96 uint32_t psw; 97 int i; 98 99 psw = psw_read(env); 100 101 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); 102 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); 103 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); 104 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); 105 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); 106 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); 107 108 for (i = 0; i < 16; ++i) { 109 if ((i & 3) == 0) { 110 qemu_fprintf(f, "\nGPR A%02d:", i); 111 } 112 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); 113 } 114 for (i = 0; i < 16; ++i) { 115 if ((i & 3) == 0) { 116 qemu_fprintf(f, "\nGPR D%02d:", i); 117 } 118 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); 119 } 120 qemu_fprintf(f, "\n"); 121 } 122 123 /* 124 * Functions to generate micro-ops 125 */ 126 127 /* Makros for generating helpers */ 128 129 #define gen_helper_1arg(name, arg) do { \ 130 TCGv_i32 helper_tmp = tcg_const_i32(arg); \ 131 gen_helper_##name(cpu_env, helper_tmp); \ 132 tcg_temp_free_i32(helper_tmp); \ 133 } while (0) 134 135 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ 136 TCGv arg00 = tcg_temp_new(); \ 137 TCGv arg01 = tcg_temp_new(); \ 138 TCGv arg11 = tcg_temp_new(); \ 139 tcg_gen_sari_tl(arg00, arg0, 16); \ 140 tcg_gen_ext16s_tl(arg01, arg0); \ 141 tcg_gen_ext16s_tl(arg11, arg1); \ 142 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 143 tcg_temp_free(arg00); \ 144 tcg_temp_free(arg01); \ 145 tcg_temp_free(arg11); \ 146 } while (0) 147 148 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ 149 TCGv arg00 = tcg_temp_new(); \ 150 TCGv arg01 = tcg_temp_new(); \ 151 TCGv arg10 = tcg_temp_new(); \ 152 TCGv arg11 = tcg_temp_new(); \ 153 tcg_gen_sari_tl(arg00, arg0, 16); \ 154 tcg_gen_ext16s_tl(arg01, arg0); \ 155 tcg_gen_sari_tl(arg11, arg1, 16); \ 156 tcg_gen_ext16s_tl(arg10, arg1); \ 157 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 158 tcg_temp_free(arg00); \ 159 tcg_temp_free(arg01); \ 160 tcg_temp_free(arg10); \ 161 tcg_temp_free(arg11); \ 162 } while (0) 163 164 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ 165 TCGv arg00 = tcg_temp_new(); \ 166 TCGv arg01 = tcg_temp_new(); \ 167 TCGv arg10 = tcg_temp_new(); \ 168 TCGv arg11 = tcg_temp_new(); \ 169 tcg_gen_sari_tl(arg00, arg0, 16); \ 170 tcg_gen_ext16s_tl(arg01, arg0); \ 171 tcg_gen_sari_tl(arg10, arg1, 16); \ 172 tcg_gen_ext16s_tl(arg11, arg1); \ 173 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 174 tcg_temp_free(arg00); \ 175 tcg_temp_free(arg01); \ 176 tcg_temp_free(arg10); \ 177 tcg_temp_free(arg11); \ 178 } while (0) 179 180 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ 181 TCGv arg00 = tcg_temp_new(); \ 182 TCGv arg01 = tcg_temp_new(); \ 183 TCGv arg11 = tcg_temp_new(); \ 184 tcg_gen_sari_tl(arg01, arg0, 16); \ 185 tcg_gen_ext16s_tl(arg00, arg0); \ 186 tcg_gen_sari_tl(arg11, arg1, 16); \ 187 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 188 tcg_temp_free(arg00); \ 189 tcg_temp_free(arg01); \ 190 tcg_temp_free(arg11); \ 191 } while (0) 192 193 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ 194 TCGv_i64 ret = tcg_temp_new_i64(); \ 195 TCGv_i64 arg1 = tcg_temp_new_i64(); \ 196 \ 197 tcg_gen_concat_i32_i64(arg1, al1, ah1); \ 198 gen_helper_##name(ret, arg1, arg2); \ 199 tcg_gen_extr_i64_i32(rl, rh, ret); \ 200 \ 201 tcg_temp_free_i64(ret); \ 202 tcg_temp_free_i64(arg1); \ 203 } while (0) 204 205 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ 206 TCGv_i64 ret = tcg_temp_new_i64(); \ 207 \ 208 gen_helper_##name(ret, cpu_env, arg1, arg2); \ 209 tcg_gen_extr_i64_i32(rl, rh, ret); \ 210 \ 211 tcg_temp_free_i64(ret); \ 212 } while (0) 213 214 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) 215 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ 216 ((offset & 0x0fffff) << 1)) 217 218 /* For two 32-bit registers used a 64-bit register, the first 219 registernumber needs to be even. Otherwise we trap. */ 220 static inline void generate_trap(DisasContext *ctx, int class, int tin); 221 #define CHECK_REG_PAIR(reg) do { \ 222 if (reg & 0x1) { \ 223 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ 224 } \ 225 } while (0) 226 227 /* Functions for load/save to/from memory */ 228 229 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, 230 int16_t con, TCGMemOp mop) 231 { 232 TCGv temp = tcg_temp_new(); 233 tcg_gen_addi_tl(temp, r2, con); 234 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 235 tcg_temp_free(temp); 236 } 237 238 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, 239 int16_t con, TCGMemOp mop) 240 { 241 TCGv temp = tcg_temp_new(); 242 tcg_gen_addi_tl(temp, r2, con); 243 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 244 tcg_temp_free(temp); 245 } 246 247 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 248 { 249 TCGv_i64 temp = tcg_temp_new_i64(); 250 251 tcg_gen_concat_i32_i64(temp, rl, rh); 252 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ); 253 254 tcg_temp_free_i64(temp); 255 } 256 257 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 258 DisasContext *ctx) 259 { 260 TCGv temp = tcg_temp_new(); 261 tcg_gen_addi_tl(temp, base, con); 262 gen_st_2regs_64(rh, rl, temp, ctx); 263 tcg_temp_free(temp); 264 } 265 266 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 267 { 268 TCGv_i64 temp = tcg_temp_new_i64(); 269 270 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ); 271 /* write back to two 32 bit regs */ 272 tcg_gen_extr_i64_i32(rl, rh, temp); 273 274 tcg_temp_free_i64(temp); 275 } 276 277 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 278 DisasContext *ctx) 279 { 280 TCGv temp = tcg_temp_new(); 281 tcg_gen_addi_tl(temp, base, con); 282 gen_ld_2regs_64(rh, rl, temp, ctx); 283 tcg_temp_free(temp); 284 } 285 286 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 287 TCGMemOp mop) 288 { 289 TCGv temp = tcg_temp_new(); 290 tcg_gen_addi_tl(temp, r2, off); 291 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 292 tcg_gen_mov_tl(r2, temp); 293 tcg_temp_free(temp); 294 } 295 296 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 297 TCGMemOp mop) 298 { 299 TCGv temp = tcg_temp_new(); 300 tcg_gen_addi_tl(temp, r2, off); 301 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 302 tcg_gen_mov_tl(r2, temp); 303 tcg_temp_free(temp); 304 } 305 306 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ 307 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) 308 { 309 TCGv temp = tcg_temp_new(); 310 TCGv temp2 = tcg_temp_new(); 311 312 CHECK_REG_PAIR(ereg); 313 /* temp = (M(EA, word) */ 314 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 315 /* temp = temp & ~E[a][63:32]) */ 316 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); 317 /* temp2 = (E[a][31:0] & E[a][63:32]); */ 318 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); 319 /* temp = temp | temp2; */ 320 tcg_gen_or_tl(temp, temp, temp2); 321 /* M(EA, word) = temp; */ 322 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); 323 324 tcg_temp_free(temp); 325 tcg_temp_free(temp2); 326 } 327 328 /* tmp = M(EA, word); 329 M(EA, word) = D[a]; 330 D[a] = tmp[31:0];*/ 331 static void gen_swap(DisasContext *ctx, int reg, TCGv ea) 332 { 333 TCGv temp = tcg_temp_new(); 334 335 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 336 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); 337 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 338 339 tcg_temp_free(temp); 340 } 341 342 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) 343 { 344 TCGv temp = tcg_temp_new(); 345 TCGv temp2 = tcg_temp_new(); 346 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 347 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, 348 cpu_gpr_d[reg], temp); 349 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 350 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 351 352 tcg_temp_free(temp); 353 tcg_temp_free(temp2); 354 } 355 356 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) 357 { 358 TCGv temp = tcg_temp_new(); 359 TCGv temp2 = tcg_temp_new(); 360 TCGv temp3 = tcg_temp_new(); 361 362 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 363 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); 364 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); 365 tcg_gen_or_tl(temp2, temp2, temp3); 366 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 367 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 368 369 tcg_temp_free(temp); 370 tcg_temp_free(temp2); 371 tcg_temp_free(temp3); 372 } 373 374 375 /* We generate loads and store to core special function register (csfr) through 376 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 377 makros R, A and E, which allow read-only, all and endinit protected access. 378 These makros also specify in which ISA version the csfr was introduced. */ 379 #define R(ADDRESS, REG, FEATURE) \ 380 case ADDRESS: \ 381 if (tricore_feature(env, FEATURE)) { \ 382 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ 383 } \ 384 break; 385 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 386 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 387 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) 388 { 389 /* since we're caching PSW make this a special case */ 390 if (offset == 0xfe04) { 391 gen_helper_psw_read(ret, cpu_env); 392 } else { 393 switch (offset) { 394 #include "csfr.def" 395 } 396 } 397 } 398 #undef R 399 #undef A 400 #undef E 401 402 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, 403 since no execption occurs */ 404 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ 405 case ADDRESS: \ 406 if (tricore_feature(env, FEATURE)) { \ 407 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ 408 } \ 409 break; 410 /* Endinit protected registers 411 TODO: Since the endinit bit is in a register of a not yet implemented 412 watchdog device, we handle endinit protected registers like 413 all-access registers for now. */ 414 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) 415 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1, 416 int32_t offset) 417 { 418 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 419 /* since we're caching PSW make this a special case */ 420 if (offset == 0xfe04) { 421 gen_helper_psw_write(cpu_env, r1); 422 } else { 423 switch (offset) { 424 #include "csfr.def" 425 } 426 } 427 } else { 428 /* generate privilege trap */ 429 } 430 } 431 432 /* Functions for arithmetic instructions */ 433 434 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) 435 { 436 TCGv t0 = tcg_temp_new_i32(); 437 TCGv result = tcg_temp_new_i32(); 438 /* Addition and set V/SV bits */ 439 tcg_gen_add_tl(result, r1, r2); 440 /* calc V bit */ 441 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 442 tcg_gen_xor_tl(t0, r1, r2); 443 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 444 /* Calc SV bit */ 445 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 446 /* Calc AV/SAV bits */ 447 tcg_gen_add_tl(cpu_PSW_AV, result, result); 448 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 449 /* calc SAV */ 450 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 451 /* write back result */ 452 tcg_gen_mov_tl(ret, result); 453 454 tcg_temp_free(result); 455 tcg_temp_free(t0); 456 } 457 458 static inline void 459 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 460 { 461 TCGv temp = tcg_temp_new(); 462 TCGv_i64 t0 = tcg_temp_new_i64(); 463 TCGv_i64 t1 = tcg_temp_new_i64(); 464 TCGv_i64 result = tcg_temp_new_i64(); 465 466 tcg_gen_add_i64(result, r1, r2); 467 /* calc v bit */ 468 tcg_gen_xor_i64(t1, result, r1); 469 tcg_gen_xor_i64(t0, r1, r2); 470 tcg_gen_andc_i64(t1, t1, t0); 471 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 472 /* calc SV bit */ 473 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 474 /* calc AV/SAV bits */ 475 tcg_gen_extrh_i64_i32(temp, result); 476 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 477 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 478 /* calc SAV */ 479 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 480 /* write back result */ 481 tcg_gen_mov_i64(ret, result); 482 483 tcg_temp_free(temp); 484 tcg_temp_free_i64(result); 485 tcg_temp_free_i64(t0); 486 tcg_temp_free_i64(t1); 487 } 488 489 static inline void 490 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 491 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), 492 void(*op2)(TCGv, TCGv, TCGv)) 493 { 494 TCGv temp = tcg_temp_new(); 495 TCGv temp2 = tcg_temp_new(); 496 TCGv temp3 = tcg_temp_new(); 497 TCGv temp4 = tcg_temp_new(); 498 499 (*op1)(temp, r1_low, r2); 500 /* calc V0 bit */ 501 tcg_gen_xor_tl(temp2, temp, r1_low); 502 tcg_gen_xor_tl(temp3, r1_low, r2); 503 if (op1 == tcg_gen_add_tl) { 504 tcg_gen_andc_tl(temp2, temp2, temp3); 505 } else { 506 tcg_gen_and_tl(temp2, temp2, temp3); 507 } 508 509 (*op2)(temp3, r1_high, r3); 510 /* calc V1 bit */ 511 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); 512 tcg_gen_xor_tl(temp4, r1_high, r3); 513 if (op2 == tcg_gen_add_tl) { 514 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); 515 } else { 516 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); 517 } 518 /* combine V0/V1 bits */ 519 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); 520 /* calc sv bit */ 521 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 522 /* write result */ 523 tcg_gen_mov_tl(ret_low, temp); 524 tcg_gen_mov_tl(ret_high, temp3); 525 /* calc AV bit */ 526 tcg_gen_add_tl(temp, ret_low, ret_low); 527 tcg_gen_xor_tl(temp, temp, ret_low); 528 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 529 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); 530 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 531 /* calc SAV bit */ 532 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 533 534 tcg_temp_free(temp); 535 tcg_temp_free(temp2); 536 tcg_temp_free(temp3); 537 tcg_temp_free(temp4); 538 } 539 540 /* ret = r2 + (r1 * r3); */ 541 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 542 { 543 TCGv_i64 t1 = tcg_temp_new_i64(); 544 TCGv_i64 t2 = tcg_temp_new_i64(); 545 TCGv_i64 t3 = tcg_temp_new_i64(); 546 547 tcg_gen_ext_i32_i64(t1, r1); 548 tcg_gen_ext_i32_i64(t2, r2); 549 tcg_gen_ext_i32_i64(t3, r3); 550 551 tcg_gen_mul_i64(t1, t1, t3); 552 tcg_gen_add_i64(t1, t2, t1); 553 554 tcg_gen_extrl_i64_i32(ret, t1); 555 /* calc V 556 t1 > 0x7fffffff */ 557 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 558 /* t1 < -0x80000000 */ 559 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 560 tcg_gen_or_i64(t2, t2, t3); 561 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 562 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 563 /* Calc SV bit */ 564 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 565 /* Calc AV/SAV bits */ 566 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 567 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 568 /* calc SAV */ 569 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 570 571 tcg_temp_free_i64(t1); 572 tcg_temp_free_i64(t2); 573 tcg_temp_free_i64(t3); 574 } 575 576 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 577 { 578 TCGv temp = tcg_const_i32(con); 579 gen_madd32_d(ret, r1, r2, temp); 580 tcg_temp_free(temp); 581 } 582 583 static inline void 584 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 585 TCGv r3) 586 { 587 TCGv t1 = tcg_temp_new(); 588 TCGv t2 = tcg_temp_new(); 589 TCGv t3 = tcg_temp_new(); 590 TCGv t4 = tcg_temp_new(); 591 592 tcg_gen_muls2_tl(t1, t2, r1, r3); 593 /* only the add can overflow */ 594 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); 595 /* calc V bit */ 596 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 597 tcg_gen_xor_tl(t1, r2_high, t2); 598 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); 599 /* Calc SV bit */ 600 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 601 /* Calc AV/SAV bits */ 602 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 603 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 604 /* calc SAV */ 605 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 606 /* write back the result */ 607 tcg_gen_mov_tl(ret_low, t3); 608 tcg_gen_mov_tl(ret_high, t4); 609 610 tcg_temp_free(t1); 611 tcg_temp_free(t2); 612 tcg_temp_free(t3); 613 tcg_temp_free(t4); 614 } 615 616 static inline void 617 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 618 TCGv r3) 619 { 620 TCGv_i64 t1 = tcg_temp_new_i64(); 621 TCGv_i64 t2 = tcg_temp_new_i64(); 622 TCGv_i64 t3 = tcg_temp_new_i64(); 623 624 tcg_gen_extu_i32_i64(t1, r1); 625 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 626 tcg_gen_extu_i32_i64(t3, r3); 627 628 tcg_gen_mul_i64(t1, t1, t3); 629 tcg_gen_add_i64(t2, t2, t1); 630 /* write back result */ 631 tcg_gen_extr_i64_i32(ret_low, ret_high, t2); 632 /* only the add overflows, if t2 < t1 633 calc V bit */ 634 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); 635 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 636 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 637 /* Calc SV bit */ 638 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 639 /* Calc AV/SAV bits */ 640 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 641 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 642 /* calc SAV */ 643 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 644 645 tcg_temp_free_i64(t1); 646 tcg_temp_free_i64(t2); 647 tcg_temp_free_i64(t3); 648 } 649 650 static inline void 651 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 652 int32_t con) 653 { 654 TCGv temp = tcg_const_i32(con); 655 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 656 tcg_temp_free(temp); 657 } 658 659 static inline void 660 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 661 int32_t con) 662 { 663 TCGv temp = tcg_const_i32(con); 664 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 665 tcg_temp_free(temp); 666 } 667 668 static inline void 669 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 670 TCGv r3, uint32_t n, uint32_t mode) 671 { 672 TCGv temp = tcg_const_i32(n); 673 TCGv temp2 = tcg_temp_new(); 674 TCGv_i64 temp64 = tcg_temp_new_i64(); 675 switch (mode) { 676 case MODE_LL: 677 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 678 break; 679 case MODE_LU: 680 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 681 break; 682 case MODE_UL: 683 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 684 break; 685 case MODE_UU: 686 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 687 break; 688 } 689 tcg_gen_extr_i64_i32(temp, temp2, temp64); 690 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 691 tcg_gen_add_tl, tcg_gen_add_tl); 692 tcg_temp_free(temp); 693 tcg_temp_free(temp2); 694 tcg_temp_free_i64(temp64); 695 } 696 697 static inline void 698 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 699 TCGv r3, uint32_t n, uint32_t mode) 700 { 701 TCGv temp = tcg_const_i32(n); 702 TCGv temp2 = tcg_temp_new(); 703 TCGv_i64 temp64 = tcg_temp_new_i64(); 704 switch (mode) { 705 case MODE_LL: 706 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 707 break; 708 case MODE_LU: 709 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 710 break; 711 case MODE_UL: 712 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 713 break; 714 case MODE_UU: 715 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 716 break; 717 } 718 tcg_gen_extr_i64_i32(temp, temp2, temp64); 719 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 720 tcg_gen_sub_tl, tcg_gen_add_tl); 721 tcg_temp_free(temp); 722 tcg_temp_free(temp2); 723 tcg_temp_free_i64(temp64); 724 } 725 726 static inline void 727 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 728 TCGv r3, uint32_t n, uint32_t mode) 729 { 730 TCGv temp = tcg_const_i32(n); 731 TCGv_i64 temp64 = tcg_temp_new_i64(); 732 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 733 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 734 switch (mode) { 735 case MODE_LL: 736 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 737 break; 738 case MODE_LU: 739 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 740 break; 741 case MODE_UL: 742 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 743 break; 744 case MODE_UU: 745 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 746 break; 747 } 748 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 749 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 750 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 751 tcg_gen_sub_i64(temp64, temp64_2, temp64); 752 tcg_gen_shli_i64(temp64, temp64, 16); 753 754 gen_add64_d(temp64_2, temp64_3, temp64); 755 /* write back result */ 756 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 757 758 tcg_temp_free(temp); 759 tcg_temp_free_i64(temp64); 760 tcg_temp_free_i64(temp64_2); 761 tcg_temp_free_i64(temp64_3); 762 } 763 764 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); 765 766 static inline void 767 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 768 TCGv r3, uint32_t n, uint32_t mode) 769 { 770 TCGv temp = tcg_const_i32(n); 771 TCGv temp2 = tcg_temp_new(); 772 TCGv temp3 = tcg_temp_new(); 773 TCGv_i64 temp64 = tcg_temp_new_i64(); 774 775 switch (mode) { 776 case MODE_LL: 777 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 778 break; 779 case MODE_LU: 780 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 781 break; 782 case MODE_UL: 783 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 784 break; 785 case MODE_UU: 786 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 787 break; 788 } 789 tcg_gen_extr_i64_i32(temp, temp2, temp64); 790 gen_adds(ret_low, r1_low, temp); 791 tcg_gen_mov_tl(temp, cpu_PSW_V); 792 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 793 gen_adds(ret_high, r1_high, temp2); 794 /* combine v bits */ 795 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 796 /* combine av bits */ 797 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 798 799 tcg_temp_free(temp); 800 tcg_temp_free(temp2); 801 tcg_temp_free(temp3); 802 tcg_temp_free_i64(temp64); 803 804 } 805 806 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); 807 808 static inline void 809 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 810 TCGv r3, uint32_t n, uint32_t mode) 811 { 812 TCGv temp = tcg_const_i32(n); 813 TCGv temp2 = tcg_temp_new(); 814 TCGv temp3 = tcg_temp_new(); 815 TCGv_i64 temp64 = tcg_temp_new_i64(); 816 817 switch (mode) { 818 case MODE_LL: 819 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 820 break; 821 case MODE_LU: 822 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 823 break; 824 case MODE_UL: 825 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 826 break; 827 case MODE_UU: 828 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 829 break; 830 } 831 tcg_gen_extr_i64_i32(temp, temp2, temp64); 832 gen_subs(ret_low, r1_low, temp); 833 tcg_gen_mov_tl(temp, cpu_PSW_V); 834 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 835 gen_adds(ret_high, r1_high, temp2); 836 /* combine v bits */ 837 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 838 /* combine av bits */ 839 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 840 841 tcg_temp_free(temp); 842 tcg_temp_free(temp2); 843 tcg_temp_free(temp3); 844 tcg_temp_free_i64(temp64); 845 846 } 847 848 static inline void 849 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 850 TCGv r3, uint32_t n, uint32_t mode) 851 { 852 TCGv temp = tcg_const_i32(n); 853 TCGv_i64 temp64 = tcg_temp_new_i64(); 854 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 855 856 switch (mode) { 857 case MODE_LL: 858 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 859 break; 860 case MODE_LU: 861 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 862 break; 863 case MODE_UL: 864 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 865 break; 866 case MODE_UU: 867 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 868 break; 869 } 870 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 871 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 872 tcg_gen_sub_i64(temp64, temp64_2, temp64); 873 tcg_gen_shli_i64(temp64, temp64, 16); 874 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 875 876 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 877 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 878 879 tcg_temp_free(temp); 880 tcg_temp_free_i64(temp64); 881 tcg_temp_free_i64(temp64_2); 882 } 883 884 885 static inline void 886 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 887 TCGv r3, uint32_t n, uint32_t mode) 888 { 889 TCGv temp = tcg_const_i32(n); 890 TCGv_i64 temp64 = tcg_temp_new_i64(); 891 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 892 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 893 switch (mode) { 894 case MODE_LL: 895 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 896 break; 897 case MODE_LU: 898 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 899 break; 900 case MODE_UL: 901 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 902 break; 903 case MODE_UU: 904 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 905 break; 906 } 907 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 908 gen_add64_d(temp64_3, temp64_2, temp64); 909 /* write back result */ 910 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 911 912 tcg_temp_free(temp); 913 tcg_temp_free_i64(temp64); 914 tcg_temp_free_i64(temp64_2); 915 tcg_temp_free_i64(temp64_3); 916 } 917 918 static inline void 919 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 920 TCGv r3, uint32_t n, uint32_t mode) 921 { 922 TCGv temp = tcg_const_i32(n); 923 TCGv_i64 temp64 = tcg_temp_new_i64(); 924 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 925 switch (mode) { 926 case MODE_LL: 927 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 928 break; 929 case MODE_LU: 930 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 931 break; 932 case MODE_UL: 933 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 934 break; 935 case MODE_UU: 936 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 937 break; 938 } 939 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 940 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 941 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 942 943 tcg_temp_free(temp); 944 tcg_temp_free_i64(temp64); 945 tcg_temp_free_i64(temp64_2); 946 } 947 948 static inline void 949 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 950 uint32_t mode) 951 { 952 TCGv temp = tcg_const_i32(n); 953 TCGv_i64 temp64 = tcg_temp_new_i64(); 954 switch (mode) { 955 case MODE_LL: 956 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 957 break; 958 case MODE_LU: 959 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 960 break; 961 case MODE_UL: 962 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 963 break; 964 case MODE_UU: 965 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 966 break; 967 } 968 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); 969 970 tcg_temp_free(temp); 971 tcg_temp_free_i64(temp64); 972 } 973 974 static inline void 975 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 976 { 977 TCGv temp = tcg_temp_new(); 978 TCGv temp2 = tcg_temp_new(); 979 980 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 981 tcg_gen_shli_tl(temp, r1, 16); 982 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); 983 984 tcg_temp_free(temp); 985 tcg_temp_free(temp2); 986 } 987 988 static inline void 989 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 990 { 991 TCGv temp = tcg_const_i32(n); 992 TCGv temp2 = tcg_temp_new(); 993 TCGv_i64 temp64 = tcg_temp_new_i64(); 994 switch (mode) { 995 case MODE_LL: 996 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 997 break; 998 case MODE_LU: 999 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1000 break; 1001 case MODE_UL: 1002 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1003 break; 1004 case MODE_UU: 1005 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1006 break; 1007 } 1008 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1009 tcg_gen_shli_tl(temp, r1, 16); 1010 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); 1011 1012 tcg_temp_free(temp); 1013 tcg_temp_free(temp2); 1014 tcg_temp_free_i64(temp64); 1015 } 1016 1017 1018 static inline void 1019 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1020 uint32_t n, uint32_t mode) 1021 { 1022 TCGv temp = tcg_const_i32(n); 1023 TCGv_i64 temp64 = tcg_temp_new_i64(); 1024 switch (mode) { 1025 case MODE_LL: 1026 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1027 break; 1028 case MODE_LU: 1029 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1030 break; 1031 case MODE_UL: 1032 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1033 break; 1034 case MODE_UU: 1035 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1036 break; 1037 } 1038 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 1039 1040 tcg_temp_free(temp); 1041 tcg_temp_free_i64(temp64); 1042 } 1043 1044 static inline void 1045 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1046 { 1047 TCGv temp = tcg_temp_new(); 1048 TCGv temp2 = tcg_temp_new(); 1049 1050 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1051 tcg_gen_shli_tl(temp, r1, 16); 1052 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); 1053 1054 tcg_temp_free(temp); 1055 tcg_temp_free(temp2); 1056 } 1057 1058 static inline void 1059 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1060 { 1061 TCGv temp = tcg_const_i32(n); 1062 TCGv temp2 = tcg_temp_new(); 1063 TCGv_i64 temp64 = tcg_temp_new_i64(); 1064 switch (mode) { 1065 case MODE_LL: 1066 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1067 break; 1068 case MODE_LU: 1069 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1070 break; 1071 case MODE_UL: 1072 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1073 break; 1074 case MODE_UU: 1075 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1076 break; 1077 } 1078 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1079 tcg_gen_shli_tl(temp, r1, 16); 1080 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); 1081 1082 tcg_temp_free(temp); 1083 tcg_temp_free(temp2); 1084 tcg_temp_free_i64(temp64); 1085 } 1086 1087 static inline void 1088 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1089 { 1090 TCGv temp = tcg_const_i32(n); 1091 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp); 1092 tcg_temp_free(temp); 1093 } 1094 1095 static inline void 1096 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1097 { 1098 TCGv temp = tcg_const_i32(n); 1099 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp); 1100 tcg_temp_free(temp); 1101 } 1102 1103 static inline void 1104 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1105 uint32_t up_shift, CPUTriCoreState *env) 1106 { 1107 TCGv temp = tcg_temp_new(); 1108 TCGv temp2 = tcg_temp_new(); 1109 TCGv temp3 = tcg_temp_new(); 1110 TCGv_i64 t1 = tcg_temp_new_i64(); 1111 TCGv_i64 t2 = tcg_temp_new_i64(); 1112 TCGv_i64 t3 = tcg_temp_new_i64(); 1113 1114 tcg_gen_ext_i32_i64(t2, arg2); 1115 tcg_gen_ext_i32_i64(t3, arg3); 1116 1117 tcg_gen_mul_i64(t2, t2, t3); 1118 tcg_gen_shli_i64(t2, t2, n); 1119 1120 tcg_gen_ext_i32_i64(t1, arg1); 1121 tcg_gen_sari_i64(t2, t2, up_shift); 1122 1123 tcg_gen_add_i64(t3, t1, t2); 1124 tcg_gen_extrl_i64_i32(temp3, t3); 1125 /* calc v bit */ 1126 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1127 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1128 tcg_gen_or_i64(t1, t1, t2); 1129 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1130 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1131 /* We produce an overflow on the host if the mul before was 1132 (0x80000000 * 0x80000000) << 1). If this is the 1133 case, we negate the ovf. */ 1134 if (n == 1) { 1135 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1136 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1137 tcg_gen_and_tl(temp, temp, temp2); 1138 tcg_gen_shli_tl(temp, temp, 31); 1139 /* negate v bit, if special condition */ 1140 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1141 } 1142 /* Calc SV bit */ 1143 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1144 /* Calc AV/SAV bits */ 1145 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1146 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1147 /* calc SAV */ 1148 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1149 /* write back result */ 1150 tcg_gen_mov_tl(ret, temp3); 1151 1152 tcg_temp_free(temp); 1153 tcg_temp_free(temp2); 1154 tcg_temp_free(temp3); 1155 tcg_temp_free_i64(t1); 1156 tcg_temp_free_i64(t2); 1157 tcg_temp_free_i64(t3); 1158 } 1159 1160 static inline void 1161 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1162 { 1163 TCGv temp = tcg_temp_new(); 1164 TCGv temp2 = tcg_temp_new(); 1165 if (n == 0) { 1166 tcg_gen_mul_tl(temp, arg2, arg3); 1167 } else { /* n is expected to be 1 */ 1168 tcg_gen_mul_tl(temp, arg2, arg3); 1169 tcg_gen_shli_tl(temp, temp, 1); 1170 /* catch special case r1 = r2 = 0x8000 */ 1171 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1172 tcg_gen_sub_tl(temp, temp, temp2); 1173 } 1174 gen_add_d(ret, arg1, temp); 1175 1176 tcg_temp_free(temp); 1177 tcg_temp_free(temp2); 1178 } 1179 1180 static inline void 1181 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1182 { 1183 TCGv temp = tcg_temp_new(); 1184 TCGv temp2 = tcg_temp_new(); 1185 if (n == 0) { 1186 tcg_gen_mul_tl(temp, arg2, arg3); 1187 } else { /* n is expected to be 1 */ 1188 tcg_gen_mul_tl(temp, arg2, arg3); 1189 tcg_gen_shli_tl(temp, temp, 1); 1190 /* catch special case r1 = r2 = 0x8000 */ 1191 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1192 tcg_gen_sub_tl(temp, temp, temp2); 1193 } 1194 gen_adds(ret, arg1, temp); 1195 1196 tcg_temp_free(temp); 1197 tcg_temp_free(temp2); 1198 } 1199 1200 static inline void 1201 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1202 TCGv arg3, uint32_t n) 1203 { 1204 TCGv temp = tcg_temp_new(); 1205 TCGv temp2 = tcg_temp_new(); 1206 TCGv_i64 t1 = tcg_temp_new_i64(); 1207 TCGv_i64 t2 = tcg_temp_new_i64(); 1208 TCGv_i64 t3 = tcg_temp_new_i64(); 1209 1210 if (n == 0) { 1211 tcg_gen_mul_tl(temp, arg2, arg3); 1212 } else { /* n is expected to be 1 */ 1213 tcg_gen_mul_tl(temp, arg2, arg3); 1214 tcg_gen_shli_tl(temp, temp, 1); 1215 /* catch special case r1 = r2 = 0x8000 */ 1216 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1217 tcg_gen_sub_tl(temp, temp, temp2); 1218 } 1219 tcg_gen_ext_i32_i64(t2, temp); 1220 tcg_gen_shli_i64(t2, t2, 16); 1221 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1222 gen_add64_d(t3, t1, t2); 1223 /* write back result */ 1224 tcg_gen_extr_i64_i32(rl, rh, t3); 1225 1226 tcg_temp_free_i64(t1); 1227 tcg_temp_free_i64(t2); 1228 tcg_temp_free_i64(t3); 1229 tcg_temp_free(temp); 1230 tcg_temp_free(temp2); 1231 } 1232 1233 static inline void 1234 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1235 TCGv arg3, uint32_t n) 1236 { 1237 TCGv temp = tcg_temp_new(); 1238 TCGv temp2 = tcg_temp_new(); 1239 TCGv_i64 t1 = tcg_temp_new_i64(); 1240 TCGv_i64 t2 = tcg_temp_new_i64(); 1241 1242 if (n == 0) { 1243 tcg_gen_mul_tl(temp, arg2, arg3); 1244 } else { /* n is expected to be 1 */ 1245 tcg_gen_mul_tl(temp, arg2, arg3); 1246 tcg_gen_shli_tl(temp, temp, 1); 1247 /* catch special case r1 = r2 = 0x8000 */ 1248 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1249 tcg_gen_sub_tl(temp, temp, temp2); 1250 } 1251 tcg_gen_ext_i32_i64(t2, temp); 1252 tcg_gen_shli_i64(t2, t2, 16); 1253 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1254 1255 gen_helper_add64_ssov(t1, cpu_env, t1, t2); 1256 tcg_gen_extr_i64_i32(rl, rh, t1); 1257 1258 tcg_temp_free(temp); 1259 tcg_temp_free(temp2); 1260 tcg_temp_free_i64(t1); 1261 tcg_temp_free_i64(t2); 1262 } 1263 1264 static inline void 1265 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1266 TCGv arg3, uint32_t n, CPUTriCoreState *env) 1267 { 1268 TCGv_i64 t1 = tcg_temp_new_i64(); 1269 TCGv_i64 t2 = tcg_temp_new_i64(); 1270 TCGv_i64 t3 = tcg_temp_new_i64(); 1271 TCGv_i64 t4 = tcg_temp_new_i64(); 1272 TCGv temp, temp2; 1273 1274 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1275 tcg_gen_ext_i32_i64(t2, arg2); 1276 tcg_gen_ext_i32_i64(t3, arg3); 1277 1278 tcg_gen_mul_i64(t2, t2, t3); 1279 if (n != 0) { 1280 tcg_gen_shli_i64(t2, t2, 1); 1281 } 1282 tcg_gen_add_i64(t4, t1, t2); 1283 /* calc v bit */ 1284 tcg_gen_xor_i64(t3, t4, t1); 1285 tcg_gen_xor_i64(t2, t1, t2); 1286 tcg_gen_andc_i64(t3, t3, t2); 1287 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1288 /* We produce an overflow on the host if the mul before was 1289 (0x80000000 * 0x80000000) << 1). If this is the 1290 case, we negate the ovf. */ 1291 if (n == 1) { 1292 temp = tcg_temp_new(); 1293 temp2 = tcg_temp_new(); 1294 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1295 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1296 tcg_gen_and_tl(temp, temp, temp2); 1297 tcg_gen_shli_tl(temp, temp, 31); 1298 /* negate v bit, if special condition */ 1299 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1300 1301 tcg_temp_free(temp); 1302 tcg_temp_free(temp2); 1303 } 1304 /* write back result */ 1305 tcg_gen_extr_i64_i32(rl, rh, t4); 1306 /* Calc SV bit */ 1307 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1308 /* Calc AV/SAV bits */ 1309 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1310 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1311 /* calc SAV */ 1312 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1313 1314 tcg_temp_free_i64(t1); 1315 tcg_temp_free_i64(t2); 1316 tcg_temp_free_i64(t3); 1317 tcg_temp_free_i64(t4); 1318 } 1319 1320 static inline void 1321 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1322 uint32_t up_shift) 1323 { 1324 TCGv_i64 t1 = tcg_temp_new_i64(); 1325 TCGv_i64 t2 = tcg_temp_new_i64(); 1326 TCGv_i64 t3 = tcg_temp_new_i64(); 1327 1328 tcg_gen_ext_i32_i64(t1, arg1); 1329 tcg_gen_ext_i32_i64(t2, arg2); 1330 tcg_gen_ext_i32_i64(t3, arg3); 1331 1332 tcg_gen_mul_i64(t2, t2, t3); 1333 tcg_gen_sari_i64(t2, t2, up_shift - n); 1334 1335 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); 1336 1337 tcg_temp_free_i64(t1); 1338 tcg_temp_free_i64(t2); 1339 tcg_temp_free_i64(t3); 1340 } 1341 1342 static inline void 1343 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1344 TCGv arg3, uint32_t n) 1345 { 1346 TCGv_i64 r1 = tcg_temp_new_i64(); 1347 TCGv temp = tcg_const_i32(n); 1348 1349 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1350 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); 1351 tcg_gen_extr_i64_i32(rl, rh, r1); 1352 1353 tcg_temp_free_i64(r1); 1354 tcg_temp_free(temp); 1355 } 1356 /* ret = r2 - (r1 * r3); */ 1357 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 1358 { 1359 TCGv_i64 t1 = tcg_temp_new_i64(); 1360 TCGv_i64 t2 = tcg_temp_new_i64(); 1361 TCGv_i64 t3 = tcg_temp_new_i64(); 1362 1363 tcg_gen_ext_i32_i64(t1, r1); 1364 tcg_gen_ext_i32_i64(t2, r2); 1365 tcg_gen_ext_i32_i64(t3, r3); 1366 1367 tcg_gen_mul_i64(t1, t1, t3); 1368 tcg_gen_sub_i64(t1, t2, t1); 1369 1370 tcg_gen_extrl_i64_i32(ret, t1); 1371 /* calc V 1372 t2 > 0x7fffffff */ 1373 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 1374 /* result < -0x80000000 */ 1375 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 1376 tcg_gen_or_i64(t2, t2, t3); 1377 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 1378 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1379 1380 /* Calc SV bit */ 1381 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1382 /* Calc AV/SAV bits */ 1383 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 1384 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 1385 /* calc SAV */ 1386 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1387 1388 tcg_temp_free_i64(t1); 1389 tcg_temp_free_i64(t2); 1390 tcg_temp_free_i64(t3); 1391 } 1392 1393 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 1394 { 1395 TCGv temp = tcg_const_i32(con); 1396 gen_msub32_d(ret, r1, r2, temp); 1397 tcg_temp_free(temp); 1398 } 1399 1400 static inline void 1401 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1402 TCGv r3) 1403 { 1404 TCGv t1 = tcg_temp_new(); 1405 TCGv t2 = tcg_temp_new(); 1406 TCGv t3 = tcg_temp_new(); 1407 TCGv t4 = tcg_temp_new(); 1408 1409 tcg_gen_muls2_tl(t1, t2, r1, r3); 1410 /* only the sub can overflow */ 1411 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); 1412 /* calc V bit */ 1413 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 1414 tcg_gen_xor_tl(t1, r2_high, t2); 1415 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); 1416 /* Calc SV bit */ 1417 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1418 /* Calc AV/SAV bits */ 1419 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 1420 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 1421 /* calc SAV */ 1422 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1423 /* write back the result */ 1424 tcg_gen_mov_tl(ret_low, t3); 1425 tcg_gen_mov_tl(ret_high, t4); 1426 1427 tcg_temp_free(t1); 1428 tcg_temp_free(t2); 1429 tcg_temp_free(t3); 1430 tcg_temp_free(t4); 1431 } 1432 1433 static inline void 1434 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1435 int32_t con) 1436 { 1437 TCGv temp = tcg_const_i32(con); 1438 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1439 tcg_temp_free(temp); 1440 } 1441 1442 static inline void 1443 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1444 TCGv r3) 1445 { 1446 TCGv_i64 t1 = tcg_temp_new_i64(); 1447 TCGv_i64 t2 = tcg_temp_new_i64(); 1448 TCGv_i64 t3 = tcg_temp_new_i64(); 1449 1450 tcg_gen_extu_i32_i64(t1, r1); 1451 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 1452 tcg_gen_extu_i32_i64(t3, r3); 1453 1454 tcg_gen_mul_i64(t1, t1, t3); 1455 tcg_gen_sub_i64(t3, t2, t1); 1456 tcg_gen_extr_i64_i32(ret_low, ret_high, t3); 1457 /* calc V bit, only the sub can overflow, if t1 > t2 */ 1458 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); 1459 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1460 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1461 /* Calc SV bit */ 1462 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1463 /* Calc AV/SAV bits */ 1464 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 1465 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 1466 /* calc SAV */ 1467 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1468 1469 tcg_temp_free_i64(t1); 1470 tcg_temp_free_i64(t2); 1471 tcg_temp_free_i64(t3); 1472 } 1473 1474 static inline void 1475 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1476 int32_t con) 1477 { 1478 TCGv temp = tcg_const_i32(con); 1479 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1480 tcg_temp_free(temp); 1481 } 1482 1483 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) 1484 { 1485 TCGv temp = tcg_const_i32(r2); 1486 gen_add_d(ret, r1, temp); 1487 tcg_temp_free(temp); 1488 } 1489 /* calculate the carry bit too */ 1490 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) 1491 { 1492 TCGv t0 = tcg_temp_new_i32(); 1493 TCGv result = tcg_temp_new_i32(); 1494 1495 tcg_gen_movi_tl(t0, 0); 1496 /* Addition and set C/V/SV bits */ 1497 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); 1498 /* calc V bit */ 1499 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1500 tcg_gen_xor_tl(t0, r1, r2); 1501 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1502 /* Calc SV bit */ 1503 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1504 /* Calc AV/SAV bits */ 1505 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1506 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1507 /* calc SAV */ 1508 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1509 /* write back result */ 1510 tcg_gen_mov_tl(ret, result); 1511 1512 tcg_temp_free(result); 1513 tcg_temp_free(t0); 1514 } 1515 1516 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) 1517 { 1518 TCGv temp = tcg_const_i32(con); 1519 gen_add_CC(ret, r1, temp); 1520 tcg_temp_free(temp); 1521 } 1522 1523 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) 1524 { 1525 TCGv carry = tcg_temp_new_i32(); 1526 TCGv t0 = tcg_temp_new_i32(); 1527 TCGv result = tcg_temp_new_i32(); 1528 1529 tcg_gen_movi_tl(t0, 0); 1530 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); 1531 /* Addition, carry and set C/V/SV bits */ 1532 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); 1533 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); 1534 /* calc V bit */ 1535 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1536 tcg_gen_xor_tl(t0, r1, r2); 1537 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1538 /* Calc SV bit */ 1539 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1540 /* Calc AV/SAV bits */ 1541 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1542 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1543 /* calc SAV */ 1544 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1545 /* write back result */ 1546 tcg_gen_mov_tl(ret, result); 1547 1548 tcg_temp_free(result); 1549 tcg_temp_free(t0); 1550 tcg_temp_free(carry); 1551 } 1552 1553 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) 1554 { 1555 TCGv temp = tcg_const_i32(con); 1556 gen_addc_CC(ret, r1, temp); 1557 tcg_temp_free(temp); 1558 } 1559 1560 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1561 TCGv r4) 1562 { 1563 TCGv temp = tcg_temp_new(); 1564 TCGv temp2 = tcg_temp_new(); 1565 TCGv result = tcg_temp_new(); 1566 TCGv mask = tcg_temp_new(); 1567 TCGv t0 = tcg_const_i32(0); 1568 1569 /* create mask for sticky bits */ 1570 tcg_gen_setcond_tl(cond, mask, r4, t0); 1571 tcg_gen_shli_tl(mask, mask, 31); 1572 1573 tcg_gen_add_tl(result, r1, r2); 1574 /* Calc PSW_V */ 1575 tcg_gen_xor_tl(temp, result, r1); 1576 tcg_gen_xor_tl(temp2, r1, r2); 1577 tcg_gen_andc_tl(temp, temp, temp2); 1578 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1579 /* Set PSW_SV */ 1580 tcg_gen_and_tl(temp, temp, mask); 1581 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1582 /* calc AV bit */ 1583 tcg_gen_add_tl(temp, result, result); 1584 tcg_gen_xor_tl(temp, temp, result); 1585 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1586 /* calc SAV bit */ 1587 tcg_gen_and_tl(temp, temp, mask); 1588 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1589 /* write back result */ 1590 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1591 1592 tcg_temp_free(t0); 1593 tcg_temp_free(temp); 1594 tcg_temp_free(temp2); 1595 tcg_temp_free(result); 1596 tcg_temp_free(mask); 1597 } 1598 1599 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, 1600 TCGv r3, TCGv r4) 1601 { 1602 TCGv temp = tcg_const_i32(r2); 1603 gen_cond_add(cond, r1, temp, r3, r4); 1604 tcg_temp_free(temp); 1605 } 1606 1607 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) 1608 { 1609 TCGv temp = tcg_temp_new_i32(); 1610 TCGv result = tcg_temp_new_i32(); 1611 1612 tcg_gen_sub_tl(result, r1, r2); 1613 /* calc V bit */ 1614 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1615 tcg_gen_xor_tl(temp, r1, r2); 1616 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1617 /* calc SV bit */ 1618 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1619 /* Calc AV bit */ 1620 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1621 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1622 /* calc SAV bit */ 1623 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1624 /* write back result */ 1625 tcg_gen_mov_tl(ret, result); 1626 1627 tcg_temp_free(temp); 1628 tcg_temp_free(result); 1629 } 1630 1631 static inline void 1632 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 1633 { 1634 TCGv temp = tcg_temp_new(); 1635 TCGv_i64 t0 = tcg_temp_new_i64(); 1636 TCGv_i64 t1 = tcg_temp_new_i64(); 1637 TCGv_i64 result = tcg_temp_new_i64(); 1638 1639 tcg_gen_sub_i64(result, r1, r2); 1640 /* calc v bit */ 1641 tcg_gen_xor_i64(t1, result, r1); 1642 tcg_gen_xor_i64(t0, r1, r2); 1643 tcg_gen_and_i64(t1, t1, t0); 1644 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 1645 /* calc SV bit */ 1646 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1647 /* calc AV/SAV bits */ 1648 tcg_gen_extrh_i64_i32(temp, result); 1649 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 1650 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 1651 /* calc SAV */ 1652 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1653 /* write back result */ 1654 tcg_gen_mov_i64(ret, result); 1655 1656 tcg_temp_free(temp); 1657 tcg_temp_free_i64(result); 1658 tcg_temp_free_i64(t0); 1659 tcg_temp_free_i64(t1); 1660 } 1661 1662 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) 1663 { 1664 TCGv result = tcg_temp_new(); 1665 TCGv temp = tcg_temp_new(); 1666 1667 tcg_gen_sub_tl(result, r1, r2); 1668 /* calc C bit */ 1669 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); 1670 /* calc V bit */ 1671 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1672 tcg_gen_xor_tl(temp, r1, r2); 1673 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1674 /* calc SV bit */ 1675 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1676 /* Calc AV bit */ 1677 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1678 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1679 /* calc SAV bit */ 1680 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1681 /* write back result */ 1682 tcg_gen_mov_tl(ret, result); 1683 1684 tcg_temp_free(result); 1685 tcg_temp_free(temp); 1686 } 1687 1688 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) 1689 { 1690 TCGv temp = tcg_temp_new(); 1691 tcg_gen_not_tl(temp, r2); 1692 gen_addc_CC(ret, r1, temp); 1693 tcg_temp_free(temp); 1694 } 1695 1696 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1697 TCGv r4) 1698 { 1699 TCGv temp = tcg_temp_new(); 1700 TCGv temp2 = tcg_temp_new(); 1701 TCGv result = tcg_temp_new(); 1702 TCGv mask = tcg_temp_new(); 1703 TCGv t0 = tcg_const_i32(0); 1704 1705 /* create mask for sticky bits */ 1706 tcg_gen_setcond_tl(cond, mask, r4, t0); 1707 tcg_gen_shli_tl(mask, mask, 31); 1708 1709 tcg_gen_sub_tl(result, r1, r2); 1710 /* Calc PSW_V */ 1711 tcg_gen_xor_tl(temp, result, r1); 1712 tcg_gen_xor_tl(temp2, r1, r2); 1713 tcg_gen_and_tl(temp, temp, temp2); 1714 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1715 /* Set PSW_SV */ 1716 tcg_gen_and_tl(temp, temp, mask); 1717 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1718 /* calc AV bit */ 1719 tcg_gen_add_tl(temp, result, result); 1720 tcg_gen_xor_tl(temp, temp, result); 1721 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1722 /* calc SAV bit */ 1723 tcg_gen_and_tl(temp, temp, mask); 1724 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1725 /* write back result */ 1726 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1727 1728 tcg_temp_free(t0); 1729 tcg_temp_free(temp); 1730 tcg_temp_free(temp2); 1731 tcg_temp_free(result); 1732 tcg_temp_free(mask); 1733 } 1734 1735 static inline void 1736 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1737 TCGv r3, uint32_t n, uint32_t mode) 1738 { 1739 TCGv temp = tcg_const_i32(n); 1740 TCGv temp2 = tcg_temp_new(); 1741 TCGv_i64 temp64 = tcg_temp_new_i64(); 1742 switch (mode) { 1743 case MODE_LL: 1744 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1745 break; 1746 case MODE_LU: 1747 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1748 break; 1749 case MODE_UL: 1750 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1751 break; 1752 case MODE_UU: 1753 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1754 break; 1755 } 1756 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1757 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1758 tcg_gen_sub_tl, tcg_gen_sub_tl); 1759 tcg_temp_free(temp); 1760 tcg_temp_free(temp2); 1761 tcg_temp_free_i64(temp64); 1762 } 1763 1764 static inline void 1765 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1766 TCGv r3, uint32_t n, uint32_t mode) 1767 { 1768 TCGv temp = tcg_const_i32(n); 1769 TCGv temp2 = tcg_temp_new(); 1770 TCGv temp3 = tcg_temp_new(); 1771 TCGv_i64 temp64 = tcg_temp_new_i64(); 1772 1773 switch (mode) { 1774 case MODE_LL: 1775 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1776 break; 1777 case MODE_LU: 1778 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1779 break; 1780 case MODE_UL: 1781 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1782 break; 1783 case MODE_UU: 1784 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1785 break; 1786 } 1787 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1788 gen_subs(ret_low, r1_low, temp); 1789 tcg_gen_mov_tl(temp, cpu_PSW_V); 1790 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 1791 gen_subs(ret_high, r1_high, temp2); 1792 /* combine v bits */ 1793 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 1794 /* combine av bits */ 1795 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 1796 1797 tcg_temp_free(temp); 1798 tcg_temp_free(temp2); 1799 tcg_temp_free(temp3); 1800 tcg_temp_free_i64(temp64); 1801 } 1802 1803 static inline void 1804 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1805 TCGv r3, uint32_t n, uint32_t mode) 1806 { 1807 TCGv temp = tcg_const_i32(n); 1808 TCGv_i64 temp64 = tcg_temp_new_i64(); 1809 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1810 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1811 switch (mode) { 1812 case MODE_LL: 1813 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 1814 break; 1815 case MODE_LU: 1816 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 1817 break; 1818 case MODE_UL: 1819 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 1820 break; 1821 case MODE_UU: 1822 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 1823 break; 1824 } 1825 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1826 gen_sub64_d(temp64_3, temp64_2, temp64); 1827 /* write back result */ 1828 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 1829 1830 tcg_temp_free(temp); 1831 tcg_temp_free_i64(temp64); 1832 tcg_temp_free_i64(temp64_2); 1833 tcg_temp_free_i64(temp64_3); 1834 } 1835 1836 static inline void 1837 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1838 TCGv r3, uint32_t n, uint32_t mode) 1839 { 1840 TCGv temp = tcg_const_i32(n); 1841 TCGv_i64 temp64 = tcg_temp_new_i64(); 1842 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1843 switch (mode) { 1844 case MODE_LL: 1845 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 1846 break; 1847 case MODE_LU: 1848 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 1849 break; 1850 case MODE_UL: 1851 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 1852 break; 1853 case MODE_UU: 1854 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 1855 break; 1856 } 1857 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1858 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 1859 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 1860 1861 tcg_temp_free(temp); 1862 tcg_temp_free_i64(temp64); 1863 tcg_temp_free_i64(temp64_2); 1864 } 1865 1866 static inline void 1867 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 1868 uint32_t mode) 1869 { 1870 TCGv temp = tcg_const_i32(n); 1871 TCGv_i64 temp64 = tcg_temp_new_i64(); 1872 switch (mode) { 1873 case MODE_LL: 1874 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1875 break; 1876 case MODE_LU: 1877 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1878 break; 1879 case MODE_UL: 1880 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1881 break; 1882 case MODE_UU: 1883 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1884 break; 1885 } 1886 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); 1887 1888 tcg_temp_free(temp); 1889 tcg_temp_free_i64(temp64); 1890 } 1891 1892 static inline void 1893 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1894 { 1895 TCGv temp = tcg_temp_new(); 1896 TCGv temp2 = tcg_temp_new(); 1897 1898 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1899 tcg_gen_shli_tl(temp, r1, 16); 1900 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); 1901 1902 tcg_temp_free(temp); 1903 tcg_temp_free(temp2); 1904 } 1905 1906 static inline void 1907 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1908 uint32_t n, uint32_t mode) 1909 { 1910 TCGv temp = tcg_const_i32(n); 1911 TCGv_i64 temp64 = tcg_temp_new_i64(); 1912 switch (mode) { 1913 case MODE_LL: 1914 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1915 break; 1916 case MODE_LU: 1917 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1918 break; 1919 case MODE_UL: 1920 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1921 break; 1922 case MODE_UU: 1923 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1924 break; 1925 } 1926 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 1927 1928 tcg_temp_free(temp); 1929 tcg_temp_free_i64(temp64); 1930 } 1931 1932 static inline void 1933 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1934 { 1935 TCGv temp = tcg_temp_new(); 1936 TCGv temp2 = tcg_temp_new(); 1937 1938 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1939 tcg_gen_shli_tl(temp, r1, 16); 1940 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); 1941 1942 tcg_temp_free(temp); 1943 tcg_temp_free(temp2); 1944 } 1945 1946 static inline void 1947 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1948 { 1949 TCGv temp = tcg_const_i32(n); 1950 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); 1951 tcg_temp_free(temp); 1952 } 1953 1954 static inline void 1955 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1956 { 1957 TCGv temp = tcg_const_i32(n); 1958 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); 1959 tcg_temp_free(temp); 1960 } 1961 1962 static inline void 1963 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1964 uint32_t up_shift, CPUTriCoreState *env) 1965 { 1966 TCGv temp = tcg_temp_new(); 1967 TCGv temp2 = tcg_temp_new(); 1968 TCGv temp3 = tcg_temp_new(); 1969 TCGv_i64 t1 = tcg_temp_new_i64(); 1970 TCGv_i64 t2 = tcg_temp_new_i64(); 1971 TCGv_i64 t3 = tcg_temp_new_i64(); 1972 TCGv_i64 t4 = tcg_temp_new_i64(); 1973 1974 tcg_gen_ext_i32_i64(t2, arg2); 1975 tcg_gen_ext_i32_i64(t3, arg3); 1976 1977 tcg_gen_mul_i64(t2, t2, t3); 1978 1979 tcg_gen_ext_i32_i64(t1, arg1); 1980 /* if we shift part of the fraction out, we need to round up */ 1981 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1982 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1983 tcg_gen_sari_i64(t2, t2, up_shift - n); 1984 tcg_gen_add_i64(t2, t2, t4); 1985 1986 tcg_gen_sub_i64(t3, t1, t2); 1987 tcg_gen_extrl_i64_i32(temp3, t3); 1988 /* calc v bit */ 1989 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1990 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1991 tcg_gen_or_i64(t1, t1, t2); 1992 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1993 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1994 /* Calc SV bit */ 1995 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1996 /* Calc AV/SAV bits */ 1997 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1998 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1999 /* calc SAV */ 2000 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2001 /* write back result */ 2002 tcg_gen_mov_tl(ret, temp3); 2003 2004 tcg_temp_free(temp); 2005 tcg_temp_free(temp2); 2006 tcg_temp_free(temp3); 2007 tcg_temp_free_i64(t1); 2008 tcg_temp_free_i64(t2); 2009 tcg_temp_free_i64(t3); 2010 tcg_temp_free_i64(t4); 2011 } 2012 2013 static inline void 2014 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 2015 { 2016 TCGv temp = tcg_temp_new(); 2017 TCGv temp2 = tcg_temp_new(); 2018 if (n == 0) { 2019 tcg_gen_mul_tl(temp, arg2, arg3); 2020 } else { /* n is expected to be 1 */ 2021 tcg_gen_mul_tl(temp, arg2, arg3); 2022 tcg_gen_shli_tl(temp, temp, 1); 2023 /* catch special case r1 = r2 = 0x8000 */ 2024 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2025 tcg_gen_sub_tl(temp, temp, temp2); 2026 } 2027 gen_sub_d(ret, arg1, temp); 2028 2029 tcg_temp_free(temp); 2030 tcg_temp_free(temp2); 2031 } 2032 2033 static inline void 2034 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 2035 { 2036 TCGv temp = tcg_temp_new(); 2037 TCGv temp2 = tcg_temp_new(); 2038 if (n == 0) { 2039 tcg_gen_mul_tl(temp, arg2, arg3); 2040 } else { /* n is expected to be 1 */ 2041 tcg_gen_mul_tl(temp, arg2, arg3); 2042 tcg_gen_shli_tl(temp, temp, 1); 2043 /* catch special case r1 = r2 = 0x8000 */ 2044 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2045 tcg_gen_sub_tl(temp, temp, temp2); 2046 } 2047 gen_subs(ret, arg1, temp); 2048 2049 tcg_temp_free(temp); 2050 tcg_temp_free(temp2); 2051 } 2052 2053 static inline void 2054 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2055 TCGv arg3, uint32_t n) 2056 { 2057 TCGv temp = tcg_temp_new(); 2058 TCGv temp2 = tcg_temp_new(); 2059 TCGv_i64 t1 = tcg_temp_new_i64(); 2060 TCGv_i64 t2 = tcg_temp_new_i64(); 2061 TCGv_i64 t3 = tcg_temp_new_i64(); 2062 2063 if (n == 0) { 2064 tcg_gen_mul_tl(temp, arg2, arg3); 2065 } else { /* n is expected to be 1 */ 2066 tcg_gen_mul_tl(temp, arg2, arg3); 2067 tcg_gen_shli_tl(temp, temp, 1); 2068 /* catch special case r1 = r2 = 0x8000 */ 2069 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2070 tcg_gen_sub_tl(temp, temp, temp2); 2071 } 2072 tcg_gen_ext_i32_i64(t2, temp); 2073 tcg_gen_shli_i64(t2, t2, 16); 2074 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 2075 gen_sub64_d(t3, t1, t2); 2076 /* write back result */ 2077 tcg_gen_extr_i64_i32(rl, rh, t3); 2078 2079 tcg_temp_free_i64(t1); 2080 tcg_temp_free_i64(t2); 2081 tcg_temp_free_i64(t3); 2082 tcg_temp_free(temp); 2083 tcg_temp_free(temp2); 2084 } 2085 2086 static inline void 2087 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2088 TCGv arg3, uint32_t n) 2089 { 2090 TCGv temp = tcg_temp_new(); 2091 TCGv temp2 = tcg_temp_new(); 2092 TCGv_i64 t1 = tcg_temp_new_i64(); 2093 TCGv_i64 t2 = tcg_temp_new_i64(); 2094 2095 if (n == 0) { 2096 tcg_gen_mul_tl(temp, arg2, arg3); 2097 } else { /* n is expected to be 1 */ 2098 tcg_gen_mul_tl(temp, arg2, arg3); 2099 tcg_gen_shli_tl(temp, temp, 1); 2100 /* catch special case r1 = r2 = 0x8000 */ 2101 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2102 tcg_gen_sub_tl(temp, temp, temp2); 2103 } 2104 tcg_gen_ext_i32_i64(t2, temp); 2105 tcg_gen_shli_i64(t2, t2, 16); 2106 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 2107 2108 gen_helper_sub64_ssov(t1, cpu_env, t1, t2); 2109 tcg_gen_extr_i64_i32(rl, rh, t1); 2110 2111 tcg_temp_free(temp); 2112 tcg_temp_free(temp2); 2113 tcg_temp_free_i64(t1); 2114 tcg_temp_free_i64(t2); 2115 } 2116 2117 static inline void 2118 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2119 TCGv arg3, uint32_t n, CPUTriCoreState *env) 2120 { 2121 TCGv_i64 t1 = tcg_temp_new_i64(); 2122 TCGv_i64 t2 = tcg_temp_new_i64(); 2123 TCGv_i64 t3 = tcg_temp_new_i64(); 2124 TCGv_i64 t4 = tcg_temp_new_i64(); 2125 TCGv temp, temp2; 2126 2127 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 2128 tcg_gen_ext_i32_i64(t2, arg2); 2129 tcg_gen_ext_i32_i64(t3, arg3); 2130 2131 tcg_gen_mul_i64(t2, t2, t3); 2132 if (n != 0) { 2133 tcg_gen_shli_i64(t2, t2, 1); 2134 } 2135 tcg_gen_sub_i64(t4, t1, t2); 2136 /* calc v bit */ 2137 tcg_gen_xor_i64(t3, t4, t1); 2138 tcg_gen_xor_i64(t2, t1, t2); 2139 tcg_gen_and_i64(t3, t3, t2); 2140 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 2141 /* We produce an overflow on the host if the mul before was 2142 (0x80000000 * 0x80000000) << 1). If this is the 2143 case, we negate the ovf. */ 2144 if (n == 1) { 2145 temp = tcg_temp_new(); 2146 temp2 = tcg_temp_new(); 2147 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 2148 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 2149 tcg_gen_and_tl(temp, temp, temp2); 2150 tcg_gen_shli_tl(temp, temp, 31); 2151 /* negate v bit, if special condition */ 2152 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 2153 2154 tcg_temp_free(temp); 2155 tcg_temp_free(temp2); 2156 } 2157 /* write back result */ 2158 tcg_gen_extr_i64_i32(rl, rh, t4); 2159 /* Calc SV bit */ 2160 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2161 /* Calc AV/SAV bits */ 2162 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2163 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2164 /* calc SAV */ 2165 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2166 2167 tcg_temp_free_i64(t1); 2168 tcg_temp_free_i64(t2); 2169 tcg_temp_free_i64(t3); 2170 tcg_temp_free_i64(t4); 2171 } 2172 2173 static inline void 2174 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 2175 uint32_t up_shift) 2176 { 2177 TCGv_i64 t1 = tcg_temp_new_i64(); 2178 TCGv_i64 t2 = tcg_temp_new_i64(); 2179 TCGv_i64 t3 = tcg_temp_new_i64(); 2180 TCGv_i64 t4 = tcg_temp_new_i64(); 2181 2182 tcg_gen_ext_i32_i64(t1, arg1); 2183 tcg_gen_ext_i32_i64(t2, arg2); 2184 tcg_gen_ext_i32_i64(t3, arg3); 2185 2186 tcg_gen_mul_i64(t2, t2, t3); 2187 /* if we shift part of the fraction out, we need to round up */ 2188 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 2189 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 2190 tcg_gen_sari_i64(t3, t2, up_shift - n); 2191 tcg_gen_add_i64(t3, t3, t4); 2192 2193 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); 2194 2195 tcg_temp_free_i64(t1); 2196 tcg_temp_free_i64(t2); 2197 tcg_temp_free_i64(t3); 2198 tcg_temp_free_i64(t4); 2199 } 2200 2201 static inline void 2202 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2203 TCGv arg3, uint32_t n) 2204 { 2205 TCGv_i64 r1 = tcg_temp_new_i64(); 2206 TCGv temp = tcg_const_i32(n); 2207 2208 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 2209 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); 2210 tcg_gen_extr_i64_i32(rl, rh, r1); 2211 2212 tcg_temp_free_i64(r1); 2213 tcg_temp_free(temp); 2214 } 2215 2216 static inline void 2217 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2218 TCGv r3, uint32_t n, uint32_t mode) 2219 { 2220 TCGv temp = tcg_const_i32(n); 2221 TCGv temp2 = tcg_temp_new(); 2222 TCGv_i64 temp64 = tcg_temp_new_i64(); 2223 switch (mode) { 2224 case MODE_LL: 2225 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2226 break; 2227 case MODE_LU: 2228 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2229 break; 2230 case MODE_UL: 2231 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2232 break; 2233 case MODE_UU: 2234 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2235 break; 2236 } 2237 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2238 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 2239 tcg_gen_add_tl, tcg_gen_sub_tl); 2240 tcg_temp_free(temp); 2241 tcg_temp_free(temp2); 2242 tcg_temp_free_i64(temp64); 2243 } 2244 2245 static inline void 2246 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2247 TCGv r3, uint32_t n, uint32_t mode) 2248 { 2249 TCGv temp = tcg_const_i32(n); 2250 TCGv_i64 temp64 = tcg_temp_new_i64(); 2251 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2252 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 2253 switch (mode) { 2254 case MODE_LL: 2255 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2256 break; 2257 case MODE_LU: 2258 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2259 break; 2260 case MODE_UL: 2261 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2262 break; 2263 case MODE_UU: 2264 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2265 break; 2266 } 2267 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 2268 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2269 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2270 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2271 tcg_gen_shli_i64(temp64, temp64, 16); 2272 2273 gen_sub64_d(temp64_2, temp64_3, temp64); 2274 /* write back result */ 2275 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 2276 2277 tcg_temp_free(temp); 2278 tcg_temp_free_i64(temp64); 2279 tcg_temp_free_i64(temp64_2); 2280 tcg_temp_free_i64(temp64_3); 2281 } 2282 2283 static inline void 2284 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2285 { 2286 TCGv temp = tcg_const_i32(n); 2287 TCGv temp2 = tcg_temp_new(); 2288 TCGv_i64 temp64 = tcg_temp_new_i64(); 2289 switch (mode) { 2290 case MODE_LL: 2291 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2292 break; 2293 case MODE_LU: 2294 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2295 break; 2296 case MODE_UL: 2297 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2298 break; 2299 case MODE_UU: 2300 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2301 break; 2302 } 2303 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2304 tcg_gen_shli_tl(temp, r1, 16); 2305 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); 2306 2307 tcg_temp_free(temp); 2308 tcg_temp_free(temp2); 2309 tcg_temp_free_i64(temp64); 2310 } 2311 2312 static inline void 2313 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2314 TCGv r3, uint32_t n, uint32_t mode) 2315 { 2316 TCGv temp = tcg_const_i32(n); 2317 TCGv temp2 = tcg_temp_new(); 2318 TCGv temp3 = tcg_temp_new(); 2319 TCGv_i64 temp64 = tcg_temp_new_i64(); 2320 2321 switch (mode) { 2322 case MODE_LL: 2323 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2324 break; 2325 case MODE_LU: 2326 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2327 break; 2328 case MODE_UL: 2329 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2330 break; 2331 case MODE_UU: 2332 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2333 break; 2334 } 2335 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2336 gen_adds(ret_low, r1_low, temp); 2337 tcg_gen_mov_tl(temp, cpu_PSW_V); 2338 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 2339 gen_subs(ret_high, r1_high, temp2); 2340 /* combine v bits */ 2341 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 2342 /* combine av bits */ 2343 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 2344 2345 tcg_temp_free(temp); 2346 tcg_temp_free(temp2); 2347 tcg_temp_free(temp3); 2348 tcg_temp_free_i64(temp64); 2349 } 2350 2351 static inline void 2352 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2353 TCGv r3, uint32_t n, uint32_t mode) 2354 { 2355 TCGv temp = tcg_const_i32(n); 2356 TCGv_i64 temp64 = tcg_temp_new_i64(); 2357 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2358 2359 switch (mode) { 2360 case MODE_LL: 2361 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2362 break; 2363 case MODE_LU: 2364 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2365 break; 2366 case MODE_UL: 2367 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2368 break; 2369 case MODE_UU: 2370 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2371 break; 2372 } 2373 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2374 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2375 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2376 tcg_gen_shli_i64(temp64, temp64, 16); 2377 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 2378 2379 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 2380 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2381 2382 tcg_temp_free(temp); 2383 tcg_temp_free_i64(temp64); 2384 tcg_temp_free_i64(temp64_2); 2385 } 2386 2387 static inline void 2388 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2389 { 2390 TCGv temp = tcg_const_i32(n); 2391 TCGv temp2 = tcg_temp_new(); 2392 TCGv_i64 temp64 = tcg_temp_new_i64(); 2393 switch (mode) { 2394 case MODE_LL: 2395 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2396 break; 2397 case MODE_LU: 2398 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2399 break; 2400 case MODE_UL: 2401 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2402 break; 2403 case MODE_UU: 2404 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2405 break; 2406 } 2407 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2408 tcg_gen_shli_tl(temp, r1, 16); 2409 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); 2410 2411 tcg_temp_free(temp); 2412 tcg_temp_free(temp2); 2413 tcg_temp_free_i64(temp64); 2414 } 2415 2416 static inline void gen_abs(TCGv ret, TCGv r1) 2417 { 2418 tcg_gen_abs_tl(ret, r1); 2419 /* overflow can only happen, if r1 = 0x80000000 */ 2420 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); 2421 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2422 /* calc SV bit */ 2423 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2424 /* Calc AV bit */ 2425 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2426 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2427 /* calc SAV bit */ 2428 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2429 } 2430 2431 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) 2432 { 2433 TCGv temp = tcg_temp_new_i32(); 2434 TCGv result = tcg_temp_new_i32(); 2435 2436 tcg_gen_sub_tl(result, r1, r2); 2437 tcg_gen_sub_tl(temp, r2, r1); 2438 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); 2439 2440 /* calc V bit */ 2441 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 2442 tcg_gen_xor_tl(temp, result, r2); 2443 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); 2444 tcg_gen_xor_tl(temp, r1, r2); 2445 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 2446 /* calc SV bit */ 2447 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2448 /* Calc AV bit */ 2449 tcg_gen_add_tl(cpu_PSW_AV, result, result); 2450 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 2451 /* calc SAV bit */ 2452 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2453 /* write back result */ 2454 tcg_gen_mov_tl(ret, result); 2455 2456 tcg_temp_free(temp); 2457 tcg_temp_free(result); 2458 } 2459 2460 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) 2461 { 2462 TCGv temp = tcg_const_i32(con); 2463 gen_absdif(ret, r1, temp); 2464 tcg_temp_free(temp); 2465 } 2466 2467 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) 2468 { 2469 TCGv temp = tcg_const_i32(con); 2470 gen_helper_absdif_ssov(ret, cpu_env, r1, temp); 2471 tcg_temp_free(temp); 2472 } 2473 2474 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) 2475 { 2476 TCGv high = tcg_temp_new(); 2477 TCGv low = tcg_temp_new(); 2478 2479 tcg_gen_muls2_tl(low, high, r1, r2); 2480 tcg_gen_mov_tl(ret, low); 2481 /* calc V bit */ 2482 tcg_gen_sari_tl(low, low, 31); 2483 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); 2484 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2485 /* calc SV bit */ 2486 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2487 /* Calc AV bit */ 2488 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2489 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2490 /* calc SAV bit */ 2491 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2492 2493 tcg_temp_free(high); 2494 tcg_temp_free(low); 2495 } 2496 2497 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) 2498 { 2499 TCGv temp = tcg_const_i32(con); 2500 gen_mul_i32s(ret, r1, temp); 2501 tcg_temp_free(temp); 2502 } 2503 2504 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2505 { 2506 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); 2507 /* clear V bit */ 2508 tcg_gen_movi_tl(cpu_PSW_V, 0); 2509 /* calc SV bit */ 2510 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2511 /* Calc AV bit */ 2512 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2513 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2514 /* calc SAV bit */ 2515 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2516 } 2517 2518 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, 2519 int32_t con) 2520 { 2521 TCGv temp = tcg_const_i32(con); 2522 gen_mul_i64s(ret_low, ret_high, r1, temp); 2523 tcg_temp_free(temp); 2524 } 2525 2526 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2527 { 2528 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); 2529 /* clear V bit */ 2530 tcg_gen_movi_tl(cpu_PSW_V, 0); 2531 /* calc SV bit */ 2532 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2533 /* Calc AV bit */ 2534 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2535 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2536 /* calc SAV bit */ 2537 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2538 } 2539 2540 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, 2541 int32_t con) 2542 { 2543 TCGv temp = tcg_const_i32(con); 2544 gen_mul_i64u(ret_low, ret_high, r1, temp); 2545 tcg_temp_free(temp); 2546 } 2547 2548 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) 2549 { 2550 TCGv temp = tcg_const_i32(con); 2551 gen_helper_mul_ssov(ret, cpu_env, r1, temp); 2552 tcg_temp_free(temp); 2553 } 2554 2555 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) 2556 { 2557 TCGv temp = tcg_const_i32(con); 2558 gen_helper_mul_suov(ret, cpu_env, r1, temp); 2559 tcg_temp_free(temp); 2560 } 2561 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ 2562 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2563 { 2564 TCGv temp = tcg_const_i32(con); 2565 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); 2566 tcg_temp_free(temp); 2567 } 2568 2569 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2570 { 2571 TCGv temp = tcg_const_i32(con); 2572 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); 2573 tcg_temp_free(temp); 2574 } 2575 2576 static void 2577 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) 2578 { 2579 TCGv temp = tcg_temp_new(); 2580 TCGv_i64 temp_64 = tcg_temp_new_i64(); 2581 TCGv_i64 temp2_64 = tcg_temp_new_i64(); 2582 2583 if (n == 0) { 2584 if (up_shift == 32) { 2585 tcg_gen_muls2_tl(rh, rl, arg1, arg2); 2586 } else if (up_shift == 16) { 2587 tcg_gen_ext_i32_i64(temp_64, arg1); 2588 tcg_gen_ext_i32_i64(temp2_64, arg2); 2589 2590 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2591 tcg_gen_shri_i64(temp_64, temp_64, up_shift); 2592 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2593 } else { 2594 tcg_gen_muls2_tl(rl, rh, arg1, arg2); 2595 } 2596 /* reset v bit */ 2597 tcg_gen_movi_tl(cpu_PSW_V, 0); 2598 } else { /* n is expected to be 1 */ 2599 tcg_gen_ext_i32_i64(temp_64, arg1); 2600 tcg_gen_ext_i32_i64(temp2_64, arg2); 2601 2602 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2603 2604 if (up_shift == 0) { 2605 tcg_gen_shli_i64(temp_64, temp_64, 1); 2606 } else { 2607 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); 2608 } 2609 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2610 /* overflow only occurs if r1 = r2 = 0x8000 */ 2611 if (up_shift == 0) {/* result is 64 bit */ 2612 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, 2613 0x80000000); 2614 } else { /* result is 32 bit */ 2615 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, 2616 0x80000000); 2617 } 2618 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2619 /* calc sv overflow bit */ 2620 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2621 } 2622 /* calc av overflow bit */ 2623 if (up_shift == 0) { 2624 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2625 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2626 } else { 2627 tcg_gen_add_tl(cpu_PSW_AV, rl, rl); 2628 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); 2629 } 2630 /* calc sav overflow bit */ 2631 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2632 tcg_temp_free(temp); 2633 tcg_temp_free_i64(temp_64); 2634 tcg_temp_free_i64(temp2_64); 2635 } 2636 2637 static void 2638 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2639 { 2640 TCGv temp = tcg_temp_new(); 2641 if (n == 0) { 2642 tcg_gen_mul_tl(ret, arg1, arg2); 2643 } else { /* n is expected to be 1 */ 2644 tcg_gen_mul_tl(ret, arg1, arg2); 2645 tcg_gen_shli_tl(ret, ret, 1); 2646 /* catch special case r1 = r2 = 0x8000 */ 2647 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); 2648 tcg_gen_sub_tl(ret, ret, temp); 2649 } 2650 /* reset v bit */ 2651 tcg_gen_movi_tl(cpu_PSW_V, 0); 2652 /* calc av overflow bit */ 2653 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2654 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2655 /* calc sav overflow bit */ 2656 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2657 2658 tcg_temp_free(temp); 2659 } 2660 2661 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2662 { 2663 TCGv temp = tcg_temp_new(); 2664 if (n == 0) { 2665 tcg_gen_mul_tl(ret, arg1, arg2); 2666 tcg_gen_addi_tl(ret, ret, 0x8000); 2667 } else { 2668 tcg_gen_mul_tl(ret, arg1, arg2); 2669 tcg_gen_shli_tl(ret, ret, 1); 2670 tcg_gen_addi_tl(ret, ret, 0x8000); 2671 /* catch special case r1 = r2 = 0x8000 */ 2672 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); 2673 tcg_gen_muli_tl(temp, temp, 0x8001); 2674 tcg_gen_sub_tl(ret, ret, temp); 2675 } 2676 /* reset v bit */ 2677 tcg_gen_movi_tl(cpu_PSW_V, 0); 2678 /* calc av overflow bit */ 2679 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2680 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2681 /* calc sav overflow bit */ 2682 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2683 /* cut halfword off */ 2684 tcg_gen_andi_tl(ret, ret, 0xffff0000); 2685 2686 tcg_temp_free(temp); 2687 } 2688 2689 static inline void 2690 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2691 TCGv r3) 2692 { 2693 TCGv_i64 temp64 = tcg_temp_new_i64(); 2694 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2695 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); 2696 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2697 tcg_temp_free_i64(temp64); 2698 } 2699 2700 static inline void 2701 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2702 int32_t con) 2703 { 2704 TCGv temp = tcg_const_i32(con); 2705 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2706 tcg_temp_free(temp); 2707 } 2708 2709 static inline void 2710 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2711 TCGv r3) 2712 { 2713 TCGv_i64 temp64 = tcg_temp_new_i64(); 2714 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2715 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); 2716 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2717 tcg_temp_free_i64(temp64); 2718 } 2719 2720 static inline void 2721 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2722 int32_t con) 2723 { 2724 TCGv temp = tcg_const_i32(con); 2725 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2726 tcg_temp_free(temp); 2727 } 2728 2729 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2730 { 2731 TCGv temp = tcg_const_i32(con); 2732 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); 2733 tcg_temp_free(temp); 2734 } 2735 2736 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2737 { 2738 TCGv temp = tcg_const_i32(con); 2739 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); 2740 tcg_temp_free(temp); 2741 } 2742 2743 static inline void 2744 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2745 TCGv r3) 2746 { 2747 TCGv_i64 temp64 = tcg_temp_new_i64(); 2748 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2749 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); 2750 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2751 tcg_temp_free_i64(temp64); 2752 } 2753 2754 static inline void 2755 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2756 int32_t con) 2757 { 2758 TCGv temp = tcg_const_i32(con); 2759 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2760 tcg_temp_free(temp); 2761 } 2762 2763 static inline void 2764 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2765 TCGv r3) 2766 { 2767 TCGv_i64 temp64 = tcg_temp_new_i64(); 2768 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2769 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); 2770 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2771 tcg_temp_free_i64(temp64); 2772 } 2773 2774 static inline void 2775 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2776 int32_t con) 2777 { 2778 TCGv temp = tcg_const_i32(con); 2779 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2780 tcg_temp_free(temp); 2781 } 2782 2783 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) 2784 { 2785 TCGv sat_neg = tcg_const_i32(low); 2786 TCGv temp = tcg_const_i32(up); 2787 2788 /* sat_neg = (arg < low ) ? low : arg; */ 2789 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg); 2790 2791 /* ret = (sat_neg > up ) ? up : sat_neg; */ 2792 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg); 2793 2794 tcg_temp_free(sat_neg); 2795 tcg_temp_free(temp); 2796 } 2797 2798 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) 2799 { 2800 TCGv temp = tcg_const_i32(up); 2801 /* sat_neg = (arg > up ) ? up : arg; */ 2802 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg); 2803 tcg_temp_free(temp); 2804 } 2805 2806 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) 2807 { 2808 if (shift_count == -32) { 2809 tcg_gen_movi_tl(ret, 0); 2810 } else if (shift_count >= 0) { 2811 tcg_gen_shli_tl(ret, r1, shift_count); 2812 } else { 2813 tcg_gen_shri_tl(ret, r1, -shift_count); 2814 } 2815 } 2816 2817 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) 2818 { 2819 TCGv temp_low, temp_high; 2820 2821 if (shiftcount == -16) { 2822 tcg_gen_movi_tl(ret, 0); 2823 } else { 2824 temp_high = tcg_temp_new(); 2825 temp_low = tcg_temp_new(); 2826 2827 tcg_gen_andi_tl(temp_low, r1, 0xffff); 2828 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); 2829 gen_shi(temp_low, temp_low, shiftcount); 2830 gen_shi(ret, temp_high, shiftcount); 2831 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); 2832 2833 tcg_temp_free(temp_low); 2834 tcg_temp_free(temp_high); 2835 } 2836 } 2837 2838 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) 2839 { 2840 uint32_t msk, msk_start; 2841 TCGv temp = tcg_temp_new(); 2842 TCGv temp2 = tcg_temp_new(); 2843 TCGv t_0 = tcg_const_i32(0); 2844 2845 if (shift_count == 0) { 2846 /* Clear PSW.C and PSW.V */ 2847 tcg_gen_movi_tl(cpu_PSW_C, 0); 2848 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); 2849 tcg_gen_mov_tl(ret, r1); 2850 } else if (shift_count == -32) { 2851 /* set PSW.C */ 2852 tcg_gen_mov_tl(cpu_PSW_C, r1); 2853 /* fill ret completely with sign bit */ 2854 tcg_gen_sari_tl(ret, r1, 31); 2855 /* clear PSW.V */ 2856 tcg_gen_movi_tl(cpu_PSW_V, 0); 2857 } else if (shift_count > 0) { 2858 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count); 2859 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count); 2860 2861 /* calc carry */ 2862 msk_start = 32 - shift_count; 2863 msk = ((1 << shift_count) - 1) << msk_start; 2864 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2865 /* calc v/sv bits */ 2866 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); 2867 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); 2868 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 2869 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2870 /* calc sv */ 2871 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); 2872 /* do shift */ 2873 tcg_gen_shli_tl(ret, r1, shift_count); 2874 2875 tcg_temp_free(t_max); 2876 tcg_temp_free(t_min); 2877 } else { 2878 /* clear PSW.V */ 2879 tcg_gen_movi_tl(cpu_PSW_V, 0); 2880 /* calc carry */ 2881 msk = (1 << -shift_count) - 1; 2882 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2883 /* do shift */ 2884 tcg_gen_sari_tl(ret, r1, -shift_count); 2885 } 2886 /* calc av overflow bit */ 2887 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2888 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2889 /* calc sav overflow bit */ 2890 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2891 2892 tcg_temp_free(temp); 2893 tcg_temp_free(temp2); 2894 tcg_temp_free(t_0); 2895 } 2896 2897 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) 2898 { 2899 gen_helper_sha_ssov(ret, cpu_env, r1, r2); 2900 } 2901 2902 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) 2903 { 2904 TCGv temp = tcg_const_i32(con); 2905 gen_shas(ret, r1, temp); 2906 tcg_temp_free(temp); 2907 } 2908 2909 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) 2910 { 2911 TCGv low, high; 2912 2913 if (shift_count == 0) { 2914 tcg_gen_mov_tl(ret, r1); 2915 } else if (shift_count > 0) { 2916 low = tcg_temp_new(); 2917 high = tcg_temp_new(); 2918 2919 tcg_gen_andi_tl(high, r1, 0xffff0000); 2920 tcg_gen_shli_tl(low, r1, shift_count); 2921 tcg_gen_shli_tl(ret, high, shift_count); 2922 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2923 2924 tcg_temp_free(low); 2925 tcg_temp_free(high); 2926 } else { 2927 low = tcg_temp_new(); 2928 high = tcg_temp_new(); 2929 2930 tcg_gen_ext16s_tl(low, r1); 2931 tcg_gen_sari_tl(low, low, -shift_count); 2932 tcg_gen_sari_tl(ret, r1, -shift_count); 2933 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2934 2935 tcg_temp_free(low); 2936 tcg_temp_free(high); 2937 } 2938 2939 } 2940 2941 /* ret = {ret[30:0], (r1 cond r2)}; */ 2942 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) 2943 { 2944 TCGv temp = tcg_temp_new(); 2945 TCGv temp2 = tcg_temp_new(); 2946 2947 tcg_gen_shli_tl(temp, ret, 1); 2948 tcg_gen_setcond_tl(cond, temp2, r1, r2); 2949 tcg_gen_or_tl(ret, temp, temp2); 2950 2951 tcg_temp_free(temp); 2952 tcg_temp_free(temp2); 2953 } 2954 2955 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) 2956 { 2957 TCGv temp = tcg_const_i32(con); 2958 gen_sh_cond(cond, ret, r1, temp); 2959 tcg_temp_free(temp); 2960 } 2961 2962 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) 2963 { 2964 gen_helper_add_ssov(ret, cpu_env, r1, r2); 2965 } 2966 2967 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) 2968 { 2969 TCGv temp = tcg_const_i32(con); 2970 gen_helper_add_ssov(ret, cpu_env, r1, temp); 2971 tcg_temp_free(temp); 2972 } 2973 2974 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) 2975 { 2976 TCGv temp = tcg_const_i32(con); 2977 gen_helper_add_suov(ret, cpu_env, r1, temp); 2978 tcg_temp_free(temp); 2979 } 2980 2981 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) 2982 { 2983 gen_helper_sub_ssov(ret, cpu_env, r1, r2); 2984 } 2985 2986 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) 2987 { 2988 gen_helper_sub_suov(ret, cpu_env, r1, r2); 2989 } 2990 2991 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, 2992 int pos1, int pos2, 2993 void(*op1)(TCGv, TCGv, TCGv), 2994 void(*op2)(TCGv, TCGv, TCGv)) 2995 { 2996 TCGv temp1, temp2; 2997 2998 temp1 = tcg_temp_new(); 2999 temp2 = tcg_temp_new(); 3000 3001 tcg_gen_shri_tl(temp2, r2, pos2); 3002 tcg_gen_shri_tl(temp1, r1, pos1); 3003 3004 (*op1)(temp1, temp1, temp2); 3005 (*op2)(temp1 , ret, temp1); 3006 3007 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); 3008 3009 tcg_temp_free(temp1); 3010 tcg_temp_free(temp2); 3011 } 3012 3013 /* ret = r1[pos1] op1 r2[pos2]; */ 3014 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, 3015 int pos1, int pos2, 3016 void(*op1)(TCGv, TCGv, TCGv)) 3017 { 3018 TCGv temp1, temp2; 3019 3020 temp1 = tcg_temp_new(); 3021 temp2 = tcg_temp_new(); 3022 3023 tcg_gen_shri_tl(temp2, r2, pos2); 3024 tcg_gen_shri_tl(temp1, r1, pos1); 3025 3026 (*op1)(ret, temp1, temp2); 3027 3028 tcg_gen_andi_tl(ret, ret, 0x1); 3029 3030 tcg_temp_free(temp1); 3031 tcg_temp_free(temp2); 3032 } 3033 3034 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, 3035 void(*op)(TCGv, TCGv, TCGv)) 3036 { 3037 TCGv temp = tcg_temp_new(); 3038 TCGv temp2 = tcg_temp_new(); 3039 /* temp = (arg1 cond arg2 )*/ 3040 tcg_gen_setcond_tl(cond, temp, r1, r2); 3041 /* temp2 = ret[0]*/ 3042 tcg_gen_andi_tl(temp2, ret, 0x1); 3043 /* temp = temp insn temp2 */ 3044 (*op)(temp, temp, temp2); 3045 /* ret = {ret[31:1], temp} */ 3046 tcg_gen_deposit_tl(ret, ret, temp, 0, 1); 3047 3048 tcg_temp_free(temp); 3049 tcg_temp_free(temp2); 3050 } 3051 3052 static inline void 3053 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, 3054 void(*op)(TCGv, TCGv, TCGv)) 3055 { 3056 TCGv temp = tcg_const_i32(con); 3057 gen_accumulating_cond(cond, ret, r1, temp, op); 3058 tcg_temp_free(temp); 3059 } 3060 3061 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ 3062 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2) 3063 { 3064 tcg_gen_setcond_tl(cond, ret, r1, r2); 3065 tcg_gen_neg_tl(ret, ret); 3066 } 3067 3068 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) 3069 { 3070 TCGv b0 = tcg_temp_new(); 3071 TCGv b1 = tcg_temp_new(); 3072 TCGv b2 = tcg_temp_new(); 3073 TCGv b3 = tcg_temp_new(); 3074 3075 /* byte 0 */ 3076 tcg_gen_andi_tl(b0, r1, 0xff); 3077 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); 3078 3079 /* byte 1 */ 3080 tcg_gen_andi_tl(b1, r1, 0xff00); 3081 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); 3082 3083 /* byte 2 */ 3084 tcg_gen_andi_tl(b2, r1, 0xff0000); 3085 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); 3086 3087 /* byte 3 */ 3088 tcg_gen_andi_tl(b3, r1, 0xff000000); 3089 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); 3090 3091 /* combine them */ 3092 tcg_gen_or_tl(ret, b0, b1); 3093 tcg_gen_or_tl(ret, ret, b2); 3094 tcg_gen_or_tl(ret, ret, b3); 3095 3096 tcg_temp_free(b0); 3097 tcg_temp_free(b1); 3098 tcg_temp_free(b2); 3099 tcg_temp_free(b3); 3100 } 3101 3102 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) 3103 { 3104 TCGv h0 = tcg_temp_new(); 3105 TCGv h1 = tcg_temp_new(); 3106 3107 /* halfword 0 */ 3108 tcg_gen_andi_tl(h0, r1, 0xffff); 3109 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); 3110 3111 /* halfword 1 */ 3112 tcg_gen_andi_tl(h1, r1, 0xffff0000); 3113 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); 3114 3115 /* combine them */ 3116 tcg_gen_or_tl(ret, h0, h1); 3117 3118 tcg_temp_free(h0); 3119 tcg_temp_free(h1); 3120 } 3121 /* mask = ((1 << width) -1) << pos; 3122 ret = (r1 & ~mask) | (r2 << pos) & mask); */ 3123 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) 3124 { 3125 TCGv mask = tcg_temp_new(); 3126 TCGv temp = tcg_temp_new(); 3127 TCGv temp2 = tcg_temp_new(); 3128 3129 tcg_gen_movi_tl(mask, 1); 3130 tcg_gen_shl_tl(mask, mask, width); 3131 tcg_gen_subi_tl(mask, mask, 1); 3132 tcg_gen_shl_tl(mask, mask, pos); 3133 3134 tcg_gen_shl_tl(temp, r2, pos); 3135 tcg_gen_and_tl(temp, temp, mask); 3136 tcg_gen_andc_tl(temp2, r1, mask); 3137 tcg_gen_or_tl(ret, temp, temp2); 3138 3139 tcg_temp_free(mask); 3140 tcg_temp_free(temp); 3141 tcg_temp_free(temp2); 3142 } 3143 3144 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) 3145 { 3146 TCGv_i64 temp = tcg_temp_new_i64(); 3147 3148 gen_helper_bsplit(temp, r1); 3149 tcg_gen_extr_i64_i32(rl, rh, temp); 3150 3151 tcg_temp_free_i64(temp); 3152 } 3153 3154 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) 3155 { 3156 TCGv_i64 temp = tcg_temp_new_i64(); 3157 3158 gen_helper_unpack(temp, r1); 3159 tcg_gen_extr_i64_i32(rl, rh, temp); 3160 3161 tcg_temp_free_i64(temp); 3162 } 3163 3164 static inline void 3165 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 3166 { 3167 TCGv_i64 ret = tcg_temp_new_i64(); 3168 3169 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 3170 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); 3171 } else { 3172 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); 3173 } 3174 tcg_gen_extr_i64_i32(rl, rh, ret); 3175 3176 tcg_temp_free_i64(ret); 3177 } 3178 3179 static inline void 3180 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 3181 { 3182 TCGv_i64 ret = tcg_temp_new_i64(); 3183 3184 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 3185 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); 3186 } else { 3187 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); 3188 } 3189 tcg_gen_extr_i64_i32(rl, rh, ret); 3190 3191 tcg_temp_free_i64(ret); 3192 } 3193 3194 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) 3195 { 3196 TCGv temp = tcg_temp_new(); 3197 /* calc AV bit */ 3198 tcg_gen_add_tl(temp, arg_low, arg_low); 3199 tcg_gen_xor_tl(temp, temp, arg_low); 3200 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); 3201 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); 3202 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 3203 /* calc SAV bit */ 3204 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3205 tcg_gen_movi_tl(cpu_PSW_V, 0); 3206 tcg_temp_free(temp); 3207 } 3208 3209 static void gen_calc_usb_mulr_h(TCGv arg) 3210 { 3211 TCGv temp = tcg_temp_new(); 3212 /* calc AV bit */ 3213 tcg_gen_add_tl(temp, arg, arg); 3214 tcg_gen_xor_tl(temp, temp, arg); 3215 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); 3216 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 3217 /* calc SAV bit */ 3218 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3219 /* clear V bit */ 3220 tcg_gen_movi_tl(cpu_PSW_V, 0); 3221 tcg_temp_free(temp); 3222 } 3223 3224 /* helpers for generating program flow micro-ops */ 3225 3226 static inline void gen_save_pc(target_ulong pc) 3227 { 3228 tcg_gen_movi_tl(cpu_PC, pc); 3229 } 3230 3231 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3232 { 3233 if (unlikely(ctx->singlestep_enabled)) { 3234 return false; 3235 } 3236 3237 #ifndef CONFIG_USER_ONLY 3238 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3239 #else 3240 return true; 3241 #endif 3242 } 3243 3244 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3245 { 3246 if (use_goto_tb(ctx, dest)) { 3247 tcg_gen_goto_tb(n); 3248 gen_save_pc(dest); 3249 tcg_gen_exit_tb(ctx->tb, n); 3250 } else { 3251 gen_save_pc(dest); 3252 if (ctx->singlestep_enabled) { 3253 /* raise exception debug */ 3254 } 3255 tcg_gen_exit_tb(NULL, 0); 3256 } 3257 } 3258 3259 static void generate_trap(DisasContext *ctx, int class, int tin) 3260 { 3261 TCGv_i32 classtemp = tcg_const_i32(class); 3262 TCGv_i32 tintemp = tcg_const_i32(tin); 3263 3264 gen_save_pc(ctx->pc); 3265 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); 3266 ctx->bstate = BS_EXCP; 3267 3268 tcg_temp_free(classtemp); 3269 tcg_temp_free(tintemp); 3270 } 3271 3272 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, 3273 TCGv r2, int16_t address) 3274 { 3275 TCGLabel *jumpLabel = gen_new_label(); 3276 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); 3277 3278 gen_goto_tb(ctx, 1, ctx->next_pc); 3279 3280 gen_set_label(jumpLabel); 3281 gen_goto_tb(ctx, 0, ctx->pc + address * 2); 3282 } 3283 3284 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, 3285 int r2, int16_t address) 3286 { 3287 TCGv temp = tcg_const_i32(r2); 3288 gen_branch_cond(ctx, cond, r1, temp, address); 3289 tcg_temp_free(temp); 3290 } 3291 3292 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) 3293 { 3294 TCGLabel *l1 = gen_new_label(); 3295 3296 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); 3297 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); 3298 gen_goto_tb(ctx, 1, ctx->pc + offset); 3299 gen_set_label(l1); 3300 gen_goto_tb(ctx, 0, ctx->next_pc); 3301 } 3302 3303 static void gen_fcall_save_ctx(DisasContext *ctx) 3304 { 3305 TCGv temp = tcg_temp_new(); 3306 3307 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); 3308 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); 3309 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 3310 tcg_gen_mov_tl(cpu_gpr_a[10], temp); 3311 3312 tcg_temp_free(temp); 3313 } 3314 3315 static void gen_fret(DisasContext *ctx) 3316 { 3317 TCGv temp = tcg_temp_new(); 3318 3319 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); 3320 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); 3321 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); 3322 tcg_gen_mov_tl(cpu_PC, temp); 3323 tcg_gen_exit_tb(NULL, 0); 3324 ctx->bstate = BS_BRANCH; 3325 3326 tcg_temp_free(temp); 3327 } 3328 3329 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 3330 int r2 , int32_t constant , int32_t offset) 3331 { 3332 TCGv temp, temp2; 3333 int n; 3334 3335 switch (opc) { 3336 /* SB-format jumps */ 3337 case OPC1_16_SB_J: 3338 case OPC1_32_B_J: 3339 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3340 break; 3341 case OPC1_32_B_CALL: 3342 case OPC1_16_SB_CALL: 3343 gen_helper_1arg(call, ctx->next_pc); 3344 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3345 break; 3346 case OPC1_16_SB_JZ: 3347 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); 3348 break; 3349 case OPC1_16_SB_JNZ: 3350 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); 3351 break; 3352 /* SBC-format jumps */ 3353 case OPC1_16_SBC_JEQ: 3354 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); 3355 break; 3356 case OPC1_16_SBC_JEQ2: 3357 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, 3358 offset + 16); 3359 break; 3360 case OPC1_16_SBC_JNE: 3361 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); 3362 break; 3363 case OPC1_16_SBC_JNE2: 3364 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 3365 constant, offset + 16); 3366 break; 3367 /* SBRN-format jumps */ 3368 case OPC1_16_SBRN_JZ_T: 3369 temp = tcg_temp_new(); 3370 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 3371 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3372 tcg_temp_free(temp); 3373 break; 3374 case OPC1_16_SBRN_JNZ_T: 3375 temp = tcg_temp_new(); 3376 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 3377 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3378 tcg_temp_free(temp); 3379 break; 3380 /* SBR-format jumps */ 3381 case OPC1_16_SBR_JEQ: 3382 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 3383 offset); 3384 break; 3385 case OPC1_16_SBR_JEQ2: 3386 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 3387 offset + 16); 3388 break; 3389 case OPC1_16_SBR_JNE: 3390 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 3391 offset); 3392 break; 3393 case OPC1_16_SBR_JNE2: 3394 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 3395 offset + 16); 3396 break; 3397 case OPC1_16_SBR_JNZ: 3398 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); 3399 break; 3400 case OPC1_16_SBR_JNZ_A: 3401 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3402 break; 3403 case OPC1_16_SBR_JGEZ: 3404 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); 3405 break; 3406 case OPC1_16_SBR_JGTZ: 3407 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); 3408 break; 3409 case OPC1_16_SBR_JLEZ: 3410 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); 3411 break; 3412 case OPC1_16_SBR_JLTZ: 3413 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); 3414 break; 3415 case OPC1_16_SBR_JZ: 3416 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); 3417 break; 3418 case OPC1_16_SBR_JZ_A: 3419 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3420 break; 3421 case OPC1_16_SBR_LOOP: 3422 gen_loop(ctx, r1, offset * 2 - 32); 3423 break; 3424 /* SR-format jumps */ 3425 case OPC1_16_SR_JI: 3426 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); 3427 tcg_gen_exit_tb(NULL, 0); 3428 break; 3429 case OPC2_32_SYS_RET: 3430 case OPC2_16_SR_RET: 3431 gen_helper_ret(cpu_env); 3432 tcg_gen_exit_tb(NULL, 0); 3433 break; 3434 /* B-format */ 3435 case OPC1_32_B_CALLA: 3436 gen_helper_1arg(call, ctx->next_pc); 3437 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3438 break; 3439 case OPC1_32_B_FCALL: 3440 gen_fcall_save_ctx(ctx); 3441 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3442 break; 3443 case OPC1_32_B_FCALLA: 3444 gen_fcall_save_ctx(ctx); 3445 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3446 break; 3447 case OPC1_32_B_JLA: 3448 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 3449 /* fall through */ 3450 case OPC1_32_B_JA: 3451 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3452 break; 3453 case OPC1_32_B_JL: 3454 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 3455 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3456 break; 3457 /* BOL format */ 3458 case OPCM_32_BRC_EQ_NEQ: 3459 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { 3460 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); 3461 } else { 3462 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); 3463 } 3464 break; 3465 case OPCM_32_BRC_GE: 3466 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { 3467 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); 3468 } else { 3469 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3470 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, 3471 offset); 3472 } 3473 break; 3474 case OPCM_32_BRC_JLT: 3475 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { 3476 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); 3477 } else { 3478 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3479 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, 3480 offset); 3481 } 3482 break; 3483 case OPCM_32_BRC_JNE: 3484 temp = tcg_temp_new(); 3485 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { 3486 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3487 /* subi is unconditional */ 3488 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3489 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3490 } else { 3491 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3492 /* addi is unconditional */ 3493 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3494 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3495 } 3496 tcg_temp_free(temp); 3497 break; 3498 /* BRN format */ 3499 case OPCM_32_BRN_JTT: 3500 n = MASK_OP_BRN_N(ctx->opcode); 3501 3502 temp = tcg_temp_new(); 3503 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); 3504 3505 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { 3506 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3507 } else { 3508 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3509 } 3510 tcg_temp_free(temp); 3511 break; 3512 /* BRR Format */ 3513 case OPCM_32_BRR_EQ_NEQ: 3514 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { 3515 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], 3516 offset); 3517 } else { 3518 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3519 offset); 3520 } 3521 break; 3522 case OPCM_32_BRR_ADDR_EQ_NEQ: 3523 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { 3524 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], 3525 offset); 3526 } else { 3527 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], 3528 offset); 3529 } 3530 break; 3531 case OPCM_32_BRR_GE: 3532 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { 3533 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3534 offset); 3535 } else { 3536 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3537 offset); 3538 } 3539 break; 3540 case OPCM_32_BRR_JLT: 3541 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { 3542 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], 3543 offset); 3544 } else { 3545 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3546 offset); 3547 } 3548 break; 3549 case OPCM_32_BRR_LOOP: 3550 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { 3551 gen_loop(ctx, r2, offset * 2); 3552 } else { 3553 /* OPC2_32_BRR_LOOPU */ 3554 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3555 } 3556 break; 3557 case OPCM_32_BRR_JNE: 3558 temp = tcg_temp_new(); 3559 temp2 = tcg_temp_new(); 3560 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { 3561 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3562 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3563 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3564 /* subi is unconditional */ 3565 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3566 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3567 } else { 3568 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3569 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3570 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3571 /* addi is unconditional */ 3572 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3573 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3574 } 3575 tcg_temp_free(temp); 3576 tcg_temp_free(temp2); 3577 break; 3578 case OPCM_32_BRR_JNZ: 3579 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { 3580 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3581 } else { 3582 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3583 } 3584 break; 3585 default: 3586 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3587 } 3588 ctx->bstate = BS_BRANCH; 3589 } 3590 3591 3592 /* 3593 * Functions for decoding instructions 3594 */ 3595 3596 static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1) 3597 { 3598 int r1; 3599 int32_t const4; 3600 TCGv temp, temp2; 3601 3602 r1 = MASK_OP_SRC_S1D(ctx->opcode); 3603 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); 3604 3605 switch (op1) { 3606 case OPC1_16_SRC_ADD: 3607 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3608 break; 3609 case OPC1_16_SRC_ADD_A15: 3610 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); 3611 break; 3612 case OPC1_16_SRC_ADD_15A: 3613 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); 3614 break; 3615 case OPC1_16_SRC_ADD_A: 3616 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); 3617 break; 3618 case OPC1_16_SRC_CADD: 3619 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3620 cpu_gpr_d[15]); 3621 break; 3622 case OPC1_16_SRC_CADDN: 3623 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3624 cpu_gpr_d[15]); 3625 break; 3626 case OPC1_16_SRC_CMOV: 3627 temp = tcg_const_tl(0); 3628 temp2 = tcg_const_tl(const4); 3629 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3630 temp2, cpu_gpr_d[r1]); 3631 tcg_temp_free(temp); 3632 tcg_temp_free(temp2); 3633 break; 3634 case OPC1_16_SRC_CMOVN: 3635 temp = tcg_const_tl(0); 3636 temp2 = tcg_const_tl(const4); 3637 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3638 temp2, cpu_gpr_d[r1]); 3639 tcg_temp_free(temp); 3640 tcg_temp_free(temp2); 3641 break; 3642 case OPC1_16_SRC_EQ: 3643 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3644 const4); 3645 break; 3646 case OPC1_16_SRC_LT: 3647 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3648 const4); 3649 break; 3650 case OPC1_16_SRC_MOV: 3651 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3652 break; 3653 case OPC1_16_SRC_MOV_A: 3654 const4 = MASK_OP_SRC_CONST4(ctx->opcode); 3655 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); 3656 break; 3657 case OPC1_16_SRC_MOV_E: 3658 if (tricore_feature(env, TRICORE_FEATURE_16)) { 3659 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3660 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); 3661 } else { 3662 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3663 } 3664 break; 3665 case OPC1_16_SRC_SH: 3666 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3667 break; 3668 case OPC1_16_SRC_SHA: 3669 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3670 break; 3671 default: 3672 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3673 } 3674 } 3675 3676 static void decode_srr_opc(DisasContext *ctx, int op1) 3677 { 3678 int r1, r2; 3679 TCGv temp; 3680 3681 r1 = MASK_OP_SRR_S1D(ctx->opcode); 3682 r2 = MASK_OP_SRR_S2(ctx->opcode); 3683 3684 switch (op1) { 3685 case OPC1_16_SRR_ADD: 3686 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3687 break; 3688 case OPC1_16_SRR_ADD_A15: 3689 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3690 break; 3691 case OPC1_16_SRR_ADD_15A: 3692 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3693 break; 3694 case OPC1_16_SRR_ADD_A: 3695 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); 3696 break; 3697 case OPC1_16_SRR_ADDS: 3698 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3699 break; 3700 case OPC1_16_SRR_AND: 3701 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3702 break; 3703 case OPC1_16_SRR_CMOV: 3704 temp = tcg_const_tl(0); 3705 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3706 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3707 tcg_temp_free(temp); 3708 break; 3709 case OPC1_16_SRR_CMOVN: 3710 temp = tcg_const_tl(0); 3711 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3712 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3713 tcg_temp_free(temp); 3714 break; 3715 case OPC1_16_SRR_EQ: 3716 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3717 cpu_gpr_d[r2]); 3718 break; 3719 case OPC1_16_SRR_LT: 3720 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3721 cpu_gpr_d[r2]); 3722 break; 3723 case OPC1_16_SRR_MOV: 3724 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); 3725 break; 3726 case OPC1_16_SRR_MOV_A: 3727 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); 3728 break; 3729 case OPC1_16_SRR_MOV_AA: 3730 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); 3731 break; 3732 case OPC1_16_SRR_MOV_D: 3733 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); 3734 break; 3735 case OPC1_16_SRR_MUL: 3736 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3737 break; 3738 case OPC1_16_SRR_OR: 3739 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3740 break; 3741 case OPC1_16_SRR_SUB: 3742 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3743 break; 3744 case OPC1_16_SRR_SUB_A15B: 3745 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3746 break; 3747 case OPC1_16_SRR_SUB_15AB: 3748 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3749 break; 3750 case OPC1_16_SRR_SUBS: 3751 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3752 break; 3753 case OPC1_16_SRR_XOR: 3754 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3755 break; 3756 default: 3757 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3758 } 3759 } 3760 3761 static void decode_ssr_opc(DisasContext *ctx, int op1) 3762 { 3763 int r1, r2; 3764 3765 r1 = MASK_OP_SSR_S1(ctx->opcode); 3766 r2 = MASK_OP_SSR_S2(ctx->opcode); 3767 3768 switch (op1) { 3769 case OPC1_16_SSR_ST_A: 3770 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3771 break; 3772 case OPC1_16_SSR_ST_A_POSTINC: 3773 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3774 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3775 break; 3776 case OPC1_16_SSR_ST_B: 3777 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3778 break; 3779 case OPC1_16_SSR_ST_B_POSTINC: 3780 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3781 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3782 break; 3783 case OPC1_16_SSR_ST_H: 3784 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3785 break; 3786 case OPC1_16_SSR_ST_H_POSTINC: 3787 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3788 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3789 break; 3790 case OPC1_16_SSR_ST_W: 3791 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3792 break; 3793 case OPC1_16_SSR_ST_W_POSTINC: 3794 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3795 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3796 break; 3797 default: 3798 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3799 } 3800 } 3801 3802 static void decode_sc_opc(DisasContext *ctx, int op1) 3803 { 3804 int32_t const16; 3805 3806 const16 = MASK_OP_SC_CONST8(ctx->opcode); 3807 3808 switch (op1) { 3809 case OPC1_16_SC_AND: 3810 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3811 break; 3812 case OPC1_16_SC_BISR: 3813 gen_helper_1arg(bisr, const16 & 0xff); 3814 break; 3815 case OPC1_16_SC_LD_A: 3816 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3817 break; 3818 case OPC1_16_SC_LD_W: 3819 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3820 break; 3821 case OPC1_16_SC_MOV: 3822 tcg_gen_movi_tl(cpu_gpr_d[15], const16); 3823 break; 3824 case OPC1_16_SC_OR: 3825 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3826 break; 3827 case OPC1_16_SC_ST_A: 3828 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3829 break; 3830 case OPC1_16_SC_ST_W: 3831 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3832 break; 3833 case OPC1_16_SC_SUB_A: 3834 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); 3835 break; 3836 default: 3837 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3838 } 3839 } 3840 3841 static void decode_slr_opc(DisasContext *ctx, int op1) 3842 { 3843 int r1, r2; 3844 3845 r1 = MASK_OP_SLR_D(ctx->opcode); 3846 r2 = MASK_OP_SLR_S2(ctx->opcode); 3847 3848 switch (op1) { 3849 /* SLR-format */ 3850 case OPC1_16_SLR_LD_A: 3851 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3852 break; 3853 case OPC1_16_SLR_LD_A_POSTINC: 3854 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3855 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3856 break; 3857 case OPC1_16_SLR_LD_BU: 3858 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3859 break; 3860 case OPC1_16_SLR_LD_BU_POSTINC: 3861 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3862 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3863 break; 3864 case OPC1_16_SLR_LD_H: 3865 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3866 break; 3867 case OPC1_16_SLR_LD_H_POSTINC: 3868 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3869 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3870 break; 3871 case OPC1_16_SLR_LD_W: 3872 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3873 break; 3874 case OPC1_16_SLR_LD_W_POSTINC: 3875 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3876 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3877 break; 3878 default: 3879 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3880 } 3881 } 3882 3883 static void decode_sro_opc(DisasContext *ctx, int op1) 3884 { 3885 int r2; 3886 int32_t address; 3887 3888 r2 = MASK_OP_SRO_S2(ctx->opcode); 3889 address = MASK_OP_SRO_OFF4(ctx->opcode); 3890 3891 /* SRO-format */ 3892 switch (op1) { 3893 case OPC1_16_SRO_LD_A: 3894 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3895 break; 3896 case OPC1_16_SRO_LD_BU: 3897 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3898 break; 3899 case OPC1_16_SRO_LD_H: 3900 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW); 3901 break; 3902 case OPC1_16_SRO_LD_W: 3903 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3904 break; 3905 case OPC1_16_SRO_ST_A: 3906 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3907 break; 3908 case OPC1_16_SRO_ST_B: 3909 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3910 break; 3911 case OPC1_16_SRO_ST_H: 3912 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3913 break; 3914 case OPC1_16_SRO_ST_W: 3915 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3916 break; 3917 default: 3918 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3919 } 3920 } 3921 3922 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) 3923 { 3924 uint32_t op2; 3925 op2 = MASK_OP_SR_OP2(ctx->opcode); 3926 3927 switch (op2) { 3928 case OPC2_16_SR_NOP: 3929 break; 3930 case OPC2_16_SR_RET: 3931 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 3932 break; 3933 case OPC2_16_SR_RFE: 3934 gen_helper_rfe(cpu_env); 3935 tcg_gen_exit_tb(NULL, 0); 3936 ctx->bstate = BS_BRANCH; 3937 break; 3938 case OPC2_16_SR_DEBUG: 3939 /* raise EXCP_DEBUG */ 3940 break; 3941 case OPC2_16_SR_FRET: 3942 gen_fret(ctx); 3943 break; 3944 default: 3945 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3946 } 3947 } 3948 3949 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx) 3950 { 3951 uint32_t op2; 3952 uint32_t r1; 3953 TCGv temp; 3954 3955 r1 = MASK_OP_SR_S1D(ctx->opcode); 3956 op2 = MASK_OP_SR_OP2(ctx->opcode); 3957 3958 switch (op2) { 3959 case OPC2_16_SR_RSUB: 3960 /* overflow only if r1 = -0x80000000 */ 3961 temp = tcg_const_i32(-0x80000000); 3962 /* calc V bit */ 3963 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp); 3964 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 3965 /* calc SV bit */ 3966 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 3967 /* sub */ 3968 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3969 /* calc av */ 3970 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); 3971 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); 3972 /* calc sav */ 3973 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3974 tcg_temp_free(temp); 3975 break; 3976 case OPC2_16_SR_SAT_B: 3977 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); 3978 break; 3979 case OPC2_16_SR_SAT_BU: 3980 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); 3981 break; 3982 case OPC2_16_SR_SAT_H: 3983 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); 3984 break; 3985 case OPC2_16_SR_SAT_HU: 3986 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); 3987 break; 3988 default: 3989 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3990 } 3991 } 3992 3993 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) 3994 { 3995 int op1; 3996 int r1, r2; 3997 int32_t const16; 3998 int32_t address; 3999 TCGv temp; 4000 4001 op1 = MASK_OP_MAJOR(ctx->opcode); 4002 4003 /* handle ADDSC.A opcode only being 6 bit long */ 4004 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { 4005 op1 = OPC1_16_SRRS_ADDSC_A; 4006 } 4007 4008 switch (op1) { 4009 case OPC1_16_SRC_ADD: 4010 case OPC1_16_SRC_ADD_A15: 4011 case OPC1_16_SRC_ADD_15A: 4012 case OPC1_16_SRC_ADD_A: 4013 case OPC1_16_SRC_CADD: 4014 case OPC1_16_SRC_CADDN: 4015 case OPC1_16_SRC_CMOV: 4016 case OPC1_16_SRC_CMOVN: 4017 case OPC1_16_SRC_EQ: 4018 case OPC1_16_SRC_LT: 4019 case OPC1_16_SRC_MOV: 4020 case OPC1_16_SRC_MOV_A: 4021 case OPC1_16_SRC_MOV_E: 4022 case OPC1_16_SRC_SH: 4023 case OPC1_16_SRC_SHA: 4024 decode_src_opc(env, ctx, op1); 4025 break; 4026 /* SRR-format */ 4027 case OPC1_16_SRR_ADD: 4028 case OPC1_16_SRR_ADD_A15: 4029 case OPC1_16_SRR_ADD_15A: 4030 case OPC1_16_SRR_ADD_A: 4031 case OPC1_16_SRR_ADDS: 4032 case OPC1_16_SRR_AND: 4033 case OPC1_16_SRR_CMOV: 4034 case OPC1_16_SRR_CMOVN: 4035 case OPC1_16_SRR_EQ: 4036 case OPC1_16_SRR_LT: 4037 case OPC1_16_SRR_MOV: 4038 case OPC1_16_SRR_MOV_A: 4039 case OPC1_16_SRR_MOV_AA: 4040 case OPC1_16_SRR_MOV_D: 4041 case OPC1_16_SRR_MUL: 4042 case OPC1_16_SRR_OR: 4043 case OPC1_16_SRR_SUB: 4044 case OPC1_16_SRR_SUB_A15B: 4045 case OPC1_16_SRR_SUB_15AB: 4046 case OPC1_16_SRR_SUBS: 4047 case OPC1_16_SRR_XOR: 4048 decode_srr_opc(ctx, op1); 4049 break; 4050 /* SSR-format */ 4051 case OPC1_16_SSR_ST_A: 4052 case OPC1_16_SSR_ST_A_POSTINC: 4053 case OPC1_16_SSR_ST_B: 4054 case OPC1_16_SSR_ST_B_POSTINC: 4055 case OPC1_16_SSR_ST_H: 4056 case OPC1_16_SSR_ST_H_POSTINC: 4057 case OPC1_16_SSR_ST_W: 4058 case OPC1_16_SSR_ST_W_POSTINC: 4059 decode_ssr_opc(ctx, op1); 4060 break; 4061 /* SRRS-format */ 4062 case OPC1_16_SRRS_ADDSC_A: 4063 r2 = MASK_OP_SRRS_S2(ctx->opcode); 4064 r1 = MASK_OP_SRRS_S1D(ctx->opcode); 4065 const16 = MASK_OP_SRRS_N(ctx->opcode); 4066 temp = tcg_temp_new(); 4067 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); 4068 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); 4069 tcg_temp_free(temp); 4070 break; 4071 /* SLRO-format */ 4072 case OPC1_16_SLRO_LD_A: 4073 r1 = MASK_OP_SLRO_D(ctx->opcode); 4074 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4075 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4076 break; 4077 case OPC1_16_SLRO_LD_BU: 4078 r1 = MASK_OP_SLRO_D(ctx->opcode); 4079 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4080 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 4081 break; 4082 case OPC1_16_SLRO_LD_H: 4083 r1 = MASK_OP_SLRO_D(ctx->opcode); 4084 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4085 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 4086 break; 4087 case OPC1_16_SLRO_LD_W: 4088 r1 = MASK_OP_SLRO_D(ctx->opcode); 4089 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4090 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4091 break; 4092 /* SB-format */ 4093 case OPC1_16_SB_CALL: 4094 case OPC1_16_SB_J: 4095 case OPC1_16_SB_JNZ: 4096 case OPC1_16_SB_JZ: 4097 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); 4098 gen_compute_branch(ctx, op1, 0, 0, 0, address); 4099 break; 4100 /* SBC-format */ 4101 case OPC1_16_SBC_JEQ: 4102 case OPC1_16_SBC_JNE: 4103 address = MASK_OP_SBC_DISP4(ctx->opcode); 4104 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 4105 gen_compute_branch(ctx, op1, 0, 0, const16, address); 4106 break; 4107 case OPC1_16_SBC_JEQ2: 4108 case OPC1_16_SBC_JNE2: 4109 if (tricore_feature(env, TRICORE_FEATURE_16)) { 4110 address = MASK_OP_SBC_DISP4(ctx->opcode); 4111 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 4112 gen_compute_branch(ctx, op1, 0, 0, const16, address); 4113 } else { 4114 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4115 } 4116 break; 4117 /* SBRN-format */ 4118 case OPC1_16_SBRN_JNZ_T: 4119 case OPC1_16_SBRN_JZ_T: 4120 address = MASK_OP_SBRN_DISP4(ctx->opcode); 4121 const16 = MASK_OP_SBRN_N(ctx->opcode); 4122 gen_compute_branch(ctx, op1, 0, 0, const16, address); 4123 break; 4124 /* SBR-format */ 4125 case OPC1_16_SBR_JEQ2: 4126 case OPC1_16_SBR_JNE2: 4127 if (tricore_feature(env, TRICORE_FEATURE_16)) { 4128 r1 = MASK_OP_SBR_S2(ctx->opcode); 4129 address = MASK_OP_SBR_DISP4(ctx->opcode); 4130 gen_compute_branch(ctx, op1, r1, 0, 0, address); 4131 } else { 4132 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4133 } 4134 break; 4135 case OPC1_16_SBR_JEQ: 4136 case OPC1_16_SBR_JGEZ: 4137 case OPC1_16_SBR_JGTZ: 4138 case OPC1_16_SBR_JLEZ: 4139 case OPC1_16_SBR_JLTZ: 4140 case OPC1_16_SBR_JNE: 4141 case OPC1_16_SBR_JNZ: 4142 case OPC1_16_SBR_JNZ_A: 4143 case OPC1_16_SBR_JZ: 4144 case OPC1_16_SBR_JZ_A: 4145 case OPC1_16_SBR_LOOP: 4146 r1 = MASK_OP_SBR_S2(ctx->opcode); 4147 address = MASK_OP_SBR_DISP4(ctx->opcode); 4148 gen_compute_branch(ctx, op1, r1, 0, 0, address); 4149 break; 4150 /* SC-format */ 4151 case OPC1_16_SC_AND: 4152 case OPC1_16_SC_BISR: 4153 case OPC1_16_SC_LD_A: 4154 case OPC1_16_SC_LD_W: 4155 case OPC1_16_SC_MOV: 4156 case OPC1_16_SC_OR: 4157 case OPC1_16_SC_ST_A: 4158 case OPC1_16_SC_ST_W: 4159 case OPC1_16_SC_SUB_A: 4160 decode_sc_opc(ctx, op1); 4161 break; 4162 /* SLR-format */ 4163 case OPC1_16_SLR_LD_A: 4164 case OPC1_16_SLR_LD_A_POSTINC: 4165 case OPC1_16_SLR_LD_BU: 4166 case OPC1_16_SLR_LD_BU_POSTINC: 4167 case OPC1_16_SLR_LD_H: 4168 case OPC1_16_SLR_LD_H_POSTINC: 4169 case OPC1_16_SLR_LD_W: 4170 case OPC1_16_SLR_LD_W_POSTINC: 4171 decode_slr_opc(ctx, op1); 4172 break; 4173 /* SRO-format */ 4174 case OPC1_16_SRO_LD_A: 4175 case OPC1_16_SRO_LD_BU: 4176 case OPC1_16_SRO_LD_H: 4177 case OPC1_16_SRO_LD_W: 4178 case OPC1_16_SRO_ST_A: 4179 case OPC1_16_SRO_ST_B: 4180 case OPC1_16_SRO_ST_H: 4181 case OPC1_16_SRO_ST_W: 4182 decode_sro_opc(ctx, op1); 4183 break; 4184 /* SSRO-format */ 4185 case OPC1_16_SSRO_ST_A: 4186 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4187 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4188 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4189 break; 4190 case OPC1_16_SSRO_ST_B: 4191 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4192 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4193 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 4194 break; 4195 case OPC1_16_SSRO_ST_H: 4196 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4197 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4198 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 4199 break; 4200 case OPC1_16_SSRO_ST_W: 4201 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4202 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4203 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4204 break; 4205 /* SR-format */ 4206 case OPCM_16_SR_SYSTEM: 4207 decode_sr_system(env, ctx); 4208 break; 4209 case OPCM_16_SR_ACCU: 4210 decode_sr_accu(env, ctx); 4211 break; 4212 case OPC1_16_SR_JI: 4213 r1 = MASK_OP_SR_S1D(ctx->opcode); 4214 gen_compute_branch(ctx, op1, r1, 0, 0, 0); 4215 break; 4216 case OPC1_16_SR_NOT: 4217 r1 = MASK_OP_SR_S1D(ctx->opcode); 4218 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 4219 break; 4220 default: 4221 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4222 } 4223 } 4224 4225 /* 4226 * 32 bit instructions 4227 */ 4228 4229 /* ABS-format */ 4230 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx) 4231 { 4232 int32_t op2; 4233 int32_t r1; 4234 uint32_t address; 4235 TCGv temp; 4236 4237 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4238 address = MASK_OP_ABS_OFF18(ctx->opcode); 4239 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4240 4241 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4242 4243 switch (op2) { 4244 case OPC2_32_ABS_LD_A: 4245 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 4246 break; 4247 case OPC2_32_ABS_LD_D: 4248 CHECK_REG_PAIR(r1); 4249 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4250 break; 4251 case OPC2_32_ABS_LD_DA: 4252 CHECK_REG_PAIR(r1); 4253 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4254 break; 4255 case OPC2_32_ABS_LD_W: 4256 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 4257 break; 4258 default: 4259 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4260 } 4261 4262 tcg_temp_free(temp); 4263 } 4264 4265 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx) 4266 { 4267 int32_t op2; 4268 int32_t r1; 4269 uint32_t address; 4270 TCGv temp; 4271 4272 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4273 address = MASK_OP_ABS_OFF18(ctx->opcode); 4274 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4275 4276 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4277 4278 switch (op2) { 4279 case OPC2_32_ABS_LD_B: 4280 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); 4281 break; 4282 case OPC2_32_ABS_LD_BU: 4283 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 4284 break; 4285 case OPC2_32_ABS_LD_H: 4286 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); 4287 break; 4288 case OPC2_32_ABS_LD_HU: 4289 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 4290 break; 4291 default: 4292 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4293 } 4294 4295 tcg_temp_free(temp); 4296 } 4297 4298 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx) 4299 { 4300 int32_t op2; 4301 int32_t r1; 4302 uint32_t address; 4303 TCGv temp; 4304 4305 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4306 address = MASK_OP_ABS_OFF18(ctx->opcode); 4307 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4308 4309 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4310 4311 switch (op2) { 4312 case OPC2_32_ABS_LDMST: 4313 gen_ldmst(ctx, r1, temp); 4314 break; 4315 case OPC2_32_ABS_SWAP_W: 4316 gen_swap(ctx, r1, temp); 4317 break; 4318 default: 4319 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4320 } 4321 4322 tcg_temp_free(temp); 4323 } 4324 4325 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx) 4326 { 4327 uint32_t op2; 4328 int32_t off18; 4329 4330 off18 = MASK_OP_ABS_OFF18(ctx->opcode); 4331 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4332 4333 switch (op2) { 4334 case OPC2_32_ABS_LDLCX: 4335 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); 4336 break; 4337 case OPC2_32_ABS_LDUCX: 4338 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); 4339 break; 4340 case OPC2_32_ABS_STLCX: 4341 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); 4342 break; 4343 case OPC2_32_ABS_STUCX: 4344 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); 4345 break; 4346 default: 4347 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4348 } 4349 } 4350 4351 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx) 4352 { 4353 int32_t op2; 4354 int32_t r1; 4355 uint32_t address; 4356 TCGv temp; 4357 4358 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4359 address = MASK_OP_ABS_OFF18(ctx->opcode); 4360 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4361 4362 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4363 4364 switch (op2) { 4365 case OPC2_32_ABS_ST_A: 4366 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 4367 break; 4368 case OPC2_32_ABS_ST_D: 4369 CHECK_REG_PAIR(r1); 4370 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4371 break; 4372 case OPC2_32_ABS_ST_DA: 4373 CHECK_REG_PAIR(r1); 4374 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4375 break; 4376 case OPC2_32_ABS_ST_W: 4377 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 4378 break; 4379 default: 4380 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4381 } 4382 tcg_temp_free(temp); 4383 } 4384 4385 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx) 4386 { 4387 int32_t op2; 4388 int32_t r1; 4389 uint32_t address; 4390 TCGv temp; 4391 4392 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4393 address = MASK_OP_ABS_OFF18(ctx->opcode); 4394 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4395 4396 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4397 4398 switch (op2) { 4399 case OPC2_32_ABS_ST_B: 4400 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 4401 break; 4402 case OPC2_32_ABS_ST_H: 4403 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 4404 break; 4405 default: 4406 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4407 } 4408 tcg_temp_free(temp); 4409 } 4410 4411 /* Bit-format */ 4412 4413 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx) 4414 { 4415 uint32_t op2; 4416 int r1, r2, r3; 4417 int pos1, pos2; 4418 4419 r1 = MASK_OP_BIT_S1(ctx->opcode); 4420 r2 = MASK_OP_BIT_S2(ctx->opcode); 4421 r3 = MASK_OP_BIT_D(ctx->opcode); 4422 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4423 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4424 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4425 4426 4427 switch (op2) { 4428 case OPC2_32_BIT_AND_AND_T: 4429 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4430 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); 4431 break; 4432 case OPC2_32_BIT_AND_ANDN_T: 4433 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4434 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); 4435 break; 4436 case OPC2_32_BIT_AND_NOR_T: 4437 if (TCG_TARGET_HAS_andc_i32) { 4438 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4439 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); 4440 } else { 4441 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4442 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); 4443 } 4444 break; 4445 case OPC2_32_BIT_AND_OR_T: 4446 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4447 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); 4448 break; 4449 default: 4450 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4451 } 4452 } 4453 4454 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx) 4455 { 4456 uint32_t op2; 4457 int r1, r2, r3; 4458 int pos1, pos2; 4459 r1 = MASK_OP_BIT_S1(ctx->opcode); 4460 r2 = MASK_OP_BIT_S2(ctx->opcode); 4461 r3 = MASK_OP_BIT_D(ctx->opcode); 4462 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4463 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4464 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4465 4466 switch (op2) { 4467 case OPC2_32_BIT_AND_T: 4468 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4469 pos1, pos2, &tcg_gen_and_tl); 4470 break; 4471 case OPC2_32_BIT_ANDN_T: 4472 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4473 pos1, pos2, &tcg_gen_andc_tl); 4474 break; 4475 case OPC2_32_BIT_NOR_T: 4476 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4477 pos1, pos2, &tcg_gen_nor_tl); 4478 break; 4479 case OPC2_32_BIT_OR_T: 4480 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4481 pos1, pos2, &tcg_gen_or_tl); 4482 break; 4483 default: 4484 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4485 } 4486 } 4487 4488 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx) 4489 { 4490 uint32_t op2; 4491 int r1, r2, r3; 4492 int pos1, pos2; 4493 TCGv temp; 4494 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4495 r1 = MASK_OP_BIT_S1(ctx->opcode); 4496 r2 = MASK_OP_BIT_S2(ctx->opcode); 4497 r3 = MASK_OP_BIT_D(ctx->opcode); 4498 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4499 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4500 4501 temp = tcg_temp_new(); 4502 4503 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); 4504 if (op2 == OPC2_32_BIT_INSN_T) { 4505 tcg_gen_not_tl(temp, temp); 4506 } 4507 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); 4508 tcg_temp_free(temp); 4509 } 4510 4511 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx) 4512 { 4513 uint32_t op2; 4514 4515 int r1, r2, r3; 4516 int pos1, pos2; 4517 4518 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4519 r1 = MASK_OP_BIT_S1(ctx->opcode); 4520 r2 = MASK_OP_BIT_S2(ctx->opcode); 4521 r3 = MASK_OP_BIT_D(ctx->opcode); 4522 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4523 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4524 4525 switch (op2) { 4526 case OPC2_32_BIT_NAND_T: 4527 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4528 pos1, pos2, &tcg_gen_nand_tl); 4529 break; 4530 case OPC2_32_BIT_ORN_T: 4531 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4532 pos1, pos2, &tcg_gen_orc_tl); 4533 break; 4534 case OPC2_32_BIT_XNOR_T: 4535 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4536 pos1, pos2, &tcg_gen_eqv_tl); 4537 break; 4538 case OPC2_32_BIT_XOR_T: 4539 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4540 pos1, pos2, &tcg_gen_xor_tl); 4541 break; 4542 default: 4543 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4544 } 4545 } 4546 4547 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx) 4548 { 4549 uint32_t op2; 4550 4551 int r1, r2, r3; 4552 int pos1, pos2; 4553 4554 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4555 r1 = MASK_OP_BIT_S1(ctx->opcode); 4556 r2 = MASK_OP_BIT_S2(ctx->opcode); 4557 r3 = MASK_OP_BIT_D(ctx->opcode); 4558 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4559 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4560 4561 switch (op2) { 4562 case OPC2_32_BIT_OR_AND_T: 4563 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4564 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); 4565 break; 4566 case OPC2_32_BIT_OR_ANDN_T: 4567 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4568 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); 4569 break; 4570 case OPC2_32_BIT_OR_NOR_T: 4571 if (TCG_TARGET_HAS_orc_i32) { 4572 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4573 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); 4574 } else { 4575 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4576 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); 4577 } 4578 break; 4579 case OPC2_32_BIT_OR_OR_T: 4580 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4581 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); 4582 break; 4583 default: 4584 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4585 } 4586 } 4587 4588 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx) 4589 { 4590 uint32_t op2; 4591 int r1, r2, r3; 4592 int pos1, pos2; 4593 TCGv temp; 4594 4595 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4596 r1 = MASK_OP_BIT_S1(ctx->opcode); 4597 r2 = MASK_OP_BIT_S2(ctx->opcode); 4598 r3 = MASK_OP_BIT_D(ctx->opcode); 4599 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4600 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4601 4602 temp = tcg_temp_new(); 4603 4604 switch (op2) { 4605 case OPC2_32_BIT_SH_AND_T: 4606 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4607 pos1, pos2, &tcg_gen_and_tl); 4608 break; 4609 case OPC2_32_BIT_SH_ANDN_T: 4610 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4611 pos1, pos2, &tcg_gen_andc_tl); 4612 break; 4613 case OPC2_32_BIT_SH_NOR_T: 4614 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4615 pos1, pos2, &tcg_gen_nor_tl); 4616 break; 4617 case OPC2_32_BIT_SH_OR_T: 4618 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4619 pos1, pos2, &tcg_gen_or_tl); 4620 break; 4621 default: 4622 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4623 } 4624 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4625 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4626 tcg_temp_free(temp); 4627 } 4628 4629 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx) 4630 { 4631 uint32_t op2; 4632 int r1, r2, r3; 4633 int pos1, pos2; 4634 TCGv temp; 4635 4636 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4637 r1 = MASK_OP_BIT_S1(ctx->opcode); 4638 r2 = MASK_OP_BIT_S2(ctx->opcode); 4639 r3 = MASK_OP_BIT_D(ctx->opcode); 4640 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4641 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4642 4643 temp = tcg_temp_new(); 4644 4645 switch (op2) { 4646 case OPC2_32_BIT_SH_NAND_T: 4647 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , 4648 pos1, pos2, &tcg_gen_nand_tl); 4649 break; 4650 case OPC2_32_BIT_SH_ORN_T: 4651 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4652 pos1, pos2, &tcg_gen_orc_tl); 4653 break; 4654 case OPC2_32_BIT_SH_XNOR_T: 4655 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4656 pos1, pos2, &tcg_gen_eqv_tl); 4657 break; 4658 case OPC2_32_BIT_SH_XOR_T: 4659 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4660 pos1, pos2, &tcg_gen_xor_tl); 4661 break; 4662 default: 4663 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4664 } 4665 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4666 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4667 tcg_temp_free(temp); 4668 } 4669 4670 /* BO-format */ 4671 4672 4673 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, 4674 DisasContext *ctx) 4675 { 4676 uint32_t op2; 4677 uint32_t off10; 4678 int32_t r1, r2; 4679 TCGv temp; 4680 4681 r1 = MASK_OP_BO_S1D(ctx->opcode); 4682 r2 = MASK_OP_BO_S2(ctx->opcode); 4683 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4684 op2 = MASK_OP_BO_OP2(ctx->opcode); 4685 4686 switch (op2) { 4687 case OPC2_32_BO_CACHEA_WI_SHORTOFF: 4688 case OPC2_32_BO_CACHEA_W_SHORTOFF: 4689 case OPC2_32_BO_CACHEA_I_SHORTOFF: 4690 /* instruction to access the cache */ 4691 break; 4692 case OPC2_32_BO_CACHEA_WI_POSTINC: 4693 case OPC2_32_BO_CACHEA_W_POSTINC: 4694 case OPC2_32_BO_CACHEA_I_POSTINC: 4695 /* instruction to access the cache, but we still need to handle 4696 the addressing mode */ 4697 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4698 break; 4699 case OPC2_32_BO_CACHEA_WI_PREINC: 4700 case OPC2_32_BO_CACHEA_W_PREINC: 4701 case OPC2_32_BO_CACHEA_I_PREINC: 4702 /* instruction to access the cache, but we still need to handle 4703 the addressing mode */ 4704 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4705 break; 4706 case OPC2_32_BO_CACHEI_WI_SHORTOFF: 4707 case OPC2_32_BO_CACHEI_W_SHORTOFF: 4708 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 4709 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4710 } 4711 break; 4712 case OPC2_32_BO_CACHEI_W_POSTINC: 4713 case OPC2_32_BO_CACHEI_WI_POSTINC: 4714 if (tricore_feature(env, TRICORE_FEATURE_131)) { 4715 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4716 } else { 4717 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4718 } 4719 break; 4720 case OPC2_32_BO_CACHEI_W_PREINC: 4721 case OPC2_32_BO_CACHEI_WI_PREINC: 4722 if (tricore_feature(env, TRICORE_FEATURE_131)) { 4723 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4724 } else { 4725 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4726 } 4727 break; 4728 case OPC2_32_BO_ST_A_SHORTOFF: 4729 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4730 break; 4731 case OPC2_32_BO_ST_A_POSTINC: 4732 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4733 MO_LESL); 4734 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4735 break; 4736 case OPC2_32_BO_ST_A_PREINC: 4737 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4738 break; 4739 case OPC2_32_BO_ST_B_SHORTOFF: 4740 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4741 break; 4742 case OPC2_32_BO_ST_B_POSTINC: 4743 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4744 MO_UB); 4745 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4746 break; 4747 case OPC2_32_BO_ST_B_PREINC: 4748 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4749 break; 4750 case OPC2_32_BO_ST_D_SHORTOFF: 4751 CHECK_REG_PAIR(r1); 4752 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4753 off10, ctx); 4754 break; 4755 case OPC2_32_BO_ST_D_POSTINC: 4756 CHECK_REG_PAIR(r1); 4757 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4758 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4759 break; 4760 case OPC2_32_BO_ST_D_PREINC: 4761 CHECK_REG_PAIR(r1); 4762 temp = tcg_temp_new(); 4763 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4764 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4765 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4766 tcg_temp_free(temp); 4767 break; 4768 case OPC2_32_BO_ST_DA_SHORTOFF: 4769 CHECK_REG_PAIR(r1); 4770 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4771 off10, ctx); 4772 break; 4773 case OPC2_32_BO_ST_DA_POSTINC: 4774 CHECK_REG_PAIR(r1); 4775 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4776 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4777 break; 4778 case OPC2_32_BO_ST_DA_PREINC: 4779 CHECK_REG_PAIR(r1); 4780 temp = tcg_temp_new(); 4781 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4782 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4783 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4784 tcg_temp_free(temp); 4785 break; 4786 case OPC2_32_BO_ST_H_SHORTOFF: 4787 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4788 break; 4789 case OPC2_32_BO_ST_H_POSTINC: 4790 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4791 MO_LEUW); 4792 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4793 break; 4794 case OPC2_32_BO_ST_H_PREINC: 4795 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4796 break; 4797 case OPC2_32_BO_ST_Q_SHORTOFF: 4798 temp = tcg_temp_new(); 4799 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4800 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4801 tcg_temp_free(temp); 4802 break; 4803 case OPC2_32_BO_ST_Q_POSTINC: 4804 temp = tcg_temp_new(); 4805 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4806 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, 4807 MO_LEUW); 4808 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4809 tcg_temp_free(temp); 4810 break; 4811 case OPC2_32_BO_ST_Q_PREINC: 4812 temp = tcg_temp_new(); 4813 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4814 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4815 tcg_temp_free(temp); 4816 break; 4817 case OPC2_32_BO_ST_W_SHORTOFF: 4818 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4819 break; 4820 case OPC2_32_BO_ST_W_POSTINC: 4821 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4822 MO_LEUL); 4823 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4824 break; 4825 case OPC2_32_BO_ST_W_PREINC: 4826 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4827 break; 4828 default: 4829 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4830 } 4831 } 4832 4833 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env, 4834 DisasContext *ctx) 4835 { 4836 uint32_t op2; 4837 uint32_t off10; 4838 int32_t r1, r2; 4839 TCGv temp, temp2, temp3; 4840 4841 r1 = MASK_OP_BO_S1D(ctx->opcode); 4842 r2 = MASK_OP_BO_S2(ctx->opcode); 4843 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4844 op2 = MASK_OP_BO_OP2(ctx->opcode); 4845 4846 temp = tcg_temp_new(); 4847 temp2 = tcg_temp_new(); 4848 temp3 = tcg_const_i32(off10); 4849 CHECK_REG_PAIR(r2); 4850 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4851 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4852 4853 switch (op2) { 4854 case OPC2_32_BO_CACHEA_WI_BR: 4855 case OPC2_32_BO_CACHEA_W_BR: 4856 case OPC2_32_BO_CACHEA_I_BR: 4857 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4858 break; 4859 case OPC2_32_BO_CACHEA_WI_CIRC: 4860 case OPC2_32_BO_CACHEA_W_CIRC: 4861 case OPC2_32_BO_CACHEA_I_CIRC: 4862 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4863 break; 4864 case OPC2_32_BO_ST_A_BR: 4865 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4866 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4867 break; 4868 case OPC2_32_BO_ST_A_CIRC: 4869 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4870 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4871 break; 4872 case OPC2_32_BO_ST_B_BR: 4873 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4874 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4875 break; 4876 case OPC2_32_BO_ST_B_CIRC: 4877 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4878 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4879 break; 4880 case OPC2_32_BO_ST_D_BR: 4881 CHECK_REG_PAIR(r1); 4882 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4883 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4884 break; 4885 case OPC2_32_BO_ST_D_CIRC: 4886 CHECK_REG_PAIR(r1); 4887 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4888 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4889 tcg_gen_addi_tl(temp, temp, 4); 4890 tcg_gen_rem_tl(temp, temp, temp2); 4891 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4892 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4893 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4894 break; 4895 case OPC2_32_BO_ST_DA_BR: 4896 CHECK_REG_PAIR(r1); 4897 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4898 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4899 break; 4900 case OPC2_32_BO_ST_DA_CIRC: 4901 CHECK_REG_PAIR(r1); 4902 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4903 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4904 tcg_gen_addi_tl(temp, temp, 4); 4905 tcg_gen_rem_tl(temp, temp, temp2); 4906 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4907 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4908 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4909 break; 4910 case OPC2_32_BO_ST_H_BR: 4911 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4912 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4913 break; 4914 case OPC2_32_BO_ST_H_CIRC: 4915 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4916 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4917 break; 4918 case OPC2_32_BO_ST_Q_BR: 4919 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4920 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4921 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4922 break; 4923 case OPC2_32_BO_ST_Q_CIRC: 4924 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4925 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4926 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4927 break; 4928 case OPC2_32_BO_ST_W_BR: 4929 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4930 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4931 break; 4932 case OPC2_32_BO_ST_W_CIRC: 4933 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4934 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4935 break; 4936 default: 4937 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4938 } 4939 tcg_temp_free(temp); 4940 tcg_temp_free(temp2); 4941 tcg_temp_free(temp3); 4942 } 4943 4944 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env, 4945 DisasContext *ctx) 4946 { 4947 uint32_t op2; 4948 uint32_t off10; 4949 int32_t r1, r2; 4950 TCGv temp; 4951 4952 r1 = MASK_OP_BO_S1D(ctx->opcode); 4953 r2 = MASK_OP_BO_S2(ctx->opcode); 4954 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4955 op2 = MASK_OP_BO_OP2(ctx->opcode); 4956 4957 switch (op2) { 4958 case OPC2_32_BO_LD_A_SHORTOFF: 4959 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4960 break; 4961 case OPC2_32_BO_LD_A_POSTINC: 4962 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4963 MO_LEUL); 4964 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4965 break; 4966 case OPC2_32_BO_LD_A_PREINC: 4967 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4968 break; 4969 case OPC2_32_BO_LD_B_SHORTOFF: 4970 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4971 break; 4972 case OPC2_32_BO_LD_B_POSTINC: 4973 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4974 MO_SB); 4975 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4976 break; 4977 case OPC2_32_BO_LD_B_PREINC: 4978 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4979 break; 4980 case OPC2_32_BO_LD_BU_SHORTOFF: 4981 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4982 break; 4983 case OPC2_32_BO_LD_BU_POSTINC: 4984 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4985 MO_UB); 4986 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4987 break; 4988 case OPC2_32_BO_LD_BU_PREINC: 4989 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4990 break; 4991 case OPC2_32_BO_LD_D_SHORTOFF: 4992 CHECK_REG_PAIR(r1); 4993 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4994 off10, ctx); 4995 break; 4996 case OPC2_32_BO_LD_D_POSTINC: 4997 CHECK_REG_PAIR(r1); 4998 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4999 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5000 break; 5001 case OPC2_32_BO_LD_D_PREINC: 5002 CHECK_REG_PAIR(r1); 5003 temp = tcg_temp_new(); 5004 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5005 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 5006 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 5007 tcg_temp_free(temp); 5008 break; 5009 case OPC2_32_BO_LD_DA_SHORTOFF: 5010 CHECK_REG_PAIR(r1); 5011 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 5012 off10, ctx); 5013 break; 5014 case OPC2_32_BO_LD_DA_POSTINC: 5015 CHECK_REG_PAIR(r1); 5016 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 5017 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5018 break; 5019 case OPC2_32_BO_LD_DA_PREINC: 5020 CHECK_REG_PAIR(r1); 5021 temp = tcg_temp_new(); 5022 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5023 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 5024 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 5025 tcg_temp_free(temp); 5026 break; 5027 case OPC2_32_BO_LD_H_SHORTOFF: 5028 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 5029 break; 5030 case OPC2_32_BO_LD_H_POSTINC: 5031 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5032 MO_LESW); 5033 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5034 break; 5035 case OPC2_32_BO_LD_H_PREINC: 5036 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 5037 break; 5038 case OPC2_32_BO_LD_HU_SHORTOFF: 5039 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5040 break; 5041 case OPC2_32_BO_LD_HU_POSTINC: 5042 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5043 MO_LEUW); 5044 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5045 break; 5046 case OPC2_32_BO_LD_HU_PREINC: 5047 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5048 break; 5049 case OPC2_32_BO_LD_Q_SHORTOFF: 5050 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5051 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5052 break; 5053 case OPC2_32_BO_LD_Q_POSTINC: 5054 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5055 MO_LEUW); 5056 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5057 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5058 break; 5059 case OPC2_32_BO_LD_Q_PREINC: 5060 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5061 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5062 break; 5063 case OPC2_32_BO_LD_W_SHORTOFF: 5064 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 5065 break; 5066 case OPC2_32_BO_LD_W_POSTINC: 5067 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5068 MO_LEUL); 5069 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5070 break; 5071 case OPC2_32_BO_LD_W_PREINC: 5072 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 5073 break; 5074 default: 5075 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5076 } 5077 } 5078 5079 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env, 5080 DisasContext *ctx) 5081 { 5082 uint32_t op2; 5083 uint32_t off10; 5084 int r1, r2; 5085 5086 TCGv temp, temp2, temp3; 5087 5088 r1 = MASK_OP_BO_S1D(ctx->opcode); 5089 r2 = MASK_OP_BO_S2(ctx->opcode); 5090 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 5091 op2 = MASK_OP_BO_OP2(ctx->opcode); 5092 5093 temp = tcg_temp_new(); 5094 temp2 = tcg_temp_new(); 5095 temp3 = tcg_const_i32(off10); 5096 CHECK_REG_PAIR(r2); 5097 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 5098 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5099 5100 5101 switch (op2) { 5102 case OPC2_32_BO_LD_A_BR: 5103 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 5104 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5105 break; 5106 case OPC2_32_BO_LD_A_CIRC: 5107 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 5108 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5109 break; 5110 case OPC2_32_BO_LD_B_BR: 5111 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 5112 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5113 break; 5114 case OPC2_32_BO_LD_B_CIRC: 5115 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 5116 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5117 break; 5118 case OPC2_32_BO_LD_BU_BR: 5119 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 5120 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5121 break; 5122 case OPC2_32_BO_LD_BU_CIRC: 5123 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 5124 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5125 break; 5126 case OPC2_32_BO_LD_D_BR: 5127 CHECK_REG_PAIR(r1); 5128 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 5129 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5130 break; 5131 case OPC2_32_BO_LD_D_CIRC: 5132 CHECK_REG_PAIR(r1); 5133 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 5134 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 5135 tcg_gen_addi_tl(temp, temp, 4); 5136 tcg_gen_rem_tl(temp, temp, temp2); 5137 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5138 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 5139 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5140 break; 5141 case OPC2_32_BO_LD_DA_BR: 5142 CHECK_REG_PAIR(r1); 5143 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 5144 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5145 break; 5146 case OPC2_32_BO_LD_DA_CIRC: 5147 CHECK_REG_PAIR(r1); 5148 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 5149 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 5150 tcg_gen_addi_tl(temp, temp, 4); 5151 tcg_gen_rem_tl(temp, temp, temp2); 5152 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5153 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 5154 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5155 break; 5156 case OPC2_32_BO_LD_H_BR: 5157 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 5158 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5159 break; 5160 case OPC2_32_BO_LD_H_CIRC: 5161 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 5162 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5163 break; 5164 case OPC2_32_BO_LD_HU_BR: 5165 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5166 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5167 break; 5168 case OPC2_32_BO_LD_HU_CIRC: 5169 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5170 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5171 break; 5172 case OPC2_32_BO_LD_Q_BR: 5173 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5174 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5175 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5176 break; 5177 case OPC2_32_BO_LD_Q_CIRC: 5178 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5179 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5180 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5181 break; 5182 case OPC2_32_BO_LD_W_BR: 5183 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 5184 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5185 break; 5186 case OPC2_32_BO_LD_W_CIRC: 5187 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 5188 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5189 break; 5190 default: 5191 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5192 } 5193 tcg_temp_free(temp); 5194 tcg_temp_free(temp2); 5195 tcg_temp_free(temp3); 5196 } 5197 5198 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env, 5199 DisasContext *ctx) 5200 { 5201 uint32_t op2; 5202 uint32_t off10; 5203 int r1, r2; 5204 5205 TCGv temp, temp2; 5206 5207 r1 = MASK_OP_BO_S1D(ctx->opcode); 5208 r2 = MASK_OP_BO_S2(ctx->opcode); 5209 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 5210 op2 = MASK_OP_BO_OP2(ctx->opcode); 5211 5212 5213 temp = tcg_temp_new(); 5214 temp2 = tcg_temp_new(); 5215 5216 switch (op2) { 5217 case OPC2_32_BO_LDLCX_SHORTOFF: 5218 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5219 gen_helper_ldlcx(cpu_env, temp); 5220 break; 5221 case OPC2_32_BO_LDMST_SHORTOFF: 5222 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5223 gen_ldmst(ctx, r1, temp); 5224 break; 5225 case OPC2_32_BO_LDMST_POSTINC: 5226 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 5227 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5228 break; 5229 case OPC2_32_BO_LDMST_PREINC: 5230 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5231 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 5232 break; 5233 case OPC2_32_BO_LDUCX_SHORTOFF: 5234 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5235 gen_helper_lducx(cpu_env, temp); 5236 break; 5237 case OPC2_32_BO_LEA_SHORTOFF: 5238 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); 5239 break; 5240 case OPC2_32_BO_STLCX_SHORTOFF: 5241 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5242 gen_helper_stlcx(cpu_env, temp); 5243 break; 5244 case OPC2_32_BO_STUCX_SHORTOFF: 5245 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5246 gen_helper_stucx(cpu_env, temp); 5247 break; 5248 case OPC2_32_BO_SWAP_W_SHORTOFF: 5249 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5250 gen_swap(ctx, r1, temp); 5251 break; 5252 case OPC2_32_BO_SWAP_W_POSTINC: 5253 gen_swap(ctx, r1, cpu_gpr_a[r2]); 5254 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5255 break; 5256 case OPC2_32_BO_SWAP_W_PREINC: 5257 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5258 gen_swap(ctx, r1, cpu_gpr_a[r2]); 5259 break; 5260 case OPC2_32_BO_CMPSWAP_W_SHORTOFF: 5261 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5262 gen_cmpswap(ctx, r1, temp); 5263 break; 5264 case OPC2_32_BO_CMPSWAP_W_POSTINC: 5265 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 5266 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5267 break; 5268 case OPC2_32_BO_CMPSWAP_W_PREINC: 5269 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5270 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 5271 break; 5272 case OPC2_32_BO_SWAPMSK_W_SHORTOFF: 5273 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5274 gen_swapmsk(ctx, r1, temp); 5275 break; 5276 case OPC2_32_BO_SWAPMSK_W_POSTINC: 5277 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 5278 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5279 break; 5280 case OPC2_32_BO_SWAPMSK_W_PREINC: 5281 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5282 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 5283 break; 5284 default: 5285 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5286 } 5287 tcg_temp_free(temp); 5288 tcg_temp_free(temp2); 5289 } 5290 5291 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env, 5292 DisasContext *ctx) 5293 { 5294 uint32_t op2; 5295 uint32_t off10; 5296 int r1, r2; 5297 5298 TCGv temp, temp2, temp3; 5299 5300 r1 = MASK_OP_BO_S1D(ctx->opcode); 5301 r2 = MASK_OP_BO_S2(ctx->opcode); 5302 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 5303 op2 = MASK_OP_BO_OP2(ctx->opcode); 5304 5305 temp = tcg_temp_new(); 5306 temp2 = tcg_temp_new(); 5307 temp3 = tcg_const_i32(off10); 5308 CHECK_REG_PAIR(r2); 5309 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 5310 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5311 5312 switch (op2) { 5313 case OPC2_32_BO_LDMST_BR: 5314 gen_ldmst(ctx, r1, temp2); 5315 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5316 break; 5317 case OPC2_32_BO_LDMST_CIRC: 5318 gen_ldmst(ctx, r1, temp2); 5319 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5320 break; 5321 case OPC2_32_BO_SWAP_W_BR: 5322 gen_swap(ctx, r1, temp2); 5323 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5324 break; 5325 case OPC2_32_BO_SWAP_W_CIRC: 5326 gen_swap(ctx, r1, temp2); 5327 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5328 break; 5329 case OPC2_32_BO_CMPSWAP_W_BR: 5330 gen_cmpswap(ctx, r1, temp2); 5331 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5332 break; 5333 case OPC2_32_BO_CMPSWAP_W_CIRC: 5334 gen_cmpswap(ctx, r1, temp2); 5335 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5336 break; 5337 case OPC2_32_BO_SWAPMSK_W_BR: 5338 gen_swapmsk(ctx, r1, temp2); 5339 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5340 break; 5341 case OPC2_32_BO_SWAPMSK_W_CIRC: 5342 gen_swapmsk(ctx, r1, temp2); 5343 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5344 break; 5345 default: 5346 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5347 } 5348 5349 tcg_temp_free(temp); 5350 tcg_temp_free(temp2); 5351 tcg_temp_free(temp3); 5352 } 5353 5354 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) 5355 { 5356 int r1, r2; 5357 int32_t address; 5358 TCGv temp; 5359 5360 r1 = MASK_OP_BOL_S1D(ctx->opcode); 5361 r2 = MASK_OP_BOL_S2(ctx->opcode); 5362 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); 5363 5364 switch (op1) { 5365 case OPC1_32_BOL_LD_A_LONGOFF: 5366 temp = tcg_temp_new(); 5367 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 5368 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); 5369 tcg_temp_free(temp); 5370 break; 5371 case OPC1_32_BOL_LD_W_LONGOFF: 5372 temp = tcg_temp_new(); 5373 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 5374 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); 5375 tcg_temp_free(temp); 5376 break; 5377 case OPC1_32_BOL_LEA_LONGOFF: 5378 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); 5379 break; 5380 case OPC1_32_BOL_ST_A_LONGOFF: 5381 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5382 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); 5383 } else { 5384 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5385 } 5386 break; 5387 case OPC1_32_BOL_ST_W_LONGOFF: 5388 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); 5389 break; 5390 case OPC1_32_BOL_LD_B_LONGOFF: 5391 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5392 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 5393 } else { 5394 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5395 } 5396 break; 5397 case OPC1_32_BOL_LD_BU_LONGOFF: 5398 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5399 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); 5400 } else { 5401 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5402 } 5403 break; 5404 case OPC1_32_BOL_LD_H_LONGOFF: 5405 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5406 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 5407 } else { 5408 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5409 } 5410 break; 5411 case OPC1_32_BOL_LD_HU_LONGOFF: 5412 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5413 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); 5414 } else { 5415 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5416 } 5417 break; 5418 case OPC1_32_BOL_ST_B_LONGOFF: 5419 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5420 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 5421 } else { 5422 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5423 } 5424 break; 5425 case OPC1_32_BOL_ST_H_LONGOFF: 5426 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5427 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 5428 } else { 5429 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5430 } 5431 break; 5432 default: 5433 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5434 } 5435 } 5436 5437 /* RC format */ 5438 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx) 5439 { 5440 uint32_t op2; 5441 int r1, r2; 5442 int32_t const9; 5443 TCGv temp; 5444 5445 r2 = MASK_OP_RC_D(ctx->opcode); 5446 r1 = MASK_OP_RC_S1(ctx->opcode); 5447 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5448 op2 = MASK_OP_RC_OP2(ctx->opcode); 5449 5450 temp = tcg_temp_new(); 5451 5452 switch (op2) { 5453 case OPC2_32_RC_AND: 5454 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5455 break; 5456 case OPC2_32_RC_ANDN: 5457 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 5458 break; 5459 case OPC2_32_RC_NAND: 5460 tcg_gen_movi_tl(temp, const9); 5461 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5462 break; 5463 case OPC2_32_RC_NOR: 5464 tcg_gen_movi_tl(temp, const9); 5465 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5466 break; 5467 case OPC2_32_RC_OR: 5468 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5469 break; 5470 case OPC2_32_RC_ORN: 5471 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 5472 break; 5473 case OPC2_32_RC_SH: 5474 const9 = sextract32(const9, 0, 6); 5475 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5476 break; 5477 case OPC2_32_RC_SH_H: 5478 const9 = sextract32(const9, 0, 5); 5479 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5480 break; 5481 case OPC2_32_RC_SHA: 5482 const9 = sextract32(const9, 0, 6); 5483 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5484 break; 5485 case OPC2_32_RC_SHA_H: 5486 const9 = sextract32(const9, 0, 5); 5487 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5488 break; 5489 case OPC2_32_RC_SHAS: 5490 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5491 break; 5492 case OPC2_32_RC_XNOR: 5493 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5494 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); 5495 break; 5496 case OPC2_32_RC_XOR: 5497 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5498 break; 5499 default: 5500 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5501 } 5502 tcg_temp_free(temp); 5503 } 5504 5505 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx) 5506 { 5507 uint32_t op2; 5508 int r1, r2; 5509 int16_t const9; 5510 5511 TCGv temp; 5512 5513 r2 = MASK_OP_RC_D(ctx->opcode); 5514 r1 = MASK_OP_RC_S1(ctx->opcode); 5515 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5516 5517 op2 = MASK_OP_RC_OP2(ctx->opcode); 5518 5519 temp = tcg_temp_new(); 5520 5521 switch (op2) { 5522 case OPC2_32_RC_ABSDIF: 5523 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5524 break; 5525 case OPC2_32_RC_ABSDIFS: 5526 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5527 break; 5528 case OPC2_32_RC_ADD: 5529 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5530 break; 5531 case OPC2_32_RC_ADDC: 5532 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5533 break; 5534 case OPC2_32_RC_ADDS: 5535 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5536 break; 5537 case OPC2_32_RC_ADDS_U: 5538 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5539 break; 5540 case OPC2_32_RC_ADDX: 5541 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5542 break; 5543 case OPC2_32_RC_AND_EQ: 5544 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5545 const9, &tcg_gen_and_tl); 5546 break; 5547 case OPC2_32_RC_AND_GE: 5548 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5549 const9, &tcg_gen_and_tl); 5550 break; 5551 case OPC2_32_RC_AND_GE_U: 5552 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5553 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5554 const9, &tcg_gen_and_tl); 5555 break; 5556 case OPC2_32_RC_AND_LT: 5557 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5558 const9, &tcg_gen_and_tl); 5559 break; 5560 case OPC2_32_RC_AND_LT_U: 5561 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5562 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5563 const9, &tcg_gen_and_tl); 5564 break; 5565 case OPC2_32_RC_AND_NE: 5566 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5567 const9, &tcg_gen_and_tl); 5568 break; 5569 case OPC2_32_RC_EQ: 5570 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5571 break; 5572 case OPC2_32_RC_EQANY_B: 5573 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5574 break; 5575 case OPC2_32_RC_EQANY_H: 5576 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5577 break; 5578 case OPC2_32_RC_GE: 5579 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5580 break; 5581 case OPC2_32_RC_GE_U: 5582 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5583 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5584 break; 5585 case OPC2_32_RC_LT: 5586 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5587 break; 5588 case OPC2_32_RC_LT_U: 5589 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5590 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5591 break; 5592 case OPC2_32_RC_MAX: 5593 tcg_gen_movi_tl(temp, const9); 5594 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5595 cpu_gpr_d[r1], temp); 5596 break; 5597 case OPC2_32_RC_MAX_U: 5598 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5599 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5600 cpu_gpr_d[r1], temp); 5601 break; 5602 case OPC2_32_RC_MIN: 5603 tcg_gen_movi_tl(temp, const9); 5604 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5605 cpu_gpr_d[r1], temp); 5606 break; 5607 case OPC2_32_RC_MIN_U: 5608 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5609 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5610 cpu_gpr_d[r1], temp); 5611 break; 5612 case OPC2_32_RC_NE: 5613 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5614 break; 5615 case OPC2_32_RC_OR_EQ: 5616 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5617 const9, &tcg_gen_or_tl); 5618 break; 5619 case OPC2_32_RC_OR_GE: 5620 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5621 const9, &tcg_gen_or_tl); 5622 break; 5623 case OPC2_32_RC_OR_GE_U: 5624 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5625 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5626 const9, &tcg_gen_or_tl); 5627 break; 5628 case OPC2_32_RC_OR_LT: 5629 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5630 const9, &tcg_gen_or_tl); 5631 break; 5632 case OPC2_32_RC_OR_LT_U: 5633 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5634 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5635 const9, &tcg_gen_or_tl); 5636 break; 5637 case OPC2_32_RC_OR_NE: 5638 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5639 const9, &tcg_gen_or_tl); 5640 break; 5641 case OPC2_32_RC_RSUB: 5642 tcg_gen_movi_tl(temp, const9); 5643 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5644 break; 5645 case OPC2_32_RC_RSUBS: 5646 tcg_gen_movi_tl(temp, const9); 5647 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5648 break; 5649 case OPC2_32_RC_RSUBS_U: 5650 tcg_gen_movi_tl(temp, const9); 5651 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5652 break; 5653 case OPC2_32_RC_SH_EQ: 5654 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5655 break; 5656 case OPC2_32_RC_SH_GE: 5657 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5658 break; 5659 case OPC2_32_RC_SH_GE_U: 5660 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5661 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5662 break; 5663 case OPC2_32_RC_SH_LT: 5664 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5665 break; 5666 case OPC2_32_RC_SH_LT_U: 5667 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5668 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5669 break; 5670 case OPC2_32_RC_SH_NE: 5671 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5672 break; 5673 case OPC2_32_RC_XOR_EQ: 5674 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5675 const9, &tcg_gen_xor_tl); 5676 break; 5677 case OPC2_32_RC_XOR_GE: 5678 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5679 const9, &tcg_gen_xor_tl); 5680 break; 5681 case OPC2_32_RC_XOR_GE_U: 5682 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5683 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5684 const9, &tcg_gen_xor_tl); 5685 break; 5686 case OPC2_32_RC_XOR_LT: 5687 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5688 const9, &tcg_gen_xor_tl); 5689 break; 5690 case OPC2_32_RC_XOR_LT_U: 5691 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5692 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5693 const9, &tcg_gen_xor_tl); 5694 break; 5695 case OPC2_32_RC_XOR_NE: 5696 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5697 const9, &tcg_gen_xor_tl); 5698 break; 5699 default: 5700 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5701 } 5702 tcg_temp_free(temp); 5703 } 5704 5705 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx) 5706 { 5707 uint32_t op2; 5708 uint32_t const9; 5709 5710 op2 = MASK_OP_RC_OP2(ctx->opcode); 5711 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5712 5713 switch (op2) { 5714 case OPC2_32_RC_BISR: 5715 gen_helper_1arg(bisr, const9); 5716 break; 5717 case OPC2_32_RC_SYSCALL: 5718 /* TODO: Add exception generation */ 5719 break; 5720 default: 5721 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5722 } 5723 } 5724 5725 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx) 5726 { 5727 uint32_t op2; 5728 int r1, r2; 5729 int16_t const9; 5730 5731 r2 = MASK_OP_RC_D(ctx->opcode); 5732 r1 = MASK_OP_RC_S1(ctx->opcode); 5733 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5734 5735 op2 = MASK_OP_RC_OP2(ctx->opcode); 5736 5737 switch (op2) { 5738 case OPC2_32_RC_MUL_32: 5739 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5740 break; 5741 case OPC2_32_RC_MUL_64: 5742 CHECK_REG_PAIR(r2); 5743 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5744 break; 5745 case OPC2_32_RC_MULS_32: 5746 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5747 break; 5748 case OPC2_32_RC_MUL_U_64: 5749 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5750 CHECK_REG_PAIR(r2); 5751 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5752 break; 5753 case OPC2_32_RC_MULS_U_32: 5754 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5755 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5756 break; 5757 default: 5758 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5759 } 5760 } 5761 5762 /* RCPW format */ 5763 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx) 5764 { 5765 uint32_t op2; 5766 int r1, r2; 5767 int32_t pos, width, const4; 5768 5769 TCGv temp; 5770 5771 op2 = MASK_OP_RCPW_OP2(ctx->opcode); 5772 r1 = MASK_OP_RCPW_S1(ctx->opcode); 5773 r2 = MASK_OP_RCPW_D(ctx->opcode); 5774 const4 = MASK_OP_RCPW_CONST4(ctx->opcode); 5775 width = MASK_OP_RCPW_WIDTH(ctx->opcode); 5776 pos = MASK_OP_RCPW_POS(ctx->opcode); 5777 5778 switch (op2) { 5779 case OPC2_32_RCPW_IMASK: 5780 CHECK_REG_PAIR(r2); 5781 /* if pos + width > 31 undefined result */ 5782 if (pos + width <= 31) { 5783 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); 5784 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); 5785 } 5786 break; 5787 case OPC2_32_RCPW_INSERT: 5788 /* if pos + width > 32 undefined result */ 5789 if (pos + width <= 32) { 5790 temp = tcg_const_i32(const4); 5791 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); 5792 tcg_temp_free(temp); 5793 } 5794 break; 5795 default: 5796 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5797 } 5798 } 5799 5800 /* RCRW format */ 5801 5802 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx) 5803 { 5804 uint32_t op2; 5805 int r1, r3, r4; 5806 int32_t width, const4; 5807 5808 TCGv temp, temp2, temp3; 5809 5810 op2 = MASK_OP_RCRW_OP2(ctx->opcode); 5811 r1 = MASK_OP_RCRW_S1(ctx->opcode); 5812 r3 = MASK_OP_RCRW_S3(ctx->opcode); 5813 r4 = MASK_OP_RCRW_D(ctx->opcode); 5814 width = MASK_OP_RCRW_WIDTH(ctx->opcode); 5815 const4 = MASK_OP_RCRW_CONST4(ctx->opcode); 5816 5817 temp = tcg_temp_new(); 5818 temp2 = tcg_temp_new(); 5819 5820 switch (op2) { 5821 case OPC2_32_RCRW_IMASK: 5822 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); 5823 tcg_gen_movi_tl(temp2, (1 << width) - 1); 5824 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); 5825 tcg_gen_movi_tl(temp2, const4); 5826 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); 5827 break; 5828 case OPC2_32_RCRW_INSERT: 5829 temp3 = tcg_temp_new(); 5830 5831 tcg_gen_movi_tl(temp, width); 5832 tcg_gen_movi_tl(temp2, const4); 5833 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f); 5834 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3); 5835 5836 tcg_temp_free(temp3); 5837 break; 5838 default: 5839 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5840 } 5841 tcg_temp_free(temp); 5842 tcg_temp_free(temp2); 5843 } 5844 5845 /* RCR format */ 5846 5847 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx) 5848 { 5849 uint32_t op2; 5850 int r1, r3, r4; 5851 int32_t const9; 5852 5853 TCGv temp, temp2; 5854 5855 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5856 r1 = MASK_OP_RCR_S1(ctx->opcode); 5857 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5858 r3 = MASK_OP_RCR_S3(ctx->opcode); 5859 r4 = MASK_OP_RCR_D(ctx->opcode); 5860 5861 switch (op2) { 5862 case OPC2_32_RCR_CADD: 5863 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5864 cpu_gpr_d[r3]); 5865 break; 5866 case OPC2_32_RCR_CADDN: 5867 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5868 cpu_gpr_d[r3]); 5869 break; 5870 case OPC2_32_RCR_SEL: 5871 temp = tcg_const_i32(0); 5872 temp2 = tcg_const_i32(const9); 5873 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5874 cpu_gpr_d[r1], temp2); 5875 tcg_temp_free(temp); 5876 tcg_temp_free(temp2); 5877 break; 5878 case OPC2_32_RCR_SELN: 5879 temp = tcg_const_i32(0); 5880 temp2 = tcg_const_i32(const9); 5881 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5882 cpu_gpr_d[r1], temp2); 5883 tcg_temp_free(temp); 5884 tcg_temp_free(temp2); 5885 break; 5886 default: 5887 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5888 } 5889 } 5890 5891 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx) 5892 { 5893 uint32_t op2; 5894 int r1, r3, r4; 5895 int32_t const9; 5896 5897 5898 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5899 r1 = MASK_OP_RCR_S1(ctx->opcode); 5900 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5901 r3 = MASK_OP_RCR_S3(ctx->opcode); 5902 r4 = MASK_OP_RCR_D(ctx->opcode); 5903 5904 switch (op2) { 5905 case OPC2_32_RCR_MADD_32: 5906 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5907 break; 5908 case OPC2_32_RCR_MADD_64: 5909 CHECK_REG_PAIR(r4); 5910 CHECK_REG_PAIR(r3); 5911 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5912 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5913 break; 5914 case OPC2_32_RCR_MADDS_32: 5915 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5916 break; 5917 case OPC2_32_RCR_MADDS_64: 5918 CHECK_REG_PAIR(r4); 5919 CHECK_REG_PAIR(r3); 5920 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5921 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5922 break; 5923 case OPC2_32_RCR_MADD_U_64: 5924 CHECK_REG_PAIR(r4); 5925 CHECK_REG_PAIR(r3); 5926 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5927 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5928 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5929 break; 5930 case OPC2_32_RCR_MADDS_U_32: 5931 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5932 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5933 break; 5934 case OPC2_32_RCR_MADDS_U_64: 5935 CHECK_REG_PAIR(r4); 5936 CHECK_REG_PAIR(r3); 5937 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5938 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5939 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5940 break; 5941 default: 5942 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5943 } 5944 } 5945 5946 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx) 5947 { 5948 uint32_t op2; 5949 int r1, r3, r4; 5950 int32_t const9; 5951 5952 5953 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5954 r1 = MASK_OP_RCR_S1(ctx->opcode); 5955 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5956 r3 = MASK_OP_RCR_S3(ctx->opcode); 5957 r4 = MASK_OP_RCR_D(ctx->opcode); 5958 5959 switch (op2) { 5960 case OPC2_32_RCR_MSUB_32: 5961 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5962 break; 5963 case OPC2_32_RCR_MSUB_64: 5964 CHECK_REG_PAIR(r4); 5965 CHECK_REG_PAIR(r3); 5966 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5967 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5968 break; 5969 case OPC2_32_RCR_MSUBS_32: 5970 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5971 break; 5972 case OPC2_32_RCR_MSUBS_64: 5973 CHECK_REG_PAIR(r4); 5974 CHECK_REG_PAIR(r3); 5975 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5976 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5977 break; 5978 case OPC2_32_RCR_MSUB_U_64: 5979 CHECK_REG_PAIR(r4); 5980 CHECK_REG_PAIR(r3); 5981 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5982 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5983 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5984 break; 5985 case OPC2_32_RCR_MSUBS_U_32: 5986 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5987 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5988 break; 5989 case OPC2_32_RCR_MSUBS_U_64: 5990 CHECK_REG_PAIR(r4); 5991 CHECK_REG_PAIR(r3); 5992 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5993 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5994 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5995 break; 5996 default: 5997 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5998 } 5999 } 6000 6001 /* RLC format */ 6002 6003 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, 6004 uint32_t op1) 6005 { 6006 int32_t const16; 6007 int r1, r2; 6008 6009 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); 6010 r1 = MASK_OP_RLC_S1(ctx->opcode); 6011 r2 = MASK_OP_RLC_D(ctx->opcode); 6012 6013 switch (op1) { 6014 case OPC1_32_RLC_ADDI: 6015 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); 6016 break; 6017 case OPC1_32_RLC_ADDIH: 6018 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); 6019 break; 6020 case OPC1_32_RLC_ADDIH_A: 6021 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); 6022 break; 6023 case OPC1_32_RLC_MFCR: 6024 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 6025 gen_mfcr(env, cpu_gpr_d[r2], const16); 6026 break; 6027 case OPC1_32_RLC_MOV: 6028 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 6029 break; 6030 case OPC1_32_RLC_MOV_64: 6031 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6032 CHECK_REG_PAIR(r2); 6033 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 6034 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); 6035 } else { 6036 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6037 } 6038 break; 6039 case OPC1_32_RLC_MOV_U: 6040 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 6041 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 6042 break; 6043 case OPC1_32_RLC_MOV_H: 6044 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); 6045 break; 6046 case OPC1_32_RLC_MOVH_A: 6047 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); 6048 break; 6049 case OPC1_32_RLC_MTCR: 6050 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 6051 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16); 6052 break; 6053 default: 6054 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6055 } 6056 } 6057 6058 /* RR format */ 6059 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) 6060 { 6061 uint32_t op2; 6062 int r3, r2, r1; 6063 6064 TCGv temp; 6065 6066 r3 = MASK_OP_RR_D(ctx->opcode); 6067 r2 = MASK_OP_RR_S2(ctx->opcode); 6068 r1 = MASK_OP_RR_S1(ctx->opcode); 6069 op2 = MASK_OP_RR_OP2(ctx->opcode); 6070 6071 switch (op2) { 6072 case OPC2_32_RR_ABS: 6073 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6074 break; 6075 case OPC2_32_RR_ABS_B: 6076 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6077 break; 6078 case OPC2_32_RR_ABS_H: 6079 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6080 break; 6081 case OPC2_32_RR_ABSDIF: 6082 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6083 break; 6084 case OPC2_32_RR_ABSDIF_B: 6085 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6086 cpu_gpr_d[r2]); 6087 break; 6088 case OPC2_32_RR_ABSDIF_H: 6089 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6090 cpu_gpr_d[r2]); 6091 break; 6092 case OPC2_32_RR_ABSDIFS: 6093 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6094 cpu_gpr_d[r2]); 6095 break; 6096 case OPC2_32_RR_ABSDIFS_H: 6097 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6098 cpu_gpr_d[r2]); 6099 break; 6100 case OPC2_32_RR_ABSS: 6101 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6102 break; 6103 case OPC2_32_RR_ABSS_H: 6104 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6105 break; 6106 case OPC2_32_RR_ADD: 6107 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6108 break; 6109 case OPC2_32_RR_ADD_B: 6110 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6111 break; 6112 case OPC2_32_RR_ADD_H: 6113 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6114 break; 6115 case OPC2_32_RR_ADDC: 6116 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6117 break; 6118 case OPC2_32_RR_ADDS: 6119 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6120 break; 6121 case OPC2_32_RR_ADDS_H: 6122 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6123 cpu_gpr_d[r2]); 6124 break; 6125 case OPC2_32_RR_ADDS_HU: 6126 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6127 cpu_gpr_d[r2]); 6128 break; 6129 case OPC2_32_RR_ADDS_U: 6130 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6131 cpu_gpr_d[r2]); 6132 break; 6133 case OPC2_32_RR_ADDX: 6134 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6135 break; 6136 case OPC2_32_RR_AND_EQ: 6137 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6138 cpu_gpr_d[r2], &tcg_gen_and_tl); 6139 break; 6140 case OPC2_32_RR_AND_GE: 6141 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6142 cpu_gpr_d[r2], &tcg_gen_and_tl); 6143 break; 6144 case OPC2_32_RR_AND_GE_U: 6145 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6146 cpu_gpr_d[r2], &tcg_gen_and_tl); 6147 break; 6148 case OPC2_32_RR_AND_LT: 6149 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6150 cpu_gpr_d[r2], &tcg_gen_and_tl); 6151 break; 6152 case OPC2_32_RR_AND_LT_U: 6153 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6154 cpu_gpr_d[r2], &tcg_gen_and_tl); 6155 break; 6156 case OPC2_32_RR_AND_NE: 6157 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6158 cpu_gpr_d[r2], &tcg_gen_and_tl); 6159 break; 6160 case OPC2_32_RR_EQ: 6161 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6162 cpu_gpr_d[r2]); 6163 break; 6164 case OPC2_32_RR_EQ_B: 6165 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6166 break; 6167 case OPC2_32_RR_EQ_H: 6168 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6169 break; 6170 case OPC2_32_RR_EQ_W: 6171 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6172 break; 6173 case OPC2_32_RR_EQANY_B: 6174 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6175 break; 6176 case OPC2_32_RR_EQANY_H: 6177 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6178 break; 6179 case OPC2_32_RR_GE: 6180 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6181 cpu_gpr_d[r2]); 6182 break; 6183 case OPC2_32_RR_GE_U: 6184 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6185 cpu_gpr_d[r2]); 6186 break; 6187 case OPC2_32_RR_LT: 6188 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6189 cpu_gpr_d[r2]); 6190 break; 6191 case OPC2_32_RR_LT_U: 6192 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6193 cpu_gpr_d[r2]); 6194 break; 6195 case OPC2_32_RR_LT_B: 6196 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6197 break; 6198 case OPC2_32_RR_LT_BU: 6199 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6200 break; 6201 case OPC2_32_RR_LT_H: 6202 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6203 break; 6204 case OPC2_32_RR_LT_HU: 6205 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6206 break; 6207 case OPC2_32_RR_LT_W: 6208 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6209 break; 6210 case OPC2_32_RR_LT_WU: 6211 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6212 break; 6213 case OPC2_32_RR_MAX: 6214 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6215 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6216 break; 6217 case OPC2_32_RR_MAX_U: 6218 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6219 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6220 break; 6221 case OPC2_32_RR_MAX_B: 6222 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6223 break; 6224 case OPC2_32_RR_MAX_BU: 6225 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6226 break; 6227 case OPC2_32_RR_MAX_H: 6228 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6229 break; 6230 case OPC2_32_RR_MAX_HU: 6231 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6232 break; 6233 case OPC2_32_RR_MIN: 6234 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6235 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6236 break; 6237 case OPC2_32_RR_MIN_U: 6238 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6239 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6240 break; 6241 case OPC2_32_RR_MIN_B: 6242 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6243 break; 6244 case OPC2_32_RR_MIN_BU: 6245 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6246 break; 6247 case OPC2_32_RR_MIN_H: 6248 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6249 break; 6250 case OPC2_32_RR_MIN_HU: 6251 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6252 break; 6253 case OPC2_32_RR_MOV: 6254 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6255 break; 6256 case OPC2_32_RR_MOV_64: 6257 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6258 temp = tcg_temp_new(); 6259 6260 CHECK_REG_PAIR(r3); 6261 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 6262 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6263 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 6264 6265 tcg_temp_free(temp); 6266 } else { 6267 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6268 } 6269 break; 6270 case OPC2_32_RR_MOVS_64: 6271 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6272 CHECK_REG_PAIR(r3); 6273 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6274 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); 6275 } else { 6276 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6277 } 6278 break; 6279 case OPC2_32_RR_NE: 6280 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6281 cpu_gpr_d[r2]); 6282 break; 6283 case OPC2_32_RR_OR_EQ: 6284 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6285 cpu_gpr_d[r2], &tcg_gen_or_tl); 6286 break; 6287 case OPC2_32_RR_OR_GE: 6288 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6289 cpu_gpr_d[r2], &tcg_gen_or_tl); 6290 break; 6291 case OPC2_32_RR_OR_GE_U: 6292 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6293 cpu_gpr_d[r2], &tcg_gen_or_tl); 6294 break; 6295 case OPC2_32_RR_OR_LT: 6296 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6297 cpu_gpr_d[r2], &tcg_gen_or_tl); 6298 break; 6299 case OPC2_32_RR_OR_LT_U: 6300 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6301 cpu_gpr_d[r2], &tcg_gen_or_tl); 6302 break; 6303 case OPC2_32_RR_OR_NE: 6304 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6305 cpu_gpr_d[r2], &tcg_gen_or_tl); 6306 break; 6307 case OPC2_32_RR_SAT_B: 6308 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); 6309 break; 6310 case OPC2_32_RR_SAT_BU: 6311 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); 6312 break; 6313 case OPC2_32_RR_SAT_H: 6314 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); 6315 break; 6316 case OPC2_32_RR_SAT_HU: 6317 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); 6318 break; 6319 case OPC2_32_RR_SH_EQ: 6320 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6321 cpu_gpr_d[r2]); 6322 break; 6323 case OPC2_32_RR_SH_GE: 6324 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6325 cpu_gpr_d[r2]); 6326 break; 6327 case OPC2_32_RR_SH_GE_U: 6328 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6329 cpu_gpr_d[r2]); 6330 break; 6331 case OPC2_32_RR_SH_LT: 6332 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6333 cpu_gpr_d[r2]); 6334 break; 6335 case OPC2_32_RR_SH_LT_U: 6336 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6337 cpu_gpr_d[r2]); 6338 break; 6339 case OPC2_32_RR_SH_NE: 6340 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6341 cpu_gpr_d[r2]); 6342 break; 6343 case OPC2_32_RR_SUB: 6344 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6345 break; 6346 case OPC2_32_RR_SUB_B: 6347 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6348 break; 6349 case OPC2_32_RR_SUB_H: 6350 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6351 break; 6352 case OPC2_32_RR_SUBC: 6353 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6354 break; 6355 case OPC2_32_RR_SUBS: 6356 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6357 break; 6358 case OPC2_32_RR_SUBS_U: 6359 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6360 break; 6361 case OPC2_32_RR_SUBS_H: 6362 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6363 cpu_gpr_d[r2]); 6364 break; 6365 case OPC2_32_RR_SUBS_HU: 6366 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6367 cpu_gpr_d[r2]); 6368 break; 6369 case OPC2_32_RR_SUBX: 6370 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6371 break; 6372 case OPC2_32_RR_XOR_EQ: 6373 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6374 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6375 break; 6376 case OPC2_32_RR_XOR_GE: 6377 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6378 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6379 break; 6380 case OPC2_32_RR_XOR_GE_U: 6381 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6382 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6383 break; 6384 case OPC2_32_RR_XOR_LT: 6385 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6386 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6387 break; 6388 case OPC2_32_RR_XOR_LT_U: 6389 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6390 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6391 break; 6392 case OPC2_32_RR_XOR_NE: 6393 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6394 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6395 break; 6396 default: 6397 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6398 } 6399 } 6400 6401 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) 6402 { 6403 uint32_t op2; 6404 int r3, r2, r1; 6405 TCGv temp; 6406 6407 r3 = MASK_OP_RR_D(ctx->opcode); 6408 r2 = MASK_OP_RR_S2(ctx->opcode); 6409 r1 = MASK_OP_RR_S1(ctx->opcode); 6410 6411 temp = tcg_temp_new(); 6412 op2 = MASK_OP_RR_OP2(ctx->opcode); 6413 6414 switch (op2) { 6415 case OPC2_32_RR_AND: 6416 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6417 break; 6418 case OPC2_32_RR_ANDN: 6419 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6420 break; 6421 case OPC2_32_RR_CLO: 6422 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6423 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); 6424 break; 6425 case OPC2_32_RR_CLO_H: 6426 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6427 break; 6428 case OPC2_32_RR_CLS: 6429 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6430 break; 6431 case OPC2_32_RR_CLS_H: 6432 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6433 break; 6434 case OPC2_32_RR_CLZ: 6435 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); 6436 break; 6437 case OPC2_32_RR_CLZ_H: 6438 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6439 break; 6440 case OPC2_32_RR_NAND: 6441 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6442 break; 6443 case OPC2_32_RR_NOR: 6444 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6445 break; 6446 case OPC2_32_RR_OR: 6447 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6448 break; 6449 case OPC2_32_RR_ORN: 6450 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6451 break; 6452 case OPC2_32_RR_SH: 6453 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6454 break; 6455 case OPC2_32_RR_SH_H: 6456 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6457 break; 6458 case OPC2_32_RR_SHA: 6459 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6460 break; 6461 case OPC2_32_RR_SHA_H: 6462 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6463 break; 6464 case OPC2_32_RR_SHAS: 6465 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6466 break; 6467 case OPC2_32_RR_XNOR: 6468 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6469 break; 6470 case OPC2_32_RR_XOR: 6471 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6472 break; 6473 default: 6474 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6475 } 6476 tcg_temp_free(temp); 6477 } 6478 6479 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx) 6480 { 6481 uint32_t op2, n; 6482 int r1, r2, r3; 6483 TCGv temp; 6484 6485 op2 = MASK_OP_RR_OP2(ctx->opcode); 6486 r3 = MASK_OP_RR_D(ctx->opcode); 6487 r2 = MASK_OP_RR_S2(ctx->opcode); 6488 r1 = MASK_OP_RR_S1(ctx->opcode); 6489 n = MASK_OP_RR_N(ctx->opcode); 6490 6491 switch (op2) { 6492 case OPC2_32_RR_ADD_A: 6493 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6494 break; 6495 case OPC2_32_RR_ADDSC_A: 6496 temp = tcg_temp_new(); 6497 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); 6498 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); 6499 tcg_temp_free(temp); 6500 break; 6501 case OPC2_32_RR_ADDSC_AT: 6502 temp = tcg_temp_new(); 6503 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); 6504 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); 6505 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); 6506 tcg_temp_free(temp); 6507 break; 6508 case OPC2_32_RR_EQ_A: 6509 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 6510 cpu_gpr_a[r2]); 6511 break; 6512 case OPC2_32_RR_EQZ: 6513 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6514 break; 6515 case OPC2_32_RR_GE_A: 6516 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6517 cpu_gpr_a[r2]); 6518 break; 6519 case OPC2_32_RR_LT_A: 6520 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6521 cpu_gpr_a[r2]); 6522 break; 6523 case OPC2_32_RR_MOV_A: 6524 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); 6525 break; 6526 case OPC2_32_RR_MOV_AA: 6527 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); 6528 break; 6529 case OPC2_32_RR_MOV_D: 6530 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); 6531 break; 6532 case OPC2_32_RR_NE_A: 6533 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 6534 cpu_gpr_a[r2]); 6535 break; 6536 case OPC2_32_RR_NEZ_A: 6537 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6538 break; 6539 case OPC2_32_RR_SUB_A: 6540 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6541 break; 6542 default: 6543 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6544 } 6545 } 6546 6547 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) 6548 { 6549 uint32_t op2; 6550 int r1; 6551 6552 op2 = MASK_OP_RR_OP2(ctx->opcode); 6553 r1 = MASK_OP_RR_S1(ctx->opcode); 6554 6555 switch (op2) { 6556 case OPC2_32_RR_JI: 6557 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6558 break; 6559 case OPC2_32_RR_JLI: 6560 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 6561 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6562 break; 6563 case OPC2_32_RR_CALLI: 6564 gen_helper_1arg(call, ctx->next_pc); 6565 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6566 break; 6567 case OPC2_32_RR_FCALLI: 6568 gen_fcall_save_ctx(ctx); 6569 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6570 break; 6571 default: 6572 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6573 } 6574 tcg_gen_exit_tb(NULL, 0); 6575 ctx->bstate = BS_BRANCH; 6576 } 6577 6578 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) 6579 { 6580 uint32_t op2; 6581 int r1, r2, r3; 6582 6583 TCGv temp, temp2, temp3; 6584 6585 op2 = MASK_OP_RR_OP2(ctx->opcode); 6586 r3 = MASK_OP_RR_D(ctx->opcode); 6587 r2 = MASK_OP_RR_S2(ctx->opcode); 6588 r1 = MASK_OP_RR_S1(ctx->opcode); 6589 6590 switch (op2) { 6591 case OPC2_32_RR_BMERGE: 6592 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6593 break; 6594 case OPC2_32_RR_BSPLIT: 6595 CHECK_REG_PAIR(r3); 6596 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6597 break; 6598 case OPC2_32_RR_DVINIT_B: 6599 CHECK_REG_PAIR(r3); 6600 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6601 cpu_gpr_d[r2]); 6602 break; 6603 case OPC2_32_RR_DVINIT_BU: 6604 temp = tcg_temp_new(); 6605 temp2 = tcg_temp_new(); 6606 temp3 = tcg_temp_new(); 6607 CHECK_REG_PAIR(r3); 6608 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); 6609 /* reset av */ 6610 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6611 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 6612 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6613 tcg_gen_abs_tl(temp, temp3); 6614 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6615 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6616 } else { 6617 /* overflow = (D[b] == 0) */ 6618 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6619 } 6620 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6621 /* sv */ 6622 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6623 /* write result */ 6624 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); 6625 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6626 6627 tcg_temp_free(temp); 6628 tcg_temp_free(temp2); 6629 tcg_temp_free(temp3); 6630 break; 6631 case OPC2_32_RR_DVINIT_H: 6632 CHECK_REG_PAIR(r3); 6633 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6634 cpu_gpr_d[r2]); 6635 break; 6636 case OPC2_32_RR_DVINIT_HU: 6637 temp = tcg_temp_new(); 6638 temp2 = tcg_temp_new(); 6639 temp3 = tcg_temp_new(); 6640 CHECK_REG_PAIR(r3); 6641 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); 6642 /* reset av */ 6643 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6644 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 6645 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6646 tcg_gen_abs_tl(temp, temp3); 6647 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); 6648 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6649 } else { 6650 /* overflow = (D[b] == 0) */ 6651 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6652 } 6653 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6654 /* sv */ 6655 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6656 /* write result */ 6657 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); 6658 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6659 tcg_temp_free(temp); 6660 tcg_temp_free(temp2); 6661 tcg_temp_free(temp3); 6662 break; 6663 case OPC2_32_RR_DVINIT: 6664 temp = tcg_temp_new(); 6665 temp2 = tcg_temp_new(); 6666 CHECK_REG_PAIR(r3); 6667 /* overflow = ((D[b] == 0) || 6668 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ 6669 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); 6670 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); 6671 tcg_gen_and_tl(temp, temp, temp2); 6672 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); 6673 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 6674 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6675 /* sv */ 6676 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6677 /* reset av */ 6678 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6679 /* write result */ 6680 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6681 /* sign extend to high reg */ 6682 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); 6683 tcg_temp_free(temp); 6684 tcg_temp_free(temp2); 6685 break; 6686 case OPC2_32_RR_DVINIT_U: 6687 /* overflow = (D[b] == 0) */ 6688 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6689 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6690 /* sv */ 6691 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6692 /* reset av */ 6693 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6694 /* write result */ 6695 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6696 /* zero extend to high reg*/ 6697 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); 6698 break; 6699 case OPC2_32_RR_PARITY: 6700 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6701 break; 6702 case OPC2_32_RR_UNPACK: 6703 CHECK_REG_PAIR(r3); 6704 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6705 break; 6706 case OPC2_32_RR_CRC32: 6707 if (tricore_feature(env, TRICORE_FEATURE_161)) { 6708 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6709 } else { 6710 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6711 } 6712 break; 6713 case OPC2_32_RR_DIV: 6714 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6715 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6716 cpu_gpr_d[r2]); 6717 } else { 6718 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6719 } 6720 break; 6721 case OPC2_32_RR_DIV_U: 6722 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6723 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], 6724 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6725 } else { 6726 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6727 } 6728 break; 6729 case OPC2_32_RR_MUL_F: 6730 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6731 break; 6732 case OPC2_32_RR_DIV_F: 6733 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6734 break; 6735 case OPC2_32_RR_CMP_F: 6736 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6737 break; 6738 case OPC2_32_RR_FTOI: 6739 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6740 break; 6741 case OPC2_32_RR_ITOF: 6742 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6743 break; 6744 case OPC2_32_RR_FTOUZ: 6745 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6746 break; 6747 case OPC2_32_RR_UPDFL: 6748 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); 6749 break; 6750 case OPC2_32_RR_UTOF: 6751 gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6752 break; 6753 case OPC2_32_RR_FTOIZ: 6754 gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6755 break; 6756 case OPC2_32_RR_QSEED_F: 6757 gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6758 break; 6759 default: 6760 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6761 } 6762 } 6763 6764 /* RR1 Format */ 6765 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx) 6766 { 6767 uint32_t op2; 6768 6769 int r1, r2, r3; 6770 TCGv n; 6771 TCGv_i64 temp64; 6772 6773 r1 = MASK_OP_RR1_S1(ctx->opcode); 6774 r2 = MASK_OP_RR1_S2(ctx->opcode); 6775 r3 = MASK_OP_RR1_D(ctx->opcode); 6776 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode)); 6777 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6778 6779 switch (op2) { 6780 case OPC2_32_RR1_MUL_H_32_LL: 6781 temp64 = tcg_temp_new_i64(); 6782 CHECK_REG_PAIR(r3); 6783 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6784 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6785 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6786 tcg_temp_free_i64(temp64); 6787 break; 6788 case OPC2_32_RR1_MUL_H_32_LU: 6789 temp64 = tcg_temp_new_i64(); 6790 CHECK_REG_PAIR(r3); 6791 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6792 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6793 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6794 tcg_temp_free_i64(temp64); 6795 break; 6796 case OPC2_32_RR1_MUL_H_32_UL: 6797 temp64 = tcg_temp_new_i64(); 6798 CHECK_REG_PAIR(r3); 6799 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6800 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6801 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6802 tcg_temp_free_i64(temp64); 6803 break; 6804 case OPC2_32_RR1_MUL_H_32_UU: 6805 temp64 = tcg_temp_new_i64(); 6806 CHECK_REG_PAIR(r3); 6807 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6808 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6809 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6810 tcg_temp_free_i64(temp64); 6811 break; 6812 case OPC2_32_RR1_MULM_H_64_LL: 6813 temp64 = tcg_temp_new_i64(); 6814 CHECK_REG_PAIR(r3); 6815 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6816 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6817 /* reset V bit */ 6818 tcg_gen_movi_tl(cpu_PSW_V, 0); 6819 /* reset AV bit */ 6820 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6821 tcg_temp_free_i64(temp64); 6822 break; 6823 case OPC2_32_RR1_MULM_H_64_LU: 6824 temp64 = tcg_temp_new_i64(); 6825 CHECK_REG_PAIR(r3); 6826 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6827 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6828 /* reset V bit */ 6829 tcg_gen_movi_tl(cpu_PSW_V, 0); 6830 /* reset AV bit */ 6831 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6832 tcg_temp_free_i64(temp64); 6833 break; 6834 case OPC2_32_RR1_MULM_H_64_UL: 6835 temp64 = tcg_temp_new_i64(); 6836 CHECK_REG_PAIR(r3); 6837 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6838 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6839 /* reset V bit */ 6840 tcg_gen_movi_tl(cpu_PSW_V, 0); 6841 /* reset AV bit */ 6842 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6843 tcg_temp_free_i64(temp64); 6844 break; 6845 case OPC2_32_RR1_MULM_H_64_UU: 6846 temp64 = tcg_temp_new_i64(); 6847 CHECK_REG_PAIR(r3); 6848 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6849 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6850 /* reset V bit */ 6851 tcg_gen_movi_tl(cpu_PSW_V, 0); 6852 /* reset AV bit */ 6853 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6854 tcg_temp_free_i64(temp64); 6855 6856 break; 6857 case OPC2_32_RR1_MULR_H_16_LL: 6858 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6859 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6860 break; 6861 case OPC2_32_RR1_MULR_H_16_LU: 6862 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6863 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6864 break; 6865 case OPC2_32_RR1_MULR_H_16_UL: 6866 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6867 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6868 break; 6869 case OPC2_32_RR1_MULR_H_16_UU: 6870 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6871 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6872 break; 6873 default: 6874 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6875 } 6876 tcg_temp_free(n); 6877 } 6878 6879 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx) 6880 { 6881 uint32_t op2; 6882 int r1, r2, r3; 6883 uint32_t n; 6884 6885 TCGv temp, temp2; 6886 6887 r1 = MASK_OP_RR1_S1(ctx->opcode); 6888 r2 = MASK_OP_RR1_S2(ctx->opcode); 6889 r3 = MASK_OP_RR1_D(ctx->opcode); 6890 n = MASK_OP_RR1_N(ctx->opcode); 6891 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6892 6893 temp = tcg_temp_new(); 6894 temp2 = tcg_temp_new(); 6895 6896 switch (op2) { 6897 case OPC2_32_RR1_MUL_Q_32: 6898 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); 6899 break; 6900 case OPC2_32_RR1_MUL_Q_64: 6901 CHECK_REG_PAIR(r3); 6902 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6903 n, 0); 6904 break; 6905 case OPC2_32_RR1_MUL_Q_32_L: 6906 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6907 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6908 break; 6909 case OPC2_32_RR1_MUL_Q_64_L: 6910 CHECK_REG_PAIR(r3); 6911 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6912 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6913 break; 6914 case OPC2_32_RR1_MUL_Q_32_U: 6915 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6916 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6917 break; 6918 case OPC2_32_RR1_MUL_Q_64_U: 6919 CHECK_REG_PAIR(r3); 6920 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6921 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6922 break; 6923 case OPC2_32_RR1_MUL_Q_32_LL: 6924 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6925 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6926 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6927 break; 6928 case OPC2_32_RR1_MUL_Q_32_UU: 6929 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6930 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6931 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6932 break; 6933 case OPC2_32_RR1_MULR_Q_32_L: 6934 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6935 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6936 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6937 break; 6938 case OPC2_32_RR1_MULR_Q_32_U: 6939 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6940 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6941 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6942 break; 6943 default: 6944 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6945 } 6946 tcg_temp_free(temp); 6947 tcg_temp_free(temp2); 6948 } 6949 6950 /* RR2 format */ 6951 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx) 6952 { 6953 uint32_t op2; 6954 int r1, r2, r3; 6955 6956 op2 = MASK_OP_RR2_OP2(ctx->opcode); 6957 r1 = MASK_OP_RR2_S1(ctx->opcode); 6958 r2 = MASK_OP_RR2_S2(ctx->opcode); 6959 r3 = MASK_OP_RR2_D(ctx->opcode); 6960 switch (op2) { 6961 case OPC2_32_RR2_MUL_32: 6962 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6963 break; 6964 case OPC2_32_RR2_MUL_64: 6965 CHECK_REG_PAIR(r3); 6966 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6967 cpu_gpr_d[r2]); 6968 break; 6969 case OPC2_32_RR2_MULS_32: 6970 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6971 cpu_gpr_d[r2]); 6972 break; 6973 case OPC2_32_RR2_MUL_U_64: 6974 CHECK_REG_PAIR(r3); 6975 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6976 cpu_gpr_d[r2]); 6977 break; 6978 case OPC2_32_RR2_MULS_U_32: 6979 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6980 cpu_gpr_d[r2]); 6981 break; 6982 default: 6983 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6984 } 6985 } 6986 6987 /* RRPW format */ 6988 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) 6989 { 6990 uint32_t op2; 6991 int r1, r2, r3; 6992 int32_t pos, width; 6993 6994 op2 = MASK_OP_RRPW_OP2(ctx->opcode); 6995 r1 = MASK_OP_RRPW_S1(ctx->opcode); 6996 r2 = MASK_OP_RRPW_S2(ctx->opcode); 6997 r3 = MASK_OP_RRPW_D(ctx->opcode); 6998 pos = MASK_OP_RRPW_POS(ctx->opcode); 6999 width = MASK_OP_RRPW_WIDTH(ctx->opcode); 7000 7001 switch (op2) { 7002 case OPC2_32_RRPW_EXTR: 7003 if (pos + width <= 31) { 7004 /* optimize special cases */ 7005 if ((pos == 0) && (width == 8)) { 7006 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 7007 } else if ((pos == 0) && (width == 16)) { 7008 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 7009 } else { 7010 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width); 7011 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width); 7012 } 7013 } 7014 break; 7015 case OPC2_32_RRPW_EXTR_U: 7016 if (width == 0) { 7017 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 7018 } else { 7019 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); 7020 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width)); 7021 } 7022 break; 7023 case OPC2_32_RRPW_IMASK: 7024 CHECK_REG_PAIR(r3); 7025 if (pos + width <= 31) { 7026 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos); 7027 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); 7028 } 7029 break; 7030 case OPC2_32_RRPW_INSERT: 7031 if (pos + width <= 32) { 7032 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 7033 pos, width); 7034 } 7035 break; 7036 default: 7037 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7038 } 7039 } 7040 7041 /* RRR format */ 7042 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx) 7043 { 7044 uint32_t op2; 7045 int r1, r2, r3, r4; 7046 TCGv temp; 7047 7048 op2 = MASK_OP_RRR_OP2(ctx->opcode); 7049 r1 = MASK_OP_RRR_S1(ctx->opcode); 7050 r2 = MASK_OP_RRR_S2(ctx->opcode); 7051 r3 = MASK_OP_RRR_S3(ctx->opcode); 7052 r4 = MASK_OP_RRR_D(ctx->opcode); 7053 7054 switch (op2) { 7055 case OPC2_32_RRR_CADD: 7056 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 7057 cpu_gpr_d[r4], cpu_gpr_d[r3]); 7058 break; 7059 case OPC2_32_RRR_CADDN: 7060 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 7061 cpu_gpr_d[r3]); 7062 break; 7063 case OPC2_32_RRR_CSUB: 7064 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 7065 cpu_gpr_d[r3]); 7066 break; 7067 case OPC2_32_RRR_CSUBN: 7068 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 7069 cpu_gpr_d[r3]); 7070 break; 7071 case OPC2_32_RRR_SEL: 7072 temp = tcg_const_i32(0); 7073 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 7074 cpu_gpr_d[r1], cpu_gpr_d[r2]); 7075 tcg_temp_free(temp); 7076 break; 7077 case OPC2_32_RRR_SELN: 7078 temp = tcg_const_i32(0); 7079 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 7080 cpu_gpr_d[r1], cpu_gpr_d[r2]); 7081 tcg_temp_free(temp); 7082 break; 7083 default: 7084 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7085 } 7086 } 7087 7088 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) 7089 { 7090 uint32_t op2; 7091 7092 int r1, r2, r3, r4; 7093 7094 op2 = MASK_OP_RRR_OP2(ctx->opcode); 7095 r1 = MASK_OP_RRR_S1(ctx->opcode); 7096 r2 = MASK_OP_RRR_S2(ctx->opcode); 7097 r3 = MASK_OP_RRR_S3(ctx->opcode); 7098 r4 = MASK_OP_RRR_D(ctx->opcode); 7099 7100 switch (op2) { 7101 case OPC2_32_RRR_DVADJ: 7102 CHECK_REG_PAIR(r3); 7103 CHECK_REG_PAIR(r4); 7104 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7105 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7106 break; 7107 case OPC2_32_RRR_DVSTEP: 7108 CHECK_REG_PAIR(r3); 7109 CHECK_REG_PAIR(r4); 7110 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7111 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7112 break; 7113 case OPC2_32_RRR_DVSTEP_U: 7114 CHECK_REG_PAIR(r3); 7115 CHECK_REG_PAIR(r4); 7116 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7117 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7118 break; 7119 case OPC2_32_RRR_IXMAX: 7120 CHECK_REG_PAIR(r3); 7121 CHECK_REG_PAIR(r4); 7122 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7123 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7124 break; 7125 case OPC2_32_RRR_IXMAX_U: 7126 CHECK_REG_PAIR(r3); 7127 CHECK_REG_PAIR(r4); 7128 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7129 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7130 break; 7131 case OPC2_32_RRR_IXMIN: 7132 CHECK_REG_PAIR(r3); 7133 CHECK_REG_PAIR(r4); 7134 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7135 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7136 break; 7137 case OPC2_32_RRR_IXMIN_U: 7138 CHECK_REG_PAIR(r3); 7139 CHECK_REG_PAIR(r4); 7140 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7141 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7142 break; 7143 case OPC2_32_RRR_PACK: 7144 CHECK_REG_PAIR(r3); 7145 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], 7146 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 7147 break; 7148 case OPC2_32_RRR_ADD_F: 7149 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 7150 break; 7151 case OPC2_32_RRR_SUB_F: 7152 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 7153 break; 7154 case OPC2_32_RRR_MADD_F: 7155 gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7156 cpu_gpr_d[r2], cpu_gpr_d[r3]); 7157 break; 7158 case OPC2_32_RRR_MSUB_F: 7159 gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7160 cpu_gpr_d[r2], cpu_gpr_d[r3]); 7161 break; 7162 default: 7163 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7164 } 7165 } 7166 7167 /* RRR2 format */ 7168 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx) 7169 { 7170 uint32_t op2; 7171 uint32_t r1, r2, r3, r4; 7172 7173 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 7174 r1 = MASK_OP_RRR2_S1(ctx->opcode); 7175 r2 = MASK_OP_RRR2_S2(ctx->opcode); 7176 r3 = MASK_OP_RRR2_S3(ctx->opcode); 7177 r4 = MASK_OP_RRR2_D(ctx->opcode); 7178 switch (op2) { 7179 case OPC2_32_RRR2_MADD_32: 7180 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 7181 cpu_gpr_d[r2]); 7182 break; 7183 case OPC2_32_RRR2_MADD_64: 7184 CHECK_REG_PAIR(r4); 7185 CHECK_REG_PAIR(r3); 7186 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7187 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7188 break; 7189 case OPC2_32_RRR2_MADDS_32: 7190 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7191 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7192 break; 7193 case OPC2_32_RRR2_MADDS_64: 7194 CHECK_REG_PAIR(r4); 7195 CHECK_REG_PAIR(r3); 7196 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7197 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7198 break; 7199 case OPC2_32_RRR2_MADD_U_64: 7200 CHECK_REG_PAIR(r4); 7201 CHECK_REG_PAIR(r3); 7202 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7203 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7204 break; 7205 case OPC2_32_RRR2_MADDS_U_32: 7206 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7207 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7208 break; 7209 case OPC2_32_RRR2_MADDS_U_64: 7210 CHECK_REG_PAIR(r4); 7211 CHECK_REG_PAIR(r3); 7212 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7213 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7214 break; 7215 default: 7216 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7217 } 7218 } 7219 7220 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx) 7221 { 7222 uint32_t op2; 7223 uint32_t r1, r2, r3, r4; 7224 7225 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 7226 r1 = MASK_OP_RRR2_S1(ctx->opcode); 7227 r2 = MASK_OP_RRR2_S2(ctx->opcode); 7228 r3 = MASK_OP_RRR2_S3(ctx->opcode); 7229 r4 = MASK_OP_RRR2_D(ctx->opcode); 7230 7231 switch (op2) { 7232 case OPC2_32_RRR2_MSUB_32: 7233 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 7234 cpu_gpr_d[r2]); 7235 break; 7236 case OPC2_32_RRR2_MSUB_64: 7237 CHECK_REG_PAIR(r4); 7238 CHECK_REG_PAIR(r3); 7239 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7240 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7241 break; 7242 case OPC2_32_RRR2_MSUBS_32: 7243 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7244 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7245 break; 7246 case OPC2_32_RRR2_MSUBS_64: 7247 CHECK_REG_PAIR(r4); 7248 CHECK_REG_PAIR(r3); 7249 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7250 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7251 break; 7252 case OPC2_32_RRR2_MSUB_U_64: 7253 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7254 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7255 break; 7256 case OPC2_32_RRR2_MSUBS_U_32: 7257 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7258 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7259 break; 7260 case OPC2_32_RRR2_MSUBS_U_64: 7261 CHECK_REG_PAIR(r4); 7262 CHECK_REG_PAIR(r3); 7263 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7264 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7265 break; 7266 default: 7267 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7268 } 7269 } 7270 7271 /* RRR1 format */ 7272 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx) 7273 { 7274 uint32_t op2; 7275 uint32_t r1, r2, r3, r4, n; 7276 7277 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7278 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7279 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7280 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7281 r4 = MASK_OP_RRR1_D(ctx->opcode); 7282 n = MASK_OP_RRR1_N(ctx->opcode); 7283 7284 switch (op2) { 7285 case OPC2_32_RRR1_MADD_H_LL: 7286 CHECK_REG_PAIR(r4); 7287 CHECK_REG_PAIR(r3); 7288 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7289 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7290 break; 7291 case OPC2_32_RRR1_MADD_H_LU: 7292 CHECK_REG_PAIR(r4); 7293 CHECK_REG_PAIR(r3); 7294 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7295 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7296 break; 7297 case OPC2_32_RRR1_MADD_H_UL: 7298 CHECK_REG_PAIR(r4); 7299 CHECK_REG_PAIR(r3); 7300 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7301 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7302 break; 7303 case OPC2_32_RRR1_MADD_H_UU: 7304 CHECK_REG_PAIR(r4); 7305 CHECK_REG_PAIR(r3); 7306 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7307 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7308 break; 7309 case OPC2_32_RRR1_MADDS_H_LL: 7310 CHECK_REG_PAIR(r4); 7311 CHECK_REG_PAIR(r3); 7312 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7313 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7314 break; 7315 case OPC2_32_RRR1_MADDS_H_LU: 7316 CHECK_REG_PAIR(r4); 7317 CHECK_REG_PAIR(r3); 7318 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7319 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7320 break; 7321 case OPC2_32_RRR1_MADDS_H_UL: 7322 CHECK_REG_PAIR(r4); 7323 CHECK_REG_PAIR(r3); 7324 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7325 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7326 break; 7327 case OPC2_32_RRR1_MADDS_H_UU: 7328 CHECK_REG_PAIR(r4); 7329 CHECK_REG_PAIR(r3); 7330 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7331 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7332 break; 7333 case OPC2_32_RRR1_MADDM_H_LL: 7334 CHECK_REG_PAIR(r4); 7335 CHECK_REG_PAIR(r3); 7336 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7337 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7338 break; 7339 case OPC2_32_RRR1_MADDM_H_LU: 7340 CHECK_REG_PAIR(r4); 7341 CHECK_REG_PAIR(r3); 7342 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7343 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7344 break; 7345 case OPC2_32_RRR1_MADDM_H_UL: 7346 CHECK_REG_PAIR(r4); 7347 CHECK_REG_PAIR(r3); 7348 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7349 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7350 break; 7351 case OPC2_32_RRR1_MADDM_H_UU: 7352 CHECK_REG_PAIR(r4); 7353 CHECK_REG_PAIR(r3); 7354 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7355 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7356 break; 7357 case OPC2_32_RRR1_MADDMS_H_LL: 7358 CHECK_REG_PAIR(r4); 7359 CHECK_REG_PAIR(r3); 7360 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7361 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7362 break; 7363 case OPC2_32_RRR1_MADDMS_H_LU: 7364 CHECK_REG_PAIR(r4); 7365 CHECK_REG_PAIR(r3); 7366 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7367 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7368 break; 7369 case OPC2_32_RRR1_MADDMS_H_UL: 7370 CHECK_REG_PAIR(r4); 7371 CHECK_REG_PAIR(r3); 7372 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7373 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7374 break; 7375 case OPC2_32_RRR1_MADDMS_H_UU: 7376 CHECK_REG_PAIR(r4); 7377 CHECK_REG_PAIR(r3); 7378 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7379 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7380 break; 7381 case OPC2_32_RRR1_MADDR_H_LL: 7382 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7383 cpu_gpr_d[r2], n, MODE_LL); 7384 break; 7385 case OPC2_32_RRR1_MADDR_H_LU: 7386 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7387 cpu_gpr_d[r2], n, MODE_LU); 7388 break; 7389 case OPC2_32_RRR1_MADDR_H_UL: 7390 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7391 cpu_gpr_d[r2], n, MODE_UL); 7392 break; 7393 case OPC2_32_RRR1_MADDR_H_UU: 7394 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7395 cpu_gpr_d[r2], n, MODE_UU); 7396 break; 7397 case OPC2_32_RRR1_MADDRS_H_LL: 7398 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7399 cpu_gpr_d[r2], n, MODE_LL); 7400 break; 7401 case OPC2_32_RRR1_MADDRS_H_LU: 7402 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7403 cpu_gpr_d[r2], n, MODE_LU); 7404 break; 7405 case OPC2_32_RRR1_MADDRS_H_UL: 7406 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7407 cpu_gpr_d[r2], n, MODE_UL); 7408 break; 7409 case OPC2_32_RRR1_MADDRS_H_UU: 7410 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7411 cpu_gpr_d[r2], n, MODE_UU); 7412 break; 7413 default: 7414 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7415 } 7416 } 7417 7418 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) 7419 { 7420 uint32_t op2; 7421 uint32_t r1, r2, r3, r4, n; 7422 TCGv temp, temp2; 7423 7424 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7425 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7426 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7427 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7428 r4 = MASK_OP_RRR1_D(ctx->opcode); 7429 n = MASK_OP_RRR1_N(ctx->opcode); 7430 7431 temp = tcg_const_i32(n); 7432 temp2 = tcg_temp_new(); 7433 7434 switch (op2) { 7435 case OPC2_32_RRR1_MADD_Q_32: 7436 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7437 cpu_gpr_d[r2], n, 32, env); 7438 break; 7439 case OPC2_32_RRR1_MADD_Q_64: 7440 CHECK_REG_PAIR(r4); 7441 CHECK_REG_PAIR(r3); 7442 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7443 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7444 n, env); 7445 break; 7446 case OPC2_32_RRR1_MADD_Q_32_L: 7447 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7448 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7449 temp, n, 16, env); 7450 break; 7451 case OPC2_32_RRR1_MADD_Q_64_L: 7452 CHECK_REG_PAIR(r4); 7453 CHECK_REG_PAIR(r3); 7454 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7455 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7456 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7457 n, env); 7458 break; 7459 case OPC2_32_RRR1_MADD_Q_32_U: 7460 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7461 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7462 temp, n, 16, env); 7463 break; 7464 case OPC2_32_RRR1_MADD_Q_64_U: 7465 CHECK_REG_PAIR(r4); 7466 CHECK_REG_PAIR(r3); 7467 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7468 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7469 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7470 n, env); 7471 break; 7472 case OPC2_32_RRR1_MADD_Q_32_LL: 7473 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7474 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7475 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7476 break; 7477 case OPC2_32_RRR1_MADD_Q_64_LL: 7478 CHECK_REG_PAIR(r4); 7479 CHECK_REG_PAIR(r3); 7480 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7481 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7482 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7483 cpu_gpr_d[r3+1], temp, temp2, n); 7484 break; 7485 case OPC2_32_RRR1_MADD_Q_32_UU: 7486 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7487 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7488 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7489 break; 7490 case OPC2_32_RRR1_MADD_Q_64_UU: 7491 CHECK_REG_PAIR(r4); 7492 CHECK_REG_PAIR(r3); 7493 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7494 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7495 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7496 cpu_gpr_d[r3+1], temp, temp2, n); 7497 break; 7498 case OPC2_32_RRR1_MADDS_Q_32: 7499 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7500 cpu_gpr_d[r2], n, 32); 7501 break; 7502 case OPC2_32_RRR1_MADDS_Q_64: 7503 CHECK_REG_PAIR(r4); 7504 CHECK_REG_PAIR(r3); 7505 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7506 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7507 n); 7508 break; 7509 case OPC2_32_RRR1_MADDS_Q_32_L: 7510 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7511 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7512 temp, n, 16); 7513 break; 7514 case OPC2_32_RRR1_MADDS_Q_64_L: 7515 CHECK_REG_PAIR(r4); 7516 CHECK_REG_PAIR(r3); 7517 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7518 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7519 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7520 n); 7521 break; 7522 case OPC2_32_RRR1_MADDS_Q_32_U: 7523 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7524 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7525 temp, n, 16); 7526 break; 7527 case OPC2_32_RRR1_MADDS_Q_64_U: 7528 CHECK_REG_PAIR(r4); 7529 CHECK_REG_PAIR(r3); 7530 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7531 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7532 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7533 n); 7534 break; 7535 case OPC2_32_RRR1_MADDS_Q_32_LL: 7536 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7537 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7538 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7539 break; 7540 case OPC2_32_RRR1_MADDS_Q_64_LL: 7541 CHECK_REG_PAIR(r4); 7542 CHECK_REG_PAIR(r3); 7543 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7544 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7545 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7546 cpu_gpr_d[r3+1], temp, temp2, n); 7547 break; 7548 case OPC2_32_RRR1_MADDS_Q_32_UU: 7549 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7550 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7551 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7552 break; 7553 case OPC2_32_RRR1_MADDS_Q_64_UU: 7554 CHECK_REG_PAIR(r4); 7555 CHECK_REG_PAIR(r3); 7556 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7557 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7558 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7559 cpu_gpr_d[r3+1], temp, temp2, n); 7560 break; 7561 case OPC2_32_RRR1_MADDR_H_64_UL: 7562 CHECK_REG_PAIR(r3); 7563 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7564 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7565 break; 7566 case OPC2_32_RRR1_MADDRS_H_64_UL: 7567 CHECK_REG_PAIR(r3); 7568 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7569 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7570 break; 7571 case OPC2_32_RRR1_MADDR_Q_32_LL: 7572 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7573 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7574 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7575 break; 7576 case OPC2_32_RRR1_MADDR_Q_32_UU: 7577 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7578 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7579 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7580 break; 7581 case OPC2_32_RRR1_MADDRS_Q_32_LL: 7582 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7583 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7584 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7585 break; 7586 case OPC2_32_RRR1_MADDRS_Q_32_UU: 7587 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7588 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7589 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7590 break; 7591 default: 7592 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7593 } 7594 tcg_temp_free(temp); 7595 tcg_temp_free(temp2); 7596 } 7597 7598 static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx) 7599 { 7600 uint32_t op2; 7601 uint32_t r1, r2, r3, r4, n; 7602 7603 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7604 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7605 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7606 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7607 r4 = MASK_OP_RRR1_D(ctx->opcode); 7608 n = MASK_OP_RRR1_N(ctx->opcode); 7609 7610 switch (op2) { 7611 case OPC2_32_RRR1_MADDSU_H_32_LL: 7612 CHECK_REG_PAIR(r4); 7613 CHECK_REG_PAIR(r3); 7614 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7615 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7616 break; 7617 case OPC2_32_RRR1_MADDSU_H_32_LU: 7618 CHECK_REG_PAIR(r4); 7619 CHECK_REG_PAIR(r3); 7620 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7621 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7622 break; 7623 case OPC2_32_RRR1_MADDSU_H_32_UL: 7624 CHECK_REG_PAIR(r4); 7625 CHECK_REG_PAIR(r3); 7626 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7627 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7628 break; 7629 case OPC2_32_RRR1_MADDSU_H_32_UU: 7630 CHECK_REG_PAIR(r4); 7631 CHECK_REG_PAIR(r3); 7632 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7633 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7634 break; 7635 case OPC2_32_RRR1_MADDSUS_H_32_LL: 7636 CHECK_REG_PAIR(r4); 7637 CHECK_REG_PAIR(r3); 7638 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7639 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7640 n, MODE_LL); 7641 break; 7642 case OPC2_32_RRR1_MADDSUS_H_32_LU: 7643 CHECK_REG_PAIR(r4); 7644 CHECK_REG_PAIR(r3); 7645 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7646 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7647 n, MODE_LU); 7648 break; 7649 case OPC2_32_RRR1_MADDSUS_H_32_UL: 7650 CHECK_REG_PAIR(r4); 7651 CHECK_REG_PAIR(r3); 7652 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7653 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7654 n, MODE_UL); 7655 break; 7656 case OPC2_32_RRR1_MADDSUS_H_32_UU: 7657 CHECK_REG_PAIR(r4); 7658 CHECK_REG_PAIR(r3); 7659 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7660 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7661 n, MODE_UU); 7662 break; 7663 case OPC2_32_RRR1_MADDSUM_H_64_LL: 7664 CHECK_REG_PAIR(r4); 7665 CHECK_REG_PAIR(r3); 7666 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7667 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7668 n, MODE_LL); 7669 break; 7670 case OPC2_32_RRR1_MADDSUM_H_64_LU: 7671 CHECK_REG_PAIR(r4); 7672 CHECK_REG_PAIR(r3); 7673 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7674 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7675 n, MODE_LU); 7676 break; 7677 case OPC2_32_RRR1_MADDSUM_H_64_UL: 7678 CHECK_REG_PAIR(r4); 7679 CHECK_REG_PAIR(r3); 7680 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7681 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7682 n, MODE_UL); 7683 break; 7684 case OPC2_32_RRR1_MADDSUM_H_64_UU: 7685 CHECK_REG_PAIR(r4); 7686 CHECK_REG_PAIR(r3); 7687 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7688 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7689 n, MODE_UU); 7690 break; 7691 case OPC2_32_RRR1_MADDSUMS_H_64_LL: 7692 CHECK_REG_PAIR(r4); 7693 CHECK_REG_PAIR(r3); 7694 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7695 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7696 n, MODE_LL); 7697 break; 7698 case OPC2_32_RRR1_MADDSUMS_H_64_LU: 7699 CHECK_REG_PAIR(r4); 7700 CHECK_REG_PAIR(r3); 7701 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7702 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7703 n, MODE_LU); 7704 break; 7705 case OPC2_32_RRR1_MADDSUMS_H_64_UL: 7706 CHECK_REG_PAIR(r4); 7707 CHECK_REG_PAIR(r3); 7708 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7709 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7710 n, MODE_UL); 7711 break; 7712 case OPC2_32_RRR1_MADDSUMS_H_64_UU: 7713 CHECK_REG_PAIR(r4); 7714 CHECK_REG_PAIR(r3); 7715 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7716 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7717 n, MODE_UU); 7718 break; 7719 case OPC2_32_RRR1_MADDSUR_H_16_LL: 7720 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7721 cpu_gpr_d[r2], n, MODE_LL); 7722 break; 7723 case OPC2_32_RRR1_MADDSUR_H_16_LU: 7724 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7725 cpu_gpr_d[r2], n, MODE_LU); 7726 break; 7727 case OPC2_32_RRR1_MADDSUR_H_16_UL: 7728 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7729 cpu_gpr_d[r2], n, MODE_UL); 7730 break; 7731 case OPC2_32_RRR1_MADDSUR_H_16_UU: 7732 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7733 cpu_gpr_d[r2], n, MODE_UU); 7734 break; 7735 case OPC2_32_RRR1_MADDSURS_H_16_LL: 7736 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7737 cpu_gpr_d[r2], n, MODE_LL); 7738 break; 7739 case OPC2_32_RRR1_MADDSURS_H_16_LU: 7740 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7741 cpu_gpr_d[r2], n, MODE_LU); 7742 break; 7743 case OPC2_32_RRR1_MADDSURS_H_16_UL: 7744 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7745 cpu_gpr_d[r2], n, MODE_UL); 7746 break; 7747 case OPC2_32_RRR1_MADDSURS_H_16_UU: 7748 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7749 cpu_gpr_d[r2], n, MODE_UU); 7750 break; 7751 default: 7752 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7753 } 7754 } 7755 7756 static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx) 7757 { 7758 uint32_t op2; 7759 uint32_t r1, r2, r3, r4, n; 7760 7761 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7762 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7763 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7764 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7765 r4 = MASK_OP_RRR1_D(ctx->opcode); 7766 n = MASK_OP_RRR1_N(ctx->opcode); 7767 7768 switch (op2) { 7769 case OPC2_32_RRR1_MSUB_H_LL: 7770 CHECK_REG_PAIR(r4); 7771 CHECK_REG_PAIR(r3); 7772 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7773 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7774 break; 7775 case OPC2_32_RRR1_MSUB_H_LU: 7776 CHECK_REG_PAIR(r4); 7777 CHECK_REG_PAIR(r3); 7778 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7779 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7780 break; 7781 case OPC2_32_RRR1_MSUB_H_UL: 7782 CHECK_REG_PAIR(r4); 7783 CHECK_REG_PAIR(r3); 7784 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7785 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7786 break; 7787 case OPC2_32_RRR1_MSUB_H_UU: 7788 CHECK_REG_PAIR(r4); 7789 CHECK_REG_PAIR(r3); 7790 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7791 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7792 break; 7793 case OPC2_32_RRR1_MSUBS_H_LL: 7794 CHECK_REG_PAIR(r4); 7795 CHECK_REG_PAIR(r3); 7796 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7797 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7798 break; 7799 case OPC2_32_RRR1_MSUBS_H_LU: 7800 CHECK_REG_PAIR(r4); 7801 CHECK_REG_PAIR(r3); 7802 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7803 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7804 break; 7805 case OPC2_32_RRR1_MSUBS_H_UL: 7806 CHECK_REG_PAIR(r4); 7807 CHECK_REG_PAIR(r3); 7808 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7809 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7810 break; 7811 case OPC2_32_RRR1_MSUBS_H_UU: 7812 CHECK_REG_PAIR(r4); 7813 CHECK_REG_PAIR(r3); 7814 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7815 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7816 break; 7817 case OPC2_32_RRR1_MSUBM_H_LL: 7818 CHECK_REG_PAIR(r4); 7819 CHECK_REG_PAIR(r3); 7820 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7821 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7822 break; 7823 case OPC2_32_RRR1_MSUBM_H_LU: 7824 CHECK_REG_PAIR(r4); 7825 CHECK_REG_PAIR(r3); 7826 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7827 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7828 break; 7829 case OPC2_32_RRR1_MSUBM_H_UL: 7830 CHECK_REG_PAIR(r4); 7831 CHECK_REG_PAIR(r3); 7832 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7833 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7834 break; 7835 case OPC2_32_RRR1_MSUBM_H_UU: 7836 CHECK_REG_PAIR(r4); 7837 CHECK_REG_PAIR(r3); 7838 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7839 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7840 break; 7841 case OPC2_32_RRR1_MSUBMS_H_LL: 7842 CHECK_REG_PAIR(r4); 7843 CHECK_REG_PAIR(r3); 7844 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7845 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7846 break; 7847 case OPC2_32_RRR1_MSUBMS_H_LU: 7848 CHECK_REG_PAIR(r4); 7849 CHECK_REG_PAIR(r3); 7850 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7851 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7852 break; 7853 case OPC2_32_RRR1_MSUBMS_H_UL: 7854 CHECK_REG_PAIR(r4); 7855 CHECK_REG_PAIR(r3); 7856 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7857 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7858 break; 7859 case OPC2_32_RRR1_MSUBMS_H_UU: 7860 CHECK_REG_PAIR(r4); 7861 CHECK_REG_PAIR(r3); 7862 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7863 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7864 break; 7865 case OPC2_32_RRR1_MSUBR_H_LL: 7866 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7867 cpu_gpr_d[r2], n, MODE_LL); 7868 break; 7869 case OPC2_32_RRR1_MSUBR_H_LU: 7870 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7871 cpu_gpr_d[r2], n, MODE_LU); 7872 break; 7873 case OPC2_32_RRR1_MSUBR_H_UL: 7874 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7875 cpu_gpr_d[r2], n, MODE_UL); 7876 break; 7877 case OPC2_32_RRR1_MSUBR_H_UU: 7878 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7879 cpu_gpr_d[r2], n, MODE_UU); 7880 break; 7881 case OPC2_32_RRR1_MSUBRS_H_LL: 7882 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7883 cpu_gpr_d[r2], n, MODE_LL); 7884 break; 7885 case OPC2_32_RRR1_MSUBRS_H_LU: 7886 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7887 cpu_gpr_d[r2], n, MODE_LU); 7888 break; 7889 case OPC2_32_RRR1_MSUBRS_H_UL: 7890 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7891 cpu_gpr_d[r2], n, MODE_UL); 7892 break; 7893 case OPC2_32_RRR1_MSUBRS_H_UU: 7894 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7895 cpu_gpr_d[r2], n, MODE_UU); 7896 break; 7897 default: 7898 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7899 } 7900 } 7901 7902 static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx) 7903 { 7904 uint32_t op2; 7905 uint32_t r1, r2, r3, r4, n; 7906 TCGv temp, temp2; 7907 7908 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7909 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7910 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7911 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7912 r4 = MASK_OP_RRR1_D(ctx->opcode); 7913 n = MASK_OP_RRR1_N(ctx->opcode); 7914 7915 temp = tcg_const_i32(n); 7916 temp2 = tcg_temp_new(); 7917 7918 switch (op2) { 7919 case OPC2_32_RRR1_MSUB_Q_32: 7920 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7921 cpu_gpr_d[r2], n, 32, env); 7922 break; 7923 case OPC2_32_RRR1_MSUB_Q_64: 7924 CHECK_REG_PAIR(r4); 7925 CHECK_REG_PAIR(r3); 7926 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7927 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7928 n, env); 7929 break; 7930 case OPC2_32_RRR1_MSUB_Q_32_L: 7931 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7932 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7933 temp, n, 16, env); 7934 break; 7935 case OPC2_32_RRR1_MSUB_Q_64_L: 7936 CHECK_REG_PAIR(r4); 7937 CHECK_REG_PAIR(r3); 7938 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7939 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7940 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7941 n, env); 7942 break; 7943 case OPC2_32_RRR1_MSUB_Q_32_U: 7944 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7945 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7946 temp, n, 16, env); 7947 break; 7948 case OPC2_32_RRR1_MSUB_Q_64_U: 7949 CHECK_REG_PAIR(r4); 7950 CHECK_REG_PAIR(r3); 7951 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7952 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7953 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7954 n, env); 7955 break; 7956 case OPC2_32_RRR1_MSUB_Q_32_LL: 7957 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7958 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7959 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7960 break; 7961 case OPC2_32_RRR1_MSUB_Q_64_LL: 7962 CHECK_REG_PAIR(r4); 7963 CHECK_REG_PAIR(r3); 7964 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7965 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7966 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7967 cpu_gpr_d[r3+1], temp, temp2, n); 7968 break; 7969 case OPC2_32_RRR1_MSUB_Q_32_UU: 7970 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7971 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7972 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7973 break; 7974 case OPC2_32_RRR1_MSUB_Q_64_UU: 7975 CHECK_REG_PAIR(r4); 7976 CHECK_REG_PAIR(r3); 7977 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7978 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7979 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7980 cpu_gpr_d[r3+1], temp, temp2, n); 7981 break; 7982 case OPC2_32_RRR1_MSUBS_Q_32: 7983 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7984 cpu_gpr_d[r2], n, 32); 7985 break; 7986 case OPC2_32_RRR1_MSUBS_Q_64: 7987 CHECK_REG_PAIR(r4); 7988 CHECK_REG_PAIR(r3); 7989 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7990 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7991 n); 7992 break; 7993 case OPC2_32_RRR1_MSUBS_Q_32_L: 7994 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7995 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7996 temp, n, 16); 7997 break; 7998 case OPC2_32_RRR1_MSUBS_Q_64_L: 7999 CHECK_REG_PAIR(r4); 8000 CHECK_REG_PAIR(r3); 8001 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 8002 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8003 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 8004 n); 8005 break; 8006 case OPC2_32_RRR1_MSUBS_Q_32_U: 8007 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 8008 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8009 temp, n, 16); 8010 break; 8011 case OPC2_32_RRR1_MSUBS_Q_64_U: 8012 CHECK_REG_PAIR(r4); 8013 CHECK_REG_PAIR(r3); 8014 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 8015 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8016 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 8017 n); 8018 break; 8019 case OPC2_32_RRR1_MSUBS_Q_32_LL: 8020 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 8021 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 8022 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8023 break; 8024 case OPC2_32_RRR1_MSUBS_Q_64_LL: 8025 CHECK_REG_PAIR(r4); 8026 CHECK_REG_PAIR(r3); 8027 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 8028 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 8029 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8030 cpu_gpr_d[r3+1], temp, temp2, n); 8031 break; 8032 case OPC2_32_RRR1_MSUBS_Q_32_UU: 8033 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 8034 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 8035 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8036 break; 8037 case OPC2_32_RRR1_MSUBS_Q_64_UU: 8038 CHECK_REG_PAIR(r4); 8039 CHECK_REG_PAIR(r3); 8040 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 8041 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 8042 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8043 cpu_gpr_d[r3+1], temp, temp2, n); 8044 break; 8045 case OPC2_32_RRR1_MSUBR_H_64_UL: 8046 CHECK_REG_PAIR(r3); 8047 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 8048 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 8049 break; 8050 case OPC2_32_RRR1_MSUBRS_H_64_UL: 8051 CHECK_REG_PAIR(r3); 8052 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 8053 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 8054 break; 8055 case OPC2_32_RRR1_MSUBR_Q_32_LL: 8056 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 8057 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 8058 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8059 break; 8060 case OPC2_32_RRR1_MSUBR_Q_32_UU: 8061 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 8062 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 8063 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8064 break; 8065 case OPC2_32_RRR1_MSUBRS_Q_32_LL: 8066 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 8067 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 8068 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8069 break; 8070 case OPC2_32_RRR1_MSUBRS_Q_32_UU: 8071 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 8072 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 8073 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8074 break; 8075 default: 8076 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8077 } 8078 tcg_temp_free(temp); 8079 tcg_temp_free(temp2); 8080 } 8081 8082 static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx) 8083 { 8084 uint32_t op2; 8085 uint32_t r1, r2, r3, r4, n; 8086 8087 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 8088 r1 = MASK_OP_RRR1_S1(ctx->opcode); 8089 r2 = MASK_OP_RRR1_S2(ctx->opcode); 8090 r3 = MASK_OP_RRR1_S3(ctx->opcode); 8091 r4 = MASK_OP_RRR1_D(ctx->opcode); 8092 n = MASK_OP_RRR1_N(ctx->opcode); 8093 8094 switch (op2) { 8095 case OPC2_32_RRR1_MSUBAD_H_32_LL: 8096 CHECK_REG_PAIR(r4); 8097 CHECK_REG_PAIR(r3); 8098 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8099 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 8100 break; 8101 case OPC2_32_RRR1_MSUBAD_H_32_LU: 8102 CHECK_REG_PAIR(r4); 8103 CHECK_REG_PAIR(r3); 8104 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8105 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 8106 break; 8107 case OPC2_32_RRR1_MSUBAD_H_32_UL: 8108 CHECK_REG_PAIR(r4); 8109 CHECK_REG_PAIR(r3); 8110 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8111 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 8112 break; 8113 case OPC2_32_RRR1_MSUBAD_H_32_UU: 8114 CHECK_REG_PAIR(r4); 8115 CHECK_REG_PAIR(r3); 8116 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8117 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 8118 break; 8119 case OPC2_32_RRR1_MSUBADS_H_32_LL: 8120 CHECK_REG_PAIR(r4); 8121 CHECK_REG_PAIR(r3); 8122 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8123 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8124 n, MODE_LL); 8125 break; 8126 case OPC2_32_RRR1_MSUBADS_H_32_LU: 8127 CHECK_REG_PAIR(r4); 8128 CHECK_REG_PAIR(r3); 8129 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8130 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8131 n, MODE_LU); 8132 break; 8133 case OPC2_32_RRR1_MSUBADS_H_32_UL: 8134 CHECK_REG_PAIR(r4); 8135 CHECK_REG_PAIR(r3); 8136 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8137 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8138 n, MODE_UL); 8139 break; 8140 case OPC2_32_RRR1_MSUBADS_H_32_UU: 8141 CHECK_REG_PAIR(r4); 8142 CHECK_REG_PAIR(r3); 8143 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8144 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8145 n, MODE_UU); 8146 break; 8147 case OPC2_32_RRR1_MSUBADM_H_64_LL: 8148 CHECK_REG_PAIR(r4); 8149 CHECK_REG_PAIR(r3); 8150 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8151 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8152 n, MODE_LL); 8153 break; 8154 case OPC2_32_RRR1_MSUBADM_H_64_LU: 8155 CHECK_REG_PAIR(r4); 8156 CHECK_REG_PAIR(r3); 8157 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8158 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8159 n, MODE_LU); 8160 break; 8161 case OPC2_32_RRR1_MSUBADM_H_64_UL: 8162 CHECK_REG_PAIR(r4); 8163 CHECK_REG_PAIR(r3); 8164 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8165 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8166 n, MODE_UL); 8167 break; 8168 case OPC2_32_RRR1_MSUBADM_H_64_UU: 8169 CHECK_REG_PAIR(r4); 8170 CHECK_REG_PAIR(r3); 8171 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8172 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8173 n, MODE_UU); 8174 break; 8175 case OPC2_32_RRR1_MSUBADMS_H_64_LL: 8176 CHECK_REG_PAIR(r4); 8177 CHECK_REG_PAIR(r3); 8178 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8179 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8180 n, MODE_LL); 8181 break; 8182 case OPC2_32_RRR1_MSUBADMS_H_64_LU: 8183 CHECK_REG_PAIR(r4); 8184 CHECK_REG_PAIR(r3); 8185 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8186 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8187 n, MODE_LU); 8188 break; 8189 case OPC2_32_RRR1_MSUBADMS_H_64_UL: 8190 CHECK_REG_PAIR(r4); 8191 CHECK_REG_PAIR(r3); 8192 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8193 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8194 n, MODE_UL); 8195 break; 8196 case OPC2_32_RRR1_MSUBADMS_H_64_UU: 8197 CHECK_REG_PAIR(r4); 8198 CHECK_REG_PAIR(r3); 8199 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8200 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8201 n, MODE_UU); 8202 break; 8203 case OPC2_32_RRR1_MSUBADR_H_16_LL: 8204 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8205 cpu_gpr_d[r2], n, MODE_LL); 8206 break; 8207 case OPC2_32_RRR1_MSUBADR_H_16_LU: 8208 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8209 cpu_gpr_d[r2], n, MODE_LU); 8210 break; 8211 case OPC2_32_RRR1_MSUBADR_H_16_UL: 8212 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8213 cpu_gpr_d[r2], n, MODE_UL); 8214 break; 8215 case OPC2_32_RRR1_MSUBADR_H_16_UU: 8216 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8217 cpu_gpr_d[r2], n, MODE_UU); 8218 break; 8219 case OPC2_32_RRR1_MSUBADRS_H_16_LL: 8220 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8221 cpu_gpr_d[r2], n, MODE_LL); 8222 break; 8223 case OPC2_32_RRR1_MSUBADRS_H_16_LU: 8224 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8225 cpu_gpr_d[r2], n, MODE_LU); 8226 break; 8227 case OPC2_32_RRR1_MSUBADRS_H_16_UL: 8228 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8229 cpu_gpr_d[r2], n, MODE_UL); 8230 break; 8231 case OPC2_32_RRR1_MSUBADRS_H_16_UU: 8232 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8233 cpu_gpr_d[r2], n, MODE_UU); 8234 break; 8235 default: 8236 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8237 } 8238 } 8239 8240 /* RRRR format */ 8241 static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx) 8242 { 8243 uint32_t op2; 8244 int r1, r2, r3, r4; 8245 TCGv tmp_width, tmp_pos; 8246 8247 r1 = MASK_OP_RRRR_S1(ctx->opcode); 8248 r2 = MASK_OP_RRRR_S2(ctx->opcode); 8249 r3 = MASK_OP_RRRR_S3(ctx->opcode); 8250 r4 = MASK_OP_RRRR_D(ctx->opcode); 8251 op2 = MASK_OP_RRRR_OP2(ctx->opcode); 8252 8253 tmp_pos = tcg_temp_new(); 8254 tmp_width = tcg_temp_new(); 8255 8256 switch (op2) { 8257 case OPC2_32_RRRR_DEXTR: 8258 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 8259 if (r1 == r2) { 8260 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 8261 } else { 8262 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); 8263 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 8264 tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos); 8265 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos); 8266 } 8267 break; 8268 case OPC2_32_RRRR_EXTR: 8269 case OPC2_32_RRRR_EXTR_U: 8270 CHECK_REG_PAIR(r3); 8271 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 8272 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 8273 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); 8274 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 8275 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 8276 tcg_gen_subfi_tl(tmp_width, 32, tmp_width); 8277 if (op2 == OPC2_32_RRRR_EXTR) { 8278 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 8279 } else { 8280 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 8281 } 8282 break; 8283 case OPC2_32_RRRR_INSERT: 8284 CHECK_REG_PAIR(r3); 8285 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 8286 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 8287 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, 8288 tmp_pos); 8289 break; 8290 default: 8291 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8292 } 8293 tcg_temp_free(tmp_pos); 8294 tcg_temp_free(tmp_width); 8295 } 8296 8297 /* RRRW format */ 8298 static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) 8299 { 8300 uint32_t op2; 8301 int r1, r2, r3, r4; 8302 int32_t width; 8303 8304 TCGv temp, temp2; 8305 8306 op2 = MASK_OP_RRRW_OP2(ctx->opcode); 8307 r1 = MASK_OP_RRRW_S1(ctx->opcode); 8308 r2 = MASK_OP_RRRW_S2(ctx->opcode); 8309 r3 = MASK_OP_RRRW_S3(ctx->opcode); 8310 r4 = MASK_OP_RRRW_D(ctx->opcode); 8311 width = MASK_OP_RRRW_WIDTH(ctx->opcode); 8312 8313 temp = tcg_temp_new(); 8314 8315 switch (op2) { 8316 case OPC2_32_RRRW_EXTR: 8317 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 8318 tcg_gen_addi_tl(temp, temp, width); 8319 tcg_gen_subfi_tl(temp, 32, temp); 8320 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 8321 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); 8322 break; 8323 case OPC2_32_RRRW_EXTR_U: 8324 if (width == 0) { 8325 tcg_gen_movi_tl(cpu_gpr_d[r4], 0); 8326 } else { 8327 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 8328 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 8329 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); 8330 } 8331 break; 8332 case OPC2_32_RRRW_IMASK: 8333 temp2 = tcg_temp_new(); 8334 8335 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 8336 tcg_gen_movi_tl(temp2, (1 << width) - 1); 8337 tcg_gen_shl_tl(temp2, temp2, temp); 8338 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); 8339 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); 8340 8341 tcg_temp_free(temp2); 8342 break; 8343 case OPC2_32_RRRW_INSERT: 8344 temp2 = tcg_temp_new(); 8345 8346 tcg_gen_movi_tl(temp, width); 8347 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); 8348 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); 8349 8350 tcg_temp_free(temp2); 8351 break; 8352 default: 8353 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8354 } 8355 tcg_temp_free(temp); 8356 } 8357 8358 /* SYS Format*/ 8359 static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) 8360 { 8361 uint32_t op2; 8362 uint32_t r1; 8363 TCGLabel *l1; 8364 TCGv tmp; 8365 8366 op2 = MASK_OP_SYS_OP2(ctx->opcode); 8367 r1 = MASK_OP_SYS_S1D(ctx->opcode); 8368 8369 switch (op2) { 8370 case OPC2_32_SYS_DEBUG: 8371 /* raise EXCP_DEBUG */ 8372 break; 8373 case OPC2_32_SYS_DISABLE: 8374 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); 8375 break; 8376 case OPC2_32_SYS_DSYNC: 8377 break; 8378 case OPC2_32_SYS_ENABLE: 8379 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3); 8380 break; 8381 case OPC2_32_SYS_ISYNC: 8382 break; 8383 case OPC2_32_SYS_NOP: 8384 break; 8385 case OPC2_32_SYS_RET: 8386 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 8387 break; 8388 case OPC2_32_SYS_FRET: 8389 gen_fret(ctx); 8390 break; 8391 case OPC2_32_SYS_RFE: 8392 gen_helper_rfe(cpu_env); 8393 tcg_gen_exit_tb(NULL, 0); 8394 ctx->bstate = BS_BRANCH; 8395 break; 8396 case OPC2_32_SYS_RFM: 8397 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 8398 tmp = tcg_temp_new(); 8399 l1 = gen_new_label(); 8400 8401 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR)); 8402 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); 8403 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); 8404 gen_helper_rfm(cpu_env); 8405 gen_set_label(l1); 8406 tcg_gen_exit_tb(NULL, 0); 8407 ctx->bstate = BS_BRANCH; 8408 tcg_temp_free(tmp); 8409 } else { 8410 /* generate privilege trap */ 8411 } 8412 break; 8413 case OPC2_32_SYS_RSLCX: 8414 gen_helper_rslcx(cpu_env); 8415 break; 8416 case OPC2_32_SYS_SVLCX: 8417 gen_helper_svlcx(cpu_env); 8418 break; 8419 case OPC2_32_SYS_RESTORE: 8420 if (tricore_feature(env, TRICORE_FEATURE_16)) { 8421 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM || 8422 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) { 8423 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); 8424 } /* else raise privilege trap */ 8425 } else { 8426 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8427 } 8428 break; 8429 case OPC2_32_SYS_TRAPSV: 8430 l1 = gen_new_label(); 8431 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); 8432 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); 8433 gen_set_label(l1); 8434 break; 8435 case OPC2_32_SYS_TRAPV: 8436 l1 = gen_new_label(); 8437 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); 8438 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); 8439 gen_set_label(l1); 8440 break; 8441 default: 8442 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8443 } 8444 } 8445 8446 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) 8447 { 8448 int op1; 8449 int32_t r1, r2, r3; 8450 int32_t address, const16; 8451 int8_t b, const4; 8452 int32_t bpos; 8453 TCGv temp, temp2, temp3; 8454 8455 op1 = MASK_OP_MAJOR(ctx->opcode); 8456 8457 /* handle JNZ.T opcode only being 7 bit long */ 8458 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { 8459 op1 = OPCM_32_BRN_JTT; 8460 } 8461 8462 switch (op1) { 8463 /* ABS-format */ 8464 case OPCM_32_ABS_LDW: 8465 decode_abs_ldw(env, ctx); 8466 break; 8467 case OPCM_32_ABS_LDB: 8468 decode_abs_ldb(env, ctx); 8469 break; 8470 case OPCM_32_ABS_LDMST_SWAP: 8471 decode_abs_ldst_swap(env, ctx); 8472 break; 8473 case OPCM_32_ABS_LDST_CONTEXT: 8474 decode_abs_ldst_context(env, ctx); 8475 break; 8476 case OPCM_32_ABS_STORE: 8477 decode_abs_store(env, ctx); 8478 break; 8479 case OPCM_32_ABS_STOREB_H: 8480 decode_abs_storeb_h(env, ctx); 8481 break; 8482 case OPC1_32_ABS_STOREQ: 8483 address = MASK_OP_ABS_OFF18(ctx->opcode); 8484 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8485 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 8486 temp2 = tcg_temp_new(); 8487 8488 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); 8489 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); 8490 8491 tcg_temp_free(temp2); 8492 tcg_temp_free(temp); 8493 break; 8494 case OPC1_32_ABS_LD_Q: 8495 address = MASK_OP_ABS_OFF18(ctx->opcode); 8496 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8497 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 8498 8499 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 8500 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 8501 8502 tcg_temp_free(temp); 8503 break; 8504 case OPC1_32_ABS_LEA: 8505 address = MASK_OP_ABS_OFF18(ctx->opcode); 8506 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8507 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); 8508 break; 8509 /* ABSB-format */ 8510 case OPC1_32_ABSB_ST_T: 8511 address = MASK_OP_ABS_OFF18(ctx->opcode); 8512 b = MASK_OP_ABSB_B(ctx->opcode); 8513 bpos = MASK_OP_ABSB_BPOS(ctx->opcode); 8514 8515 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 8516 temp2 = tcg_temp_new(); 8517 8518 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); 8519 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); 8520 tcg_gen_ori_tl(temp2, temp2, (b << bpos)); 8521 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); 8522 8523 tcg_temp_free(temp); 8524 tcg_temp_free(temp2); 8525 break; 8526 /* B-format */ 8527 case OPC1_32_B_CALL: 8528 case OPC1_32_B_CALLA: 8529 case OPC1_32_B_FCALL: 8530 case OPC1_32_B_FCALLA: 8531 case OPC1_32_B_J: 8532 case OPC1_32_B_JA: 8533 case OPC1_32_B_JL: 8534 case OPC1_32_B_JLA: 8535 address = MASK_OP_B_DISP24_SEXT(ctx->opcode); 8536 gen_compute_branch(ctx, op1, 0, 0, 0, address); 8537 break; 8538 /* Bit-format */ 8539 case OPCM_32_BIT_ANDACC: 8540 decode_bit_andacc(env, ctx); 8541 break; 8542 case OPCM_32_BIT_LOGICAL_T1: 8543 decode_bit_logical_t(env, ctx); 8544 break; 8545 case OPCM_32_BIT_INSERT: 8546 decode_bit_insert(env, ctx); 8547 break; 8548 case OPCM_32_BIT_LOGICAL_T2: 8549 decode_bit_logical_t2(env, ctx); 8550 break; 8551 case OPCM_32_BIT_ORAND: 8552 decode_bit_orand(env, ctx); 8553 break; 8554 case OPCM_32_BIT_SH_LOGIC1: 8555 decode_bit_sh_logic1(env, ctx); 8556 break; 8557 case OPCM_32_BIT_SH_LOGIC2: 8558 decode_bit_sh_logic2(env, ctx); 8559 break; 8560 /* BO Format */ 8561 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: 8562 decode_bo_addrmode_post_pre_base(env, ctx); 8563 break; 8564 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: 8565 decode_bo_addrmode_bitreverse_circular(env, ctx); 8566 break; 8567 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: 8568 decode_bo_addrmode_ld_post_pre_base(env, ctx); 8569 break; 8570 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: 8571 decode_bo_addrmode_ld_bitreverse_circular(env, ctx); 8572 break; 8573 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: 8574 decode_bo_addrmode_stctx_post_pre_base(env, ctx); 8575 break; 8576 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: 8577 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx); 8578 break; 8579 /* BOL-format */ 8580 case OPC1_32_BOL_LD_A_LONGOFF: 8581 case OPC1_32_BOL_LD_W_LONGOFF: 8582 case OPC1_32_BOL_LEA_LONGOFF: 8583 case OPC1_32_BOL_ST_W_LONGOFF: 8584 case OPC1_32_BOL_ST_A_LONGOFF: 8585 case OPC1_32_BOL_LD_B_LONGOFF: 8586 case OPC1_32_BOL_LD_BU_LONGOFF: 8587 case OPC1_32_BOL_LD_H_LONGOFF: 8588 case OPC1_32_BOL_LD_HU_LONGOFF: 8589 case OPC1_32_BOL_ST_B_LONGOFF: 8590 case OPC1_32_BOL_ST_H_LONGOFF: 8591 decode_bol_opc(env, ctx, op1); 8592 break; 8593 /* BRC Format */ 8594 case OPCM_32_BRC_EQ_NEQ: 8595 case OPCM_32_BRC_GE: 8596 case OPCM_32_BRC_JLT: 8597 case OPCM_32_BRC_JNE: 8598 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); 8599 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); 8600 r1 = MASK_OP_BRC_S1(ctx->opcode); 8601 gen_compute_branch(ctx, op1, r1, 0, const4, address); 8602 break; 8603 /* BRN Format */ 8604 case OPCM_32_BRN_JTT: 8605 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); 8606 r1 = MASK_OP_BRN_S1(ctx->opcode); 8607 gen_compute_branch(ctx, op1, r1, 0, 0, address); 8608 break; 8609 /* BRR Format */ 8610 case OPCM_32_BRR_EQ_NEQ: 8611 case OPCM_32_BRR_ADDR_EQ_NEQ: 8612 case OPCM_32_BRR_GE: 8613 case OPCM_32_BRR_JLT: 8614 case OPCM_32_BRR_JNE: 8615 case OPCM_32_BRR_JNZ: 8616 case OPCM_32_BRR_LOOP: 8617 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); 8618 r2 = MASK_OP_BRR_S2(ctx->opcode); 8619 r1 = MASK_OP_BRR_S1(ctx->opcode); 8620 gen_compute_branch(ctx, op1, r1, r2, 0, address); 8621 break; 8622 /* RC Format */ 8623 case OPCM_32_RC_LOGICAL_SHIFT: 8624 decode_rc_logical_shift(env, ctx); 8625 break; 8626 case OPCM_32_RC_ACCUMULATOR: 8627 decode_rc_accumulator(env, ctx); 8628 break; 8629 case OPCM_32_RC_SERVICEROUTINE: 8630 decode_rc_serviceroutine(env, ctx); 8631 break; 8632 case OPCM_32_RC_MUL: 8633 decode_rc_mul(env, ctx); 8634 break; 8635 /* RCPW Format */ 8636 case OPCM_32_RCPW_MASK_INSERT: 8637 decode_rcpw_insert(env, ctx); 8638 break; 8639 /* RCRR Format */ 8640 case OPC1_32_RCRR_INSERT: 8641 r1 = MASK_OP_RCRR_S1(ctx->opcode); 8642 r2 = MASK_OP_RCRR_S3(ctx->opcode); 8643 r3 = MASK_OP_RCRR_D(ctx->opcode); 8644 const16 = MASK_OP_RCRR_CONST4(ctx->opcode); 8645 temp = tcg_const_i32(const16); 8646 temp2 = tcg_temp_new(); /* width*/ 8647 temp3 = tcg_temp_new(); /* pos */ 8648 8649 CHECK_REG_PAIR(r3); 8650 8651 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f); 8652 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 8653 8654 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); 8655 8656 tcg_temp_free(temp); 8657 tcg_temp_free(temp2); 8658 tcg_temp_free(temp3); 8659 break; 8660 /* RCRW Format */ 8661 case OPCM_32_RCRW_MASK_INSERT: 8662 decode_rcrw_insert(env, ctx); 8663 break; 8664 /* RCR Format */ 8665 case OPCM_32_RCR_COND_SELECT: 8666 decode_rcr_cond_select(env, ctx); 8667 break; 8668 case OPCM_32_RCR_MADD: 8669 decode_rcr_madd(env, ctx); 8670 break; 8671 case OPCM_32_RCR_MSUB: 8672 decode_rcr_msub(env, ctx); 8673 break; 8674 /* RLC Format */ 8675 case OPC1_32_RLC_ADDI: 8676 case OPC1_32_RLC_ADDIH: 8677 case OPC1_32_RLC_ADDIH_A: 8678 case OPC1_32_RLC_MFCR: 8679 case OPC1_32_RLC_MOV: 8680 case OPC1_32_RLC_MOV_64: 8681 case OPC1_32_RLC_MOV_U: 8682 case OPC1_32_RLC_MOV_H: 8683 case OPC1_32_RLC_MOVH_A: 8684 case OPC1_32_RLC_MTCR: 8685 decode_rlc_opc(env, ctx, op1); 8686 break; 8687 /* RR Format */ 8688 case OPCM_32_RR_ACCUMULATOR: 8689 decode_rr_accumulator(env, ctx); 8690 break; 8691 case OPCM_32_RR_LOGICAL_SHIFT: 8692 decode_rr_logical_shift(env, ctx); 8693 break; 8694 case OPCM_32_RR_ADDRESS: 8695 decode_rr_address(env, ctx); 8696 break; 8697 case OPCM_32_RR_IDIRECT: 8698 decode_rr_idirect(env, ctx); 8699 break; 8700 case OPCM_32_RR_DIVIDE: 8701 decode_rr_divide(env, ctx); 8702 break; 8703 /* RR1 Format */ 8704 case OPCM_32_RR1_MUL: 8705 decode_rr1_mul(env, ctx); 8706 break; 8707 case OPCM_32_RR1_MULQ: 8708 decode_rr1_mulq(env, ctx); 8709 break; 8710 /* RR2 format */ 8711 case OPCM_32_RR2_MUL: 8712 decode_rr2_mul(env, ctx); 8713 break; 8714 /* RRPW format */ 8715 case OPCM_32_RRPW_EXTRACT_INSERT: 8716 decode_rrpw_extract_insert(env, ctx); 8717 break; 8718 case OPC1_32_RRPW_DEXTR: 8719 r1 = MASK_OP_RRPW_S1(ctx->opcode); 8720 r2 = MASK_OP_RRPW_S2(ctx->opcode); 8721 r3 = MASK_OP_RRPW_D(ctx->opcode); 8722 const16 = MASK_OP_RRPW_POS(ctx->opcode); 8723 if (r1 == r2) { 8724 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16); 8725 } else { 8726 temp = tcg_temp_new(); 8727 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16); 8728 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16); 8729 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 8730 tcg_temp_free(temp); 8731 } 8732 break; 8733 /* RRR Format */ 8734 case OPCM_32_RRR_COND_SELECT: 8735 decode_rrr_cond_select(env, ctx); 8736 break; 8737 case OPCM_32_RRR_DIVIDE: 8738 decode_rrr_divide(env, ctx); 8739 break; 8740 /* RRR2 Format */ 8741 case OPCM_32_RRR2_MADD: 8742 decode_rrr2_madd(env, ctx); 8743 break; 8744 case OPCM_32_RRR2_MSUB: 8745 decode_rrr2_msub(env, ctx); 8746 break; 8747 /* RRR1 format */ 8748 case OPCM_32_RRR1_MADD: 8749 decode_rrr1_madd(env, ctx); 8750 break; 8751 case OPCM_32_RRR1_MADDQ_H: 8752 decode_rrr1_maddq_h(env, ctx); 8753 break; 8754 case OPCM_32_RRR1_MADDSU_H: 8755 decode_rrr1_maddsu_h(env, ctx); 8756 break; 8757 case OPCM_32_RRR1_MSUB_H: 8758 decode_rrr1_msub(env, ctx); 8759 break; 8760 case OPCM_32_RRR1_MSUB_Q: 8761 decode_rrr1_msubq_h(env, ctx); 8762 break; 8763 case OPCM_32_RRR1_MSUBAD_H: 8764 decode_rrr1_msubad_h(env, ctx); 8765 break; 8766 /* RRRR format */ 8767 case OPCM_32_RRRR_EXTRACT_INSERT: 8768 decode_rrrr_extract_insert(env, ctx); 8769 break; 8770 /* RRRW format */ 8771 case OPCM_32_RRRW_EXTRACT_INSERT: 8772 decode_rrrw_extract_insert(env, ctx); 8773 break; 8774 /* SYS format */ 8775 case OPCM_32_SYS_INTERRUPTS: 8776 decode_sys_interrupts(env, ctx); 8777 break; 8778 case OPC1_32_SYS_RSTV: 8779 tcg_gen_movi_tl(cpu_PSW_V, 0); 8780 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); 8781 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 8782 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); 8783 break; 8784 default: 8785 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8786 } 8787 } 8788 8789 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch) 8790 { 8791 /* 16-Bit Instruction */ 8792 if ((ctx->opcode & 0x1) == 0) { 8793 ctx->next_pc = ctx->pc + 2; 8794 decode_16Bit_opc(env, ctx); 8795 /* 32-Bit Instruction */ 8796 } else { 8797 ctx->next_pc = ctx->pc + 4; 8798 decode_32Bit_opc(env, ctx); 8799 } 8800 } 8801 8802 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8803 { 8804 CPUTriCoreState *env = cs->env_ptr; 8805 DisasContext ctx; 8806 target_ulong pc_start; 8807 int num_insns = 0; 8808 8809 pc_start = tb->pc; 8810 ctx.pc = pc_start; 8811 ctx.saved_pc = -1; 8812 ctx.tb = tb; 8813 ctx.singlestep_enabled = cs->singlestep_enabled; 8814 ctx.bstate = BS_NONE; 8815 ctx.mem_idx = cpu_mmu_index(env, false); 8816 ctx.hflags = (uint32_t)tb->flags; 8817 8818 tcg_clear_temp_count(); 8819 gen_tb_start(tb); 8820 while (ctx.bstate == BS_NONE) { 8821 tcg_gen_insn_start(ctx.pc); 8822 num_insns++; 8823 8824 ctx.opcode = cpu_ldl_code(env, ctx.pc); 8825 decode_opc(env, &ctx, 0); 8826 8827 if (num_insns >= max_insns || tcg_op_buf_full()) { 8828 gen_save_pc(ctx.next_pc); 8829 tcg_gen_exit_tb(NULL, 0); 8830 break; 8831 } 8832 ctx.pc = ctx.next_pc; 8833 } 8834 8835 gen_tb_end(tb, num_insns); 8836 tb->size = ctx.pc - pc_start; 8837 tb->icount = num_insns; 8838 8839 if (tcg_check_temp_count()) { 8840 printf("LEAK at %08x\n", env->PC); 8841 } 8842 8843 #ifdef DEBUG_DISAS 8844 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 8845 && qemu_log_in_addr_range(pc_start)) { 8846 qemu_log_lock(); 8847 qemu_log("IN: %s\n", lookup_symbol(pc_start)); 8848 log_target_disas(cs, pc_start, ctx.pc - pc_start); 8849 qemu_log("\n"); 8850 qemu_log_unlock(); 8851 } 8852 #endif 8853 } 8854 8855 void 8856 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, 8857 target_ulong *data) 8858 { 8859 env->PC = data[0]; 8860 } 8861 /* 8862 * 8863 * Initialization 8864 * 8865 */ 8866 8867 void cpu_state_reset(CPUTriCoreState *env) 8868 { 8869 /* Reset Regs to Default Value */ 8870 env->PSW = 0xb80; 8871 fpu_set_state(env); 8872 } 8873 8874 static void tricore_tcg_init_csfr(void) 8875 { 8876 cpu_PCXI = tcg_global_mem_new(cpu_env, 8877 offsetof(CPUTriCoreState, PCXI), "PCXI"); 8878 cpu_PSW = tcg_global_mem_new(cpu_env, 8879 offsetof(CPUTriCoreState, PSW), "PSW"); 8880 cpu_PC = tcg_global_mem_new(cpu_env, 8881 offsetof(CPUTriCoreState, PC), "PC"); 8882 cpu_ICR = tcg_global_mem_new(cpu_env, 8883 offsetof(CPUTriCoreState, ICR), "ICR"); 8884 } 8885 8886 void tricore_tcg_init(void) 8887 { 8888 int i; 8889 8890 /* reg init */ 8891 for (i = 0 ; i < 16 ; i++) { 8892 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, 8893 offsetof(CPUTriCoreState, gpr_a[i]), 8894 regnames_a[i]); 8895 } 8896 for (i = 0 ; i < 16 ; i++) { 8897 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env, 8898 offsetof(CPUTriCoreState, gpr_d[i]), 8899 regnames_d[i]); 8900 } 8901 tricore_tcg_init_csfr(); 8902 /* init PSW flag cache */ 8903 cpu_PSW_C = tcg_global_mem_new(cpu_env, 8904 offsetof(CPUTriCoreState, PSW_USB_C), 8905 "PSW_C"); 8906 cpu_PSW_V = tcg_global_mem_new(cpu_env, 8907 offsetof(CPUTriCoreState, PSW_USB_V), 8908 "PSW_V"); 8909 cpu_PSW_SV = tcg_global_mem_new(cpu_env, 8910 offsetof(CPUTriCoreState, PSW_USB_SV), 8911 "PSW_SV"); 8912 cpu_PSW_AV = tcg_global_mem_new(cpu_env, 8913 offsetof(CPUTriCoreState, PSW_USB_AV), 8914 "PSW_AV"); 8915 cpu_PSW_SAV = tcg_global_mem_new(cpu_env, 8916 offsetof(CPUTriCoreState, PSW_USB_SAV), 8917 "PSW_SAV"); 8918 } 8919