1 /* 2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2.1 of the License, or (at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public 15 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 20 #include "cpu.h" 21 #include "exec/exec-all.h" 22 #include "fpu/softfloat.h" 23 #include "qemu/qemu-print.h" 24 25 enum { 26 TLBRET_DIRTY = -4, 27 TLBRET_INVALID = -3, 28 TLBRET_NOMATCH = -2, 29 TLBRET_BADADDR = -1, 30 TLBRET_MATCH = 0 31 }; 32 33 #if defined(CONFIG_SOFTMMU) 34 static int get_physical_address(CPUTriCoreState *env, hwaddr *physical, 35 int *prot, target_ulong address, 36 int rw, int access_type) 37 { 38 int ret = TLBRET_MATCH; 39 40 *physical = address & 0xFFFFFFFF; 41 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 42 43 return ret; 44 } 45 #endif 46 47 /* TODO: Add exeption support*/ 48 static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, 49 int rw, int tlb_error) 50 { 51 } 52 53 int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, 54 int rw, int mmu_idx) 55 { 56 TriCoreCPU *cpu = TRICORE_CPU(cs); 57 CPUTriCoreState *env = &cpu->env; 58 hwaddr physical; 59 int prot; 60 int access_type; 61 int ret = 0; 62 63 rw &= 1; 64 access_type = ACCESS_INT; 65 ret = get_physical_address(env, &physical, &prot, 66 address, rw, access_type); 67 qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx 68 " prot %d\n", __func__, address, ret, physical, prot); 69 70 if (ret == TLBRET_MATCH) { 71 tlb_set_page(cs, address & TARGET_PAGE_MASK, 72 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, 73 mmu_idx, TARGET_PAGE_SIZE); 74 ret = 0; 75 } else if (ret < 0) { 76 raise_mmu_exception(env, address, rw, ret); 77 ret = 1; 78 } 79 80 return ret; 81 } 82 83 static void tricore_cpu_list_entry(gpointer data, gpointer user_data) 84 { 85 ObjectClass *oc = data; 86 const char *typename; 87 char *name; 88 89 typename = object_class_get_name(oc); 90 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU)); 91 qemu_printf(" %s\n", name); 92 g_free(name); 93 } 94 95 void tricore_cpu_list(void) 96 { 97 GSList *list; 98 99 list = object_class_get_list_sorted(TYPE_TRICORE_CPU, false); 100 qemu_printf("Available CPUs:\n"); 101 g_slist_foreach(list, tricore_cpu_list_entry, NULL); 102 g_slist_free(list); 103 } 104 105 void fpu_set_state(CPUTriCoreState *env) 106 { 107 set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status); 108 set_flush_inputs_to_zero(1, &env->fp_status); 109 set_flush_to_zero(1, &env->fp_status); 110 set_default_nan_mode(1, &env->fp_status); 111 } 112 113 uint32_t psw_read(CPUTriCoreState *env) 114 { 115 /* clear all USB bits */ 116 env->PSW &= 0x6ffffff; 117 /* now set them from the cache */ 118 env->PSW |= ((env->PSW_USB_C != 0) << 31); 119 env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1); 120 env->PSW |= ((env->PSW_USB_SV & (1 << 31)) >> 2); 121 env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3); 122 env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4); 123 124 return env->PSW; 125 } 126 127 void psw_write(CPUTriCoreState *env, uint32_t val) 128 { 129 env->PSW_USB_C = (val & MASK_USB_C); 130 env->PSW_USB_V = (val & MASK_USB_V) << 1; 131 env->PSW_USB_SV = (val & MASK_USB_SV) << 2; 132 env->PSW_USB_AV = (val & MASK_USB_AV) << 3; 133 env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4; 134 env->PSW = val; 135 136 fpu_set_state(env); 137 } 138