1 /* 2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2.1 of the License, or (at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public 15 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "hw/registerfields.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "fpu/softfloat-helpers.h" 24 #include "qemu/qemu-print.h" 25 26 enum { 27 TLBRET_DIRTY = -4, 28 TLBRET_INVALID = -3, 29 TLBRET_NOMATCH = -2, 30 TLBRET_BADADDR = -1, 31 TLBRET_MATCH = 0 32 }; 33 34 #if defined(CONFIG_SOFTMMU) 35 static int get_physical_address(CPUTriCoreState *env, hwaddr *physical, 36 int *prot, target_ulong address, 37 MMUAccessType access_type, int mmu_idx) 38 { 39 int ret = TLBRET_MATCH; 40 41 *physical = address & 0xFFFFFFFF; 42 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 43 44 return ret; 45 } 46 47 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 48 { 49 TriCoreCPU *cpu = TRICORE_CPU(cs); 50 hwaddr phys_addr; 51 int prot; 52 int mmu_idx = cpu_mmu_index(&cpu->env, false); 53 54 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 55 MMU_DATA_LOAD, mmu_idx)) { 56 return -1; 57 } 58 return phys_addr; 59 } 60 #endif 61 62 /* TODO: Add exeption support*/ 63 static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, 64 int rw, int tlb_error) 65 { 66 } 67 68 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 69 MMUAccessType rw, int mmu_idx, 70 bool probe, uintptr_t retaddr) 71 { 72 TriCoreCPU *cpu = TRICORE_CPU(cs); 73 CPUTriCoreState *env = &cpu->env; 74 hwaddr physical; 75 int prot; 76 int ret = 0; 77 78 rw &= 1; 79 ret = get_physical_address(env, &physical, &prot, 80 address, rw, mmu_idx); 81 82 qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " 83 HWADDR_FMT_plx " prot %d\n", 84 __func__, (target_ulong)address, ret, physical, prot); 85 86 if (ret == TLBRET_MATCH) { 87 tlb_set_page(cs, address & TARGET_PAGE_MASK, 88 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, 89 mmu_idx, TARGET_PAGE_SIZE); 90 return true; 91 } else { 92 assert(ret < 0); 93 if (probe) { 94 return false; 95 } 96 raise_mmu_exception(env, address, rw, ret); 97 cpu_loop_exit_restore(cs, retaddr); 98 } 99 } 100 101 static void tricore_cpu_list_entry(gpointer data, gpointer user_data) 102 { 103 ObjectClass *oc = data; 104 const char *typename; 105 char *name; 106 107 typename = object_class_get_name(oc); 108 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU)); 109 qemu_printf(" %s\n", name); 110 g_free(name); 111 } 112 113 void tricore_cpu_list(void) 114 { 115 GSList *list; 116 117 list = object_class_get_list_sorted(TYPE_TRICORE_CPU, false); 118 qemu_printf("Available CPUs:\n"); 119 g_slist_foreach(list, tricore_cpu_list_entry, NULL); 120 g_slist_free(list); 121 } 122 123 void fpu_set_state(CPUTriCoreState *env) 124 { 125 set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status); 126 set_flush_inputs_to_zero(1, &env->fp_status); 127 set_flush_to_zero(1, &env->fp_status); 128 set_default_nan_mode(1, &env->fp_status); 129 } 130 131 uint32_t psw_read(CPUTriCoreState *env) 132 { 133 /* clear all USB bits */ 134 env->PSW &= 0x6ffffff; 135 /* now set them from the cache */ 136 env->PSW |= ((env->PSW_USB_C != 0) << 31); 137 env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1); 138 env->PSW |= ((env->PSW_USB_SV & (1 << 31)) >> 2); 139 env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3); 140 env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4); 141 142 return env->PSW; 143 } 144 145 void psw_write(CPUTriCoreState *env, uint32_t val) 146 { 147 env->PSW_USB_C = (val & MASK_USB_C); 148 env->PSW_USB_V = (val & MASK_USB_V) << 1; 149 env->PSW_USB_SV = (val & MASK_USB_SV) << 2; 150 env->PSW_USB_AV = (val & MASK_USB_AV) << 3; 151 env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4; 152 env->PSW = val; 153 154 fpu_set_state(env); 155 } 156 157 #define FIELD_GETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ 158 uint32_t NAME(CPUTriCoreState *env) \ 159 { \ 160 if (tricore_feature(env, TRICORE_FEATURE_##FEATURE)) { \ 161 return FIELD_EX32(env->REG, REG, FIELD ## _ ## FEATURE); \ 162 } \ 163 return FIELD_EX32(env->REG, REG, FIELD ## _13); \ 164 } 165 166 #define FIELD_GETTER(NAME, REG, FIELD) \ 167 uint32_t NAME(CPUTriCoreState *env) \ 168 { \ 169 return FIELD_EX32(env->REG, REG, FIELD); \ 170 } 171 172 #define FIELD_SETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ 173 void NAME(CPUTriCoreState *env, uint32_t val) \ 174 { \ 175 if (tricore_feature(env, TRICORE_FEATURE_##FEATURE)) { \ 176 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _ ## FEATURE, val); \ 177 } \ 178 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _13, val); \ 179 } 180 181 #define FIELD_SETTER(NAME, REG, FIELD) \ 182 void NAME(CPUTriCoreState *env, uint32_t val) \ 183 { \ 184 env->REG = FIELD_DP32(env->REG, REG, FIELD, val); \ 185 } 186 187 FIELD_GETTER_WITH_FEATURE(pcxi_get_pcpn, PCXI, PCPN, 161) 188 FIELD_SETTER_WITH_FEATURE(pcxi_set_pcpn, PCXI, PCPN, 161) 189 FIELD_GETTER_WITH_FEATURE(pcxi_get_pie, PCXI, PIE, 161) 190 FIELD_SETTER_WITH_FEATURE(pcxi_set_pie, PCXI, PIE, 161) 191 FIELD_GETTER_WITH_FEATURE(pcxi_get_ul, PCXI, UL, 161) 192 FIELD_SETTER_WITH_FEATURE(pcxi_set_ul, PCXI, UL, 161) 193 FIELD_GETTER(pcxi_get_pcxs, PCXI, PCXS) 194 FIELD_GETTER(pcxi_get_pcxo, PCXI, PCXO) 195 196 FIELD_GETTER_WITH_FEATURE(icr_get_ie, ICR, IE, 161) 197 FIELD_SETTER_WITH_FEATURE(icr_set_ie, ICR, IE, 161) 198 FIELD_GETTER(icr_get_ccpn, ICR, CCPN) 199 FIELD_SETTER(icr_set_ccpn, ICR, CCPN) 200