1 /* 2 * TriCore emulation for qemu: main CPU struct. 3 * 4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef TRICORE_CPU_H 21 #define TRICORE_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 #include "exec/cpu-defs.h" 26 #include "tricore-defs.h" 27 28 struct tricore_boot_info; 29 30 typedef struct tricore_def_t tricore_def_t; 31 32 typedef struct CPUTriCoreState CPUTriCoreState; 33 struct CPUTriCoreState { 34 /* GPR Register */ 35 uint32_t gpr_a[16]; 36 uint32_t gpr_d[16]; 37 /* CSFR Register */ 38 uint32_t PCXI; 39 /* Frequently accessed PSW_USB bits are stored separately for efficiency. 40 This contains all the other bits. Use psw_{read,write} to access 41 the whole PSW. */ 42 uint32_t PSW; 43 44 /* PSW flag cache for faster execution 45 */ 46 uint32_t PSW_USB_C; 47 uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */ 48 uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */ 49 uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */ 50 uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */ 51 52 uint32_t PC; 53 uint32_t SYSCON; 54 uint32_t CPU_ID; 55 uint32_t CORE_ID; 56 uint32_t BIV; 57 uint32_t BTV; 58 uint32_t ISP; 59 uint32_t ICR; 60 uint32_t FCX; 61 uint32_t LCX; 62 uint32_t COMPAT; 63 64 /* Mem Protection Register */ 65 uint32_t DPR0_0L; 66 uint32_t DPR0_0U; 67 uint32_t DPR0_1L; 68 uint32_t DPR0_1U; 69 uint32_t DPR0_2L; 70 uint32_t DPR0_2U; 71 uint32_t DPR0_3L; 72 uint32_t DPR0_3U; 73 74 uint32_t DPR1_0L; 75 uint32_t DPR1_0U; 76 uint32_t DPR1_1L; 77 uint32_t DPR1_1U; 78 uint32_t DPR1_2L; 79 uint32_t DPR1_2U; 80 uint32_t DPR1_3L; 81 uint32_t DPR1_3U; 82 83 uint32_t DPR2_0L; 84 uint32_t DPR2_0U; 85 uint32_t DPR2_1L; 86 uint32_t DPR2_1U; 87 uint32_t DPR2_2L; 88 uint32_t DPR2_2U; 89 uint32_t DPR2_3L; 90 uint32_t DPR2_3U; 91 92 uint32_t DPR3_0L; 93 uint32_t DPR3_0U; 94 uint32_t DPR3_1L; 95 uint32_t DPR3_1U; 96 uint32_t DPR3_2L; 97 uint32_t DPR3_2U; 98 uint32_t DPR3_3L; 99 uint32_t DPR3_3U; 100 101 uint32_t CPR0_0L; 102 uint32_t CPR0_0U; 103 uint32_t CPR0_1L; 104 uint32_t CPR0_1U; 105 uint32_t CPR0_2L; 106 uint32_t CPR0_2U; 107 uint32_t CPR0_3L; 108 uint32_t CPR0_3U; 109 110 uint32_t CPR1_0L; 111 uint32_t CPR1_0U; 112 uint32_t CPR1_1L; 113 uint32_t CPR1_1U; 114 uint32_t CPR1_2L; 115 uint32_t CPR1_2U; 116 uint32_t CPR1_3L; 117 uint32_t CPR1_3U; 118 119 uint32_t CPR2_0L; 120 uint32_t CPR2_0U; 121 uint32_t CPR2_1L; 122 uint32_t CPR2_1U; 123 uint32_t CPR2_2L; 124 uint32_t CPR2_2U; 125 uint32_t CPR2_3L; 126 uint32_t CPR2_3U; 127 128 uint32_t CPR3_0L; 129 uint32_t CPR3_0U; 130 uint32_t CPR3_1L; 131 uint32_t CPR3_1U; 132 uint32_t CPR3_2L; 133 uint32_t CPR3_2U; 134 uint32_t CPR3_3L; 135 uint32_t CPR3_3U; 136 137 uint32_t DPM0; 138 uint32_t DPM1; 139 uint32_t DPM2; 140 uint32_t DPM3; 141 142 uint32_t CPM0; 143 uint32_t CPM1; 144 uint32_t CPM2; 145 uint32_t CPM3; 146 147 /* Memory Management Registers */ 148 uint32_t MMU_CON; 149 uint32_t MMU_ASI; 150 uint32_t MMU_TVA; 151 uint32_t MMU_TPA; 152 uint32_t MMU_TPX; 153 uint32_t MMU_TFA; 154 /* {1.3.1 only */ 155 uint32_t BMACON; 156 uint32_t SMACON; 157 uint32_t DIEAR; 158 uint32_t DIETR; 159 uint32_t CCDIER; 160 uint32_t MIECON; 161 uint32_t PIEAR; 162 uint32_t PIETR; 163 uint32_t CCPIER; 164 /*} */ 165 /* Debug Registers */ 166 uint32_t DBGSR; 167 uint32_t EXEVT; 168 uint32_t CREVT; 169 uint32_t SWEVT; 170 uint32_t TR0EVT; 171 uint32_t TR1EVT; 172 uint32_t DMS; 173 uint32_t DCX; 174 uint32_t DBGTCR; 175 uint32_t CCTRL; 176 uint32_t CCNT; 177 uint32_t ICNT; 178 uint32_t M1CNT; 179 uint32_t M2CNT; 180 uint32_t M3CNT; 181 /* Floating Point Registers */ 182 float_status fp_status; 183 /* QEMU */ 184 int error_code; 185 uint32_t hflags; /* CPU State */ 186 187 /* Internal CPU feature flags. */ 188 uint64_t features; 189 190 const tricore_def_t *cpu_model; 191 void *irq[8]; 192 struct QEMUTimer *timer; /* Internal timer */ 193 }; 194 195 /** 196 * TriCoreCPU: 197 * @env: #CPUTriCoreState 198 * 199 * A TriCore CPU. 200 */ 201 struct TriCoreCPU { 202 /*< private >*/ 203 CPUState parent_obj; 204 /*< public >*/ 205 206 CPUNegativeOffsetState neg; 207 CPUTriCoreState env; 208 }; 209 210 211 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 212 void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 213 214 215 #define MASK_PCXI_PCPN 0xff000000 216 #define MASK_PCXI_PIE_1_3 0x00800000 217 #define MASK_PCXI_PIE_1_6 0x00200000 218 #define MASK_PCXI_UL 0x00400000 219 #define MASK_PCXI_PCXS 0x000f0000 220 #define MASK_PCXI_PCXO 0x0000ffff 221 222 #define MASK_PSW_USB 0xff000000 223 #define MASK_USB_C 0x80000000 224 #define MASK_USB_V 0x40000000 225 #define MASK_USB_SV 0x20000000 226 #define MASK_USB_AV 0x10000000 227 #define MASK_USB_SAV 0x08000000 228 #define MASK_PSW_PRS 0x00003000 229 #define MASK_PSW_IO 0x00000c00 230 #define MASK_PSW_IS 0x00000200 231 #define MASK_PSW_GW 0x00000100 232 #define MASK_PSW_CDE 0x00000080 233 #define MASK_PSW_CDC 0x0000007f 234 #define MASK_PSW_FPU_RM 0x3000000 235 236 #define MASK_SYSCON_PRO_TEN 0x2 237 #define MASK_SYSCON_FCD_SF 0x1 238 239 #define MASK_CPUID_MOD 0xffff0000 240 #define MASK_CPUID_MOD_32B 0x0000ff00 241 #define MASK_CPUID_REV 0x000000ff 242 243 #define MASK_ICR_PIPN 0x00ff0000 244 #define MASK_ICR_IE_1_3 0x00000100 245 #define MASK_ICR_IE_1_6 0x00008000 246 #define MASK_ICR_CCPN 0x000000ff 247 248 #define MASK_FCX_FCXS 0x000f0000 249 #define MASK_FCX_FCXO 0x0000ffff 250 251 #define MASK_LCX_LCXS 0x000f0000 252 #define MASK_LCX_LCX0 0x0000ffff 253 254 #define MASK_DBGSR_DE 0x1 255 #define MASK_DBGSR_HALT 0x6 256 #define MASK_DBGSR_SUSP 0x10 257 #define MASK_DBGSR_PREVSUSP 0x20 258 #define MASK_DBGSR_PEVT 0x40 259 #define MASK_DBGSR_EVTSRC 0x1f00 260 261 #define TRICORE_HFLAG_KUU 0x3 262 #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */ 263 #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */ 264 #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */ 265 266 enum tricore_features { 267 TRICORE_FEATURE_13, 268 TRICORE_FEATURE_131, 269 TRICORE_FEATURE_16, 270 TRICORE_FEATURE_161, 271 }; 272 273 static inline int tricore_feature(CPUTriCoreState *env, int feature) 274 { 275 return (env->features & (1ULL << feature)) != 0; 276 } 277 278 /* TriCore Traps Classes*/ 279 enum { 280 TRAPC_NONE = -1, 281 TRAPC_MMU = 0, 282 TRAPC_PROT = 1, 283 TRAPC_INSN_ERR = 2, 284 TRAPC_CTX_MNG = 3, 285 TRAPC_SYSBUS = 4, 286 TRAPC_ASSERT = 5, 287 TRAPC_SYSCALL = 6, 288 TRAPC_NMI = 7, 289 TRAPC_IRQ = 8 290 }; 291 292 /* Class 0 TIN */ 293 enum { 294 TIN0_VAF = 0, 295 TIN0_VAP = 1, 296 }; 297 298 /* Class 1 TIN */ 299 enum { 300 TIN1_PRIV = 1, 301 TIN1_MPR = 2, 302 TIN1_MPW = 3, 303 TIN1_MPX = 4, 304 TIN1_MPP = 5, 305 TIN1_MPN = 6, 306 TIN1_GRWP = 7, 307 }; 308 309 /* Class 2 TIN */ 310 enum { 311 TIN2_IOPC = 1, 312 TIN2_UOPC = 2, 313 TIN2_OPD = 3, 314 TIN2_ALN = 4, 315 TIN2_MEM = 5, 316 }; 317 318 /* Class 3 TIN */ 319 enum { 320 TIN3_FCD = 1, 321 TIN3_CDO = 2, 322 TIN3_CDU = 3, 323 TIN3_FCU = 4, 324 TIN3_CSU = 5, 325 TIN3_CTYP = 6, 326 TIN3_NEST = 7, 327 }; 328 329 /* Class 4 TIN */ 330 enum { 331 TIN4_PSE = 1, 332 TIN4_DSE = 2, 333 TIN4_DAE = 3, 334 TIN4_CAE = 4, 335 TIN4_PIE = 5, 336 TIN4_DIE = 6, 337 }; 338 339 /* Class 5 TIN */ 340 enum { 341 TIN5_OVF = 1, 342 TIN5_SOVF = 1, 343 }; 344 345 /* Class 6 TIN 346 * 347 * Is always TIN6_SYS 348 */ 349 350 /* Class 7 TIN */ 351 enum { 352 TIN7_NMI = 0, 353 }; 354 355 uint32_t psw_read(CPUTriCoreState *env); 356 void psw_write(CPUTriCoreState *env, uint32_t val); 357 358 void fpu_set_state(CPUTriCoreState *env); 359 360 #define MMU_USER_IDX 2 361 362 void tricore_cpu_list(void); 363 364 #define cpu_signal_handler cpu_tricore_signal_handler 365 #define cpu_list tricore_cpu_list 366 367 static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) 368 { 369 return 0; 370 } 371 372 typedef CPUTriCoreState CPUArchState; 373 typedef TriCoreCPU ArchCPU; 374 375 #include "exec/cpu-all.h" 376 377 enum { 378 /* 1 bit to define user level / supervisor access */ 379 ACCESS_USER = 0x00, 380 ACCESS_SUPER = 0x01, 381 /* 1 bit to indicate direction */ 382 ACCESS_STORE = 0x02, 383 /* Type of instruction that generated the access */ 384 ACCESS_CODE = 0x10, /* Code fetch access */ 385 ACCESS_INT = 0x20, /* Integer load/store access */ 386 ACCESS_FLOAT = 0x30, /* floating point load/store access */ 387 }; 388 389 void cpu_state_reset(CPUTriCoreState *s); 390 void tricore_tcg_init(void); 391 int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); 392 393 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, 394 target_ulong *cs_base, uint32_t *flags) 395 { 396 *pc = env->PC; 397 *cs_base = 0; 398 *flags = 0; 399 } 400 401 #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU 402 #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX 403 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU 404 405 /* helpers.c */ 406 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 407 MMUAccessType access_type, int mmu_idx, 408 bool probe, uintptr_t retaddr); 409 410 #endif /* TRICORE_CPU_H */ 411