1 /* 2 * TriCore emulation for qemu: main CPU struct. 3 * 4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef TRICORE_CPU_H 21 #define TRICORE_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 #include "tricore-defs.h" 26 27 struct tricore_boot_info; 28 29 typedef struct tricore_def_t tricore_def_t; 30 31 typedef struct CPUArchState { 32 /* GPR Register */ 33 uint32_t gpr_a[16]; 34 uint32_t gpr_d[16]; 35 /* CSFR Register */ 36 uint32_t PCXI; 37 /* Frequently accessed PSW_USB bits are stored separately for efficiency. 38 This contains all the other bits. Use psw_{read,write} to access 39 the whole PSW. */ 40 uint32_t PSW; 41 42 /* PSW flag cache for faster execution 43 */ 44 uint32_t PSW_USB_C; 45 uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */ 46 uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */ 47 uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */ 48 uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */ 49 50 uint32_t PC; 51 uint32_t SYSCON; 52 uint32_t CPU_ID; 53 uint32_t CORE_ID; 54 uint32_t BIV; 55 uint32_t BTV; 56 uint32_t ISP; 57 uint32_t ICR; 58 uint32_t FCX; 59 uint32_t LCX; 60 uint32_t COMPAT; 61 62 /* Mem Protection Register */ 63 uint32_t DPR0_0L; 64 uint32_t DPR0_0U; 65 uint32_t DPR0_1L; 66 uint32_t DPR0_1U; 67 uint32_t DPR0_2L; 68 uint32_t DPR0_2U; 69 uint32_t DPR0_3L; 70 uint32_t DPR0_3U; 71 72 uint32_t DPR1_0L; 73 uint32_t DPR1_0U; 74 uint32_t DPR1_1L; 75 uint32_t DPR1_1U; 76 uint32_t DPR1_2L; 77 uint32_t DPR1_2U; 78 uint32_t DPR1_3L; 79 uint32_t DPR1_3U; 80 81 uint32_t DPR2_0L; 82 uint32_t DPR2_0U; 83 uint32_t DPR2_1L; 84 uint32_t DPR2_1U; 85 uint32_t DPR2_2L; 86 uint32_t DPR2_2U; 87 uint32_t DPR2_3L; 88 uint32_t DPR2_3U; 89 90 uint32_t DPR3_0L; 91 uint32_t DPR3_0U; 92 uint32_t DPR3_1L; 93 uint32_t DPR3_1U; 94 uint32_t DPR3_2L; 95 uint32_t DPR3_2U; 96 uint32_t DPR3_3L; 97 uint32_t DPR3_3U; 98 99 uint32_t CPR0_0L; 100 uint32_t CPR0_0U; 101 uint32_t CPR0_1L; 102 uint32_t CPR0_1U; 103 uint32_t CPR0_2L; 104 uint32_t CPR0_2U; 105 uint32_t CPR0_3L; 106 uint32_t CPR0_3U; 107 108 uint32_t CPR1_0L; 109 uint32_t CPR1_0U; 110 uint32_t CPR1_1L; 111 uint32_t CPR1_1U; 112 uint32_t CPR1_2L; 113 uint32_t CPR1_2U; 114 uint32_t CPR1_3L; 115 uint32_t CPR1_3U; 116 117 uint32_t CPR2_0L; 118 uint32_t CPR2_0U; 119 uint32_t CPR2_1L; 120 uint32_t CPR2_1U; 121 uint32_t CPR2_2L; 122 uint32_t CPR2_2U; 123 uint32_t CPR2_3L; 124 uint32_t CPR2_3U; 125 126 uint32_t CPR3_0L; 127 uint32_t CPR3_0U; 128 uint32_t CPR3_1L; 129 uint32_t CPR3_1U; 130 uint32_t CPR3_2L; 131 uint32_t CPR3_2U; 132 uint32_t CPR3_3L; 133 uint32_t CPR3_3U; 134 135 uint32_t DPM0; 136 uint32_t DPM1; 137 uint32_t DPM2; 138 uint32_t DPM3; 139 140 uint32_t CPM0; 141 uint32_t CPM1; 142 uint32_t CPM2; 143 uint32_t CPM3; 144 145 /* Memory Management Registers */ 146 uint32_t MMU_CON; 147 uint32_t MMU_ASI; 148 uint32_t MMU_TVA; 149 uint32_t MMU_TPA; 150 uint32_t MMU_TPX; 151 uint32_t MMU_TFA; 152 /* {1.3.1 only */ 153 uint32_t BMACON; 154 uint32_t SMACON; 155 uint32_t DIEAR; 156 uint32_t DIETR; 157 uint32_t CCDIER; 158 uint32_t MIECON; 159 uint32_t PIEAR; 160 uint32_t PIETR; 161 uint32_t CCPIER; 162 /*} */ 163 /* Debug Registers */ 164 uint32_t DBGSR; 165 uint32_t EXEVT; 166 uint32_t CREVT; 167 uint32_t SWEVT; 168 uint32_t TR0EVT; 169 uint32_t TR1EVT; 170 uint32_t DMS; 171 uint32_t DCX; 172 uint32_t DBGTCR; 173 uint32_t CCTRL; 174 uint32_t CCNT; 175 uint32_t ICNT; 176 uint32_t M1CNT; 177 uint32_t M2CNT; 178 uint32_t M3CNT; 179 /* Floating Point Registers */ 180 float_status fp_status; 181 /* QEMU */ 182 int error_code; 183 uint32_t hflags; /* CPU State */ 184 185 /* Internal CPU feature flags. */ 186 uint64_t features; 187 188 const tricore_def_t *cpu_model; 189 void *irq[8]; 190 struct QEMUTimer *timer; /* Internal timer */ 191 } CPUTriCoreState; 192 193 /** 194 * TriCoreCPU: 195 * @env: #CPUTriCoreState 196 * 197 * A TriCore CPU. 198 */ 199 struct TriCoreCPU { 200 /*< private >*/ 201 CPUState parent_obj; 202 /*< public >*/ 203 204 CPUNegativeOffsetState neg; 205 CPUTriCoreState env; 206 }; 207 208 209 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 210 void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 211 212 213 #define MASK_PCXI_PCPN 0xff000000 214 #define MASK_PCXI_PIE_1_3 0x00800000 215 #define MASK_PCXI_PIE_1_6 0x00200000 216 #define MASK_PCXI_UL 0x00400000 217 #define MASK_PCXI_PCXS 0x000f0000 218 #define MASK_PCXI_PCXO 0x0000ffff 219 220 #define MASK_PSW_USB 0xff000000 221 #define MASK_USB_C 0x80000000 222 #define MASK_USB_V 0x40000000 223 #define MASK_USB_SV 0x20000000 224 #define MASK_USB_AV 0x10000000 225 #define MASK_USB_SAV 0x08000000 226 #define MASK_PSW_PRS 0x00003000 227 #define MASK_PSW_IO 0x00000c00 228 #define MASK_PSW_IS 0x00000200 229 #define MASK_PSW_GW 0x00000100 230 #define MASK_PSW_CDE 0x00000080 231 #define MASK_PSW_CDC 0x0000007f 232 #define MASK_PSW_FPU_RM 0x3000000 233 234 #define MASK_SYSCON_PRO_TEN 0x2 235 #define MASK_SYSCON_FCD_SF 0x1 236 237 #define MASK_CPUID_MOD 0xffff0000 238 #define MASK_CPUID_MOD_32B 0x0000ff00 239 #define MASK_CPUID_REV 0x000000ff 240 241 #define MASK_ICR_PIPN 0x00ff0000 242 #define MASK_ICR_IE_1_3 0x00000100 243 #define MASK_ICR_IE_1_6 0x00008000 244 #define MASK_ICR_CCPN 0x000000ff 245 246 #define MASK_FCX_FCXS 0x000f0000 247 #define MASK_FCX_FCXO 0x0000ffff 248 249 #define MASK_LCX_LCXS 0x000f0000 250 #define MASK_LCX_LCX0 0x0000ffff 251 252 #define MASK_DBGSR_DE 0x1 253 #define MASK_DBGSR_HALT 0x6 254 #define MASK_DBGSR_SUSP 0x10 255 #define MASK_DBGSR_PREVSUSP 0x20 256 #define MASK_DBGSR_PEVT 0x40 257 #define MASK_DBGSR_EVTSRC 0x1f00 258 259 #define TRICORE_HFLAG_KUU 0x3 260 #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */ 261 #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */ 262 #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */ 263 264 enum tricore_features { 265 TRICORE_FEATURE_13, 266 TRICORE_FEATURE_131, 267 TRICORE_FEATURE_16, 268 TRICORE_FEATURE_161, 269 }; 270 271 static inline int tricore_feature(CPUTriCoreState *env, int feature) 272 { 273 return (env->features & (1ULL << feature)) != 0; 274 } 275 276 /* TriCore Traps Classes*/ 277 enum { 278 TRAPC_NONE = -1, 279 TRAPC_MMU = 0, 280 TRAPC_PROT = 1, 281 TRAPC_INSN_ERR = 2, 282 TRAPC_CTX_MNG = 3, 283 TRAPC_SYSBUS = 4, 284 TRAPC_ASSERT = 5, 285 TRAPC_SYSCALL = 6, 286 TRAPC_NMI = 7, 287 TRAPC_IRQ = 8 288 }; 289 290 /* Class 0 TIN */ 291 enum { 292 TIN0_VAF = 0, 293 TIN0_VAP = 1, 294 }; 295 296 /* Class 1 TIN */ 297 enum { 298 TIN1_PRIV = 1, 299 TIN1_MPR = 2, 300 TIN1_MPW = 3, 301 TIN1_MPX = 4, 302 TIN1_MPP = 5, 303 TIN1_MPN = 6, 304 TIN1_GRWP = 7, 305 }; 306 307 /* Class 2 TIN */ 308 enum { 309 TIN2_IOPC = 1, 310 TIN2_UOPC = 2, 311 TIN2_OPD = 3, 312 TIN2_ALN = 4, 313 TIN2_MEM = 5, 314 }; 315 316 /* Class 3 TIN */ 317 enum { 318 TIN3_FCD = 1, 319 TIN3_CDO = 2, 320 TIN3_CDU = 3, 321 TIN3_FCU = 4, 322 TIN3_CSU = 5, 323 TIN3_CTYP = 6, 324 TIN3_NEST = 7, 325 }; 326 327 /* Class 4 TIN */ 328 enum { 329 TIN4_PSE = 1, 330 TIN4_DSE = 2, 331 TIN4_DAE = 3, 332 TIN4_CAE = 4, 333 TIN4_PIE = 5, 334 TIN4_DIE = 6, 335 }; 336 337 /* Class 5 TIN */ 338 enum { 339 TIN5_OVF = 1, 340 TIN5_SOVF = 1, 341 }; 342 343 /* Class 6 TIN 344 * 345 * Is always TIN6_SYS 346 */ 347 348 /* Class 7 TIN */ 349 enum { 350 TIN7_NMI = 0, 351 }; 352 353 uint32_t psw_read(CPUTriCoreState *env); 354 void psw_write(CPUTriCoreState *env, uint32_t val); 355 int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n); 356 int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); 357 358 void fpu_set_state(CPUTriCoreState *env); 359 360 #define MMU_USER_IDX 2 361 362 void tricore_cpu_list(void); 363 364 #define cpu_list tricore_cpu_list 365 366 static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) 367 { 368 return 0; 369 } 370 371 typedef TriCoreCPU ArchCPU; 372 373 #include "exec/cpu-all.h" 374 375 void cpu_state_reset(CPUTriCoreState *s); 376 void tricore_tcg_init(void); 377 378 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, 379 target_ulong *cs_base, uint32_t *flags) 380 { 381 *pc = env->PC; 382 *cs_base = 0; 383 *flags = 0; 384 } 385 386 #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU 387 #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX 388 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU 389 390 /* helpers.c */ 391 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 392 MMUAccessType access_type, int mmu_idx, 393 bool probe, uintptr_t retaddr); 394 395 #endif /* TRICORE_CPU_H */ 396