1 /* 2 SPARC translation 3 4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> 5 Copyright (C) 2003-2005 Fabrice Bellard 6 7 This library is free software; you can redistribute it and/or 8 modify it under the terms of the GNU Lesser General Public 9 License as published by the Free Software Foundation; either 10 version 2 of the License, or (at your option) any later version. 11 12 This library is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 Lesser General Public License for more details. 16 17 You should have received a copy of the GNU Lesser General Public 18 License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 23 #include "cpu.h" 24 #include "disas/disas.h" 25 #include "exec/helper-proto.h" 26 #include "exec/exec-all.h" 27 #include "tcg/tcg-op.h" 28 #include "exec/cpu_ldst.h" 29 30 #include "exec/helper-gen.h" 31 32 #include "trace-tcg.h" 33 #include "exec/translator.h" 34 #include "exec/log.h" 35 #include "asi.h" 36 37 38 #define DEBUG_DISAS 39 40 #define DYNAMIC_PC 1 /* dynamic pc value */ 41 #define JUMP_PC 2 /* dynamic pc value which takes only two values 42 according to jump_pc[T2] */ 43 44 #define DISAS_EXIT DISAS_TARGET_0 45 46 /* global register indexes */ 47 static TCGv_ptr cpu_regwptr; 48 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; 49 static TCGv_i32 cpu_cc_op; 50 static TCGv_i32 cpu_psr; 51 static TCGv cpu_fsr, cpu_pc, cpu_npc; 52 static TCGv cpu_regs[32]; 53 static TCGv cpu_y; 54 #ifndef CONFIG_USER_ONLY 55 static TCGv cpu_tbr; 56 #endif 57 static TCGv cpu_cond; 58 #ifdef TARGET_SPARC64 59 static TCGv_i32 cpu_xcc, cpu_fprs; 60 static TCGv cpu_gsr; 61 static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; 62 static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; 63 #else 64 static TCGv cpu_wim; 65 #endif 66 /* Floating point registers */ 67 static TCGv_i64 cpu_fpr[TARGET_DPREGS]; 68 69 #include "exec/gen-icount.h" 70 71 typedef struct DisasContext { 72 DisasContextBase base; 73 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ 74 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ 75 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ 76 int mem_idx; 77 bool fpu_enabled; 78 bool address_mask_32bit; 79 #ifndef CONFIG_USER_ONLY 80 bool supervisor; 81 #ifdef TARGET_SPARC64 82 bool hypervisor; 83 #endif 84 #endif 85 86 uint32_t cc_op; /* current CC operation */ 87 sparc_def_t *def; 88 TCGv_i32 t32[3]; 89 TCGv ttl[5]; 90 int n_t32; 91 int n_ttl; 92 #ifdef TARGET_SPARC64 93 int fprs_dirty; 94 int asi; 95 #endif 96 } DisasContext; 97 98 typedef struct { 99 TCGCond cond; 100 bool is_bool; 101 bool g1, g2; 102 TCGv c1, c2; 103 } DisasCompare; 104 105 // This function uses non-native bit order 106 #define GET_FIELD(X, FROM, TO) \ 107 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) 108 109 // This function uses the order in the manuals, i.e. bit 0 is 2^0 110 #define GET_FIELD_SP(X, FROM, TO) \ 111 GET_FIELD(X, 31 - (TO), 31 - (FROM)) 112 113 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) 114 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) 115 116 #ifdef TARGET_SPARC64 117 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) 118 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) 119 #else 120 #define DFPREG(r) (r & 0x1e) 121 #define QFPREG(r) (r & 0x1c) 122 #endif 123 124 #define UA2005_HTRAP_MASK 0xff 125 #define V8_TRAP_MASK 0x7f 126 127 static int sign_extend(int x, int len) 128 { 129 len = 32 - len; 130 return (x << len) >> len; 131 } 132 133 #define IS_IMM (insn & (1<<13)) 134 135 static inline TCGv_i32 get_temp_i32(DisasContext *dc) 136 { 137 TCGv_i32 t; 138 assert(dc->n_t32 < ARRAY_SIZE(dc->t32)); 139 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32(); 140 return t; 141 } 142 143 static inline TCGv get_temp_tl(DisasContext *dc) 144 { 145 TCGv t; 146 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl)); 147 dc->ttl[dc->n_ttl++] = t = tcg_temp_new(); 148 return t; 149 } 150 151 static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) 152 { 153 #if defined(TARGET_SPARC64) 154 int bit = (rd < 32) ? 1 : 2; 155 /* If we know we've already set this bit within the TB, 156 we can avoid setting it again. */ 157 if (!(dc->fprs_dirty & bit)) { 158 dc->fprs_dirty |= bit; 159 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit); 160 } 161 #endif 162 } 163 164 /* floating point registers moves */ 165 static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) 166 { 167 #if TCG_TARGET_REG_BITS == 32 168 if (src & 1) { 169 return TCGV_LOW(cpu_fpr[src / 2]); 170 } else { 171 return TCGV_HIGH(cpu_fpr[src / 2]); 172 } 173 #else 174 TCGv_i32 ret = get_temp_i32(dc); 175 if (src & 1) { 176 tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]); 177 } else { 178 tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]); 179 } 180 return ret; 181 #endif 182 } 183 184 static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) 185 { 186 #if TCG_TARGET_REG_BITS == 32 187 if (dst & 1) { 188 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v); 189 } else { 190 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v); 191 } 192 #else 193 TCGv_i64 t = (TCGv_i64)v; 194 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t, 195 (dst & 1 ? 0 : 32), 32); 196 #endif 197 gen_update_fprs_dirty(dc, dst); 198 } 199 200 static TCGv_i32 gen_dest_fpr_F(DisasContext *dc) 201 { 202 return get_temp_i32(dc); 203 } 204 205 static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) 206 { 207 src = DFPREG(src); 208 return cpu_fpr[src / 2]; 209 } 210 211 static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v) 212 { 213 dst = DFPREG(dst); 214 tcg_gen_mov_i64(cpu_fpr[dst / 2], v); 215 gen_update_fprs_dirty(dc, dst); 216 } 217 218 static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst) 219 { 220 return cpu_fpr[DFPREG(dst) / 2]; 221 } 222 223 static void gen_op_load_fpr_QT0(unsigned int src) 224 { 225 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) + 226 offsetof(CPU_QuadU, ll.upper)); 227 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) + 228 offsetof(CPU_QuadU, ll.lower)); 229 } 230 231 static void gen_op_load_fpr_QT1(unsigned int src) 232 { 233 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) + 234 offsetof(CPU_QuadU, ll.upper)); 235 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) + 236 offsetof(CPU_QuadU, ll.lower)); 237 } 238 239 static void gen_op_store_QT0_fpr(unsigned int dst) 240 { 241 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) + 242 offsetof(CPU_QuadU, ll.upper)); 243 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) + 244 offsetof(CPU_QuadU, ll.lower)); 245 } 246 247 static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, 248 TCGv_i64 v1, TCGv_i64 v2) 249 { 250 dst = QFPREG(dst); 251 252 tcg_gen_mov_i64(cpu_fpr[dst / 2], v1); 253 tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2); 254 gen_update_fprs_dirty(dc, dst); 255 } 256 257 #ifdef TARGET_SPARC64 258 static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src) 259 { 260 src = QFPREG(src); 261 return cpu_fpr[src / 2]; 262 } 263 264 static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src) 265 { 266 src = QFPREG(src); 267 return cpu_fpr[src / 2 + 1]; 268 } 269 270 static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) 271 { 272 rd = QFPREG(rd); 273 rs = QFPREG(rs); 274 275 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); 276 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); 277 gen_update_fprs_dirty(dc, rd); 278 } 279 #endif 280 281 /* moves */ 282 #ifdef CONFIG_USER_ONLY 283 #define supervisor(dc) 0 284 #ifdef TARGET_SPARC64 285 #define hypervisor(dc) 0 286 #endif 287 #else 288 #ifdef TARGET_SPARC64 289 #define hypervisor(dc) (dc->hypervisor) 290 #define supervisor(dc) (dc->supervisor | dc->hypervisor) 291 #else 292 #define supervisor(dc) (dc->supervisor) 293 #endif 294 #endif 295 296 #ifdef TARGET_SPARC64 297 #ifndef TARGET_ABI32 298 #define AM_CHECK(dc) ((dc)->address_mask_32bit) 299 #else 300 #define AM_CHECK(dc) (1) 301 #endif 302 #endif 303 304 static inline void gen_address_mask(DisasContext *dc, TCGv addr) 305 { 306 #ifdef TARGET_SPARC64 307 if (AM_CHECK(dc)) 308 tcg_gen_andi_tl(addr, addr, 0xffffffffULL); 309 #endif 310 } 311 312 static inline TCGv gen_load_gpr(DisasContext *dc, int reg) 313 { 314 if (reg > 0) { 315 assert(reg < 32); 316 return cpu_regs[reg]; 317 } else { 318 TCGv t = get_temp_tl(dc); 319 tcg_gen_movi_tl(t, 0); 320 return t; 321 } 322 } 323 324 static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v) 325 { 326 if (reg > 0) { 327 assert(reg < 32); 328 tcg_gen_mov_tl(cpu_regs[reg], v); 329 } 330 } 331 332 static inline TCGv gen_dest_gpr(DisasContext *dc, int reg) 333 { 334 if (reg > 0) { 335 assert(reg < 32); 336 return cpu_regs[reg]; 337 } else { 338 return get_temp_tl(dc); 339 } 340 } 341 342 static inline bool use_goto_tb(DisasContext *s, target_ulong pc, 343 target_ulong npc) 344 { 345 if (unlikely(s->base.singlestep_enabled || singlestep)) { 346 return false; 347 } 348 349 #ifndef CONFIG_USER_ONLY 350 return (pc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) && 351 (npc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK); 352 #else 353 return true; 354 #endif 355 } 356 357 static inline void gen_goto_tb(DisasContext *s, int tb_num, 358 target_ulong pc, target_ulong npc) 359 { 360 if (use_goto_tb(s, pc, npc)) { 361 /* jump to same page: we can use a direct jump */ 362 tcg_gen_goto_tb(tb_num); 363 tcg_gen_movi_tl(cpu_pc, pc); 364 tcg_gen_movi_tl(cpu_npc, npc); 365 tcg_gen_exit_tb(s->base.tb, tb_num); 366 } else { 367 /* jump to another page: currently not optimized */ 368 tcg_gen_movi_tl(cpu_pc, pc); 369 tcg_gen_movi_tl(cpu_npc, npc); 370 tcg_gen_exit_tb(NULL, 0); 371 } 372 } 373 374 // XXX suboptimal 375 static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) 376 { 377 tcg_gen_extu_i32_tl(reg, src); 378 tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1); 379 } 380 381 static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) 382 { 383 tcg_gen_extu_i32_tl(reg, src); 384 tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1); 385 } 386 387 static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) 388 { 389 tcg_gen_extu_i32_tl(reg, src); 390 tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1); 391 } 392 393 static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) 394 { 395 tcg_gen_extu_i32_tl(reg, src); 396 tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1); 397 } 398 399 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) 400 { 401 tcg_gen_mov_tl(cpu_cc_src, src1); 402 tcg_gen_mov_tl(cpu_cc_src2, src2); 403 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); 404 tcg_gen_mov_tl(dst, cpu_cc_dst); 405 } 406 407 static TCGv_i32 gen_add32_carry32(void) 408 { 409 TCGv_i32 carry_32, cc_src1_32, cc_src2_32; 410 411 /* Carry is computed from a previous add: (dst < src) */ 412 #if TARGET_LONG_BITS == 64 413 cc_src1_32 = tcg_temp_new_i32(); 414 cc_src2_32 = tcg_temp_new_i32(); 415 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst); 416 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src); 417 #else 418 cc_src1_32 = cpu_cc_dst; 419 cc_src2_32 = cpu_cc_src; 420 #endif 421 422 carry_32 = tcg_temp_new_i32(); 423 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); 424 425 #if TARGET_LONG_BITS == 64 426 tcg_temp_free_i32(cc_src1_32); 427 tcg_temp_free_i32(cc_src2_32); 428 #endif 429 430 return carry_32; 431 } 432 433 static TCGv_i32 gen_sub32_carry32(void) 434 { 435 TCGv_i32 carry_32, cc_src1_32, cc_src2_32; 436 437 /* Carry is computed from a previous borrow: (src1 < src2) */ 438 #if TARGET_LONG_BITS == 64 439 cc_src1_32 = tcg_temp_new_i32(); 440 cc_src2_32 = tcg_temp_new_i32(); 441 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src); 442 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2); 443 #else 444 cc_src1_32 = cpu_cc_src; 445 cc_src2_32 = cpu_cc_src2; 446 #endif 447 448 carry_32 = tcg_temp_new_i32(); 449 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); 450 451 #if TARGET_LONG_BITS == 64 452 tcg_temp_free_i32(cc_src1_32); 453 tcg_temp_free_i32(cc_src2_32); 454 #endif 455 456 return carry_32; 457 } 458 459 static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1, 460 TCGv src2, int update_cc) 461 { 462 TCGv_i32 carry_32; 463 TCGv carry; 464 465 switch (dc->cc_op) { 466 case CC_OP_DIV: 467 case CC_OP_LOGIC: 468 /* Carry is known to be zero. Fall back to plain ADD. */ 469 if (update_cc) { 470 gen_op_add_cc(dst, src1, src2); 471 } else { 472 tcg_gen_add_tl(dst, src1, src2); 473 } 474 return; 475 476 case CC_OP_ADD: 477 case CC_OP_TADD: 478 case CC_OP_TADDTV: 479 if (TARGET_LONG_BITS == 32) { 480 /* We can re-use the host's hardware carry generation by using 481 an ADD2 opcode. We discard the low part of the output. 482 Ideally we'd combine this operation with the add that 483 generated the carry in the first place. */ 484 carry = tcg_temp_new(); 485 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2); 486 tcg_temp_free(carry); 487 goto add_done; 488 } 489 carry_32 = gen_add32_carry32(); 490 break; 491 492 case CC_OP_SUB: 493 case CC_OP_TSUB: 494 case CC_OP_TSUBTV: 495 carry_32 = gen_sub32_carry32(); 496 break; 497 498 default: 499 /* We need external help to produce the carry. */ 500 carry_32 = tcg_temp_new_i32(); 501 gen_helper_compute_C_icc(carry_32, cpu_env); 502 break; 503 } 504 505 #if TARGET_LONG_BITS == 64 506 carry = tcg_temp_new(); 507 tcg_gen_extu_i32_i64(carry, carry_32); 508 #else 509 carry = carry_32; 510 #endif 511 512 tcg_gen_add_tl(dst, src1, src2); 513 tcg_gen_add_tl(dst, dst, carry); 514 515 tcg_temp_free_i32(carry_32); 516 #if TARGET_LONG_BITS == 64 517 tcg_temp_free(carry); 518 #endif 519 520 add_done: 521 if (update_cc) { 522 tcg_gen_mov_tl(cpu_cc_src, src1); 523 tcg_gen_mov_tl(cpu_cc_src2, src2); 524 tcg_gen_mov_tl(cpu_cc_dst, dst); 525 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); 526 dc->cc_op = CC_OP_ADDX; 527 } 528 } 529 530 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) 531 { 532 tcg_gen_mov_tl(cpu_cc_src, src1); 533 tcg_gen_mov_tl(cpu_cc_src2, src2); 534 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); 535 tcg_gen_mov_tl(dst, cpu_cc_dst); 536 } 537 538 static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1, 539 TCGv src2, int update_cc) 540 { 541 TCGv_i32 carry_32; 542 TCGv carry; 543 544 switch (dc->cc_op) { 545 case CC_OP_DIV: 546 case CC_OP_LOGIC: 547 /* Carry is known to be zero. Fall back to plain SUB. */ 548 if (update_cc) { 549 gen_op_sub_cc(dst, src1, src2); 550 } else { 551 tcg_gen_sub_tl(dst, src1, src2); 552 } 553 return; 554 555 case CC_OP_ADD: 556 case CC_OP_TADD: 557 case CC_OP_TADDTV: 558 carry_32 = gen_add32_carry32(); 559 break; 560 561 case CC_OP_SUB: 562 case CC_OP_TSUB: 563 case CC_OP_TSUBTV: 564 if (TARGET_LONG_BITS == 32) { 565 /* We can re-use the host's hardware carry generation by using 566 a SUB2 opcode. We discard the low part of the output. 567 Ideally we'd combine this operation with the add that 568 generated the carry in the first place. */ 569 carry = tcg_temp_new(); 570 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2); 571 tcg_temp_free(carry); 572 goto sub_done; 573 } 574 carry_32 = gen_sub32_carry32(); 575 break; 576 577 default: 578 /* We need external help to produce the carry. */ 579 carry_32 = tcg_temp_new_i32(); 580 gen_helper_compute_C_icc(carry_32, cpu_env); 581 break; 582 } 583 584 #if TARGET_LONG_BITS == 64 585 carry = tcg_temp_new(); 586 tcg_gen_extu_i32_i64(carry, carry_32); 587 #else 588 carry = carry_32; 589 #endif 590 591 tcg_gen_sub_tl(dst, src1, src2); 592 tcg_gen_sub_tl(dst, dst, carry); 593 594 tcg_temp_free_i32(carry_32); 595 #if TARGET_LONG_BITS == 64 596 tcg_temp_free(carry); 597 #endif 598 599 sub_done: 600 if (update_cc) { 601 tcg_gen_mov_tl(cpu_cc_src, src1); 602 tcg_gen_mov_tl(cpu_cc_src2, src2); 603 tcg_gen_mov_tl(cpu_cc_dst, dst); 604 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); 605 dc->cc_op = CC_OP_SUBX; 606 } 607 } 608 609 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) 610 { 611 TCGv r_temp, zero, t0; 612 613 r_temp = tcg_temp_new(); 614 t0 = tcg_temp_new(); 615 616 /* old op: 617 if (!(env->y & 1)) 618 T1 = 0; 619 */ 620 zero = tcg_const_tl(0); 621 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff); 622 tcg_gen_andi_tl(r_temp, cpu_y, 0x1); 623 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff); 624 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero, 625 zero, cpu_cc_src2); 626 tcg_temp_free(zero); 627 628 // b2 = T0 & 1; 629 // env->y = (b2 << 31) | (env->y >> 1); 630 tcg_gen_extract_tl(t0, cpu_y, 1, 31); 631 tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1); 632 633 // b1 = N ^ V; 634 gen_mov_reg_N(t0, cpu_psr); 635 gen_mov_reg_V(r_temp, cpu_psr); 636 tcg_gen_xor_tl(t0, t0, r_temp); 637 tcg_temp_free(r_temp); 638 639 // T0 = (b1 << 31) | (T0 >> 1); 640 // src1 = T0; 641 tcg_gen_shli_tl(t0, t0, 31); 642 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); 643 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); 644 tcg_temp_free(t0); 645 646 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); 647 648 tcg_gen_mov_tl(dst, cpu_cc_dst); 649 } 650 651 static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext) 652 { 653 #if TARGET_LONG_BITS == 32 654 if (sign_ext) { 655 tcg_gen_muls2_tl(dst, cpu_y, src1, src2); 656 } else { 657 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2); 658 } 659 #else 660 TCGv t0 = tcg_temp_new_i64(); 661 TCGv t1 = tcg_temp_new_i64(); 662 663 if (sign_ext) { 664 tcg_gen_ext32s_i64(t0, src1); 665 tcg_gen_ext32s_i64(t1, src2); 666 } else { 667 tcg_gen_ext32u_i64(t0, src1); 668 tcg_gen_ext32u_i64(t1, src2); 669 } 670 671 tcg_gen_mul_i64(dst, t0, t1); 672 tcg_temp_free(t0); 673 tcg_temp_free(t1); 674 675 tcg_gen_shri_i64(cpu_y, dst, 32); 676 #endif 677 } 678 679 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) 680 { 681 /* zero-extend truncated operands before multiplication */ 682 gen_op_multiply(dst, src1, src2, 0); 683 } 684 685 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) 686 { 687 /* sign-extend truncated operands before multiplication */ 688 gen_op_multiply(dst, src1, src2, 1); 689 } 690 691 // 1 692 static inline void gen_op_eval_ba(TCGv dst) 693 { 694 tcg_gen_movi_tl(dst, 1); 695 } 696 697 // Z 698 static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src) 699 { 700 gen_mov_reg_Z(dst, src); 701 } 702 703 // Z | (N ^ V) 704 static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) 705 { 706 TCGv t0 = tcg_temp_new(); 707 gen_mov_reg_N(t0, src); 708 gen_mov_reg_V(dst, src); 709 tcg_gen_xor_tl(dst, dst, t0); 710 gen_mov_reg_Z(t0, src); 711 tcg_gen_or_tl(dst, dst, t0); 712 tcg_temp_free(t0); 713 } 714 715 // N ^ V 716 static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) 717 { 718 TCGv t0 = tcg_temp_new(); 719 gen_mov_reg_V(t0, src); 720 gen_mov_reg_N(dst, src); 721 tcg_gen_xor_tl(dst, dst, t0); 722 tcg_temp_free(t0); 723 } 724 725 // C | Z 726 static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) 727 { 728 TCGv t0 = tcg_temp_new(); 729 gen_mov_reg_Z(t0, src); 730 gen_mov_reg_C(dst, src); 731 tcg_gen_or_tl(dst, dst, t0); 732 tcg_temp_free(t0); 733 } 734 735 // C 736 static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) 737 { 738 gen_mov_reg_C(dst, src); 739 } 740 741 // V 742 static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) 743 { 744 gen_mov_reg_V(dst, src); 745 } 746 747 // 0 748 static inline void gen_op_eval_bn(TCGv dst) 749 { 750 tcg_gen_movi_tl(dst, 0); 751 } 752 753 // N 754 static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) 755 { 756 gen_mov_reg_N(dst, src); 757 } 758 759 // !Z 760 static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src) 761 { 762 gen_mov_reg_Z(dst, src); 763 tcg_gen_xori_tl(dst, dst, 0x1); 764 } 765 766 // !(Z | (N ^ V)) 767 static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src) 768 { 769 gen_op_eval_ble(dst, src); 770 tcg_gen_xori_tl(dst, dst, 0x1); 771 } 772 773 // !(N ^ V) 774 static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src) 775 { 776 gen_op_eval_bl(dst, src); 777 tcg_gen_xori_tl(dst, dst, 0x1); 778 } 779 780 // !(C | Z) 781 static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) 782 { 783 gen_op_eval_bleu(dst, src); 784 tcg_gen_xori_tl(dst, dst, 0x1); 785 } 786 787 // !C 788 static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) 789 { 790 gen_mov_reg_C(dst, src); 791 tcg_gen_xori_tl(dst, dst, 0x1); 792 } 793 794 // !N 795 static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) 796 { 797 gen_mov_reg_N(dst, src); 798 tcg_gen_xori_tl(dst, dst, 0x1); 799 } 800 801 // !V 802 static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) 803 { 804 gen_mov_reg_V(dst, src); 805 tcg_gen_xori_tl(dst, dst, 0x1); 806 } 807 808 /* 809 FPSR bit field FCC1 | FCC0: 810 0 = 811 1 < 812 2 > 813 3 unordered 814 */ 815 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, 816 unsigned int fcc_offset) 817 { 818 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); 819 tcg_gen_andi_tl(reg, reg, 0x1); 820 } 821 822 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, 823 unsigned int fcc_offset) 824 { 825 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); 826 tcg_gen_andi_tl(reg, reg, 0x1); 827 } 828 829 // !0: FCC0 | FCC1 830 static inline void gen_op_eval_fbne(TCGv dst, TCGv src, 831 unsigned int fcc_offset) 832 { 833 TCGv t0 = tcg_temp_new(); 834 gen_mov_reg_FCC0(dst, src, fcc_offset); 835 gen_mov_reg_FCC1(t0, src, fcc_offset); 836 tcg_gen_or_tl(dst, dst, t0); 837 tcg_temp_free(t0); 838 } 839 840 // 1 or 2: FCC0 ^ FCC1 841 static inline void gen_op_eval_fblg(TCGv dst, TCGv src, 842 unsigned int fcc_offset) 843 { 844 TCGv t0 = tcg_temp_new(); 845 gen_mov_reg_FCC0(dst, src, fcc_offset); 846 gen_mov_reg_FCC1(t0, src, fcc_offset); 847 tcg_gen_xor_tl(dst, dst, t0); 848 tcg_temp_free(t0); 849 } 850 851 // 1 or 3: FCC0 852 static inline void gen_op_eval_fbul(TCGv dst, TCGv src, 853 unsigned int fcc_offset) 854 { 855 gen_mov_reg_FCC0(dst, src, fcc_offset); 856 } 857 858 // 1: FCC0 & !FCC1 859 static inline void gen_op_eval_fbl(TCGv dst, TCGv src, 860 unsigned int fcc_offset) 861 { 862 TCGv t0 = tcg_temp_new(); 863 gen_mov_reg_FCC0(dst, src, fcc_offset); 864 gen_mov_reg_FCC1(t0, src, fcc_offset); 865 tcg_gen_andc_tl(dst, dst, t0); 866 tcg_temp_free(t0); 867 } 868 869 // 2 or 3: FCC1 870 static inline void gen_op_eval_fbug(TCGv dst, TCGv src, 871 unsigned int fcc_offset) 872 { 873 gen_mov_reg_FCC1(dst, src, fcc_offset); 874 } 875 876 // 2: !FCC0 & FCC1 877 static inline void gen_op_eval_fbg(TCGv dst, TCGv src, 878 unsigned int fcc_offset) 879 { 880 TCGv t0 = tcg_temp_new(); 881 gen_mov_reg_FCC0(dst, src, fcc_offset); 882 gen_mov_reg_FCC1(t0, src, fcc_offset); 883 tcg_gen_andc_tl(dst, t0, dst); 884 tcg_temp_free(t0); 885 } 886 887 // 3: FCC0 & FCC1 888 static inline void gen_op_eval_fbu(TCGv dst, TCGv src, 889 unsigned int fcc_offset) 890 { 891 TCGv t0 = tcg_temp_new(); 892 gen_mov_reg_FCC0(dst, src, fcc_offset); 893 gen_mov_reg_FCC1(t0, src, fcc_offset); 894 tcg_gen_and_tl(dst, dst, t0); 895 tcg_temp_free(t0); 896 } 897 898 // 0: !(FCC0 | FCC1) 899 static inline void gen_op_eval_fbe(TCGv dst, TCGv src, 900 unsigned int fcc_offset) 901 { 902 TCGv t0 = tcg_temp_new(); 903 gen_mov_reg_FCC0(dst, src, fcc_offset); 904 gen_mov_reg_FCC1(t0, src, fcc_offset); 905 tcg_gen_or_tl(dst, dst, t0); 906 tcg_gen_xori_tl(dst, dst, 0x1); 907 tcg_temp_free(t0); 908 } 909 910 // 0 or 3: !(FCC0 ^ FCC1) 911 static inline void gen_op_eval_fbue(TCGv dst, TCGv src, 912 unsigned int fcc_offset) 913 { 914 TCGv t0 = tcg_temp_new(); 915 gen_mov_reg_FCC0(dst, src, fcc_offset); 916 gen_mov_reg_FCC1(t0, src, fcc_offset); 917 tcg_gen_xor_tl(dst, dst, t0); 918 tcg_gen_xori_tl(dst, dst, 0x1); 919 tcg_temp_free(t0); 920 } 921 922 // 0 or 2: !FCC0 923 static inline void gen_op_eval_fbge(TCGv dst, TCGv src, 924 unsigned int fcc_offset) 925 { 926 gen_mov_reg_FCC0(dst, src, fcc_offset); 927 tcg_gen_xori_tl(dst, dst, 0x1); 928 } 929 930 // !1: !(FCC0 & !FCC1) 931 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, 932 unsigned int fcc_offset) 933 { 934 TCGv t0 = tcg_temp_new(); 935 gen_mov_reg_FCC0(dst, src, fcc_offset); 936 gen_mov_reg_FCC1(t0, src, fcc_offset); 937 tcg_gen_andc_tl(dst, dst, t0); 938 tcg_gen_xori_tl(dst, dst, 0x1); 939 tcg_temp_free(t0); 940 } 941 942 // 0 or 1: !FCC1 943 static inline void gen_op_eval_fble(TCGv dst, TCGv src, 944 unsigned int fcc_offset) 945 { 946 gen_mov_reg_FCC1(dst, src, fcc_offset); 947 tcg_gen_xori_tl(dst, dst, 0x1); 948 } 949 950 // !2: !(!FCC0 & FCC1) 951 static inline void gen_op_eval_fbule(TCGv dst, TCGv src, 952 unsigned int fcc_offset) 953 { 954 TCGv t0 = tcg_temp_new(); 955 gen_mov_reg_FCC0(dst, src, fcc_offset); 956 gen_mov_reg_FCC1(t0, src, fcc_offset); 957 tcg_gen_andc_tl(dst, t0, dst); 958 tcg_gen_xori_tl(dst, dst, 0x1); 959 tcg_temp_free(t0); 960 } 961 962 // !3: !(FCC0 & FCC1) 963 static inline void gen_op_eval_fbo(TCGv dst, TCGv src, 964 unsigned int fcc_offset) 965 { 966 TCGv t0 = tcg_temp_new(); 967 gen_mov_reg_FCC0(dst, src, fcc_offset); 968 gen_mov_reg_FCC1(t0, src, fcc_offset); 969 tcg_gen_and_tl(dst, dst, t0); 970 tcg_gen_xori_tl(dst, dst, 0x1); 971 tcg_temp_free(t0); 972 } 973 974 static inline void gen_branch2(DisasContext *dc, target_ulong pc1, 975 target_ulong pc2, TCGv r_cond) 976 { 977 TCGLabel *l1 = gen_new_label(); 978 979 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); 980 981 gen_goto_tb(dc, 0, pc1, pc1 + 4); 982 983 gen_set_label(l1); 984 gen_goto_tb(dc, 1, pc2, pc2 + 4); 985 } 986 987 static void gen_branch_a(DisasContext *dc, target_ulong pc1) 988 { 989 TCGLabel *l1 = gen_new_label(); 990 target_ulong npc = dc->npc; 991 992 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1); 993 994 gen_goto_tb(dc, 0, npc, pc1); 995 996 gen_set_label(l1); 997 gen_goto_tb(dc, 1, npc + 4, npc + 8); 998 999 dc->base.is_jmp = DISAS_NORETURN; 1000 } 1001 1002 static void gen_branch_n(DisasContext *dc, target_ulong pc1) 1003 { 1004 target_ulong npc = dc->npc; 1005 1006 if (likely(npc != DYNAMIC_PC)) { 1007 dc->pc = npc; 1008 dc->jump_pc[0] = pc1; 1009 dc->jump_pc[1] = npc + 4; 1010 dc->npc = JUMP_PC; 1011 } else { 1012 TCGv t, z; 1013 1014 tcg_gen_mov_tl(cpu_pc, cpu_npc); 1015 1016 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); 1017 t = tcg_const_tl(pc1); 1018 z = tcg_const_tl(0); 1019 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc); 1020 tcg_temp_free(t); 1021 tcg_temp_free(z); 1022 1023 dc->pc = DYNAMIC_PC; 1024 } 1025 } 1026 1027 static inline void gen_generic_branch(DisasContext *dc) 1028 { 1029 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]); 1030 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]); 1031 TCGv zero = tcg_const_tl(0); 1032 1033 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1); 1034 1035 tcg_temp_free(npc0); 1036 tcg_temp_free(npc1); 1037 tcg_temp_free(zero); 1038 } 1039 1040 /* call this function before using the condition register as it may 1041 have been set for a jump */ 1042 static inline void flush_cond(DisasContext *dc) 1043 { 1044 if (dc->npc == JUMP_PC) { 1045 gen_generic_branch(dc); 1046 dc->npc = DYNAMIC_PC; 1047 } 1048 } 1049 1050 static inline void save_npc(DisasContext *dc) 1051 { 1052 if (dc->npc == JUMP_PC) { 1053 gen_generic_branch(dc); 1054 dc->npc = DYNAMIC_PC; 1055 } else if (dc->npc != DYNAMIC_PC) { 1056 tcg_gen_movi_tl(cpu_npc, dc->npc); 1057 } 1058 } 1059 1060 static inline void update_psr(DisasContext *dc) 1061 { 1062 if (dc->cc_op != CC_OP_FLAGS) { 1063 dc->cc_op = CC_OP_FLAGS; 1064 gen_helper_compute_psr(cpu_env); 1065 } 1066 } 1067 1068 static inline void save_state(DisasContext *dc) 1069 { 1070 tcg_gen_movi_tl(cpu_pc, dc->pc); 1071 save_npc(dc); 1072 } 1073 1074 static void gen_exception(DisasContext *dc, int which) 1075 { 1076 TCGv_i32 t; 1077 1078 save_state(dc); 1079 t = tcg_const_i32(which); 1080 gen_helper_raise_exception(cpu_env, t); 1081 tcg_temp_free_i32(t); 1082 dc->base.is_jmp = DISAS_NORETURN; 1083 } 1084 1085 static void gen_check_align(TCGv addr, int mask) 1086 { 1087 TCGv_i32 r_mask = tcg_const_i32(mask); 1088 gen_helper_check_align(cpu_env, addr, r_mask); 1089 tcg_temp_free_i32(r_mask); 1090 } 1091 1092 static inline void gen_mov_pc_npc(DisasContext *dc) 1093 { 1094 if (dc->npc == JUMP_PC) { 1095 gen_generic_branch(dc); 1096 tcg_gen_mov_tl(cpu_pc, cpu_npc); 1097 dc->pc = DYNAMIC_PC; 1098 } else if (dc->npc == DYNAMIC_PC) { 1099 tcg_gen_mov_tl(cpu_pc, cpu_npc); 1100 dc->pc = DYNAMIC_PC; 1101 } else { 1102 dc->pc = dc->npc; 1103 } 1104 } 1105 1106 static inline void gen_op_next_insn(void) 1107 { 1108 tcg_gen_mov_tl(cpu_pc, cpu_npc); 1109 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); 1110 } 1111 1112 static void free_compare(DisasCompare *cmp) 1113 { 1114 if (!cmp->g1) { 1115 tcg_temp_free(cmp->c1); 1116 } 1117 if (!cmp->g2) { 1118 tcg_temp_free(cmp->c2); 1119 } 1120 } 1121 1122 static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, 1123 DisasContext *dc) 1124 { 1125 static int subcc_cond[16] = { 1126 TCG_COND_NEVER, 1127 TCG_COND_EQ, 1128 TCG_COND_LE, 1129 TCG_COND_LT, 1130 TCG_COND_LEU, 1131 TCG_COND_LTU, 1132 -1, /* neg */ 1133 -1, /* overflow */ 1134 TCG_COND_ALWAYS, 1135 TCG_COND_NE, 1136 TCG_COND_GT, 1137 TCG_COND_GE, 1138 TCG_COND_GTU, 1139 TCG_COND_GEU, 1140 -1, /* pos */ 1141 -1, /* no overflow */ 1142 }; 1143 1144 static int logic_cond[16] = { 1145 TCG_COND_NEVER, 1146 TCG_COND_EQ, /* eq: Z */ 1147 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */ 1148 TCG_COND_LT, /* lt: N ^ V -> N */ 1149 TCG_COND_EQ, /* leu: C | Z -> Z */ 1150 TCG_COND_NEVER, /* ltu: C -> 0 */ 1151 TCG_COND_LT, /* neg: N */ 1152 TCG_COND_NEVER, /* vs: V -> 0 */ 1153 TCG_COND_ALWAYS, 1154 TCG_COND_NE, /* ne: !Z */ 1155 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */ 1156 TCG_COND_GE, /* ge: !(N ^ V) -> !N */ 1157 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */ 1158 TCG_COND_ALWAYS, /* geu: !C -> 1 */ 1159 TCG_COND_GE, /* pos: !N */ 1160 TCG_COND_ALWAYS, /* vc: !V -> 1 */ 1161 }; 1162 1163 TCGv_i32 r_src; 1164 TCGv r_dst; 1165 1166 #ifdef TARGET_SPARC64 1167 if (xcc) { 1168 r_src = cpu_xcc; 1169 } else { 1170 r_src = cpu_psr; 1171 } 1172 #else 1173 r_src = cpu_psr; 1174 #endif 1175 1176 switch (dc->cc_op) { 1177 case CC_OP_LOGIC: 1178 cmp->cond = logic_cond[cond]; 1179 do_compare_dst_0: 1180 cmp->is_bool = false; 1181 cmp->g2 = false; 1182 cmp->c2 = tcg_const_tl(0); 1183 #ifdef TARGET_SPARC64 1184 if (!xcc) { 1185 cmp->g1 = false; 1186 cmp->c1 = tcg_temp_new(); 1187 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst); 1188 break; 1189 } 1190 #endif 1191 cmp->g1 = true; 1192 cmp->c1 = cpu_cc_dst; 1193 break; 1194 1195 case CC_OP_SUB: 1196 switch (cond) { 1197 case 6: /* neg */ 1198 case 14: /* pos */ 1199 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE); 1200 goto do_compare_dst_0; 1201 1202 case 7: /* overflow */ 1203 case 15: /* !overflow */ 1204 goto do_dynamic; 1205 1206 default: 1207 cmp->cond = subcc_cond[cond]; 1208 cmp->is_bool = false; 1209 #ifdef TARGET_SPARC64 1210 if (!xcc) { 1211 /* Note that sign-extension works for unsigned compares as 1212 long as both operands are sign-extended. */ 1213 cmp->g1 = cmp->g2 = false; 1214 cmp->c1 = tcg_temp_new(); 1215 cmp->c2 = tcg_temp_new(); 1216 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src); 1217 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2); 1218 break; 1219 } 1220 #endif 1221 cmp->g1 = cmp->g2 = true; 1222 cmp->c1 = cpu_cc_src; 1223 cmp->c2 = cpu_cc_src2; 1224 break; 1225 } 1226 break; 1227 1228 default: 1229 do_dynamic: 1230 gen_helper_compute_psr(cpu_env); 1231 dc->cc_op = CC_OP_FLAGS; 1232 /* FALLTHRU */ 1233 1234 case CC_OP_FLAGS: 1235 /* We're going to generate a boolean result. */ 1236 cmp->cond = TCG_COND_NE; 1237 cmp->is_bool = true; 1238 cmp->g1 = cmp->g2 = false; 1239 cmp->c1 = r_dst = tcg_temp_new(); 1240 cmp->c2 = tcg_const_tl(0); 1241 1242 switch (cond) { 1243 case 0x0: 1244 gen_op_eval_bn(r_dst); 1245 break; 1246 case 0x1: 1247 gen_op_eval_be(r_dst, r_src); 1248 break; 1249 case 0x2: 1250 gen_op_eval_ble(r_dst, r_src); 1251 break; 1252 case 0x3: 1253 gen_op_eval_bl(r_dst, r_src); 1254 break; 1255 case 0x4: 1256 gen_op_eval_bleu(r_dst, r_src); 1257 break; 1258 case 0x5: 1259 gen_op_eval_bcs(r_dst, r_src); 1260 break; 1261 case 0x6: 1262 gen_op_eval_bneg(r_dst, r_src); 1263 break; 1264 case 0x7: 1265 gen_op_eval_bvs(r_dst, r_src); 1266 break; 1267 case 0x8: 1268 gen_op_eval_ba(r_dst); 1269 break; 1270 case 0x9: 1271 gen_op_eval_bne(r_dst, r_src); 1272 break; 1273 case 0xa: 1274 gen_op_eval_bg(r_dst, r_src); 1275 break; 1276 case 0xb: 1277 gen_op_eval_bge(r_dst, r_src); 1278 break; 1279 case 0xc: 1280 gen_op_eval_bgu(r_dst, r_src); 1281 break; 1282 case 0xd: 1283 gen_op_eval_bcc(r_dst, r_src); 1284 break; 1285 case 0xe: 1286 gen_op_eval_bpos(r_dst, r_src); 1287 break; 1288 case 0xf: 1289 gen_op_eval_bvc(r_dst, r_src); 1290 break; 1291 } 1292 break; 1293 } 1294 } 1295 1296 static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond) 1297 { 1298 unsigned int offset; 1299 TCGv r_dst; 1300 1301 /* For now we still generate a straight boolean result. */ 1302 cmp->cond = TCG_COND_NE; 1303 cmp->is_bool = true; 1304 cmp->g1 = cmp->g2 = false; 1305 cmp->c1 = r_dst = tcg_temp_new(); 1306 cmp->c2 = tcg_const_tl(0); 1307 1308 switch (cc) { 1309 default: 1310 case 0x0: 1311 offset = 0; 1312 break; 1313 case 0x1: 1314 offset = 32 - 10; 1315 break; 1316 case 0x2: 1317 offset = 34 - 10; 1318 break; 1319 case 0x3: 1320 offset = 36 - 10; 1321 break; 1322 } 1323 1324 switch (cond) { 1325 case 0x0: 1326 gen_op_eval_bn(r_dst); 1327 break; 1328 case 0x1: 1329 gen_op_eval_fbne(r_dst, cpu_fsr, offset); 1330 break; 1331 case 0x2: 1332 gen_op_eval_fblg(r_dst, cpu_fsr, offset); 1333 break; 1334 case 0x3: 1335 gen_op_eval_fbul(r_dst, cpu_fsr, offset); 1336 break; 1337 case 0x4: 1338 gen_op_eval_fbl(r_dst, cpu_fsr, offset); 1339 break; 1340 case 0x5: 1341 gen_op_eval_fbug(r_dst, cpu_fsr, offset); 1342 break; 1343 case 0x6: 1344 gen_op_eval_fbg(r_dst, cpu_fsr, offset); 1345 break; 1346 case 0x7: 1347 gen_op_eval_fbu(r_dst, cpu_fsr, offset); 1348 break; 1349 case 0x8: 1350 gen_op_eval_ba(r_dst); 1351 break; 1352 case 0x9: 1353 gen_op_eval_fbe(r_dst, cpu_fsr, offset); 1354 break; 1355 case 0xa: 1356 gen_op_eval_fbue(r_dst, cpu_fsr, offset); 1357 break; 1358 case 0xb: 1359 gen_op_eval_fbge(r_dst, cpu_fsr, offset); 1360 break; 1361 case 0xc: 1362 gen_op_eval_fbuge(r_dst, cpu_fsr, offset); 1363 break; 1364 case 0xd: 1365 gen_op_eval_fble(r_dst, cpu_fsr, offset); 1366 break; 1367 case 0xe: 1368 gen_op_eval_fbule(r_dst, cpu_fsr, offset); 1369 break; 1370 case 0xf: 1371 gen_op_eval_fbo(r_dst, cpu_fsr, offset); 1372 break; 1373 } 1374 } 1375 1376 static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, 1377 DisasContext *dc) 1378 { 1379 DisasCompare cmp; 1380 gen_compare(&cmp, cc, cond, dc); 1381 1382 /* The interface is to return a boolean in r_dst. */ 1383 if (cmp.is_bool) { 1384 tcg_gen_mov_tl(r_dst, cmp.c1); 1385 } else { 1386 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); 1387 } 1388 1389 free_compare(&cmp); 1390 } 1391 1392 static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) 1393 { 1394 DisasCompare cmp; 1395 gen_fcompare(&cmp, cc, cond); 1396 1397 /* The interface is to return a boolean in r_dst. */ 1398 if (cmp.is_bool) { 1399 tcg_gen_mov_tl(r_dst, cmp.c1); 1400 } else { 1401 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); 1402 } 1403 1404 free_compare(&cmp); 1405 } 1406 1407 #ifdef TARGET_SPARC64 1408 // Inverted logic 1409 static const int gen_tcg_cond_reg[8] = { 1410 -1, 1411 TCG_COND_NE, 1412 TCG_COND_GT, 1413 TCG_COND_GE, 1414 -1, 1415 TCG_COND_EQ, 1416 TCG_COND_LE, 1417 TCG_COND_LT, 1418 }; 1419 1420 static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) 1421 { 1422 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]); 1423 cmp->is_bool = false; 1424 cmp->g1 = true; 1425 cmp->g2 = false; 1426 cmp->c1 = r_src; 1427 cmp->c2 = tcg_const_tl(0); 1428 } 1429 1430 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) 1431 { 1432 DisasCompare cmp; 1433 gen_compare_reg(&cmp, cond, r_src); 1434 1435 /* The interface is to return a boolean in r_dst. */ 1436 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); 1437 1438 free_compare(&cmp); 1439 } 1440 #endif 1441 1442 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) 1443 { 1444 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); 1445 target_ulong target = dc->pc + offset; 1446 1447 #ifdef TARGET_SPARC64 1448 if (unlikely(AM_CHECK(dc))) { 1449 target &= 0xffffffffULL; 1450 } 1451 #endif 1452 if (cond == 0x0) { 1453 /* unconditional not taken */ 1454 if (a) { 1455 dc->pc = dc->npc + 4; 1456 dc->npc = dc->pc + 4; 1457 } else { 1458 dc->pc = dc->npc; 1459 dc->npc = dc->pc + 4; 1460 } 1461 } else if (cond == 0x8) { 1462 /* unconditional taken */ 1463 if (a) { 1464 dc->pc = target; 1465 dc->npc = dc->pc + 4; 1466 } else { 1467 dc->pc = dc->npc; 1468 dc->npc = target; 1469 tcg_gen_mov_tl(cpu_pc, cpu_npc); 1470 } 1471 } else { 1472 flush_cond(dc); 1473 gen_cond(cpu_cond, cc, cond, dc); 1474 if (a) { 1475 gen_branch_a(dc, target); 1476 } else { 1477 gen_branch_n(dc, target); 1478 } 1479 } 1480 } 1481 1482 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) 1483 { 1484 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); 1485 target_ulong target = dc->pc + offset; 1486 1487 #ifdef TARGET_SPARC64 1488 if (unlikely(AM_CHECK(dc))) { 1489 target &= 0xffffffffULL; 1490 } 1491 #endif 1492 if (cond == 0x0) { 1493 /* unconditional not taken */ 1494 if (a) { 1495 dc->pc = dc->npc + 4; 1496 dc->npc = dc->pc + 4; 1497 } else { 1498 dc->pc = dc->npc; 1499 dc->npc = dc->pc + 4; 1500 } 1501 } else if (cond == 0x8) { 1502 /* unconditional taken */ 1503 if (a) { 1504 dc->pc = target; 1505 dc->npc = dc->pc + 4; 1506 } else { 1507 dc->pc = dc->npc; 1508 dc->npc = target; 1509 tcg_gen_mov_tl(cpu_pc, cpu_npc); 1510 } 1511 } else { 1512 flush_cond(dc); 1513 gen_fcond(cpu_cond, cc, cond); 1514 if (a) { 1515 gen_branch_a(dc, target); 1516 } else { 1517 gen_branch_n(dc, target); 1518 } 1519 } 1520 } 1521 1522 #ifdef TARGET_SPARC64 1523 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, 1524 TCGv r_reg) 1525 { 1526 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); 1527 target_ulong target = dc->pc + offset; 1528 1529 if (unlikely(AM_CHECK(dc))) { 1530 target &= 0xffffffffULL; 1531 } 1532 flush_cond(dc); 1533 gen_cond_reg(cpu_cond, cond, r_reg); 1534 if (a) { 1535 gen_branch_a(dc, target); 1536 } else { 1537 gen_branch_n(dc, target); 1538 } 1539 } 1540 1541 static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) 1542 { 1543 switch (fccno) { 1544 case 0: 1545 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2); 1546 break; 1547 case 1: 1548 gen_helper_fcmps_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2); 1549 break; 1550 case 2: 1551 gen_helper_fcmps_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2); 1552 break; 1553 case 3: 1554 gen_helper_fcmps_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2); 1555 break; 1556 } 1557 } 1558 1559 static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) 1560 { 1561 switch (fccno) { 1562 case 0: 1563 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2); 1564 break; 1565 case 1: 1566 gen_helper_fcmpd_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2); 1567 break; 1568 case 2: 1569 gen_helper_fcmpd_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2); 1570 break; 1571 case 3: 1572 gen_helper_fcmpd_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2); 1573 break; 1574 } 1575 } 1576 1577 static inline void gen_op_fcmpq(int fccno) 1578 { 1579 switch (fccno) { 1580 case 0: 1581 gen_helper_fcmpq(cpu_fsr, cpu_env); 1582 break; 1583 case 1: 1584 gen_helper_fcmpq_fcc1(cpu_fsr, cpu_env); 1585 break; 1586 case 2: 1587 gen_helper_fcmpq_fcc2(cpu_fsr, cpu_env); 1588 break; 1589 case 3: 1590 gen_helper_fcmpq_fcc3(cpu_fsr, cpu_env); 1591 break; 1592 } 1593 } 1594 1595 static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) 1596 { 1597 switch (fccno) { 1598 case 0: 1599 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2); 1600 break; 1601 case 1: 1602 gen_helper_fcmpes_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2); 1603 break; 1604 case 2: 1605 gen_helper_fcmpes_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2); 1606 break; 1607 case 3: 1608 gen_helper_fcmpes_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2); 1609 break; 1610 } 1611 } 1612 1613 static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) 1614 { 1615 switch (fccno) { 1616 case 0: 1617 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2); 1618 break; 1619 case 1: 1620 gen_helper_fcmped_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2); 1621 break; 1622 case 2: 1623 gen_helper_fcmped_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2); 1624 break; 1625 case 3: 1626 gen_helper_fcmped_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2); 1627 break; 1628 } 1629 } 1630 1631 static inline void gen_op_fcmpeq(int fccno) 1632 { 1633 switch (fccno) { 1634 case 0: 1635 gen_helper_fcmpeq(cpu_fsr, cpu_env); 1636 break; 1637 case 1: 1638 gen_helper_fcmpeq_fcc1(cpu_fsr, cpu_env); 1639 break; 1640 case 2: 1641 gen_helper_fcmpeq_fcc2(cpu_fsr, cpu_env); 1642 break; 1643 case 3: 1644 gen_helper_fcmpeq_fcc3(cpu_fsr, cpu_env); 1645 break; 1646 } 1647 } 1648 1649 #else 1650 1651 static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) 1652 { 1653 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2); 1654 } 1655 1656 static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) 1657 { 1658 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2); 1659 } 1660 1661 static inline void gen_op_fcmpq(int fccno) 1662 { 1663 gen_helper_fcmpq(cpu_fsr, cpu_env); 1664 } 1665 1666 static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) 1667 { 1668 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2); 1669 } 1670 1671 static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) 1672 { 1673 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2); 1674 } 1675 1676 static inline void gen_op_fcmpeq(int fccno) 1677 { 1678 gen_helper_fcmpeq(cpu_fsr, cpu_env); 1679 } 1680 #endif 1681 1682 static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags) 1683 { 1684 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); 1685 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); 1686 gen_exception(dc, TT_FP_EXCP); 1687 } 1688 1689 static int gen_trap_ifnofpu(DisasContext *dc) 1690 { 1691 #if !defined(CONFIG_USER_ONLY) 1692 if (!dc->fpu_enabled) { 1693 gen_exception(dc, TT_NFPU_INSN); 1694 return 1; 1695 } 1696 #endif 1697 return 0; 1698 } 1699 1700 static inline void gen_op_clear_ieee_excp_and_FTT(void) 1701 { 1702 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); 1703 } 1704 1705 static inline void gen_fop_FF(DisasContext *dc, int rd, int rs, 1706 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32)) 1707 { 1708 TCGv_i32 dst, src; 1709 1710 src = gen_load_fpr_F(dc, rs); 1711 dst = gen_dest_fpr_F(dc); 1712 1713 gen(dst, cpu_env, src); 1714 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1715 1716 gen_store_fpr_F(dc, rd, dst); 1717 } 1718 1719 static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs, 1720 void (*gen)(TCGv_i32, TCGv_i32)) 1721 { 1722 TCGv_i32 dst, src; 1723 1724 src = gen_load_fpr_F(dc, rs); 1725 dst = gen_dest_fpr_F(dc); 1726 1727 gen(dst, src); 1728 1729 gen_store_fpr_F(dc, rd, dst); 1730 } 1731 1732 static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, 1733 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32)) 1734 { 1735 TCGv_i32 dst, src1, src2; 1736 1737 src1 = gen_load_fpr_F(dc, rs1); 1738 src2 = gen_load_fpr_F(dc, rs2); 1739 dst = gen_dest_fpr_F(dc); 1740 1741 gen(dst, cpu_env, src1, src2); 1742 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1743 1744 gen_store_fpr_F(dc, rd, dst); 1745 } 1746 1747 #ifdef TARGET_SPARC64 1748 static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, 1749 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) 1750 { 1751 TCGv_i32 dst, src1, src2; 1752 1753 src1 = gen_load_fpr_F(dc, rs1); 1754 src2 = gen_load_fpr_F(dc, rs2); 1755 dst = gen_dest_fpr_F(dc); 1756 1757 gen(dst, src1, src2); 1758 1759 gen_store_fpr_F(dc, rd, dst); 1760 } 1761 #endif 1762 1763 static inline void gen_fop_DD(DisasContext *dc, int rd, int rs, 1764 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64)) 1765 { 1766 TCGv_i64 dst, src; 1767 1768 src = gen_load_fpr_D(dc, rs); 1769 dst = gen_dest_fpr_D(dc, rd); 1770 1771 gen(dst, cpu_env, src); 1772 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1773 1774 gen_store_fpr_D(dc, rd, dst); 1775 } 1776 1777 #ifdef TARGET_SPARC64 1778 static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs, 1779 void (*gen)(TCGv_i64, TCGv_i64)) 1780 { 1781 TCGv_i64 dst, src; 1782 1783 src = gen_load_fpr_D(dc, rs); 1784 dst = gen_dest_fpr_D(dc, rd); 1785 1786 gen(dst, src); 1787 1788 gen_store_fpr_D(dc, rd, dst); 1789 } 1790 #endif 1791 1792 static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, 1793 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64)) 1794 { 1795 TCGv_i64 dst, src1, src2; 1796 1797 src1 = gen_load_fpr_D(dc, rs1); 1798 src2 = gen_load_fpr_D(dc, rs2); 1799 dst = gen_dest_fpr_D(dc, rd); 1800 1801 gen(dst, cpu_env, src1, src2); 1802 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1803 1804 gen_store_fpr_D(dc, rd, dst); 1805 } 1806 1807 #ifdef TARGET_SPARC64 1808 static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, 1809 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) 1810 { 1811 TCGv_i64 dst, src1, src2; 1812 1813 src1 = gen_load_fpr_D(dc, rs1); 1814 src2 = gen_load_fpr_D(dc, rs2); 1815 dst = gen_dest_fpr_D(dc, rd); 1816 1817 gen(dst, src1, src2); 1818 1819 gen_store_fpr_D(dc, rd, dst); 1820 } 1821 1822 static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, 1823 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) 1824 { 1825 TCGv_i64 dst, src1, src2; 1826 1827 src1 = gen_load_fpr_D(dc, rs1); 1828 src2 = gen_load_fpr_D(dc, rs2); 1829 dst = gen_dest_fpr_D(dc, rd); 1830 1831 gen(dst, cpu_gsr, src1, src2); 1832 1833 gen_store_fpr_D(dc, rd, dst); 1834 } 1835 1836 static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, 1837 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) 1838 { 1839 TCGv_i64 dst, src0, src1, src2; 1840 1841 src1 = gen_load_fpr_D(dc, rs1); 1842 src2 = gen_load_fpr_D(dc, rs2); 1843 src0 = gen_load_fpr_D(dc, rd); 1844 dst = gen_dest_fpr_D(dc, rd); 1845 1846 gen(dst, src0, src1, src2); 1847 1848 gen_store_fpr_D(dc, rd, dst); 1849 } 1850 #endif 1851 1852 static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs, 1853 void (*gen)(TCGv_ptr)) 1854 { 1855 gen_op_load_fpr_QT1(QFPREG(rs)); 1856 1857 gen(cpu_env); 1858 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1859 1860 gen_op_store_QT0_fpr(QFPREG(rd)); 1861 gen_update_fprs_dirty(dc, QFPREG(rd)); 1862 } 1863 1864 #ifdef TARGET_SPARC64 1865 static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, 1866 void (*gen)(TCGv_ptr)) 1867 { 1868 gen_op_load_fpr_QT1(QFPREG(rs)); 1869 1870 gen(cpu_env); 1871 1872 gen_op_store_QT0_fpr(QFPREG(rd)); 1873 gen_update_fprs_dirty(dc, QFPREG(rd)); 1874 } 1875 #endif 1876 1877 static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, 1878 void (*gen)(TCGv_ptr)) 1879 { 1880 gen_op_load_fpr_QT0(QFPREG(rs1)); 1881 gen_op_load_fpr_QT1(QFPREG(rs2)); 1882 1883 gen(cpu_env); 1884 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1885 1886 gen_op_store_QT0_fpr(QFPREG(rd)); 1887 gen_update_fprs_dirty(dc, QFPREG(rd)); 1888 } 1889 1890 static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, 1891 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32)) 1892 { 1893 TCGv_i64 dst; 1894 TCGv_i32 src1, src2; 1895 1896 src1 = gen_load_fpr_F(dc, rs1); 1897 src2 = gen_load_fpr_F(dc, rs2); 1898 dst = gen_dest_fpr_D(dc, rd); 1899 1900 gen(dst, cpu_env, src1, src2); 1901 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1902 1903 gen_store_fpr_D(dc, rd, dst); 1904 } 1905 1906 static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, 1907 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64)) 1908 { 1909 TCGv_i64 src1, src2; 1910 1911 src1 = gen_load_fpr_D(dc, rs1); 1912 src2 = gen_load_fpr_D(dc, rs2); 1913 1914 gen(cpu_env, src1, src2); 1915 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1916 1917 gen_op_store_QT0_fpr(QFPREG(rd)); 1918 gen_update_fprs_dirty(dc, QFPREG(rd)); 1919 } 1920 1921 #ifdef TARGET_SPARC64 1922 static inline void gen_fop_DF(DisasContext *dc, int rd, int rs, 1923 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) 1924 { 1925 TCGv_i64 dst; 1926 TCGv_i32 src; 1927 1928 src = gen_load_fpr_F(dc, rs); 1929 dst = gen_dest_fpr_D(dc, rd); 1930 1931 gen(dst, cpu_env, src); 1932 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1933 1934 gen_store_fpr_D(dc, rd, dst); 1935 } 1936 #endif 1937 1938 static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs, 1939 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) 1940 { 1941 TCGv_i64 dst; 1942 TCGv_i32 src; 1943 1944 src = gen_load_fpr_F(dc, rs); 1945 dst = gen_dest_fpr_D(dc, rd); 1946 1947 gen(dst, cpu_env, src); 1948 1949 gen_store_fpr_D(dc, rd, dst); 1950 } 1951 1952 static inline void gen_fop_FD(DisasContext *dc, int rd, int rs, 1953 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64)) 1954 { 1955 TCGv_i32 dst; 1956 TCGv_i64 src; 1957 1958 src = gen_load_fpr_D(dc, rs); 1959 dst = gen_dest_fpr_F(dc); 1960 1961 gen(dst, cpu_env, src); 1962 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1963 1964 gen_store_fpr_F(dc, rd, dst); 1965 } 1966 1967 static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs, 1968 void (*gen)(TCGv_i32, TCGv_ptr)) 1969 { 1970 TCGv_i32 dst; 1971 1972 gen_op_load_fpr_QT1(QFPREG(rs)); 1973 dst = gen_dest_fpr_F(dc); 1974 1975 gen(dst, cpu_env); 1976 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1977 1978 gen_store_fpr_F(dc, rd, dst); 1979 } 1980 1981 static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs, 1982 void (*gen)(TCGv_i64, TCGv_ptr)) 1983 { 1984 TCGv_i64 dst; 1985 1986 gen_op_load_fpr_QT1(QFPREG(rs)); 1987 dst = gen_dest_fpr_D(dc, rd); 1988 1989 gen(dst, cpu_env); 1990 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); 1991 1992 gen_store_fpr_D(dc, rd, dst); 1993 } 1994 1995 static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, 1996 void (*gen)(TCGv_ptr, TCGv_i32)) 1997 { 1998 TCGv_i32 src; 1999 2000 src = gen_load_fpr_F(dc, rs); 2001 2002 gen(cpu_env, src); 2003 2004 gen_op_store_QT0_fpr(QFPREG(rd)); 2005 gen_update_fprs_dirty(dc, QFPREG(rd)); 2006 } 2007 2008 static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, 2009 void (*gen)(TCGv_ptr, TCGv_i64)) 2010 { 2011 TCGv_i64 src; 2012 2013 src = gen_load_fpr_D(dc, rs); 2014 2015 gen(cpu_env, src); 2016 2017 gen_op_store_QT0_fpr(QFPREG(rd)); 2018 gen_update_fprs_dirty(dc, QFPREG(rd)); 2019 } 2020 2021 static void gen_swap(DisasContext *dc, TCGv dst, TCGv src, 2022 TCGv addr, int mmu_idx, MemOp memop) 2023 { 2024 gen_address_mask(dc, addr); 2025 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop); 2026 } 2027 2028 static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) 2029 { 2030 TCGv m1 = tcg_const_tl(0xff); 2031 gen_address_mask(dc, addr); 2032 tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB); 2033 tcg_temp_free(m1); 2034 } 2035 2036 /* asi moves */ 2037 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 2038 typedef enum { 2039 GET_ASI_HELPER, 2040 GET_ASI_EXCP, 2041 GET_ASI_DIRECT, 2042 GET_ASI_DTWINX, 2043 GET_ASI_BLOCK, 2044 GET_ASI_SHORT, 2045 GET_ASI_BCOPY, 2046 GET_ASI_BFILL, 2047 } ASIType; 2048 2049 typedef struct { 2050 ASIType type; 2051 int asi; 2052 int mem_idx; 2053 MemOp memop; 2054 } DisasASI; 2055 2056 static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) 2057 { 2058 int asi = GET_FIELD(insn, 19, 26); 2059 ASIType type = GET_ASI_HELPER; 2060 int mem_idx = dc->mem_idx; 2061 2062 #ifndef TARGET_SPARC64 2063 /* Before v9, all asis are immediate and privileged. */ 2064 if (IS_IMM) { 2065 gen_exception(dc, TT_ILL_INSN); 2066 type = GET_ASI_EXCP; 2067 } else if (supervisor(dc) 2068 /* Note that LEON accepts ASI_USERDATA in user mode, for 2069 use with CASA. Also note that previous versions of 2070 QEMU allowed (and old versions of gcc emitted) ASI_P 2071 for LEON, which is incorrect. */ 2072 || (asi == ASI_USERDATA 2073 && (dc->def->features & CPU_FEATURE_CASA))) { 2074 switch (asi) { 2075 case ASI_USERDATA: /* User data access */ 2076 mem_idx = MMU_USER_IDX; 2077 type = GET_ASI_DIRECT; 2078 break; 2079 case ASI_KERNELDATA: /* Supervisor data access */ 2080 mem_idx = MMU_KERNEL_IDX; 2081 type = GET_ASI_DIRECT; 2082 break; 2083 case ASI_M_BYPASS: /* MMU passthrough */ 2084 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 2085 mem_idx = MMU_PHYS_IDX; 2086 type = GET_ASI_DIRECT; 2087 break; 2088 case ASI_M_BCOPY: /* Block copy, sta access */ 2089 mem_idx = MMU_KERNEL_IDX; 2090 type = GET_ASI_BCOPY; 2091 break; 2092 case ASI_M_BFILL: /* Block fill, stda access */ 2093 mem_idx = MMU_KERNEL_IDX; 2094 type = GET_ASI_BFILL; 2095 break; 2096 } 2097 2098 /* MMU_PHYS_IDX is used when the MMU is disabled to passthrough the 2099 * permissions check in get_physical_address(..). 2100 */ 2101 mem_idx = (dc->mem_idx == MMU_PHYS_IDX) ? MMU_PHYS_IDX : mem_idx; 2102 } else { 2103 gen_exception(dc, TT_PRIV_INSN); 2104 type = GET_ASI_EXCP; 2105 } 2106 #else 2107 if (IS_IMM) { 2108 asi = dc->asi; 2109 } 2110 /* With v9, all asis below 0x80 are privileged. */ 2111 /* ??? We ought to check cpu_has_hypervisor, but we didn't copy 2112 down that bit into DisasContext. For the moment that's ok, 2113 since the direct implementations below doesn't have any ASIs 2114 in the restricted [0x30, 0x7f] range, and the check will be 2115 done properly in the helper. */ 2116 if (!supervisor(dc) && asi < 0x80) { 2117 gen_exception(dc, TT_PRIV_ACT); 2118 type = GET_ASI_EXCP; 2119 } else { 2120 switch (asi) { 2121 case ASI_REAL: /* Bypass */ 2122 case ASI_REAL_IO: /* Bypass, non-cacheable */ 2123 case ASI_REAL_L: /* Bypass LE */ 2124 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 2125 case ASI_TWINX_REAL: /* Real address, twinx */ 2126 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 2127 case ASI_QUAD_LDD_PHYS: 2128 case ASI_QUAD_LDD_PHYS_L: 2129 mem_idx = MMU_PHYS_IDX; 2130 break; 2131 case ASI_N: /* Nucleus */ 2132 case ASI_NL: /* Nucleus LE */ 2133 case ASI_TWINX_N: 2134 case ASI_TWINX_NL: 2135 case ASI_NUCLEUS_QUAD_LDD: 2136 case ASI_NUCLEUS_QUAD_LDD_L: 2137 if (hypervisor(dc)) { 2138 mem_idx = MMU_PHYS_IDX; 2139 } else { 2140 mem_idx = MMU_NUCLEUS_IDX; 2141 } 2142 break; 2143 case ASI_AIUP: /* As if user primary */ 2144 case ASI_AIUPL: /* As if user primary LE */ 2145 case ASI_TWINX_AIUP: 2146 case ASI_TWINX_AIUP_L: 2147 case ASI_BLK_AIUP_4V: 2148 case ASI_BLK_AIUP_L_4V: 2149 case ASI_BLK_AIUP: 2150 case ASI_BLK_AIUPL: 2151 mem_idx = MMU_USER_IDX; 2152 break; 2153 case ASI_AIUS: /* As if user secondary */ 2154 case ASI_AIUSL: /* As if user secondary LE */ 2155 case ASI_TWINX_AIUS: 2156 case ASI_TWINX_AIUS_L: 2157 case ASI_BLK_AIUS_4V: 2158 case ASI_BLK_AIUS_L_4V: 2159 case ASI_BLK_AIUS: 2160 case ASI_BLK_AIUSL: 2161 mem_idx = MMU_USER_SECONDARY_IDX; 2162 break; 2163 case ASI_S: /* Secondary */ 2164 case ASI_SL: /* Secondary LE */ 2165 case ASI_TWINX_S: 2166 case ASI_TWINX_SL: 2167 case ASI_BLK_COMMIT_S: 2168 case ASI_BLK_S: 2169 case ASI_BLK_SL: 2170 case ASI_FL8_S: 2171 case ASI_FL8_SL: 2172 case ASI_FL16_S: 2173 case ASI_FL16_SL: 2174 if (mem_idx == MMU_USER_IDX) { 2175 mem_idx = MMU_USER_SECONDARY_IDX; 2176 } else if (mem_idx == MMU_KERNEL_IDX) { 2177 mem_idx = MMU_KERNEL_SECONDARY_IDX; 2178 } 2179 break; 2180 case ASI_P: /* Primary */ 2181 case ASI_PL: /* Primary LE */ 2182 case ASI_TWINX_P: 2183 case ASI_TWINX_PL: 2184 case ASI_BLK_COMMIT_P: 2185 case ASI_BLK_P: 2186 case ASI_BLK_PL: 2187 case ASI_FL8_P: 2188 case ASI_FL8_PL: 2189 case ASI_FL16_P: 2190 case ASI_FL16_PL: 2191 break; 2192 } 2193 switch (asi) { 2194 case ASI_REAL: 2195 case ASI_REAL_IO: 2196 case ASI_REAL_L: 2197 case ASI_REAL_IO_L: 2198 case ASI_N: 2199 case ASI_NL: 2200 case ASI_AIUP: 2201 case ASI_AIUPL: 2202 case ASI_AIUS: 2203 case ASI_AIUSL: 2204 case ASI_S: 2205 case ASI_SL: 2206 case ASI_P: 2207 case ASI_PL: 2208 type = GET_ASI_DIRECT; 2209 break; 2210 case ASI_TWINX_REAL: 2211 case ASI_TWINX_REAL_L: 2212 case ASI_TWINX_N: 2213 case ASI_TWINX_NL: 2214 case ASI_TWINX_AIUP: 2215 case ASI_TWINX_AIUP_L: 2216 case ASI_TWINX_AIUS: 2217 case ASI_TWINX_AIUS_L: 2218 case ASI_TWINX_P: 2219 case ASI_TWINX_PL: 2220 case ASI_TWINX_S: 2221 case ASI_TWINX_SL: 2222 case ASI_QUAD_LDD_PHYS: 2223 case ASI_QUAD_LDD_PHYS_L: 2224 case ASI_NUCLEUS_QUAD_LDD: 2225 case ASI_NUCLEUS_QUAD_LDD_L: 2226 type = GET_ASI_DTWINX; 2227 break; 2228 case ASI_BLK_COMMIT_P: 2229 case ASI_BLK_COMMIT_S: 2230 case ASI_BLK_AIUP_4V: 2231 case ASI_BLK_AIUP_L_4V: 2232 case ASI_BLK_AIUP: 2233 case ASI_BLK_AIUPL: 2234 case ASI_BLK_AIUS_4V: 2235 case ASI_BLK_AIUS_L_4V: 2236 case ASI_BLK_AIUS: 2237 case ASI_BLK_AIUSL: 2238 case ASI_BLK_S: 2239 case ASI_BLK_SL: 2240 case ASI_BLK_P: 2241 case ASI_BLK_PL: 2242 type = GET_ASI_BLOCK; 2243 break; 2244 case ASI_FL8_S: 2245 case ASI_FL8_SL: 2246 case ASI_FL8_P: 2247 case ASI_FL8_PL: 2248 memop = MO_UB; 2249 type = GET_ASI_SHORT; 2250 break; 2251 case ASI_FL16_S: 2252 case ASI_FL16_SL: 2253 case ASI_FL16_P: 2254 case ASI_FL16_PL: 2255 memop = MO_TEUW; 2256 type = GET_ASI_SHORT; 2257 break; 2258 } 2259 /* The little-endian asis all have bit 3 set. */ 2260 if (asi & 8) { 2261 memop ^= MO_BSWAP; 2262 } 2263 } 2264 #endif 2265 2266 return (DisasASI){ type, asi, mem_idx, memop }; 2267 } 2268 2269 static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, 2270 int insn, MemOp memop) 2271 { 2272 DisasASI da = get_asi(dc, insn, memop); 2273 2274 switch (da.type) { 2275 case GET_ASI_EXCP: 2276 break; 2277 case GET_ASI_DTWINX: /* Reserved for ldda. */ 2278 gen_exception(dc, TT_ILL_INSN); 2279 break; 2280 case GET_ASI_DIRECT: 2281 gen_address_mask(dc, addr); 2282 tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop); 2283 break; 2284 default: 2285 { 2286 TCGv_i32 r_asi = tcg_const_i32(da.asi); 2287 TCGv_i32 r_mop = tcg_const_i32(memop); 2288 2289 save_state(dc); 2290 #ifdef TARGET_SPARC64 2291 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_mop); 2292 #else 2293 { 2294 TCGv_i64 t64 = tcg_temp_new_i64(); 2295 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); 2296 tcg_gen_trunc_i64_tl(dst, t64); 2297 tcg_temp_free_i64(t64); 2298 } 2299 #endif 2300 tcg_temp_free_i32(r_mop); 2301 tcg_temp_free_i32(r_asi); 2302 } 2303 break; 2304 } 2305 } 2306 2307 static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, 2308 int insn, MemOp memop) 2309 { 2310 DisasASI da = get_asi(dc, insn, memop); 2311 2312 switch (da.type) { 2313 case GET_ASI_EXCP: 2314 break; 2315 case GET_ASI_DTWINX: /* Reserved for stda. */ 2316 #ifndef TARGET_SPARC64 2317 gen_exception(dc, TT_ILL_INSN); 2318 break; 2319 #else 2320 if (!(dc->def->features & CPU_FEATURE_HYPV)) { 2321 /* Pre OpenSPARC CPUs don't have these */ 2322 gen_exception(dc, TT_ILL_INSN); 2323 return; 2324 } 2325 /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions 2326 * are ST_BLKINIT_ ASIs */ 2327 /* fall through */ 2328 #endif 2329 case GET_ASI_DIRECT: 2330 gen_address_mask(dc, addr); 2331 tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop); 2332 break; 2333 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 2334 case GET_ASI_BCOPY: 2335 /* Copy 32 bytes from the address in SRC to ADDR. */ 2336 /* ??? The original qemu code suggests 4-byte alignment, dropping 2337 the low bits, but the only place I can see this used is in the 2338 Linux kernel with 32 byte alignment, which would make more sense 2339 as a cacheline-style operation. */ 2340 { 2341 TCGv saddr = tcg_temp_new(); 2342 TCGv daddr = tcg_temp_new(); 2343 TCGv four = tcg_const_tl(4); 2344 TCGv_i32 tmp = tcg_temp_new_i32(); 2345 int i; 2346 2347 tcg_gen_andi_tl(saddr, src, -4); 2348 tcg_gen_andi_tl(daddr, addr, -4); 2349 for (i = 0; i < 32; i += 4) { 2350 /* Since the loads and stores are paired, allow the 2351 copy to happen in the host endianness. */ 2352 tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL); 2353 tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL); 2354 tcg_gen_add_tl(saddr, saddr, four); 2355 tcg_gen_add_tl(daddr, daddr, four); 2356 } 2357 2358 tcg_temp_free(saddr); 2359 tcg_temp_free(daddr); 2360 tcg_temp_free(four); 2361 tcg_temp_free_i32(tmp); 2362 } 2363 break; 2364 #endif 2365 default: 2366 { 2367 TCGv_i32 r_asi = tcg_const_i32(da.asi); 2368 TCGv_i32 r_mop = tcg_const_i32(memop & MO_SIZE); 2369 2370 save_state(dc); 2371 #ifdef TARGET_SPARC64 2372 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_mop); 2373 #else 2374 { 2375 TCGv_i64 t64 = tcg_temp_new_i64(); 2376 tcg_gen_extu_tl_i64(t64, src); 2377 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); 2378 tcg_temp_free_i64(t64); 2379 } 2380 #endif 2381 tcg_temp_free_i32(r_mop); 2382 tcg_temp_free_i32(r_asi); 2383 2384 /* A write to a TLB register may alter page maps. End the TB. */ 2385 dc->npc = DYNAMIC_PC; 2386 } 2387 break; 2388 } 2389 } 2390 2391 static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, 2392 TCGv addr, int insn) 2393 { 2394 DisasASI da = get_asi(dc, insn, MO_TEUL); 2395 2396 switch (da.type) { 2397 case GET_ASI_EXCP: 2398 break; 2399 case GET_ASI_DIRECT: 2400 gen_swap(dc, dst, src, addr, da.mem_idx, da.memop); 2401 break; 2402 default: 2403 /* ??? Should be DAE_invalid_asi. */ 2404 gen_exception(dc, TT_DATA_ACCESS); 2405 break; 2406 } 2407 } 2408 2409 static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, 2410 int insn, int rd) 2411 { 2412 DisasASI da = get_asi(dc, insn, MO_TEUL); 2413 TCGv oldv; 2414 2415 switch (da.type) { 2416 case GET_ASI_EXCP: 2417 return; 2418 case GET_ASI_DIRECT: 2419 oldv = tcg_temp_new(); 2420 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), 2421 da.mem_idx, da.memop); 2422 gen_store_gpr(dc, rd, oldv); 2423 tcg_temp_free(oldv); 2424 break; 2425 default: 2426 /* ??? Should be DAE_invalid_asi. */ 2427 gen_exception(dc, TT_DATA_ACCESS); 2428 break; 2429 } 2430 } 2431 2432 static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) 2433 { 2434 DisasASI da = get_asi(dc, insn, MO_UB); 2435 2436 switch (da.type) { 2437 case GET_ASI_EXCP: 2438 break; 2439 case GET_ASI_DIRECT: 2440 gen_ldstub(dc, dst, addr, da.mem_idx); 2441 break; 2442 default: 2443 /* ??? In theory, this should be raise DAE_invalid_asi. 2444 But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */ 2445 if (tb_cflags(dc->base.tb) & CF_PARALLEL) { 2446 gen_helper_exit_atomic(cpu_env); 2447 } else { 2448 TCGv_i32 r_asi = tcg_const_i32(da.asi); 2449 TCGv_i32 r_mop = tcg_const_i32(MO_UB); 2450 TCGv_i64 s64, t64; 2451 2452 save_state(dc); 2453 t64 = tcg_temp_new_i64(); 2454 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); 2455 2456 s64 = tcg_const_i64(0xff); 2457 gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop); 2458 tcg_temp_free_i64(s64); 2459 tcg_temp_free_i32(r_mop); 2460 tcg_temp_free_i32(r_asi); 2461 2462 tcg_gen_trunc_i64_tl(dst, t64); 2463 tcg_temp_free_i64(t64); 2464 2465 /* End the TB. */ 2466 dc->npc = DYNAMIC_PC; 2467 } 2468 break; 2469 } 2470 } 2471 #endif 2472 2473 #ifdef TARGET_SPARC64 2474 static void gen_ldf_asi(DisasContext *dc, TCGv addr, 2475 int insn, int size, int rd) 2476 { 2477 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ)); 2478 TCGv_i32 d32; 2479 TCGv_i64 d64; 2480 2481 switch (da.type) { 2482 case GET_ASI_EXCP: 2483 break; 2484 2485 case GET_ASI_DIRECT: 2486 gen_address_mask(dc, addr); 2487 switch (size) { 2488 case 4: 2489 d32 = gen_dest_fpr_F(dc); 2490 tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop); 2491 gen_store_fpr_F(dc, rd, d32); 2492 break; 2493 case 8: 2494 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, 2495 da.memop | MO_ALIGN_4); 2496 break; 2497 case 16: 2498 d64 = tcg_temp_new_i64(); 2499 tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4); 2500 tcg_gen_addi_tl(addr, addr, 8); 2501 tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, 2502 da.memop | MO_ALIGN_4); 2503 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); 2504 tcg_temp_free_i64(d64); 2505 break; 2506 default: 2507 g_assert_not_reached(); 2508 } 2509 break; 2510 2511 case GET_ASI_BLOCK: 2512 /* Valid for lddfa on aligned registers only. */ 2513 if (size == 8 && (rd & 7) == 0) { 2514 MemOp memop; 2515 TCGv eight; 2516 int i; 2517 2518 gen_address_mask(dc, addr); 2519 2520 /* The first operation checks required alignment. */ 2521 memop = da.memop | MO_ALIGN_64; 2522 eight = tcg_const_tl(8); 2523 for (i = 0; ; ++i) { 2524 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, 2525 da.mem_idx, memop); 2526 if (i == 7) { 2527 break; 2528 } 2529 tcg_gen_add_tl(addr, addr, eight); 2530 memop = da.memop; 2531 } 2532 tcg_temp_free(eight); 2533 } else { 2534 gen_exception(dc, TT_ILL_INSN); 2535 } 2536 break; 2537 2538 case GET_ASI_SHORT: 2539 /* Valid for lddfa only. */ 2540 if (size == 8) { 2541 gen_address_mask(dc, addr); 2542 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop); 2543 } else { 2544 gen_exception(dc, TT_ILL_INSN); 2545 } 2546 break; 2547 2548 default: 2549 { 2550 TCGv_i32 r_asi = tcg_const_i32(da.asi); 2551 TCGv_i32 r_mop = tcg_const_i32(da.memop); 2552 2553 save_state(dc); 2554 /* According to the table in the UA2011 manual, the only 2555 other asis that are valid for ldfa/lddfa/ldqfa are 2556 the NO_FAULT asis. We still need a helper for these, 2557 but we can just use the integer asi helper for them. */ 2558 switch (size) { 2559 case 4: 2560 d64 = tcg_temp_new_i64(); 2561 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop); 2562 d32 = gen_dest_fpr_F(dc); 2563 tcg_gen_extrl_i64_i32(d32, d64); 2564 tcg_temp_free_i64(d64); 2565 gen_store_fpr_F(dc, rd, d32); 2566 break; 2567 case 8: 2568 gen_helper_ld_asi(cpu_fpr[rd / 2], cpu_env, addr, r_asi, r_mop); 2569 break; 2570 case 16: 2571 d64 = tcg_temp_new_i64(); 2572 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop); 2573 tcg_gen_addi_tl(addr, addr, 8); 2574 gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r_mop); 2575 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); 2576 tcg_temp_free_i64(d64); 2577 break; 2578 default: 2579 g_assert_not_reached(); 2580 } 2581 tcg_temp_free_i32(r_mop); 2582 tcg_temp_free_i32(r_asi); 2583 } 2584 break; 2585 } 2586 } 2587 2588 static void gen_stf_asi(DisasContext *dc, TCGv addr, 2589 int insn, int size, int rd) 2590 { 2591 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ)); 2592 TCGv_i32 d32; 2593 2594 switch (da.type) { 2595 case GET_ASI_EXCP: 2596 break; 2597 2598 case GET_ASI_DIRECT: 2599 gen_address_mask(dc, addr); 2600 switch (size) { 2601 case 4: 2602 d32 = gen_load_fpr_F(dc, rd); 2603 tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop); 2604 break; 2605 case 8: 2606 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, 2607 da.memop | MO_ALIGN_4); 2608 break; 2609 case 16: 2610 /* Only 4-byte alignment required. However, it is legal for the 2611 cpu to signal the alignment fault, and the OS trap handler is 2612 required to fix it up. Requiring 16-byte alignment here avoids 2613 having to probe the second page before performing the first 2614 write. */ 2615 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, 2616 da.memop | MO_ALIGN_16); 2617 tcg_gen_addi_tl(addr, addr, 8); 2618 tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop); 2619 break; 2620 default: 2621 g_assert_not_reached(); 2622 } 2623 break; 2624 2625 case GET_ASI_BLOCK: 2626 /* Valid for stdfa on aligned registers only. */ 2627 if (size == 8 && (rd & 7) == 0) { 2628 MemOp memop; 2629 TCGv eight; 2630 int i; 2631 2632 gen_address_mask(dc, addr); 2633 2634 /* The first operation checks required alignment. */ 2635 memop = da.memop | MO_ALIGN_64; 2636 eight = tcg_const_tl(8); 2637 for (i = 0; ; ++i) { 2638 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, 2639 da.mem_idx, memop); 2640 if (i == 7) { 2641 break; 2642 } 2643 tcg_gen_add_tl(addr, addr, eight); 2644 memop = da.memop; 2645 } 2646 tcg_temp_free(eight); 2647 } else { 2648 gen_exception(dc, TT_ILL_INSN); 2649 } 2650 break; 2651 2652 case GET_ASI_SHORT: 2653 /* Valid for stdfa only. */ 2654 if (size == 8) { 2655 gen_address_mask(dc, addr); 2656 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop); 2657 } else { 2658 gen_exception(dc, TT_ILL_INSN); 2659 } 2660 break; 2661 2662 default: 2663 /* According to the table in the UA2011 manual, the only 2664 other asis that are valid for ldfa/lddfa/ldqfa are 2665 the PST* asis, which aren't currently handled. */ 2666 gen_exception(dc, TT_ILL_INSN); 2667 break; 2668 } 2669 } 2670 2671 static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) 2672 { 2673 DisasASI da = get_asi(dc, insn, MO_TEQ); 2674 TCGv_i64 hi = gen_dest_gpr(dc, rd); 2675 TCGv_i64 lo = gen_dest_gpr(dc, rd + 1); 2676 2677 switch (da.type) { 2678 case GET_ASI_EXCP: 2679 return; 2680 2681 case GET_ASI_DTWINX: 2682 gen_address_mask(dc, addr); 2683 tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); 2684 tcg_gen_addi_tl(addr, addr, 8); 2685 tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop); 2686 break; 2687 2688 case GET_ASI_DIRECT: 2689 { 2690 TCGv_i64 tmp = tcg_temp_new_i64(); 2691 2692 gen_address_mask(dc, addr); 2693 tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop); 2694 2695 /* Note that LE ldda acts as if each 32-bit register 2696 result is byte swapped. Having just performed one 2697 64-bit bswap, we need now to swap the writebacks. */ 2698 if ((da.memop & MO_BSWAP) == MO_TE) { 2699 tcg_gen_extr32_i64(lo, hi, tmp); 2700 } else { 2701 tcg_gen_extr32_i64(hi, lo, tmp); 2702 } 2703 tcg_temp_free_i64(tmp); 2704 } 2705 break; 2706 2707 default: 2708 /* ??? In theory we've handled all of the ASIs that are valid 2709 for ldda, and this should raise DAE_invalid_asi. However, 2710 real hardware allows others. This can be seen with e.g. 2711 FreeBSD 10.3 wrt ASI_IC_TAG. */ 2712 { 2713 TCGv_i32 r_asi = tcg_const_i32(da.asi); 2714 TCGv_i32 r_mop = tcg_const_i32(da.memop); 2715 TCGv_i64 tmp = tcg_temp_new_i64(); 2716 2717 save_state(dc); 2718 gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop); 2719 tcg_temp_free_i32(r_asi); 2720 tcg_temp_free_i32(r_mop); 2721 2722 /* See above. */ 2723 if ((da.memop & MO_BSWAP) == MO_TE) { 2724 tcg_gen_extr32_i64(lo, hi, tmp); 2725 } else { 2726 tcg_gen_extr32_i64(hi, lo, tmp); 2727 } 2728 tcg_temp_free_i64(tmp); 2729 } 2730 break; 2731 } 2732 2733 gen_store_gpr(dc, rd, hi); 2734 gen_store_gpr(dc, rd + 1, lo); 2735 } 2736 2737 static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, 2738 int insn, int rd) 2739 { 2740 DisasASI da = get_asi(dc, insn, MO_TEQ); 2741 TCGv lo = gen_load_gpr(dc, rd + 1); 2742 2743 switch (da.type) { 2744 case GET_ASI_EXCP: 2745 break; 2746 2747 case GET_ASI_DTWINX: 2748 gen_address_mask(dc, addr); 2749 tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); 2750 tcg_gen_addi_tl(addr, addr, 8); 2751 tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop); 2752 break; 2753 2754 case GET_ASI_DIRECT: 2755 { 2756 TCGv_i64 t64 = tcg_temp_new_i64(); 2757 2758 /* Note that LE stda acts as if each 32-bit register result is 2759 byte swapped. We will perform one 64-bit LE store, so now 2760 we must swap the order of the construction. */ 2761 if ((da.memop & MO_BSWAP) == MO_TE) { 2762 tcg_gen_concat32_i64(t64, lo, hi); 2763 } else { 2764 tcg_gen_concat32_i64(t64, hi, lo); 2765 } 2766 gen_address_mask(dc, addr); 2767 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop); 2768 tcg_temp_free_i64(t64); 2769 } 2770 break; 2771 2772 default: 2773 /* ??? In theory we've handled all of the ASIs that are valid 2774 for stda, and this should raise DAE_invalid_asi. */ 2775 { 2776 TCGv_i32 r_asi = tcg_const_i32(da.asi); 2777 TCGv_i32 r_mop = tcg_const_i32(da.memop); 2778 TCGv_i64 t64 = tcg_temp_new_i64(); 2779 2780 /* See above. */ 2781 if ((da.memop & MO_BSWAP) == MO_TE) { 2782 tcg_gen_concat32_i64(t64, lo, hi); 2783 } else { 2784 tcg_gen_concat32_i64(t64, hi, lo); 2785 } 2786 2787 save_state(dc); 2788 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); 2789 tcg_temp_free_i32(r_mop); 2790 tcg_temp_free_i32(r_asi); 2791 tcg_temp_free_i64(t64); 2792 } 2793 break; 2794 } 2795 } 2796 2797 static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, 2798 int insn, int rd) 2799 { 2800 DisasASI da = get_asi(dc, insn, MO_TEQ); 2801 TCGv oldv; 2802 2803 switch (da.type) { 2804 case GET_ASI_EXCP: 2805 return; 2806 case GET_ASI_DIRECT: 2807 oldv = tcg_temp_new(); 2808 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), 2809 da.mem_idx, da.memop); 2810 gen_store_gpr(dc, rd, oldv); 2811 tcg_temp_free(oldv); 2812 break; 2813 default: 2814 /* ??? Should be DAE_invalid_asi. */ 2815 gen_exception(dc, TT_DATA_ACCESS); 2816 break; 2817 } 2818 } 2819 2820 #elif !defined(CONFIG_USER_ONLY) 2821 static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) 2822 { 2823 /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12, 2824 whereby "rd + 1" elicits "error: array subscript is above array". 2825 Since we have already asserted that rd is even, the semantics 2826 are unchanged. */ 2827 TCGv lo = gen_dest_gpr(dc, rd | 1); 2828 TCGv hi = gen_dest_gpr(dc, rd); 2829 TCGv_i64 t64 = tcg_temp_new_i64(); 2830 DisasASI da = get_asi(dc, insn, MO_TEQ); 2831 2832 switch (da.type) { 2833 case GET_ASI_EXCP: 2834 tcg_temp_free_i64(t64); 2835 return; 2836 case GET_ASI_DIRECT: 2837 gen_address_mask(dc, addr); 2838 tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop); 2839 break; 2840 default: 2841 { 2842 TCGv_i32 r_asi = tcg_const_i32(da.asi); 2843 TCGv_i32 r_mop = tcg_const_i32(MO_Q); 2844 2845 save_state(dc); 2846 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); 2847 tcg_temp_free_i32(r_mop); 2848 tcg_temp_free_i32(r_asi); 2849 } 2850 break; 2851 } 2852 2853 tcg_gen_extr_i64_i32(lo, hi, t64); 2854 tcg_temp_free_i64(t64); 2855 gen_store_gpr(dc, rd | 1, lo); 2856 gen_store_gpr(dc, rd, hi); 2857 } 2858 2859 static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, 2860 int insn, int rd) 2861 { 2862 DisasASI da = get_asi(dc, insn, MO_TEQ); 2863 TCGv lo = gen_load_gpr(dc, rd + 1); 2864 TCGv_i64 t64 = tcg_temp_new_i64(); 2865 2866 tcg_gen_concat_tl_i64(t64, lo, hi); 2867 2868 switch (da.type) { 2869 case GET_ASI_EXCP: 2870 break; 2871 case GET_ASI_DIRECT: 2872 gen_address_mask(dc, addr); 2873 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop); 2874 break; 2875 case GET_ASI_BFILL: 2876 /* Store 32 bytes of T64 to ADDR. */ 2877 /* ??? The original qemu code suggests 8-byte alignment, dropping 2878 the low bits, but the only place I can see this used is in the 2879 Linux kernel with 32 byte alignment, which would make more sense 2880 as a cacheline-style operation. */ 2881 { 2882 TCGv d_addr = tcg_temp_new(); 2883 TCGv eight = tcg_const_tl(8); 2884 int i; 2885 2886 tcg_gen_andi_tl(d_addr, addr, -8); 2887 for (i = 0; i < 32; i += 8) { 2888 tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); 2889 tcg_gen_add_tl(d_addr, d_addr, eight); 2890 } 2891 2892 tcg_temp_free(d_addr); 2893 tcg_temp_free(eight); 2894 } 2895 break; 2896 default: 2897 { 2898 TCGv_i32 r_asi = tcg_const_i32(da.asi); 2899 TCGv_i32 r_mop = tcg_const_i32(MO_Q); 2900 2901 save_state(dc); 2902 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); 2903 tcg_temp_free_i32(r_mop); 2904 tcg_temp_free_i32(r_asi); 2905 } 2906 break; 2907 } 2908 2909 tcg_temp_free_i64(t64); 2910 } 2911 #endif 2912 2913 static TCGv get_src1(DisasContext *dc, unsigned int insn) 2914 { 2915 unsigned int rs1 = GET_FIELD(insn, 13, 17); 2916 return gen_load_gpr(dc, rs1); 2917 } 2918 2919 static TCGv get_src2(DisasContext *dc, unsigned int insn) 2920 { 2921 if (IS_IMM) { /* immediate */ 2922 target_long simm = GET_FIELDs(insn, 19, 31); 2923 TCGv t = get_temp_tl(dc); 2924 tcg_gen_movi_tl(t, simm); 2925 return t; 2926 } else { /* register */ 2927 unsigned int rs2 = GET_FIELD(insn, 27, 31); 2928 return gen_load_gpr(dc, rs2); 2929 } 2930 } 2931 2932 #ifdef TARGET_SPARC64 2933 static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) 2934 { 2935 TCGv_i32 c32, zero, dst, s1, s2; 2936 2937 /* We have two choices here: extend the 32 bit data and use movcond_i64, 2938 or fold the comparison down to 32 bits and use movcond_i32. Choose 2939 the later. */ 2940 c32 = tcg_temp_new_i32(); 2941 if (cmp->is_bool) { 2942 tcg_gen_extrl_i64_i32(c32, cmp->c1); 2943 } else { 2944 TCGv_i64 c64 = tcg_temp_new_i64(); 2945 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2); 2946 tcg_gen_extrl_i64_i32(c32, c64); 2947 tcg_temp_free_i64(c64); 2948 } 2949 2950 s1 = gen_load_fpr_F(dc, rs); 2951 s2 = gen_load_fpr_F(dc, rd); 2952 dst = gen_dest_fpr_F(dc); 2953 zero = tcg_const_i32(0); 2954 2955 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); 2956 2957 tcg_temp_free_i32(c32); 2958 tcg_temp_free_i32(zero); 2959 gen_store_fpr_F(dc, rd, dst); 2960 } 2961 2962 static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs) 2963 { 2964 TCGv_i64 dst = gen_dest_fpr_D(dc, rd); 2965 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2, 2966 gen_load_fpr_D(dc, rs), 2967 gen_load_fpr_D(dc, rd)); 2968 gen_store_fpr_D(dc, rd, dst); 2969 } 2970 2971 static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) 2972 { 2973 int qd = QFPREG(rd); 2974 int qs = QFPREG(rs); 2975 2976 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2, 2977 cpu_fpr[qs / 2], cpu_fpr[qd / 2]); 2978 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2, 2979 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]); 2980 2981 gen_update_fprs_dirty(dc, qd); 2982 } 2983 2984 #ifndef CONFIG_USER_ONLY 2985 static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env) 2986 { 2987 TCGv_i32 r_tl = tcg_temp_new_i32(); 2988 2989 /* load env->tl into r_tl */ 2990 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl)); 2991 2992 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */ 2993 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); 2994 2995 /* calculate offset to current trap state from env->ts, reuse r_tl */ 2996 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state)); 2997 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts)); 2998 2999 /* tsptr = env->ts[env->tl & MAXTL_MASK] */ 3000 { 3001 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr(); 3002 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl); 3003 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); 3004 tcg_temp_free_ptr(r_tl_tmp); 3005 } 3006 3007 tcg_temp_free_i32(r_tl); 3008 } 3009 #endif 3010 3011 static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, 3012 int width, bool cc, bool left) 3013 { 3014 TCGv lo1, lo2, t1, t2; 3015 uint64_t amask, tabl, tabr; 3016 int shift, imask, omask; 3017 3018 if (cc) { 3019 tcg_gen_mov_tl(cpu_cc_src, s1); 3020 tcg_gen_mov_tl(cpu_cc_src2, s2); 3021 tcg_gen_sub_tl(cpu_cc_dst, s1, s2); 3022 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); 3023 dc->cc_op = CC_OP_SUB; 3024 } 3025 3026 /* Theory of operation: there are two tables, left and right (not to 3027 be confused with the left and right versions of the opcode). These 3028 are indexed by the low 3 bits of the inputs. To make things "easy", 3029 these tables are loaded into two constants, TABL and TABR below. 3030 The operation index = (input & imask) << shift calculates the index 3031 into the constant, while val = (table >> index) & omask calculates 3032 the value we're looking for. */ 3033 switch (width) { 3034 case 8: 3035 imask = 0x7; 3036 shift = 3; 3037 omask = 0xff; 3038 if (left) { 3039 tabl = 0x80c0e0f0f8fcfeffULL; 3040 tabr = 0xff7f3f1f0f070301ULL; 3041 } else { 3042 tabl = 0x0103070f1f3f7fffULL; 3043 tabr = 0xfffefcf8f0e0c080ULL; 3044 } 3045 break; 3046 case 16: 3047 imask = 0x6; 3048 shift = 1; 3049 omask = 0xf; 3050 if (left) { 3051 tabl = 0x8cef; 3052 tabr = 0xf731; 3053 } else { 3054 tabl = 0x137f; 3055 tabr = 0xfec8; 3056 } 3057 break; 3058 case 32: 3059 imask = 0x4; 3060 shift = 0; 3061 omask = 0x3; 3062 if (left) { 3063 tabl = (2 << 2) | 3; 3064 tabr = (3 << 2) | 1; 3065 } else { 3066 tabl = (1 << 2) | 3; 3067 tabr = (3 << 2) | 2; 3068 } 3069 break; 3070 default: 3071 abort(); 3072 } 3073 3074 lo1 = tcg_temp_new(); 3075 lo2 = tcg_temp_new(); 3076 tcg_gen_andi_tl(lo1, s1, imask); 3077 tcg_gen_andi_tl(lo2, s2, imask); 3078 tcg_gen_shli_tl(lo1, lo1, shift); 3079 tcg_gen_shli_tl(lo2, lo2, shift); 3080 3081 t1 = tcg_const_tl(tabl); 3082 t2 = tcg_const_tl(tabr); 3083 tcg_gen_shr_tl(lo1, t1, lo1); 3084 tcg_gen_shr_tl(lo2, t2, lo2); 3085 tcg_gen_andi_tl(dst, lo1, omask); 3086 tcg_gen_andi_tl(lo2, lo2, omask); 3087 3088 amask = -8; 3089 if (AM_CHECK(dc)) { 3090 amask &= 0xffffffffULL; 3091 } 3092 tcg_gen_andi_tl(s1, s1, amask); 3093 tcg_gen_andi_tl(s2, s2, amask); 3094 3095 /* We want to compute 3096 dst = (s1 == s2 ? lo1 : lo1 & lo2). 3097 We've already done dst = lo1, so this reduces to 3098 dst &= (s1 == s2 ? -1 : lo2) 3099 Which we perform by 3100 lo2 |= -(s1 == s2) 3101 dst &= lo2 3102 */ 3103 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2); 3104 tcg_gen_neg_tl(t1, t1); 3105 tcg_gen_or_tl(lo2, lo2, t1); 3106 tcg_gen_and_tl(dst, dst, lo2); 3107 3108 tcg_temp_free(lo1); 3109 tcg_temp_free(lo2); 3110 tcg_temp_free(t1); 3111 tcg_temp_free(t2); 3112 } 3113 3114 static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) 3115 { 3116 TCGv tmp = tcg_temp_new(); 3117 3118 tcg_gen_add_tl(tmp, s1, s2); 3119 tcg_gen_andi_tl(dst, tmp, -8); 3120 if (left) { 3121 tcg_gen_neg_tl(tmp, tmp); 3122 } 3123 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); 3124 3125 tcg_temp_free(tmp); 3126 } 3127 3128 static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) 3129 { 3130 TCGv t1, t2, shift; 3131 3132 t1 = tcg_temp_new(); 3133 t2 = tcg_temp_new(); 3134 shift = tcg_temp_new(); 3135 3136 tcg_gen_andi_tl(shift, gsr, 7); 3137 tcg_gen_shli_tl(shift, shift, 3); 3138 tcg_gen_shl_tl(t1, s1, shift); 3139 3140 /* A shift of 64 does not produce 0 in TCG. Divide this into a 3141 shift of (up to 63) followed by a constant shift of 1. */ 3142 tcg_gen_xori_tl(shift, shift, 63); 3143 tcg_gen_shr_tl(t2, s2, shift); 3144 tcg_gen_shri_tl(t2, t2, 1); 3145 3146 tcg_gen_or_tl(dst, t1, t2); 3147 3148 tcg_temp_free(t1); 3149 tcg_temp_free(t2); 3150 tcg_temp_free(shift); 3151 } 3152 #endif 3153 3154 #define CHECK_IU_FEATURE(dc, FEATURE) \ 3155 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ 3156 goto illegal_insn; 3157 #define CHECK_FPU_FEATURE(dc, FEATURE) \ 3158 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ 3159 goto nfpu_insn; 3160 3161 /* before an instruction, dc->pc must be static */ 3162 static void disas_sparc_insn(DisasContext * dc, unsigned int insn) 3163 { 3164 unsigned int opc, rs1, rs2, rd; 3165 TCGv cpu_src1, cpu_src2; 3166 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; 3167 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; 3168 target_long simm; 3169 3170 opc = GET_FIELD(insn, 0, 1); 3171 rd = GET_FIELD(insn, 2, 6); 3172 3173 switch (opc) { 3174 case 0: /* branches/sethi */ 3175 { 3176 unsigned int xop = GET_FIELD(insn, 7, 9); 3177 int32_t target; 3178 switch (xop) { 3179 #ifdef TARGET_SPARC64 3180 case 0x1: /* V9 BPcc */ 3181 { 3182 int cc; 3183 3184 target = GET_FIELD_SP(insn, 0, 18); 3185 target = sign_extend(target, 19); 3186 target <<= 2; 3187 cc = GET_FIELD_SP(insn, 20, 21); 3188 if (cc == 0) 3189 do_branch(dc, target, insn, 0); 3190 else if (cc == 2) 3191 do_branch(dc, target, insn, 1); 3192 else 3193 goto illegal_insn; 3194 goto jmp_insn; 3195 } 3196 case 0x3: /* V9 BPr */ 3197 { 3198 target = GET_FIELD_SP(insn, 0, 13) | 3199 (GET_FIELD_SP(insn, 20, 21) << 14); 3200 target = sign_extend(target, 16); 3201 target <<= 2; 3202 cpu_src1 = get_src1(dc, insn); 3203 do_branch_reg(dc, target, insn, cpu_src1); 3204 goto jmp_insn; 3205 } 3206 case 0x5: /* V9 FBPcc */ 3207 { 3208 int cc = GET_FIELD_SP(insn, 20, 21); 3209 if (gen_trap_ifnofpu(dc)) { 3210 goto jmp_insn; 3211 } 3212 target = GET_FIELD_SP(insn, 0, 18); 3213 target = sign_extend(target, 19); 3214 target <<= 2; 3215 do_fbranch(dc, target, insn, cc); 3216 goto jmp_insn; 3217 } 3218 #else 3219 case 0x7: /* CBN+x */ 3220 { 3221 goto ncp_insn; 3222 } 3223 #endif 3224 case 0x2: /* BN+x */ 3225 { 3226 target = GET_FIELD(insn, 10, 31); 3227 target = sign_extend(target, 22); 3228 target <<= 2; 3229 do_branch(dc, target, insn, 0); 3230 goto jmp_insn; 3231 } 3232 case 0x6: /* FBN+x */ 3233 { 3234 if (gen_trap_ifnofpu(dc)) { 3235 goto jmp_insn; 3236 } 3237 target = GET_FIELD(insn, 10, 31); 3238 target = sign_extend(target, 22); 3239 target <<= 2; 3240 do_fbranch(dc, target, insn, 0); 3241 goto jmp_insn; 3242 } 3243 case 0x4: /* SETHI */ 3244 /* Special-case %g0 because that's the canonical nop. */ 3245 if (rd) { 3246 uint32_t value = GET_FIELD(insn, 10, 31); 3247 TCGv t = gen_dest_gpr(dc, rd); 3248 tcg_gen_movi_tl(t, value << 10); 3249 gen_store_gpr(dc, rd, t); 3250 } 3251 break; 3252 case 0x0: /* UNIMPL */ 3253 default: 3254 goto illegal_insn; 3255 } 3256 break; 3257 } 3258 break; 3259 case 1: /*CALL*/ 3260 { 3261 target_long target = GET_FIELDs(insn, 2, 31) << 2; 3262 TCGv o7 = gen_dest_gpr(dc, 15); 3263 3264 tcg_gen_movi_tl(o7, dc->pc); 3265 gen_store_gpr(dc, 15, o7); 3266 target += dc->pc; 3267 gen_mov_pc_npc(dc); 3268 #ifdef TARGET_SPARC64 3269 if (unlikely(AM_CHECK(dc))) { 3270 target &= 0xffffffffULL; 3271 } 3272 #endif 3273 dc->npc = target; 3274 } 3275 goto jmp_insn; 3276 case 2: /* FPU & Logical Operations */ 3277 { 3278 unsigned int xop = GET_FIELD(insn, 7, 12); 3279 TCGv cpu_dst = get_temp_tl(dc); 3280 TCGv cpu_tmp0; 3281 3282 if (xop == 0x3a) { /* generate trap */ 3283 int cond = GET_FIELD(insn, 3, 6); 3284 TCGv_i32 trap; 3285 TCGLabel *l1 = NULL; 3286 int mask; 3287 3288 if (cond == 0) { 3289 /* Trap never. */ 3290 break; 3291 } 3292 3293 save_state(dc); 3294 3295 if (cond != 8) { 3296 /* Conditional trap. */ 3297 DisasCompare cmp; 3298 #ifdef TARGET_SPARC64 3299 /* V9 icc/xcc */ 3300 int cc = GET_FIELD_SP(insn, 11, 12); 3301 if (cc == 0) { 3302 gen_compare(&cmp, 0, cond, dc); 3303 } else if (cc == 2) { 3304 gen_compare(&cmp, 1, cond, dc); 3305 } else { 3306 goto illegal_insn; 3307 } 3308 #else 3309 gen_compare(&cmp, 0, cond, dc); 3310 #endif 3311 l1 = gen_new_label(); 3312 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond), 3313 cmp.c1, cmp.c2, l1); 3314 free_compare(&cmp); 3315 } 3316 3317 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc) 3318 ? UA2005_HTRAP_MASK : V8_TRAP_MASK); 3319 3320 /* Don't use the normal temporaries, as they may well have 3321 gone out of scope with the branch above. While we're 3322 doing that we might as well pre-truncate to 32-bit. */ 3323 trap = tcg_temp_new_i32(); 3324 3325 rs1 = GET_FIELD_SP(insn, 14, 18); 3326 if (IS_IMM) { 3327 rs2 = GET_FIELD_SP(insn, 0, 7); 3328 if (rs1 == 0) { 3329 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP); 3330 /* Signal that the trap value is fully constant. */ 3331 mask = 0; 3332 } else { 3333 TCGv t1 = gen_load_gpr(dc, rs1); 3334 tcg_gen_trunc_tl_i32(trap, t1); 3335 tcg_gen_addi_i32(trap, trap, rs2); 3336 } 3337 } else { 3338 TCGv t1, t2; 3339 rs2 = GET_FIELD_SP(insn, 0, 4); 3340 t1 = gen_load_gpr(dc, rs1); 3341 t2 = gen_load_gpr(dc, rs2); 3342 tcg_gen_add_tl(t1, t1, t2); 3343 tcg_gen_trunc_tl_i32(trap, t1); 3344 } 3345 if (mask != 0) { 3346 tcg_gen_andi_i32(trap, trap, mask); 3347 tcg_gen_addi_i32(trap, trap, TT_TRAP); 3348 } 3349 3350 gen_helper_raise_exception(cpu_env, trap); 3351 tcg_temp_free_i32(trap); 3352 3353 if (cond == 8) { 3354 /* An unconditional trap ends the TB. */ 3355 dc->base.is_jmp = DISAS_NORETURN; 3356 goto jmp_insn; 3357 } else { 3358 /* A conditional trap falls through to the next insn. */ 3359 gen_set_label(l1); 3360 break; 3361 } 3362 } else if (xop == 0x28) { 3363 rs1 = GET_FIELD(insn, 13, 17); 3364 switch(rs1) { 3365 case 0: /* rdy */ 3366 #ifndef TARGET_SPARC64 3367 case 0x01 ... 0x0e: /* undefined in the SPARCv8 3368 manual, rdy on the microSPARC 3369 II */ 3370 case 0x0f: /* stbar in the SPARCv8 manual, 3371 rdy on the microSPARC II */ 3372 case 0x10 ... 0x1f: /* implementation-dependent in the 3373 SPARCv8 manual, rdy on the 3374 microSPARC II */ 3375 /* Read Asr17 */ 3376 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) { 3377 TCGv t = gen_dest_gpr(dc, rd); 3378 /* Read Asr17 for a Leon3 monoprocessor */ 3379 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1)); 3380 gen_store_gpr(dc, rd, t); 3381 break; 3382 } 3383 #endif 3384 gen_store_gpr(dc, rd, cpu_y); 3385 break; 3386 #ifdef TARGET_SPARC64 3387 case 0x2: /* V9 rdccr */ 3388 update_psr(dc); 3389 gen_helper_rdccr(cpu_dst, cpu_env); 3390 gen_store_gpr(dc, rd, cpu_dst); 3391 break; 3392 case 0x3: /* V9 rdasi */ 3393 tcg_gen_movi_tl(cpu_dst, dc->asi); 3394 gen_store_gpr(dc, rd, cpu_dst); 3395 break; 3396 case 0x4: /* V9 rdtick */ 3397 { 3398 TCGv_ptr r_tickptr; 3399 TCGv_i32 r_const; 3400 3401 r_tickptr = tcg_temp_new_ptr(); 3402 r_const = tcg_const_i32(dc->mem_idx); 3403 tcg_gen_ld_ptr(r_tickptr, cpu_env, 3404 offsetof(CPUSPARCState, tick)); 3405 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 3406 gen_io_start(); 3407 } 3408 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr, 3409 r_const); 3410 tcg_temp_free_ptr(r_tickptr); 3411 tcg_temp_free_i32(r_const); 3412 gen_store_gpr(dc, rd, cpu_dst); 3413 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 3414 gen_io_end(); 3415 } 3416 } 3417 break; 3418 case 0x5: /* V9 rdpc */ 3419 { 3420 TCGv t = gen_dest_gpr(dc, rd); 3421 if (unlikely(AM_CHECK(dc))) { 3422 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL); 3423 } else { 3424 tcg_gen_movi_tl(t, dc->pc); 3425 } 3426 gen_store_gpr(dc, rd, t); 3427 } 3428 break; 3429 case 0x6: /* V9 rdfprs */ 3430 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); 3431 gen_store_gpr(dc, rd, cpu_dst); 3432 break; 3433 case 0xf: /* V9 membar */ 3434 break; /* no effect */ 3435 case 0x13: /* Graphics Status */ 3436 if (gen_trap_ifnofpu(dc)) { 3437 goto jmp_insn; 3438 } 3439 gen_store_gpr(dc, rd, cpu_gsr); 3440 break; 3441 case 0x16: /* Softint */ 3442 tcg_gen_ld32s_tl(cpu_dst, cpu_env, 3443 offsetof(CPUSPARCState, softint)); 3444 gen_store_gpr(dc, rd, cpu_dst); 3445 break; 3446 case 0x17: /* Tick compare */ 3447 gen_store_gpr(dc, rd, cpu_tick_cmpr); 3448 break; 3449 case 0x18: /* System tick */ 3450 { 3451 TCGv_ptr r_tickptr; 3452 TCGv_i32 r_const; 3453 3454 r_tickptr = tcg_temp_new_ptr(); 3455 r_const = tcg_const_i32(dc->mem_idx); 3456 tcg_gen_ld_ptr(r_tickptr, cpu_env, 3457 offsetof(CPUSPARCState, stick)); 3458 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 3459 gen_io_start(); 3460 } 3461 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr, 3462 r_const); 3463 tcg_temp_free_ptr(r_tickptr); 3464 tcg_temp_free_i32(r_const); 3465 gen_store_gpr(dc, rd, cpu_dst); 3466 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 3467 gen_io_end(); 3468 } 3469 } 3470 break; 3471 case 0x19: /* System tick compare */ 3472 gen_store_gpr(dc, rd, cpu_stick_cmpr); 3473 break; 3474 case 0x1a: /* UltraSPARC-T1 Strand status */ 3475 /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe 3476 * this ASR as impl. dep 3477 */ 3478 CHECK_IU_FEATURE(dc, HYPV); 3479 { 3480 TCGv t = gen_dest_gpr(dc, rd); 3481 tcg_gen_movi_tl(t, 1UL); 3482 gen_store_gpr(dc, rd, t); 3483 } 3484 break; 3485 case 0x10: /* Performance Control */ 3486 case 0x11: /* Performance Instrumentation Counter */ 3487 case 0x12: /* Dispatch Control */ 3488 case 0x14: /* Softint set, WO */ 3489 case 0x15: /* Softint clear, WO */ 3490 #endif 3491 default: 3492 goto illegal_insn; 3493 } 3494 #if !defined(CONFIG_USER_ONLY) 3495 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ 3496 #ifndef TARGET_SPARC64 3497 if (!supervisor(dc)) { 3498 goto priv_insn; 3499 } 3500 update_psr(dc); 3501 gen_helper_rdpsr(cpu_dst, cpu_env); 3502 #else 3503 CHECK_IU_FEATURE(dc, HYPV); 3504 if (!hypervisor(dc)) 3505 goto priv_insn; 3506 rs1 = GET_FIELD(insn, 13, 17); 3507 switch (rs1) { 3508 case 0: // hpstate 3509 tcg_gen_ld_i64(cpu_dst, cpu_env, 3510 offsetof(CPUSPARCState, hpstate)); 3511 break; 3512 case 1: // htstate 3513 // gen_op_rdhtstate(); 3514 break; 3515 case 3: // hintp 3516 tcg_gen_mov_tl(cpu_dst, cpu_hintp); 3517 break; 3518 case 5: // htba 3519 tcg_gen_mov_tl(cpu_dst, cpu_htba); 3520 break; 3521 case 6: // hver 3522 tcg_gen_mov_tl(cpu_dst, cpu_hver); 3523 break; 3524 case 31: // hstick_cmpr 3525 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); 3526 break; 3527 default: 3528 goto illegal_insn; 3529 } 3530 #endif 3531 gen_store_gpr(dc, rd, cpu_dst); 3532 break; 3533 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ 3534 if (!supervisor(dc)) { 3535 goto priv_insn; 3536 } 3537 cpu_tmp0 = get_temp_tl(dc); 3538 #ifdef TARGET_SPARC64 3539 rs1 = GET_FIELD(insn, 13, 17); 3540 switch (rs1) { 3541 case 0: // tpc 3542 { 3543 TCGv_ptr r_tsptr; 3544 3545 r_tsptr = tcg_temp_new_ptr(); 3546 gen_load_trap_state_at_tl(r_tsptr, cpu_env); 3547 tcg_gen_ld_tl(cpu_tmp0, r_tsptr, 3548 offsetof(trap_state, tpc)); 3549 tcg_temp_free_ptr(r_tsptr); 3550 } 3551 break; 3552 case 1: // tnpc 3553 { 3554 TCGv_ptr r_tsptr; 3555 3556 r_tsptr = tcg_temp_new_ptr(); 3557 gen_load_trap_state_at_tl(r_tsptr, cpu_env); 3558 tcg_gen_ld_tl(cpu_tmp0, r_tsptr, 3559 offsetof(trap_state, tnpc)); 3560 tcg_temp_free_ptr(r_tsptr); 3561 } 3562 break; 3563 case 2: // tstate 3564 { 3565 TCGv_ptr r_tsptr; 3566 3567 r_tsptr = tcg_temp_new_ptr(); 3568 gen_load_trap_state_at_tl(r_tsptr, cpu_env); 3569 tcg_gen_ld_tl(cpu_tmp0, r_tsptr, 3570 offsetof(trap_state, tstate)); 3571 tcg_temp_free_ptr(r_tsptr); 3572 } 3573 break; 3574 case 3: // tt 3575 { 3576 TCGv_ptr r_tsptr = tcg_temp_new_ptr(); 3577 3578 gen_load_trap_state_at_tl(r_tsptr, cpu_env); 3579 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr, 3580 offsetof(trap_state, tt)); 3581 tcg_temp_free_ptr(r_tsptr); 3582 } 3583 break; 3584 case 4: // tick 3585 { 3586 TCGv_ptr r_tickptr; 3587 TCGv_i32 r_const; 3588 3589 r_tickptr = tcg_temp_new_ptr(); 3590 r_const = tcg_const_i32(dc->mem_idx); 3591 tcg_gen_ld_ptr(r_tickptr, cpu_env, 3592 offsetof(CPUSPARCState, tick)); 3593 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 3594 gen_io_start(); 3595 } 3596 gen_helper_tick_get_count(cpu_tmp0, cpu_env, 3597 r_tickptr, r_const); 3598 tcg_temp_free_ptr(r_tickptr); 3599 tcg_temp_free_i32(r_const); 3600 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 3601 gen_io_end(); 3602 } 3603 } 3604 break; 3605 case 5: // tba 3606 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); 3607 break; 3608 case 6: // pstate 3609 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, 3610 offsetof(CPUSPARCState, pstate)); 3611 break; 3612 case 7: // tl 3613 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, 3614 offsetof(CPUSPARCState, tl)); 3615 break; 3616 case 8: // pil 3617 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, 3618 offsetof(CPUSPARCState, psrpil)); 3619 break; 3620 case 9: // cwp 3621 gen_helper_rdcwp(cpu_tmp0, cpu_env); 3622 break; 3623 case 10: // cansave 3624 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, 3625 offsetof(CPUSPARCState, cansave)); 3626 break; 3627 case 11: // canrestore 3628 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, 3629 offsetof(CPUSPARCState, canrestore)); 3630 break; 3631 case 12: // cleanwin 3632 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, 3633 offsetof(CPUSPARCState, cleanwin)); 3634 break; 3635 case 13: // otherwin 3636 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, 3637 offsetof(CPUSPARCState, otherwin)); 3638 break; 3639 case 14: // wstate 3640 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, 3641 offsetof(CPUSPARCState, wstate)); 3642 break; 3643 case 16: // UA2005 gl 3644 CHECK_IU_FEATURE(dc, GL); 3645 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, 3646 offsetof(CPUSPARCState, gl)); 3647 break; 3648 case 26: // UA2005 strand status 3649 CHECK_IU_FEATURE(dc, HYPV); 3650 if (!hypervisor(dc)) 3651 goto priv_insn; 3652 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); 3653 break; 3654 case 31: // ver 3655 tcg_gen_mov_tl(cpu_tmp0, cpu_ver); 3656 break; 3657 case 15: // fq 3658 default: 3659 goto illegal_insn; 3660 } 3661 #else 3662 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); 3663 #endif 3664 gen_store_gpr(dc, rd, cpu_tmp0); 3665 break; 3666 #endif 3667 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) 3668 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ 3669 #ifdef TARGET_SPARC64 3670 gen_helper_flushw(cpu_env); 3671 #else 3672 if (!supervisor(dc)) 3673 goto priv_insn; 3674 gen_store_gpr(dc, rd, cpu_tbr); 3675 #endif 3676 break; 3677 #endif 3678 } else if (xop == 0x34) { /* FPU Operations */ 3679 if (gen_trap_ifnofpu(dc)) { 3680 goto jmp_insn; 3681 } 3682 gen_op_clear_ieee_excp_and_FTT(); 3683 rs1 = GET_FIELD(insn, 13, 17); 3684 rs2 = GET_FIELD(insn, 27, 31); 3685 xop = GET_FIELD(insn, 18, 26); 3686 3687 switch (xop) { 3688 case 0x1: /* fmovs */ 3689 cpu_src1_32 = gen_load_fpr_F(dc, rs2); 3690 gen_store_fpr_F(dc, rd, cpu_src1_32); 3691 break; 3692 case 0x5: /* fnegs */ 3693 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs); 3694 break; 3695 case 0x9: /* fabss */ 3696 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss); 3697 break; 3698 case 0x29: /* fsqrts */ 3699 CHECK_FPU_FEATURE(dc, FSQRT); 3700 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); 3701 break; 3702 case 0x2a: /* fsqrtd */ 3703 CHECK_FPU_FEATURE(dc, FSQRT); 3704 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); 3705 break; 3706 case 0x2b: /* fsqrtq */ 3707 CHECK_FPU_FEATURE(dc, FLOAT128); 3708 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq); 3709 break; 3710 case 0x41: /* fadds */ 3711 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds); 3712 break; 3713 case 0x42: /* faddd */ 3714 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd); 3715 break; 3716 case 0x43: /* faddq */ 3717 CHECK_FPU_FEATURE(dc, FLOAT128); 3718 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); 3719 break; 3720 case 0x45: /* fsubs */ 3721 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs); 3722 break; 3723 case 0x46: /* fsubd */ 3724 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd); 3725 break; 3726 case 0x47: /* fsubq */ 3727 CHECK_FPU_FEATURE(dc, FLOAT128); 3728 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); 3729 break; 3730 case 0x49: /* fmuls */ 3731 CHECK_FPU_FEATURE(dc, FMUL); 3732 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls); 3733 break; 3734 case 0x4a: /* fmuld */ 3735 CHECK_FPU_FEATURE(dc, FMUL); 3736 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); 3737 break; 3738 case 0x4b: /* fmulq */ 3739 CHECK_FPU_FEATURE(dc, FLOAT128); 3740 CHECK_FPU_FEATURE(dc, FMUL); 3741 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); 3742 break; 3743 case 0x4d: /* fdivs */ 3744 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs); 3745 break; 3746 case 0x4e: /* fdivd */ 3747 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd); 3748 break; 3749 case 0x4f: /* fdivq */ 3750 CHECK_FPU_FEATURE(dc, FLOAT128); 3751 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq); 3752 break; 3753 case 0x69: /* fsmuld */ 3754 CHECK_FPU_FEATURE(dc, FSMULD); 3755 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld); 3756 break; 3757 case 0x6e: /* fdmulq */ 3758 CHECK_FPU_FEATURE(dc, FLOAT128); 3759 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); 3760 break; 3761 case 0xc4: /* fitos */ 3762 gen_fop_FF(dc, rd, rs2, gen_helper_fitos); 3763 break; 3764 case 0xc6: /* fdtos */ 3765 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); 3766 break; 3767 case 0xc7: /* fqtos */ 3768 CHECK_FPU_FEATURE(dc, FLOAT128); 3769 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos); 3770 break; 3771 case 0xc8: /* fitod */ 3772 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod); 3773 break; 3774 case 0xc9: /* fstod */ 3775 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod); 3776 break; 3777 case 0xcb: /* fqtod */ 3778 CHECK_FPU_FEATURE(dc, FLOAT128); 3779 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod); 3780 break; 3781 case 0xcc: /* fitoq */ 3782 CHECK_FPU_FEATURE(dc, FLOAT128); 3783 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq); 3784 break; 3785 case 0xcd: /* fstoq */ 3786 CHECK_FPU_FEATURE(dc, FLOAT128); 3787 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq); 3788 break; 3789 case 0xce: /* fdtoq */ 3790 CHECK_FPU_FEATURE(dc, FLOAT128); 3791 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); 3792 break; 3793 case 0xd1: /* fstoi */ 3794 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi); 3795 break; 3796 case 0xd2: /* fdtoi */ 3797 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi); 3798 break; 3799 case 0xd3: /* fqtoi */ 3800 CHECK_FPU_FEATURE(dc, FLOAT128); 3801 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); 3802 break; 3803 #ifdef TARGET_SPARC64 3804 case 0x2: /* V9 fmovd */ 3805 cpu_src1_64 = gen_load_fpr_D(dc, rs2); 3806 gen_store_fpr_D(dc, rd, cpu_src1_64); 3807 break; 3808 case 0x3: /* V9 fmovq */ 3809 CHECK_FPU_FEATURE(dc, FLOAT128); 3810 gen_move_Q(dc, rd, rs2); 3811 break; 3812 case 0x6: /* V9 fnegd */ 3813 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd); 3814 break; 3815 case 0x7: /* V9 fnegq */ 3816 CHECK_FPU_FEATURE(dc, FLOAT128); 3817 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq); 3818 break; 3819 case 0xa: /* V9 fabsd */ 3820 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd); 3821 break; 3822 case 0xb: /* V9 fabsq */ 3823 CHECK_FPU_FEATURE(dc, FLOAT128); 3824 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); 3825 break; 3826 case 0x81: /* V9 fstox */ 3827 gen_fop_DF(dc, rd, rs2, gen_helper_fstox); 3828 break; 3829 case 0x82: /* V9 fdtox */ 3830 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox); 3831 break; 3832 case 0x83: /* V9 fqtox */ 3833 CHECK_FPU_FEATURE(dc, FLOAT128); 3834 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); 3835 break; 3836 case 0x84: /* V9 fxtos */ 3837 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos); 3838 break; 3839 case 0x88: /* V9 fxtod */ 3840 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod); 3841 break; 3842 case 0x8c: /* V9 fxtoq */ 3843 CHECK_FPU_FEATURE(dc, FLOAT128); 3844 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); 3845 break; 3846 #endif 3847 default: 3848 goto illegal_insn; 3849 } 3850 } else if (xop == 0x35) { /* FPU Operations */ 3851 #ifdef TARGET_SPARC64 3852 int cond; 3853 #endif 3854 if (gen_trap_ifnofpu(dc)) { 3855 goto jmp_insn; 3856 } 3857 gen_op_clear_ieee_excp_and_FTT(); 3858 rs1 = GET_FIELD(insn, 13, 17); 3859 rs2 = GET_FIELD(insn, 27, 31); 3860 xop = GET_FIELD(insn, 18, 26); 3861 3862 #ifdef TARGET_SPARC64 3863 #define FMOVR(sz) \ 3864 do { \ 3865 DisasCompare cmp; \ 3866 cond = GET_FIELD_SP(insn, 10, 12); \ 3867 cpu_src1 = get_src1(dc, insn); \ 3868 gen_compare_reg(&cmp, cond, cpu_src1); \ 3869 gen_fmov##sz(dc, &cmp, rd, rs2); \ 3870 free_compare(&cmp); \ 3871 } while (0) 3872 3873 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */ 3874 FMOVR(s); 3875 break; 3876 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr 3877 FMOVR(d); 3878 break; 3879 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr 3880 CHECK_FPU_FEATURE(dc, FLOAT128); 3881 FMOVR(q); 3882 break; 3883 } 3884 #undef FMOVR 3885 #endif 3886 switch (xop) { 3887 #ifdef TARGET_SPARC64 3888 #define FMOVCC(fcc, sz) \ 3889 do { \ 3890 DisasCompare cmp; \ 3891 cond = GET_FIELD_SP(insn, 14, 17); \ 3892 gen_fcompare(&cmp, fcc, cond); \ 3893 gen_fmov##sz(dc, &cmp, rd, rs2); \ 3894 free_compare(&cmp); \ 3895 } while (0) 3896 3897 case 0x001: /* V9 fmovscc %fcc0 */ 3898 FMOVCC(0, s); 3899 break; 3900 case 0x002: /* V9 fmovdcc %fcc0 */ 3901 FMOVCC(0, d); 3902 break; 3903 case 0x003: /* V9 fmovqcc %fcc0 */ 3904 CHECK_FPU_FEATURE(dc, FLOAT128); 3905 FMOVCC(0, q); 3906 break; 3907 case 0x041: /* V9 fmovscc %fcc1 */ 3908 FMOVCC(1, s); 3909 break; 3910 case 0x042: /* V9 fmovdcc %fcc1 */ 3911 FMOVCC(1, d); 3912 break; 3913 case 0x043: /* V9 fmovqcc %fcc1 */ 3914 CHECK_FPU_FEATURE(dc, FLOAT128); 3915 FMOVCC(1, q); 3916 break; 3917 case 0x081: /* V9 fmovscc %fcc2 */ 3918 FMOVCC(2, s); 3919 break; 3920 case 0x082: /* V9 fmovdcc %fcc2 */ 3921 FMOVCC(2, d); 3922 break; 3923 case 0x083: /* V9 fmovqcc %fcc2 */ 3924 CHECK_FPU_FEATURE(dc, FLOAT128); 3925 FMOVCC(2, q); 3926 break; 3927 case 0x0c1: /* V9 fmovscc %fcc3 */ 3928 FMOVCC(3, s); 3929 break; 3930 case 0x0c2: /* V9 fmovdcc %fcc3 */ 3931 FMOVCC(3, d); 3932 break; 3933 case 0x0c3: /* V9 fmovqcc %fcc3 */ 3934 CHECK_FPU_FEATURE(dc, FLOAT128); 3935 FMOVCC(3, q); 3936 break; 3937 #undef FMOVCC 3938 #define FMOVCC(xcc, sz) \ 3939 do { \ 3940 DisasCompare cmp; \ 3941 cond = GET_FIELD_SP(insn, 14, 17); \ 3942 gen_compare(&cmp, xcc, cond, dc); \ 3943 gen_fmov##sz(dc, &cmp, rd, rs2); \ 3944 free_compare(&cmp); \ 3945 } while (0) 3946 3947 case 0x101: /* V9 fmovscc %icc */ 3948 FMOVCC(0, s); 3949 break; 3950 case 0x102: /* V9 fmovdcc %icc */ 3951 FMOVCC(0, d); 3952 break; 3953 case 0x103: /* V9 fmovqcc %icc */ 3954 CHECK_FPU_FEATURE(dc, FLOAT128); 3955 FMOVCC(0, q); 3956 break; 3957 case 0x181: /* V9 fmovscc %xcc */ 3958 FMOVCC(1, s); 3959 break; 3960 case 0x182: /* V9 fmovdcc %xcc */ 3961 FMOVCC(1, d); 3962 break; 3963 case 0x183: /* V9 fmovqcc %xcc */ 3964 CHECK_FPU_FEATURE(dc, FLOAT128); 3965 FMOVCC(1, q); 3966 break; 3967 #undef FMOVCC 3968 #endif 3969 case 0x51: /* fcmps, V9 %fcc */ 3970 cpu_src1_32 = gen_load_fpr_F(dc, rs1); 3971 cpu_src2_32 = gen_load_fpr_F(dc, rs2); 3972 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32); 3973 break; 3974 case 0x52: /* fcmpd, V9 %fcc */ 3975 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 3976 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 3977 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64); 3978 break; 3979 case 0x53: /* fcmpq, V9 %fcc */ 3980 CHECK_FPU_FEATURE(dc, FLOAT128); 3981 gen_op_load_fpr_QT0(QFPREG(rs1)); 3982 gen_op_load_fpr_QT1(QFPREG(rs2)); 3983 gen_op_fcmpq(rd & 3); 3984 break; 3985 case 0x55: /* fcmpes, V9 %fcc */ 3986 cpu_src1_32 = gen_load_fpr_F(dc, rs1); 3987 cpu_src2_32 = gen_load_fpr_F(dc, rs2); 3988 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32); 3989 break; 3990 case 0x56: /* fcmped, V9 %fcc */ 3991 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 3992 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 3993 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64); 3994 break; 3995 case 0x57: /* fcmpeq, V9 %fcc */ 3996 CHECK_FPU_FEATURE(dc, FLOAT128); 3997 gen_op_load_fpr_QT0(QFPREG(rs1)); 3998 gen_op_load_fpr_QT1(QFPREG(rs2)); 3999 gen_op_fcmpeq(rd & 3); 4000 break; 4001 default: 4002 goto illegal_insn; 4003 } 4004 } else if (xop == 0x2) { 4005 TCGv dst = gen_dest_gpr(dc, rd); 4006 rs1 = GET_FIELD(insn, 13, 17); 4007 if (rs1 == 0) { 4008 /* clr/mov shortcut : or %g0, x, y -> mov x, y */ 4009 if (IS_IMM) { /* immediate */ 4010 simm = GET_FIELDs(insn, 19, 31); 4011 tcg_gen_movi_tl(dst, simm); 4012 gen_store_gpr(dc, rd, dst); 4013 } else { /* register */ 4014 rs2 = GET_FIELD(insn, 27, 31); 4015 if (rs2 == 0) { 4016 tcg_gen_movi_tl(dst, 0); 4017 gen_store_gpr(dc, rd, dst); 4018 } else { 4019 cpu_src2 = gen_load_gpr(dc, rs2); 4020 gen_store_gpr(dc, rd, cpu_src2); 4021 } 4022 } 4023 } else { 4024 cpu_src1 = get_src1(dc, insn); 4025 if (IS_IMM) { /* immediate */ 4026 simm = GET_FIELDs(insn, 19, 31); 4027 tcg_gen_ori_tl(dst, cpu_src1, simm); 4028 gen_store_gpr(dc, rd, dst); 4029 } else { /* register */ 4030 rs2 = GET_FIELD(insn, 27, 31); 4031 if (rs2 == 0) { 4032 /* mov shortcut: or x, %g0, y -> mov x, y */ 4033 gen_store_gpr(dc, rd, cpu_src1); 4034 } else { 4035 cpu_src2 = gen_load_gpr(dc, rs2); 4036 tcg_gen_or_tl(dst, cpu_src1, cpu_src2); 4037 gen_store_gpr(dc, rd, dst); 4038 } 4039 } 4040 } 4041 #ifdef TARGET_SPARC64 4042 } else if (xop == 0x25) { /* sll, V9 sllx */ 4043 cpu_src1 = get_src1(dc, insn); 4044 if (IS_IMM) { /* immediate */ 4045 simm = GET_FIELDs(insn, 20, 31); 4046 if (insn & (1 << 12)) { 4047 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f); 4048 } else { 4049 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f); 4050 } 4051 } else { /* register */ 4052 rs2 = GET_FIELD(insn, 27, 31); 4053 cpu_src2 = gen_load_gpr(dc, rs2); 4054 cpu_tmp0 = get_temp_tl(dc); 4055 if (insn & (1 << 12)) { 4056 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); 4057 } else { 4058 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); 4059 } 4060 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); 4061 } 4062 gen_store_gpr(dc, rd, cpu_dst); 4063 } else if (xop == 0x26) { /* srl, V9 srlx */ 4064 cpu_src1 = get_src1(dc, insn); 4065 if (IS_IMM) { /* immediate */ 4066 simm = GET_FIELDs(insn, 20, 31); 4067 if (insn & (1 << 12)) { 4068 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f); 4069 } else { 4070 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); 4071 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f); 4072 } 4073 } else { /* register */ 4074 rs2 = GET_FIELD(insn, 27, 31); 4075 cpu_src2 = gen_load_gpr(dc, rs2); 4076 cpu_tmp0 = get_temp_tl(dc); 4077 if (insn & (1 << 12)) { 4078 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); 4079 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); 4080 } else { 4081 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); 4082 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); 4083 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); 4084 } 4085 } 4086 gen_store_gpr(dc, rd, cpu_dst); 4087 } else if (xop == 0x27) { /* sra, V9 srax */ 4088 cpu_src1 = get_src1(dc, insn); 4089 if (IS_IMM) { /* immediate */ 4090 simm = GET_FIELDs(insn, 20, 31); 4091 if (insn & (1 << 12)) { 4092 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f); 4093 } else { 4094 tcg_gen_ext32s_i64(cpu_dst, cpu_src1); 4095 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f); 4096 } 4097 } else { /* register */ 4098 rs2 = GET_FIELD(insn, 27, 31); 4099 cpu_src2 = gen_load_gpr(dc, rs2); 4100 cpu_tmp0 = get_temp_tl(dc); 4101 if (insn & (1 << 12)) { 4102 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); 4103 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); 4104 } else { 4105 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); 4106 tcg_gen_ext32s_i64(cpu_dst, cpu_src1); 4107 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); 4108 } 4109 } 4110 gen_store_gpr(dc, rd, cpu_dst); 4111 #endif 4112 } else if (xop < 0x36) { 4113 if (xop < 0x20) { 4114 cpu_src1 = get_src1(dc, insn); 4115 cpu_src2 = get_src2(dc, insn); 4116 switch (xop & ~0x10) { 4117 case 0x0: /* add */ 4118 if (xop & 0x10) { 4119 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); 4120 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); 4121 dc->cc_op = CC_OP_ADD; 4122 } else { 4123 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); 4124 } 4125 break; 4126 case 0x1: /* and */ 4127 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); 4128 if (xop & 0x10) { 4129 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4130 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4131 dc->cc_op = CC_OP_LOGIC; 4132 } 4133 break; 4134 case 0x2: /* or */ 4135 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); 4136 if (xop & 0x10) { 4137 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4138 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4139 dc->cc_op = CC_OP_LOGIC; 4140 } 4141 break; 4142 case 0x3: /* xor */ 4143 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); 4144 if (xop & 0x10) { 4145 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4146 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4147 dc->cc_op = CC_OP_LOGIC; 4148 } 4149 break; 4150 case 0x4: /* sub */ 4151 if (xop & 0x10) { 4152 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); 4153 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); 4154 dc->cc_op = CC_OP_SUB; 4155 } else { 4156 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); 4157 } 4158 break; 4159 case 0x5: /* andn */ 4160 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); 4161 if (xop & 0x10) { 4162 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4163 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4164 dc->cc_op = CC_OP_LOGIC; 4165 } 4166 break; 4167 case 0x6: /* orn */ 4168 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); 4169 if (xop & 0x10) { 4170 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4171 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4172 dc->cc_op = CC_OP_LOGIC; 4173 } 4174 break; 4175 case 0x7: /* xorn */ 4176 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2); 4177 if (xop & 0x10) { 4178 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4179 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4180 dc->cc_op = CC_OP_LOGIC; 4181 } 4182 break; 4183 case 0x8: /* addx, V9 addc */ 4184 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2, 4185 (xop & 0x10)); 4186 break; 4187 #ifdef TARGET_SPARC64 4188 case 0x9: /* V9 mulx */ 4189 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); 4190 break; 4191 #endif 4192 case 0xa: /* umul */ 4193 CHECK_IU_FEATURE(dc, MUL); 4194 gen_op_umul(cpu_dst, cpu_src1, cpu_src2); 4195 if (xop & 0x10) { 4196 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4197 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4198 dc->cc_op = CC_OP_LOGIC; 4199 } 4200 break; 4201 case 0xb: /* smul */ 4202 CHECK_IU_FEATURE(dc, MUL); 4203 gen_op_smul(cpu_dst, cpu_src1, cpu_src2); 4204 if (xop & 0x10) { 4205 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); 4206 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 4207 dc->cc_op = CC_OP_LOGIC; 4208 } 4209 break; 4210 case 0xc: /* subx, V9 subc */ 4211 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, 4212 (xop & 0x10)); 4213 break; 4214 #ifdef TARGET_SPARC64 4215 case 0xd: /* V9 udivx */ 4216 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2); 4217 break; 4218 #endif 4219 case 0xe: /* udiv */ 4220 CHECK_IU_FEATURE(dc, DIV); 4221 if (xop & 0x10) { 4222 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1, 4223 cpu_src2); 4224 dc->cc_op = CC_OP_DIV; 4225 } else { 4226 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1, 4227 cpu_src2); 4228 } 4229 break; 4230 case 0xf: /* sdiv */ 4231 CHECK_IU_FEATURE(dc, DIV); 4232 if (xop & 0x10) { 4233 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1, 4234 cpu_src2); 4235 dc->cc_op = CC_OP_DIV; 4236 } else { 4237 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1, 4238 cpu_src2); 4239 } 4240 break; 4241 default: 4242 goto illegal_insn; 4243 } 4244 gen_store_gpr(dc, rd, cpu_dst); 4245 } else { 4246 cpu_src1 = get_src1(dc, insn); 4247 cpu_src2 = get_src2(dc, insn); 4248 switch (xop) { 4249 case 0x20: /* taddcc */ 4250 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); 4251 gen_store_gpr(dc, rd, cpu_dst); 4252 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); 4253 dc->cc_op = CC_OP_TADD; 4254 break; 4255 case 0x21: /* tsubcc */ 4256 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); 4257 gen_store_gpr(dc, rd, cpu_dst); 4258 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); 4259 dc->cc_op = CC_OP_TSUB; 4260 break; 4261 case 0x22: /* taddcctv */ 4262 gen_helper_taddcctv(cpu_dst, cpu_env, 4263 cpu_src1, cpu_src2); 4264 gen_store_gpr(dc, rd, cpu_dst); 4265 dc->cc_op = CC_OP_TADDTV; 4266 break; 4267 case 0x23: /* tsubcctv */ 4268 gen_helper_tsubcctv(cpu_dst, cpu_env, 4269 cpu_src1, cpu_src2); 4270 gen_store_gpr(dc, rd, cpu_dst); 4271 dc->cc_op = CC_OP_TSUBTV; 4272 break; 4273 case 0x24: /* mulscc */ 4274 update_psr(dc); 4275 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); 4276 gen_store_gpr(dc, rd, cpu_dst); 4277 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); 4278 dc->cc_op = CC_OP_ADD; 4279 break; 4280 #ifndef TARGET_SPARC64 4281 case 0x25: /* sll */ 4282 if (IS_IMM) { /* immediate */ 4283 simm = GET_FIELDs(insn, 20, 31); 4284 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f); 4285 } else { /* register */ 4286 cpu_tmp0 = get_temp_tl(dc); 4287 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); 4288 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); 4289 } 4290 gen_store_gpr(dc, rd, cpu_dst); 4291 break; 4292 case 0x26: /* srl */ 4293 if (IS_IMM) { /* immediate */ 4294 simm = GET_FIELDs(insn, 20, 31); 4295 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f); 4296 } else { /* register */ 4297 cpu_tmp0 = get_temp_tl(dc); 4298 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); 4299 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); 4300 } 4301 gen_store_gpr(dc, rd, cpu_dst); 4302 break; 4303 case 0x27: /* sra */ 4304 if (IS_IMM) { /* immediate */ 4305 simm = GET_FIELDs(insn, 20, 31); 4306 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f); 4307 } else { /* register */ 4308 cpu_tmp0 = get_temp_tl(dc); 4309 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); 4310 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); 4311 } 4312 gen_store_gpr(dc, rd, cpu_dst); 4313 break; 4314 #endif 4315 case 0x30: 4316 { 4317 cpu_tmp0 = get_temp_tl(dc); 4318 switch(rd) { 4319 case 0: /* wry */ 4320 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4321 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); 4322 break; 4323 #ifndef TARGET_SPARC64 4324 case 0x01 ... 0x0f: /* undefined in the 4325 SPARCv8 manual, nop 4326 on the microSPARC 4327 II */ 4328 case 0x10 ... 0x1f: /* implementation-dependent 4329 in the SPARCv8 4330 manual, nop on the 4331 microSPARC II */ 4332 if ((rd == 0x13) && (dc->def->features & 4333 CPU_FEATURE_POWERDOWN)) { 4334 /* LEON3 power-down */ 4335 save_state(dc); 4336 gen_helper_power_down(cpu_env); 4337 } 4338 break; 4339 #else 4340 case 0x2: /* V9 wrccr */ 4341 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4342 gen_helper_wrccr(cpu_env, cpu_tmp0); 4343 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); 4344 dc->cc_op = CC_OP_FLAGS; 4345 break; 4346 case 0x3: /* V9 wrasi */ 4347 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4348 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff); 4349 tcg_gen_st32_tl(cpu_tmp0, cpu_env, 4350 offsetof(CPUSPARCState, asi)); 4351 /* End TB to notice changed ASI. */ 4352 save_state(dc); 4353 gen_op_next_insn(); 4354 tcg_gen_exit_tb(NULL, 0); 4355 dc->base.is_jmp = DISAS_NORETURN; 4356 break; 4357 case 0x6: /* V9 wrfprs */ 4358 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4359 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0); 4360 dc->fprs_dirty = 0; 4361 save_state(dc); 4362 gen_op_next_insn(); 4363 tcg_gen_exit_tb(NULL, 0); 4364 dc->base.is_jmp = DISAS_NORETURN; 4365 break; 4366 case 0xf: /* V9 sir, nop if user */ 4367 #if !defined(CONFIG_USER_ONLY) 4368 if (supervisor(dc)) { 4369 ; // XXX 4370 } 4371 #endif 4372 break; 4373 case 0x13: /* Graphics Status */ 4374 if (gen_trap_ifnofpu(dc)) { 4375 goto jmp_insn; 4376 } 4377 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); 4378 break; 4379 case 0x14: /* Softint set */ 4380 if (!supervisor(dc)) 4381 goto illegal_insn; 4382 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4383 gen_helper_set_softint(cpu_env, cpu_tmp0); 4384 break; 4385 case 0x15: /* Softint clear */ 4386 if (!supervisor(dc)) 4387 goto illegal_insn; 4388 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4389 gen_helper_clear_softint(cpu_env, cpu_tmp0); 4390 break; 4391 case 0x16: /* Softint write */ 4392 if (!supervisor(dc)) 4393 goto illegal_insn; 4394 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4395 gen_helper_write_softint(cpu_env, cpu_tmp0); 4396 break; 4397 case 0x17: /* Tick compare */ 4398 #if !defined(CONFIG_USER_ONLY) 4399 if (!supervisor(dc)) 4400 goto illegal_insn; 4401 #endif 4402 { 4403 TCGv_ptr r_tickptr; 4404 4405 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, 4406 cpu_src2); 4407 r_tickptr = tcg_temp_new_ptr(); 4408 tcg_gen_ld_ptr(r_tickptr, cpu_env, 4409 offsetof(CPUSPARCState, tick)); 4410 if (tb_cflags(dc->base.tb) & 4411 CF_USE_ICOUNT) { 4412 gen_io_start(); 4413 } 4414 gen_helper_tick_set_limit(r_tickptr, 4415 cpu_tick_cmpr); 4416 tcg_temp_free_ptr(r_tickptr); 4417 /* End TB to handle timer interrupt */ 4418 dc->base.is_jmp = DISAS_EXIT; 4419 } 4420 break; 4421 case 0x18: /* System tick */ 4422 #if !defined(CONFIG_USER_ONLY) 4423 if (!supervisor(dc)) 4424 goto illegal_insn; 4425 #endif 4426 { 4427 TCGv_ptr r_tickptr; 4428 4429 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, 4430 cpu_src2); 4431 r_tickptr = tcg_temp_new_ptr(); 4432 tcg_gen_ld_ptr(r_tickptr, cpu_env, 4433 offsetof(CPUSPARCState, stick)); 4434 if (tb_cflags(dc->base.tb) & 4435 CF_USE_ICOUNT) { 4436 gen_io_start(); 4437 } 4438 gen_helper_tick_set_count(r_tickptr, 4439 cpu_tmp0); 4440 tcg_temp_free_ptr(r_tickptr); 4441 /* End TB to handle timer interrupt */ 4442 dc->base.is_jmp = DISAS_EXIT; 4443 } 4444 break; 4445 case 0x19: /* System tick compare */ 4446 #if !defined(CONFIG_USER_ONLY) 4447 if (!supervisor(dc)) 4448 goto illegal_insn; 4449 #endif 4450 { 4451 TCGv_ptr r_tickptr; 4452 4453 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, 4454 cpu_src2); 4455 r_tickptr = tcg_temp_new_ptr(); 4456 tcg_gen_ld_ptr(r_tickptr, cpu_env, 4457 offsetof(CPUSPARCState, stick)); 4458 if (tb_cflags(dc->base.tb) & 4459 CF_USE_ICOUNT) { 4460 gen_io_start(); 4461 } 4462 gen_helper_tick_set_limit(r_tickptr, 4463 cpu_stick_cmpr); 4464 tcg_temp_free_ptr(r_tickptr); 4465 /* End TB to handle timer interrupt */ 4466 dc->base.is_jmp = DISAS_EXIT; 4467 } 4468 break; 4469 4470 case 0x10: /* Performance Control */ 4471 case 0x11: /* Performance Instrumentation 4472 Counter */ 4473 case 0x12: /* Dispatch Control */ 4474 #endif 4475 default: 4476 goto illegal_insn; 4477 } 4478 } 4479 break; 4480 #if !defined(CONFIG_USER_ONLY) 4481 case 0x31: /* wrpsr, V9 saved, restored */ 4482 { 4483 if (!supervisor(dc)) 4484 goto priv_insn; 4485 #ifdef TARGET_SPARC64 4486 switch (rd) { 4487 case 0: 4488 gen_helper_saved(cpu_env); 4489 break; 4490 case 1: 4491 gen_helper_restored(cpu_env); 4492 break; 4493 case 2: /* UA2005 allclean */ 4494 case 3: /* UA2005 otherw */ 4495 case 4: /* UA2005 normalw */ 4496 case 5: /* UA2005 invalw */ 4497 // XXX 4498 default: 4499 goto illegal_insn; 4500 } 4501 #else 4502 cpu_tmp0 = get_temp_tl(dc); 4503 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4504 gen_helper_wrpsr(cpu_env, cpu_tmp0); 4505 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); 4506 dc->cc_op = CC_OP_FLAGS; 4507 save_state(dc); 4508 gen_op_next_insn(); 4509 tcg_gen_exit_tb(NULL, 0); 4510 dc->base.is_jmp = DISAS_NORETURN; 4511 #endif 4512 } 4513 break; 4514 case 0x32: /* wrwim, V9 wrpr */ 4515 { 4516 if (!supervisor(dc)) 4517 goto priv_insn; 4518 cpu_tmp0 = get_temp_tl(dc); 4519 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4520 #ifdef TARGET_SPARC64 4521 switch (rd) { 4522 case 0: // tpc 4523 { 4524 TCGv_ptr r_tsptr; 4525 4526 r_tsptr = tcg_temp_new_ptr(); 4527 gen_load_trap_state_at_tl(r_tsptr, cpu_env); 4528 tcg_gen_st_tl(cpu_tmp0, r_tsptr, 4529 offsetof(trap_state, tpc)); 4530 tcg_temp_free_ptr(r_tsptr); 4531 } 4532 break; 4533 case 1: // tnpc 4534 { 4535 TCGv_ptr r_tsptr; 4536 4537 r_tsptr = tcg_temp_new_ptr(); 4538 gen_load_trap_state_at_tl(r_tsptr, cpu_env); 4539 tcg_gen_st_tl(cpu_tmp0, r_tsptr, 4540 offsetof(trap_state, tnpc)); 4541 tcg_temp_free_ptr(r_tsptr); 4542 } 4543 break; 4544 case 2: // tstate 4545 { 4546 TCGv_ptr r_tsptr; 4547 4548 r_tsptr = tcg_temp_new_ptr(); 4549 gen_load_trap_state_at_tl(r_tsptr, cpu_env); 4550 tcg_gen_st_tl(cpu_tmp0, r_tsptr, 4551 offsetof(trap_state, 4552 tstate)); 4553 tcg_temp_free_ptr(r_tsptr); 4554 } 4555 break; 4556 case 3: // tt 4557 { 4558 TCGv_ptr r_tsptr; 4559 4560 r_tsptr = tcg_temp_new_ptr(); 4561 gen_load_trap_state_at_tl(r_tsptr, cpu_env); 4562 tcg_gen_st32_tl(cpu_tmp0, r_tsptr, 4563 offsetof(trap_state, tt)); 4564 tcg_temp_free_ptr(r_tsptr); 4565 } 4566 break; 4567 case 4: // tick 4568 { 4569 TCGv_ptr r_tickptr; 4570 4571 r_tickptr = tcg_temp_new_ptr(); 4572 tcg_gen_ld_ptr(r_tickptr, cpu_env, 4573 offsetof(CPUSPARCState, tick)); 4574 if (tb_cflags(dc->base.tb) & 4575 CF_USE_ICOUNT) { 4576 gen_io_start(); 4577 } 4578 gen_helper_tick_set_count(r_tickptr, 4579 cpu_tmp0); 4580 tcg_temp_free_ptr(r_tickptr); 4581 /* End TB to handle timer interrupt */ 4582 dc->base.is_jmp = DISAS_EXIT; 4583 } 4584 break; 4585 case 5: // tba 4586 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); 4587 break; 4588 case 6: // pstate 4589 save_state(dc); 4590 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 4591 gen_io_start(); 4592 } 4593 gen_helper_wrpstate(cpu_env, cpu_tmp0); 4594 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 4595 gen_io_end(); 4596 } 4597 dc->npc = DYNAMIC_PC; 4598 break; 4599 case 7: // tl 4600 save_state(dc); 4601 tcg_gen_st32_tl(cpu_tmp0, cpu_env, 4602 offsetof(CPUSPARCState, tl)); 4603 dc->npc = DYNAMIC_PC; 4604 break; 4605 case 8: // pil 4606 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 4607 gen_io_start(); 4608 } 4609 gen_helper_wrpil(cpu_env, cpu_tmp0); 4610 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 4611 gen_io_end(); 4612 } 4613 break; 4614 case 9: // cwp 4615 gen_helper_wrcwp(cpu_env, cpu_tmp0); 4616 break; 4617 case 10: // cansave 4618 tcg_gen_st32_tl(cpu_tmp0, cpu_env, 4619 offsetof(CPUSPARCState, 4620 cansave)); 4621 break; 4622 case 11: // canrestore 4623 tcg_gen_st32_tl(cpu_tmp0, cpu_env, 4624 offsetof(CPUSPARCState, 4625 canrestore)); 4626 break; 4627 case 12: // cleanwin 4628 tcg_gen_st32_tl(cpu_tmp0, cpu_env, 4629 offsetof(CPUSPARCState, 4630 cleanwin)); 4631 break; 4632 case 13: // otherwin 4633 tcg_gen_st32_tl(cpu_tmp0, cpu_env, 4634 offsetof(CPUSPARCState, 4635 otherwin)); 4636 break; 4637 case 14: // wstate 4638 tcg_gen_st32_tl(cpu_tmp0, cpu_env, 4639 offsetof(CPUSPARCState, 4640 wstate)); 4641 break; 4642 case 16: // UA2005 gl 4643 CHECK_IU_FEATURE(dc, GL); 4644 gen_helper_wrgl(cpu_env, cpu_tmp0); 4645 break; 4646 case 26: // UA2005 strand status 4647 CHECK_IU_FEATURE(dc, HYPV); 4648 if (!hypervisor(dc)) 4649 goto priv_insn; 4650 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); 4651 break; 4652 default: 4653 goto illegal_insn; 4654 } 4655 #else 4656 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0); 4657 if (dc->def->nwindows != 32) { 4658 tcg_gen_andi_tl(cpu_wim, cpu_wim, 4659 (1 << dc->def->nwindows) - 1); 4660 } 4661 #endif 4662 } 4663 break; 4664 case 0x33: /* wrtbr, UA2005 wrhpr */ 4665 { 4666 #ifndef TARGET_SPARC64 4667 if (!supervisor(dc)) 4668 goto priv_insn; 4669 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); 4670 #else 4671 CHECK_IU_FEATURE(dc, HYPV); 4672 if (!hypervisor(dc)) 4673 goto priv_insn; 4674 cpu_tmp0 = get_temp_tl(dc); 4675 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); 4676 switch (rd) { 4677 case 0: // hpstate 4678 tcg_gen_st_i64(cpu_tmp0, cpu_env, 4679 offsetof(CPUSPARCState, 4680 hpstate)); 4681 save_state(dc); 4682 gen_op_next_insn(); 4683 tcg_gen_exit_tb(NULL, 0); 4684 dc->base.is_jmp = DISAS_NORETURN; 4685 break; 4686 case 1: // htstate 4687 // XXX gen_op_wrhtstate(); 4688 break; 4689 case 3: // hintp 4690 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); 4691 break; 4692 case 5: // htba 4693 tcg_gen_mov_tl(cpu_htba, cpu_tmp0); 4694 break; 4695 case 31: // hstick_cmpr 4696 { 4697 TCGv_ptr r_tickptr; 4698 4699 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); 4700 r_tickptr = tcg_temp_new_ptr(); 4701 tcg_gen_ld_ptr(r_tickptr, cpu_env, 4702 offsetof(CPUSPARCState, hstick)); 4703 if (tb_cflags(dc->base.tb) & 4704 CF_USE_ICOUNT) { 4705 gen_io_start(); 4706 } 4707 gen_helper_tick_set_limit(r_tickptr, 4708 cpu_hstick_cmpr); 4709 tcg_temp_free_ptr(r_tickptr); 4710 if (tb_cflags(dc->base.tb) & 4711 CF_USE_ICOUNT) { 4712 gen_io_end(); 4713 } 4714 /* End TB to handle timer interrupt */ 4715 dc->base.is_jmp = DISAS_EXIT; 4716 } 4717 break; 4718 case 6: // hver readonly 4719 default: 4720 goto illegal_insn; 4721 } 4722 #endif 4723 } 4724 break; 4725 #endif 4726 #ifdef TARGET_SPARC64 4727 case 0x2c: /* V9 movcc */ 4728 { 4729 int cc = GET_FIELD_SP(insn, 11, 12); 4730 int cond = GET_FIELD_SP(insn, 14, 17); 4731 DisasCompare cmp; 4732 TCGv dst; 4733 4734 if (insn & (1 << 18)) { 4735 if (cc == 0) { 4736 gen_compare(&cmp, 0, cond, dc); 4737 } else if (cc == 2) { 4738 gen_compare(&cmp, 1, cond, dc); 4739 } else { 4740 goto illegal_insn; 4741 } 4742 } else { 4743 gen_fcompare(&cmp, cc, cond); 4744 } 4745 4746 /* The get_src2 above loaded the normal 13-bit 4747 immediate field, not the 11-bit field we have 4748 in movcc. But it did handle the reg case. */ 4749 if (IS_IMM) { 4750 simm = GET_FIELD_SPs(insn, 0, 10); 4751 tcg_gen_movi_tl(cpu_src2, simm); 4752 } 4753 4754 dst = gen_load_gpr(dc, rd); 4755 tcg_gen_movcond_tl(cmp.cond, dst, 4756 cmp.c1, cmp.c2, 4757 cpu_src2, dst); 4758 free_compare(&cmp); 4759 gen_store_gpr(dc, rd, dst); 4760 break; 4761 } 4762 case 0x2d: /* V9 sdivx */ 4763 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2); 4764 gen_store_gpr(dc, rd, cpu_dst); 4765 break; 4766 case 0x2e: /* V9 popc */ 4767 tcg_gen_ctpop_tl(cpu_dst, cpu_src2); 4768 gen_store_gpr(dc, rd, cpu_dst); 4769 break; 4770 case 0x2f: /* V9 movr */ 4771 { 4772 int cond = GET_FIELD_SP(insn, 10, 12); 4773 DisasCompare cmp; 4774 TCGv dst; 4775 4776 gen_compare_reg(&cmp, cond, cpu_src1); 4777 4778 /* The get_src2 above loaded the normal 13-bit 4779 immediate field, not the 10-bit field we have 4780 in movr. But it did handle the reg case. */ 4781 if (IS_IMM) { 4782 simm = GET_FIELD_SPs(insn, 0, 9); 4783 tcg_gen_movi_tl(cpu_src2, simm); 4784 } 4785 4786 dst = gen_load_gpr(dc, rd); 4787 tcg_gen_movcond_tl(cmp.cond, dst, 4788 cmp.c1, cmp.c2, 4789 cpu_src2, dst); 4790 free_compare(&cmp); 4791 gen_store_gpr(dc, rd, dst); 4792 break; 4793 } 4794 #endif 4795 default: 4796 goto illegal_insn; 4797 } 4798 } 4799 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ 4800 #ifdef TARGET_SPARC64 4801 int opf = GET_FIELD_SP(insn, 5, 13); 4802 rs1 = GET_FIELD(insn, 13, 17); 4803 rs2 = GET_FIELD(insn, 27, 31); 4804 if (gen_trap_ifnofpu(dc)) { 4805 goto jmp_insn; 4806 } 4807 4808 switch (opf) { 4809 case 0x000: /* VIS I edge8cc */ 4810 CHECK_FPU_FEATURE(dc, VIS1); 4811 cpu_src1 = gen_load_gpr(dc, rs1); 4812 cpu_src2 = gen_load_gpr(dc, rs2); 4813 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0); 4814 gen_store_gpr(dc, rd, cpu_dst); 4815 break; 4816 case 0x001: /* VIS II edge8n */ 4817 CHECK_FPU_FEATURE(dc, VIS2); 4818 cpu_src1 = gen_load_gpr(dc, rs1); 4819 cpu_src2 = gen_load_gpr(dc, rs2); 4820 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0); 4821 gen_store_gpr(dc, rd, cpu_dst); 4822 break; 4823 case 0x002: /* VIS I edge8lcc */ 4824 CHECK_FPU_FEATURE(dc, VIS1); 4825 cpu_src1 = gen_load_gpr(dc, rs1); 4826 cpu_src2 = gen_load_gpr(dc, rs2); 4827 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1); 4828 gen_store_gpr(dc, rd, cpu_dst); 4829 break; 4830 case 0x003: /* VIS II edge8ln */ 4831 CHECK_FPU_FEATURE(dc, VIS2); 4832 cpu_src1 = gen_load_gpr(dc, rs1); 4833 cpu_src2 = gen_load_gpr(dc, rs2); 4834 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1); 4835 gen_store_gpr(dc, rd, cpu_dst); 4836 break; 4837 case 0x004: /* VIS I edge16cc */ 4838 CHECK_FPU_FEATURE(dc, VIS1); 4839 cpu_src1 = gen_load_gpr(dc, rs1); 4840 cpu_src2 = gen_load_gpr(dc, rs2); 4841 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0); 4842 gen_store_gpr(dc, rd, cpu_dst); 4843 break; 4844 case 0x005: /* VIS II edge16n */ 4845 CHECK_FPU_FEATURE(dc, VIS2); 4846 cpu_src1 = gen_load_gpr(dc, rs1); 4847 cpu_src2 = gen_load_gpr(dc, rs2); 4848 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0); 4849 gen_store_gpr(dc, rd, cpu_dst); 4850 break; 4851 case 0x006: /* VIS I edge16lcc */ 4852 CHECK_FPU_FEATURE(dc, VIS1); 4853 cpu_src1 = gen_load_gpr(dc, rs1); 4854 cpu_src2 = gen_load_gpr(dc, rs2); 4855 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1); 4856 gen_store_gpr(dc, rd, cpu_dst); 4857 break; 4858 case 0x007: /* VIS II edge16ln */ 4859 CHECK_FPU_FEATURE(dc, VIS2); 4860 cpu_src1 = gen_load_gpr(dc, rs1); 4861 cpu_src2 = gen_load_gpr(dc, rs2); 4862 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1); 4863 gen_store_gpr(dc, rd, cpu_dst); 4864 break; 4865 case 0x008: /* VIS I edge32cc */ 4866 CHECK_FPU_FEATURE(dc, VIS1); 4867 cpu_src1 = gen_load_gpr(dc, rs1); 4868 cpu_src2 = gen_load_gpr(dc, rs2); 4869 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0); 4870 gen_store_gpr(dc, rd, cpu_dst); 4871 break; 4872 case 0x009: /* VIS II edge32n */ 4873 CHECK_FPU_FEATURE(dc, VIS2); 4874 cpu_src1 = gen_load_gpr(dc, rs1); 4875 cpu_src2 = gen_load_gpr(dc, rs2); 4876 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0); 4877 gen_store_gpr(dc, rd, cpu_dst); 4878 break; 4879 case 0x00a: /* VIS I edge32lcc */ 4880 CHECK_FPU_FEATURE(dc, VIS1); 4881 cpu_src1 = gen_load_gpr(dc, rs1); 4882 cpu_src2 = gen_load_gpr(dc, rs2); 4883 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1); 4884 gen_store_gpr(dc, rd, cpu_dst); 4885 break; 4886 case 0x00b: /* VIS II edge32ln */ 4887 CHECK_FPU_FEATURE(dc, VIS2); 4888 cpu_src1 = gen_load_gpr(dc, rs1); 4889 cpu_src2 = gen_load_gpr(dc, rs2); 4890 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1); 4891 gen_store_gpr(dc, rd, cpu_dst); 4892 break; 4893 case 0x010: /* VIS I array8 */ 4894 CHECK_FPU_FEATURE(dc, VIS1); 4895 cpu_src1 = gen_load_gpr(dc, rs1); 4896 cpu_src2 = gen_load_gpr(dc, rs2); 4897 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); 4898 gen_store_gpr(dc, rd, cpu_dst); 4899 break; 4900 case 0x012: /* VIS I array16 */ 4901 CHECK_FPU_FEATURE(dc, VIS1); 4902 cpu_src1 = gen_load_gpr(dc, rs1); 4903 cpu_src2 = gen_load_gpr(dc, rs2); 4904 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); 4905 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); 4906 gen_store_gpr(dc, rd, cpu_dst); 4907 break; 4908 case 0x014: /* VIS I array32 */ 4909 CHECK_FPU_FEATURE(dc, VIS1); 4910 cpu_src1 = gen_load_gpr(dc, rs1); 4911 cpu_src2 = gen_load_gpr(dc, rs2); 4912 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); 4913 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); 4914 gen_store_gpr(dc, rd, cpu_dst); 4915 break; 4916 case 0x018: /* VIS I alignaddr */ 4917 CHECK_FPU_FEATURE(dc, VIS1); 4918 cpu_src1 = gen_load_gpr(dc, rs1); 4919 cpu_src2 = gen_load_gpr(dc, rs2); 4920 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0); 4921 gen_store_gpr(dc, rd, cpu_dst); 4922 break; 4923 case 0x01a: /* VIS I alignaddrl */ 4924 CHECK_FPU_FEATURE(dc, VIS1); 4925 cpu_src1 = gen_load_gpr(dc, rs1); 4926 cpu_src2 = gen_load_gpr(dc, rs2); 4927 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1); 4928 gen_store_gpr(dc, rd, cpu_dst); 4929 break; 4930 case 0x019: /* VIS II bmask */ 4931 CHECK_FPU_FEATURE(dc, VIS2); 4932 cpu_src1 = gen_load_gpr(dc, rs1); 4933 cpu_src2 = gen_load_gpr(dc, rs2); 4934 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); 4935 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32); 4936 gen_store_gpr(dc, rd, cpu_dst); 4937 break; 4938 case 0x020: /* VIS I fcmple16 */ 4939 CHECK_FPU_FEATURE(dc, VIS1); 4940 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4941 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4942 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64); 4943 gen_store_gpr(dc, rd, cpu_dst); 4944 break; 4945 case 0x022: /* VIS I fcmpne16 */ 4946 CHECK_FPU_FEATURE(dc, VIS1); 4947 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4948 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4949 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64); 4950 gen_store_gpr(dc, rd, cpu_dst); 4951 break; 4952 case 0x024: /* VIS I fcmple32 */ 4953 CHECK_FPU_FEATURE(dc, VIS1); 4954 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4955 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4956 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64); 4957 gen_store_gpr(dc, rd, cpu_dst); 4958 break; 4959 case 0x026: /* VIS I fcmpne32 */ 4960 CHECK_FPU_FEATURE(dc, VIS1); 4961 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4962 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4963 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64); 4964 gen_store_gpr(dc, rd, cpu_dst); 4965 break; 4966 case 0x028: /* VIS I fcmpgt16 */ 4967 CHECK_FPU_FEATURE(dc, VIS1); 4968 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4969 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4970 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64); 4971 gen_store_gpr(dc, rd, cpu_dst); 4972 break; 4973 case 0x02a: /* VIS I fcmpeq16 */ 4974 CHECK_FPU_FEATURE(dc, VIS1); 4975 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4976 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4977 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64); 4978 gen_store_gpr(dc, rd, cpu_dst); 4979 break; 4980 case 0x02c: /* VIS I fcmpgt32 */ 4981 CHECK_FPU_FEATURE(dc, VIS1); 4982 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4983 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4984 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64); 4985 gen_store_gpr(dc, rd, cpu_dst); 4986 break; 4987 case 0x02e: /* VIS I fcmpeq32 */ 4988 CHECK_FPU_FEATURE(dc, VIS1); 4989 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 4990 cpu_src2_64 = gen_load_fpr_D(dc, rs2); 4991 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); 4992 gen_store_gpr(dc, rd, cpu_dst); 4993 break; 4994 case 0x031: /* VIS I fmul8x16 */ 4995 CHECK_FPU_FEATURE(dc, VIS1); 4996 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16); 4997 break; 4998 case 0x033: /* VIS I fmul8x16au */ 4999 CHECK_FPU_FEATURE(dc, VIS1); 5000 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au); 5001 break; 5002 case 0x035: /* VIS I fmul8x16al */ 5003 CHECK_FPU_FEATURE(dc, VIS1); 5004 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al); 5005 break; 5006 case 0x036: /* VIS I fmul8sux16 */ 5007 CHECK_FPU_FEATURE(dc, VIS1); 5008 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16); 5009 break; 5010 case 0x037: /* VIS I fmul8ulx16 */ 5011 CHECK_FPU_FEATURE(dc, VIS1); 5012 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16); 5013 break; 5014 case 0x038: /* VIS I fmuld8sux16 */ 5015 CHECK_FPU_FEATURE(dc, VIS1); 5016 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16); 5017 break; 5018 case 0x039: /* VIS I fmuld8ulx16 */ 5019 CHECK_FPU_FEATURE(dc, VIS1); 5020 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16); 5021 break; 5022 case 0x03a: /* VIS I fpack32 */ 5023 CHECK_FPU_FEATURE(dc, VIS1); 5024 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); 5025 break; 5026 case 0x03b: /* VIS I fpack16 */ 5027 CHECK_FPU_FEATURE(dc, VIS1); 5028 cpu_src1_64 = gen_load_fpr_D(dc, rs2); 5029 cpu_dst_32 = gen_dest_fpr_F(dc); 5030 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64); 5031 gen_store_fpr_F(dc, rd, cpu_dst_32); 5032 break; 5033 case 0x03d: /* VIS I fpackfix */ 5034 CHECK_FPU_FEATURE(dc, VIS1); 5035 cpu_src1_64 = gen_load_fpr_D(dc, rs2); 5036 cpu_dst_32 = gen_dest_fpr_F(dc); 5037 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); 5038 gen_store_fpr_F(dc, rd, cpu_dst_32); 5039 break; 5040 case 0x03e: /* VIS I pdist */ 5041 CHECK_FPU_FEATURE(dc, VIS1); 5042 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist); 5043 break; 5044 case 0x048: /* VIS I faligndata */ 5045 CHECK_FPU_FEATURE(dc, VIS1); 5046 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); 5047 break; 5048 case 0x04b: /* VIS I fpmerge */ 5049 CHECK_FPU_FEATURE(dc, VIS1); 5050 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); 5051 break; 5052 case 0x04c: /* VIS II bshuffle */ 5053 CHECK_FPU_FEATURE(dc, VIS2); 5054 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); 5055 break; 5056 case 0x04d: /* VIS I fexpand */ 5057 CHECK_FPU_FEATURE(dc, VIS1); 5058 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); 5059 break; 5060 case 0x050: /* VIS I fpadd16 */ 5061 CHECK_FPU_FEATURE(dc, VIS1); 5062 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16); 5063 break; 5064 case 0x051: /* VIS I fpadd16s */ 5065 CHECK_FPU_FEATURE(dc, VIS1); 5066 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s); 5067 break; 5068 case 0x052: /* VIS I fpadd32 */ 5069 CHECK_FPU_FEATURE(dc, VIS1); 5070 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32); 5071 break; 5072 case 0x053: /* VIS I fpadd32s */ 5073 CHECK_FPU_FEATURE(dc, VIS1); 5074 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32); 5075 break; 5076 case 0x054: /* VIS I fpsub16 */ 5077 CHECK_FPU_FEATURE(dc, VIS1); 5078 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16); 5079 break; 5080 case 0x055: /* VIS I fpsub16s */ 5081 CHECK_FPU_FEATURE(dc, VIS1); 5082 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s); 5083 break; 5084 case 0x056: /* VIS I fpsub32 */ 5085 CHECK_FPU_FEATURE(dc, VIS1); 5086 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32); 5087 break; 5088 case 0x057: /* VIS I fpsub32s */ 5089 CHECK_FPU_FEATURE(dc, VIS1); 5090 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32); 5091 break; 5092 case 0x060: /* VIS I fzero */ 5093 CHECK_FPU_FEATURE(dc, VIS1); 5094 cpu_dst_64 = gen_dest_fpr_D(dc, rd); 5095 tcg_gen_movi_i64(cpu_dst_64, 0); 5096 gen_store_fpr_D(dc, rd, cpu_dst_64); 5097 break; 5098 case 0x061: /* VIS I fzeros */ 5099 CHECK_FPU_FEATURE(dc, VIS1); 5100 cpu_dst_32 = gen_dest_fpr_F(dc); 5101 tcg_gen_movi_i32(cpu_dst_32, 0); 5102 gen_store_fpr_F(dc, rd, cpu_dst_32); 5103 break; 5104 case 0x062: /* VIS I fnor */ 5105 CHECK_FPU_FEATURE(dc, VIS1); 5106 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64); 5107 break; 5108 case 0x063: /* VIS I fnors */ 5109 CHECK_FPU_FEATURE(dc, VIS1); 5110 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32); 5111 break; 5112 case 0x064: /* VIS I fandnot2 */ 5113 CHECK_FPU_FEATURE(dc, VIS1); 5114 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64); 5115 break; 5116 case 0x065: /* VIS I fandnot2s */ 5117 CHECK_FPU_FEATURE(dc, VIS1); 5118 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32); 5119 break; 5120 case 0x066: /* VIS I fnot2 */ 5121 CHECK_FPU_FEATURE(dc, VIS1); 5122 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64); 5123 break; 5124 case 0x067: /* VIS I fnot2s */ 5125 CHECK_FPU_FEATURE(dc, VIS1); 5126 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32); 5127 break; 5128 case 0x068: /* VIS I fandnot1 */ 5129 CHECK_FPU_FEATURE(dc, VIS1); 5130 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); 5131 break; 5132 case 0x069: /* VIS I fandnot1s */ 5133 CHECK_FPU_FEATURE(dc, VIS1); 5134 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32); 5135 break; 5136 case 0x06a: /* VIS I fnot1 */ 5137 CHECK_FPU_FEATURE(dc, VIS1); 5138 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64); 5139 break; 5140 case 0x06b: /* VIS I fnot1s */ 5141 CHECK_FPU_FEATURE(dc, VIS1); 5142 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32); 5143 break; 5144 case 0x06c: /* VIS I fxor */ 5145 CHECK_FPU_FEATURE(dc, VIS1); 5146 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); 5147 break; 5148 case 0x06d: /* VIS I fxors */ 5149 CHECK_FPU_FEATURE(dc, VIS1); 5150 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32); 5151 break; 5152 case 0x06e: /* VIS I fnand */ 5153 CHECK_FPU_FEATURE(dc, VIS1); 5154 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64); 5155 break; 5156 case 0x06f: /* VIS I fnands */ 5157 CHECK_FPU_FEATURE(dc, VIS1); 5158 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32); 5159 break; 5160 case 0x070: /* VIS I fand */ 5161 CHECK_FPU_FEATURE(dc, VIS1); 5162 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64); 5163 break; 5164 case 0x071: /* VIS I fands */ 5165 CHECK_FPU_FEATURE(dc, VIS1); 5166 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32); 5167 break; 5168 case 0x072: /* VIS I fxnor */ 5169 CHECK_FPU_FEATURE(dc, VIS1); 5170 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64); 5171 break; 5172 case 0x073: /* VIS I fxnors */ 5173 CHECK_FPU_FEATURE(dc, VIS1); 5174 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32); 5175 break; 5176 case 0x074: /* VIS I fsrc1 */ 5177 CHECK_FPU_FEATURE(dc, VIS1); 5178 cpu_src1_64 = gen_load_fpr_D(dc, rs1); 5179 gen_store_fpr_D(dc, rd, cpu_src1_64); 5180 break; 5181 case 0x075: /* VIS I fsrc1s */ 5182 CHECK_FPU_FEATURE(dc, VIS1); 5183 cpu_src1_32 = gen_load_fpr_F(dc, rs1); 5184 gen_store_fpr_F(dc, rd, cpu_src1_32); 5185 break; 5186 case 0x076: /* VIS I fornot2 */ 5187 CHECK_FPU_FEATURE(dc, VIS1); 5188 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); 5189 break; 5190 case 0x077: /* VIS I fornot2s */ 5191 CHECK_FPU_FEATURE(dc, VIS1); 5192 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32); 5193 break; 5194 case 0x078: /* VIS I fsrc2 */ 5195 CHECK_FPU_FEATURE(dc, VIS1); 5196 cpu_src1_64 = gen_load_fpr_D(dc, rs2); 5197 gen_store_fpr_D(dc, rd, cpu_src1_64); 5198 break; 5199 case 0x079: /* VIS I fsrc2s */ 5200 CHECK_FPU_FEATURE(dc, VIS1); 5201 cpu_src1_32 = gen_load_fpr_F(dc, rs2); 5202 gen_store_fpr_F(dc, rd, cpu_src1_32); 5203 break; 5204 case 0x07a: /* VIS I fornot1 */ 5205 CHECK_FPU_FEATURE(dc, VIS1); 5206 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); 5207 break; 5208 case 0x07b: /* VIS I fornot1s */ 5209 CHECK_FPU_FEATURE(dc, VIS1); 5210 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32); 5211 break; 5212 case 0x07c: /* VIS I for */ 5213 CHECK_FPU_FEATURE(dc, VIS1); 5214 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64); 5215 break; 5216 case 0x07d: /* VIS I fors */ 5217 CHECK_FPU_FEATURE(dc, VIS1); 5218 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32); 5219 break; 5220 case 0x07e: /* VIS I fone */ 5221 CHECK_FPU_FEATURE(dc, VIS1); 5222 cpu_dst_64 = gen_dest_fpr_D(dc, rd); 5223 tcg_gen_movi_i64(cpu_dst_64, -1); 5224 gen_store_fpr_D(dc, rd, cpu_dst_64); 5225 break; 5226 case 0x07f: /* VIS I fones */ 5227 CHECK_FPU_FEATURE(dc, VIS1); 5228 cpu_dst_32 = gen_dest_fpr_F(dc); 5229 tcg_gen_movi_i32(cpu_dst_32, -1); 5230 gen_store_fpr_F(dc, rd, cpu_dst_32); 5231 break; 5232 case 0x080: /* VIS I shutdown */ 5233 case 0x081: /* VIS II siam */ 5234 // XXX 5235 goto illegal_insn; 5236 default: 5237 goto illegal_insn; 5238 } 5239 #else 5240 goto ncp_insn; 5241 #endif 5242 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ 5243 #ifdef TARGET_SPARC64 5244 goto illegal_insn; 5245 #else 5246 goto ncp_insn; 5247 #endif 5248 #ifdef TARGET_SPARC64 5249 } else if (xop == 0x39) { /* V9 return */ 5250 save_state(dc); 5251 cpu_src1 = get_src1(dc, insn); 5252 cpu_tmp0 = get_temp_tl(dc); 5253 if (IS_IMM) { /* immediate */ 5254 simm = GET_FIELDs(insn, 19, 31); 5255 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); 5256 } else { /* register */ 5257 rs2 = GET_FIELD(insn, 27, 31); 5258 if (rs2) { 5259 cpu_src2 = gen_load_gpr(dc, rs2); 5260 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); 5261 } else { 5262 tcg_gen_mov_tl(cpu_tmp0, cpu_src1); 5263 } 5264 } 5265 gen_helper_restore(cpu_env); 5266 gen_mov_pc_npc(dc); 5267 gen_check_align(cpu_tmp0, 3); 5268 tcg_gen_mov_tl(cpu_npc, cpu_tmp0); 5269 dc->npc = DYNAMIC_PC; 5270 goto jmp_insn; 5271 #endif 5272 } else { 5273 cpu_src1 = get_src1(dc, insn); 5274 cpu_tmp0 = get_temp_tl(dc); 5275 if (IS_IMM) { /* immediate */ 5276 simm = GET_FIELDs(insn, 19, 31); 5277 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); 5278 } else { /* register */ 5279 rs2 = GET_FIELD(insn, 27, 31); 5280 if (rs2) { 5281 cpu_src2 = gen_load_gpr(dc, rs2); 5282 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); 5283 } else { 5284 tcg_gen_mov_tl(cpu_tmp0, cpu_src1); 5285 } 5286 } 5287 switch (xop) { 5288 case 0x38: /* jmpl */ 5289 { 5290 TCGv t = gen_dest_gpr(dc, rd); 5291 tcg_gen_movi_tl(t, dc->pc); 5292 gen_store_gpr(dc, rd, t); 5293 5294 gen_mov_pc_npc(dc); 5295 gen_check_align(cpu_tmp0, 3); 5296 gen_address_mask(dc, cpu_tmp0); 5297 tcg_gen_mov_tl(cpu_npc, cpu_tmp0); 5298 dc->npc = DYNAMIC_PC; 5299 } 5300 goto jmp_insn; 5301 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) 5302 case 0x39: /* rett, V9 return */ 5303 { 5304 if (!supervisor(dc)) 5305 goto priv_insn; 5306 gen_mov_pc_npc(dc); 5307 gen_check_align(cpu_tmp0, 3); 5308 tcg_gen_mov_tl(cpu_npc, cpu_tmp0); 5309 dc->npc = DYNAMIC_PC; 5310 gen_helper_rett(cpu_env); 5311 } 5312 goto jmp_insn; 5313 #endif 5314 case 0x3b: /* flush */ 5315 if (!((dc)->def->features & CPU_FEATURE_FLUSH)) 5316 goto unimp_flush; 5317 /* nop */ 5318 break; 5319 case 0x3c: /* save */ 5320 gen_helper_save(cpu_env); 5321 gen_store_gpr(dc, rd, cpu_tmp0); 5322 break; 5323 case 0x3d: /* restore */ 5324 gen_helper_restore(cpu_env); 5325 gen_store_gpr(dc, rd, cpu_tmp0); 5326 break; 5327 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) 5328 case 0x3e: /* V9 done/retry */ 5329 { 5330 switch (rd) { 5331 case 0: 5332 if (!supervisor(dc)) 5333 goto priv_insn; 5334 dc->npc = DYNAMIC_PC; 5335 dc->pc = DYNAMIC_PC; 5336 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 5337 gen_io_start(); 5338 } 5339 gen_helper_done(cpu_env); 5340 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 5341 gen_io_end(); 5342 } 5343 goto jmp_insn; 5344 case 1: 5345 if (!supervisor(dc)) 5346 goto priv_insn; 5347 dc->npc = DYNAMIC_PC; 5348 dc->pc = DYNAMIC_PC; 5349 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 5350 gen_io_start(); 5351 } 5352 gen_helper_retry(cpu_env); 5353 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 5354 gen_io_end(); 5355 } 5356 goto jmp_insn; 5357 default: 5358 goto illegal_insn; 5359 } 5360 } 5361 break; 5362 #endif 5363 default: 5364 goto illegal_insn; 5365 } 5366 } 5367 break; 5368 } 5369 break; 5370 case 3: /* load/store instructions */ 5371 { 5372 unsigned int xop = GET_FIELD(insn, 7, 12); 5373 /* ??? gen_address_mask prevents us from using a source 5374 register directly. Always generate a temporary. */ 5375 TCGv cpu_addr = get_temp_tl(dc); 5376 5377 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn)); 5378 if (xop == 0x3c || xop == 0x3e) { 5379 /* V9 casa/casxa : no offset */ 5380 } else if (IS_IMM) { /* immediate */ 5381 simm = GET_FIELDs(insn, 19, 31); 5382 if (simm != 0) { 5383 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm); 5384 } 5385 } else { /* register */ 5386 rs2 = GET_FIELD(insn, 27, 31); 5387 if (rs2 != 0) { 5388 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2)); 5389 } 5390 } 5391 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || 5392 (xop > 0x17 && xop <= 0x1d ) || 5393 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { 5394 TCGv cpu_val = gen_dest_gpr(dc, rd); 5395 5396 switch (xop) { 5397 case 0x0: /* ld, V9 lduw, load unsigned word */ 5398 gen_address_mask(dc, cpu_addr); 5399 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); 5400 break; 5401 case 0x1: /* ldub, load unsigned byte */ 5402 gen_address_mask(dc, cpu_addr); 5403 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); 5404 break; 5405 case 0x2: /* lduh, load unsigned halfword */ 5406 gen_address_mask(dc, cpu_addr); 5407 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); 5408 break; 5409 case 0x3: /* ldd, load double word */ 5410 if (rd & 1) 5411 goto illegal_insn; 5412 else { 5413 TCGv_i64 t64; 5414 5415 gen_address_mask(dc, cpu_addr); 5416 t64 = tcg_temp_new_i64(); 5417 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx); 5418 tcg_gen_trunc_i64_tl(cpu_val, t64); 5419 tcg_gen_ext32u_tl(cpu_val, cpu_val); 5420 gen_store_gpr(dc, rd + 1, cpu_val); 5421 tcg_gen_shri_i64(t64, t64, 32); 5422 tcg_gen_trunc_i64_tl(cpu_val, t64); 5423 tcg_temp_free_i64(t64); 5424 tcg_gen_ext32u_tl(cpu_val, cpu_val); 5425 } 5426 break; 5427 case 0x9: /* ldsb, load signed byte */ 5428 gen_address_mask(dc, cpu_addr); 5429 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); 5430 break; 5431 case 0xa: /* ldsh, load signed halfword */ 5432 gen_address_mask(dc, cpu_addr); 5433 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); 5434 break; 5435 case 0xd: /* ldstub */ 5436 gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); 5437 break; 5438 case 0x0f: 5439 /* swap, swap register with memory. Also atomically */ 5440 CHECK_IU_FEATURE(dc, SWAP); 5441 cpu_src1 = gen_load_gpr(dc, rd); 5442 gen_swap(dc, cpu_val, cpu_src1, cpu_addr, 5443 dc->mem_idx, MO_TEUL); 5444 break; 5445 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 5446 case 0x10: /* lda, V9 lduwa, load word alternate */ 5447 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); 5448 break; 5449 case 0x11: /* lduba, load unsigned byte alternate */ 5450 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB); 5451 break; 5452 case 0x12: /* lduha, load unsigned halfword alternate */ 5453 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); 5454 break; 5455 case 0x13: /* ldda, load double word alternate */ 5456 if (rd & 1) { 5457 goto illegal_insn; 5458 } 5459 gen_ldda_asi(dc, cpu_addr, insn, rd); 5460 goto skip_move; 5461 case 0x19: /* ldsba, load signed byte alternate */ 5462 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB); 5463 break; 5464 case 0x1a: /* ldsha, load signed halfword alternate */ 5465 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW); 5466 break; 5467 case 0x1d: /* ldstuba -- XXX: should be atomically */ 5468 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn); 5469 break; 5470 case 0x1f: /* swapa, swap reg with alt. memory. Also 5471 atomically */ 5472 CHECK_IU_FEATURE(dc, SWAP); 5473 cpu_src1 = gen_load_gpr(dc, rd); 5474 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn); 5475 break; 5476 5477 #ifndef TARGET_SPARC64 5478 case 0x30: /* ldc */ 5479 case 0x31: /* ldcsr */ 5480 case 0x33: /* lddc */ 5481 goto ncp_insn; 5482 #endif 5483 #endif 5484 #ifdef TARGET_SPARC64 5485 case 0x08: /* V9 ldsw */ 5486 gen_address_mask(dc, cpu_addr); 5487 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); 5488 break; 5489 case 0x0b: /* V9 ldx */ 5490 gen_address_mask(dc, cpu_addr); 5491 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); 5492 break; 5493 case 0x18: /* V9 ldswa */ 5494 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); 5495 break; 5496 case 0x1b: /* V9 ldxa */ 5497 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ); 5498 break; 5499 case 0x2d: /* V9 prefetch, no effect */ 5500 goto skip_move; 5501 case 0x30: /* V9 ldfa */ 5502 if (gen_trap_ifnofpu(dc)) { 5503 goto jmp_insn; 5504 } 5505 gen_ldf_asi(dc, cpu_addr, insn, 4, rd); 5506 gen_update_fprs_dirty(dc, rd); 5507 goto skip_move; 5508 case 0x33: /* V9 lddfa */ 5509 if (gen_trap_ifnofpu(dc)) { 5510 goto jmp_insn; 5511 } 5512 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); 5513 gen_update_fprs_dirty(dc, DFPREG(rd)); 5514 goto skip_move; 5515 case 0x3d: /* V9 prefetcha, no effect */ 5516 goto skip_move; 5517 case 0x32: /* V9 ldqfa */ 5518 CHECK_FPU_FEATURE(dc, FLOAT128); 5519 if (gen_trap_ifnofpu(dc)) { 5520 goto jmp_insn; 5521 } 5522 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd)); 5523 gen_update_fprs_dirty(dc, QFPREG(rd)); 5524 goto skip_move; 5525 #endif 5526 default: 5527 goto illegal_insn; 5528 } 5529 gen_store_gpr(dc, rd, cpu_val); 5530 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 5531 skip_move: ; 5532 #endif 5533 } else if (xop >= 0x20 && xop < 0x24) { 5534 if (gen_trap_ifnofpu(dc)) { 5535 goto jmp_insn; 5536 } 5537 switch (xop) { 5538 case 0x20: /* ldf, load fpreg */ 5539 gen_address_mask(dc, cpu_addr); 5540 cpu_dst_32 = gen_dest_fpr_F(dc); 5541 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, 5542 dc->mem_idx, MO_TEUL); 5543 gen_store_fpr_F(dc, rd, cpu_dst_32); 5544 break; 5545 case 0x21: /* ldfsr, V9 ldxfsr */ 5546 #ifdef TARGET_SPARC64 5547 gen_address_mask(dc, cpu_addr); 5548 if (rd == 1) { 5549 TCGv_i64 t64 = tcg_temp_new_i64(); 5550 tcg_gen_qemu_ld_i64(t64, cpu_addr, 5551 dc->mem_idx, MO_TEQ); 5552 gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64); 5553 tcg_temp_free_i64(t64); 5554 break; 5555 } 5556 #endif 5557 cpu_dst_32 = get_temp_i32(dc); 5558 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, 5559 dc->mem_idx, MO_TEUL); 5560 gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32); 5561 break; 5562 case 0x22: /* ldqf, load quad fpreg */ 5563 CHECK_FPU_FEATURE(dc, FLOAT128); 5564 gen_address_mask(dc, cpu_addr); 5565 cpu_src1_64 = tcg_temp_new_i64(); 5566 tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx, 5567 MO_TEQ | MO_ALIGN_4); 5568 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8); 5569 cpu_src2_64 = tcg_temp_new_i64(); 5570 tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx, 5571 MO_TEQ | MO_ALIGN_4); 5572 gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64); 5573 tcg_temp_free_i64(cpu_src1_64); 5574 tcg_temp_free_i64(cpu_src2_64); 5575 break; 5576 case 0x23: /* lddf, load double fpreg */ 5577 gen_address_mask(dc, cpu_addr); 5578 cpu_dst_64 = gen_dest_fpr_D(dc, rd); 5579 tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx, 5580 MO_TEQ | MO_ALIGN_4); 5581 gen_store_fpr_D(dc, rd, cpu_dst_64); 5582 break; 5583 default: 5584 goto illegal_insn; 5585 } 5586 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || 5587 xop == 0xe || xop == 0x1e) { 5588 TCGv cpu_val = gen_load_gpr(dc, rd); 5589 5590 switch (xop) { 5591 case 0x4: /* st, store word */ 5592 gen_address_mask(dc, cpu_addr); 5593 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); 5594 break; 5595 case 0x5: /* stb, store byte */ 5596 gen_address_mask(dc, cpu_addr); 5597 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); 5598 break; 5599 case 0x6: /* sth, store halfword */ 5600 gen_address_mask(dc, cpu_addr); 5601 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); 5602 break; 5603 case 0x7: /* std, store double word */ 5604 if (rd & 1) 5605 goto illegal_insn; 5606 else { 5607 TCGv_i64 t64; 5608 TCGv lo; 5609 5610 gen_address_mask(dc, cpu_addr); 5611 lo = gen_load_gpr(dc, rd + 1); 5612 t64 = tcg_temp_new_i64(); 5613 tcg_gen_concat_tl_i64(t64, lo, cpu_val); 5614 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx); 5615 tcg_temp_free_i64(t64); 5616 } 5617 break; 5618 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 5619 case 0x14: /* sta, V9 stwa, store word alternate */ 5620 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); 5621 break; 5622 case 0x15: /* stba, store byte alternate */ 5623 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB); 5624 break; 5625 case 0x16: /* stha, store halfword alternate */ 5626 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); 5627 break; 5628 case 0x17: /* stda, store double word alternate */ 5629 if (rd & 1) { 5630 goto illegal_insn; 5631 } 5632 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd); 5633 break; 5634 #endif 5635 #ifdef TARGET_SPARC64 5636 case 0x0e: /* V9 stx */ 5637 gen_address_mask(dc, cpu_addr); 5638 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); 5639 break; 5640 case 0x1e: /* V9 stxa */ 5641 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ); 5642 break; 5643 #endif 5644 default: 5645 goto illegal_insn; 5646 } 5647 } else if (xop > 0x23 && xop < 0x28) { 5648 if (gen_trap_ifnofpu(dc)) { 5649 goto jmp_insn; 5650 } 5651 switch (xop) { 5652 case 0x24: /* stf, store fpreg */ 5653 gen_address_mask(dc, cpu_addr); 5654 cpu_src1_32 = gen_load_fpr_F(dc, rd); 5655 tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr, 5656 dc->mem_idx, MO_TEUL); 5657 break; 5658 case 0x25: /* stfsr, V9 stxfsr */ 5659 { 5660 #ifdef TARGET_SPARC64 5661 gen_address_mask(dc, cpu_addr); 5662 if (rd == 1) { 5663 tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx); 5664 break; 5665 } 5666 #endif 5667 tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx); 5668 } 5669 break; 5670 case 0x26: 5671 #ifdef TARGET_SPARC64 5672 /* V9 stqf, store quad fpreg */ 5673 CHECK_FPU_FEATURE(dc, FLOAT128); 5674 gen_address_mask(dc, cpu_addr); 5675 /* ??? While stqf only requires 4-byte alignment, it is 5676 legal for the cpu to signal the unaligned exception. 5677 The OS trap handler is then required to fix it up. 5678 For qemu, this avoids having to probe the second page 5679 before performing the first write. */ 5680 cpu_src1_64 = gen_load_fpr_Q0(dc, rd); 5681 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, 5682 dc->mem_idx, MO_TEQ | MO_ALIGN_16); 5683 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8); 5684 cpu_src2_64 = gen_load_fpr_Q1(dc, rd); 5685 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, 5686 dc->mem_idx, MO_TEQ); 5687 break; 5688 #else /* !TARGET_SPARC64 */ 5689 /* stdfq, store floating point queue */ 5690 #if defined(CONFIG_USER_ONLY) 5691 goto illegal_insn; 5692 #else 5693 if (!supervisor(dc)) 5694 goto priv_insn; 5695 if (gen_trap_ifnofpu(dc)) { 5696 goto jmp_insn; 5697 } 5698 goto nfq_insn; 5699 #endif 5700 #endif 5701 case 0x27: /* stdf, store double fpreg */ 5702 gen_address_mask(dc, cpu_addr); 5703 cpu_src1_64 = gen_load_fpr_D(dc, rd); 5704 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx, 5705 MO_TEQ | MO_ALIGN_4); 5706 break; 5707 default: 5708 goto illegal_insn; 5709 } 5710 } else if (xop > 0x33 && xop < 0x3f) { 5711 switch (xop) { 5712 #ifdef TARGET_SPARC64 5713 case 0x34: /* V9 stfa */ 5714 if (gen_trap_ifnofpu(dc)) { 5715 goto jmp_insn; 5716 } 5717 gen_stf_asi(dc, cpu_addr, insn, 4, rd); 5718 break; 5719 case 0x36: /* V9 stqfa */ 5720 { 5721 CHECK_FPU_FEATURE(dc, FLOAT128); 5722 if (gen_trap_ifnofpu(dc)) { 5723 goto jmp_insn; 5724 } 5725 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd)); 5726 } 5727 break; 5728 case 0x37: /* V9 stdfa */ 5729 if (gen_trap_ifnofpu(dc)) { 5730 goto jmp_insn; 5731 } 5732 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); 5733 break; 5734 case 0x3e: /* V9 casxa */ 5735 rs2 = GET_FIELD(insn, 27, 31); 5736 cpu_src2 = gen_load_gpr(dc, rs2); 5737 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd); 5738 break; 5739 #else 5740 case 0x34: /* stc */ 5741 case 0x35: /* stcsr */ 5742 case 0x36: /* stdcq */ 5743 case 0x37: /* stdc */ 5744 goto ncp_insn; 5745 #endif 5746 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 5747 case 0x3c: /* V9 or LEON3 casa */ 5748 #ifndef TARGET_SPARC64 5749 CHECK_IU_FEATURE(dc, CASA); 5750 #endif 5751 rs2 = GET_FIELD(insn, 27, 31); 5752 cpu_src2 = gen_load_gpr(dc, rs2); 5753 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); 5754 break; 5755 #endif 5756 default: 5757 goto illegal_insn; 5758 } 5759 } else { 5760 goto illegal_insn; 5761 } 5762 } 5763 break; 5764 } 5765 /* default case for non jump instructions */ 5766 if (dc->npc == DYNAMIC_PC) { 5767 dc->pc = DYNAMIC_PC; 5768 gen_op_next_insn(); 5769 } else if (dc->npc == JUMP_PC) { 5770 /* we can do a static jump */ 5771 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); 5772 dc->base.is_jmp = DISAS_NORETURN; 5773 } else { 5774 dc->pc = dc->npc; 5775 dc->npc = dc->npc + 4; 5776 } 5777 jmp_insn: 5778 goto egress; 5779 illegal_insn: 5780 gen_exception(dc, TT_ILL_INSN); 5781 goto egress; 5782 unimp_flush: 5783 gen_exception(dc, TT_UNIMP_FLUSH); 5784 goto egress; 5785 #if !defined(CONFIG_USER_ONLY) 5786 priv_insn: 5787 gen_exception(dc, TT_PRIV_INSN); 5788 goto egress; 5789 #endif 5790 nfpu_insn: 5791 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); 5792 goto egress; 5793 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) 5794 nfq_insn: 5795 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); 5796 goto egress; 5797 #endif 5798 #ifndef TARGET_SPARC64 5799 ncp_insn: 5800 gen_exception(dc, TT_NCP_INSN); 5801 goto egress; 5802 #endif 5803 egress: 5804 if (dc->n_t32 != 0) { 5805 int i; 5806 for (i = dc->n_t32 - 1; i >= 0; --i) { 5807 tcg_temp_free_i32(dc->t32[i]); 5808 } 5809 dc->n_t32 = 0; 5810 } 5811 if (dc->n_ttl != 0) { 5812 int i; 5813 for (i = dc->n_ttl - 1; i >= 0; --i) { 5814 tcg_temp_free(dc->ttl[i]); 5815 } 5816 dc->n_ttl = 0; 5817 } 5818 } 5819 5820 static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 5821 { 5822 DisasContext *dc = container_of(dcbase, DisasContext, base); 5823 CPUSPARCState *env = cs->env_ptr; 5824 int bound; 5825 5826 dc->pc = dc->base.pc_first; 5827 dc->npc = (target_ulong)dc->base.tb->cs_base; 5828 dc->cc_op = CC_OP_DYNAMIC; 5829 dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK; 5830 dc->def = &env->def; 5831 dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags); 5832 dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags); 5833 #ifndef CONFIG_USER_ONLY 5834 dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0; 5835 #endif 5836 #ifdef TARGET_SPARC64 5837 dc->fprs_dirty = 0; 5838 dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; 5839 #ifndef CONFIG_USER_ONLY 5840 dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0; 5841 #endif 5842 #endif 5843 /* 5844 * if we reach a page boundary, we stop generation so that the 5845 * PC of a TT_TFAULT exception is always in the right page 5846 */ 5847 bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; 5848 dc->base.max_insns = MIN(dc->base.max_insns, bound); 5849 } 5850 5851 static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs) 5852 { 5853 } 5854 5855 static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 5856 { 5857 DisasContext *dc = container_of(dcbase, DisasContext, base); 5858 5859 if (dc->npc & JUMP_PC) { 5860 assert(dc->jump_pc[1] == dc->pc + 4); 5861 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC); 5862 } else { 5863 tcg_gen_insn_start(dc->pc, dc->npc); 5864 } 5865 } 5866 5867 static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 5868 const CPUBreakpoint *bp) 5869 { 5870 DisasContext *dc = container_of(dcbase, DisasContext, base); 5871 5872 if (dc->pc != dc->base.pc_first) { 5873 save_state(dc); 5874 } 5875 gen_helper_debug(cpu_env); 5876 tcg_gen_exit_tb(NULL, 0); 5877 dc->base.is_jmp = DISAS_NORETURN; 5878 /* update pc_next so that the current instruction is included in tb->size */ 5879 dc->base.pc_next += 4; 5880 return true; 5881 } 5882 5883 static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 5884 { 5885 DisasContext *dc = container_of(dcbase, DisasContext, base); 5886 CPUSPARCState *env = cs->env_ptr; 5887 unsigned int insn; 5888 5889 insn = translator_ldl(env, dc->pc); 5890 dc->base.pc_next += 4; 5891 disas_sparc_insn(dc, insn); 5892 5893 if (dc->base.is_jmp == DISAS_NORETURN) { 5894 return; 5895 } 5896 if (dc->pc != dc->base.pc_next) { 5897 dc->base.is_jmp = DISAS_TOO_MANY; 5898 } 5899 } 5900 5901 static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 5902 { 5903 DisasContext *dc = container_of(dcbase, DisasContext, base); 5904 5905 switch (dc->base.is_jmp) { 5906 case DISAS_NEXT: 5907 case DISAS_TOO_MANY: 5908 if (dc->pc != DYNAMIC_PC && 5909 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { 5910 /* static PC and NPC: we can use direct chaining */ 5911 gen_goto_tb(dc, 0, dc->pc, dc->npc); 5912 } else { 5913 if (dc->pc != DYNAMIC_PC) { 5914 tcg_gen_movi_tl(cpu_pc, dc->pc); 5915 } 5916 save_npc(dc); 5917 tcg_gen_exit_tb(NULL, 0); 5918 } 5919 break; 5920 5921 case DISAS_NORETURN: 5922 break; 5923 5924 case DISAS_EXIT: 5925 /* Exit TB */ 5926 save_state(dc); 5927 tcg_gen_exit_tb(NULL, 0); 5928 break; 5929 5930 default: 5931 g_assert_not_reached(); 5932 } 5933 } 5934 5935 static void sparc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 5936 { 5937 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 5938 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 5939 } 5940 5941 static const TranslatorOps sparc_tr_ops = { 5942 .init_disas_context = sparc_tr_init_disas_context, 5943 .tb_start = sparc_tr_tb_start, 5944 .insn_start = sparc_tr_insn_start, 5945 .breakpoint_check = sparc_tr_breakpoint_check, 5946 .translate_insn = sparc_tr_translate_insn, 5947 .tb_stop = sparc_tr_tb_stop, 5948 .disas_log = sparc_tr_disas_log, 5949 }; 5950 5951 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 5952 { 5953 DisasContext dc = {}; 5954 5955 translator_loop(&sparc_tr_ops, &dc.base, cs, tb, max_insns); 5956 } 5957 5958 void sparc_tcg_init(void) 5959 { 5960 static const char gregnames[32][4] = { 5961 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 5962 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", 5963 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 5964 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", 5965 }; 5966 static const char fregnames[32][4] = { 5967 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14", 5968 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30", 5969 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", 5970 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", 5971 }; 5972 5973 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = { 5974 #ifdef TARGET_SPARC64 5975 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" }, 5976 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, 5977 #else 5978 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" }, 5979 #endif 5980 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" }, 5981 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" }, 5982 }; 5983 5984 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = { 5985 #ifdef TARGET_SPARC64 5986 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, 5987 { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" }, 5988 { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" }, 5989 { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr), 5990 "hstick_cmpr" }, 5991 { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" }, 5992 { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" }, 5993 { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" }, 5994 { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" }, 5995 { &cpu_ver, offsetof(CPUSPARCState, version), "ver" }, 5996 #endif 5997 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" }, 5998 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" }, 5999 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" }, 6000 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" }, 6001 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" }, 6002 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" }, 6003 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" }, 6004 { &cpu_y, offsetof(CPUSPARCState, y), "y" }, 6005 #ifndef CONFIG_USER_ONLY 6006 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" }, 6007 #endif 6008 }; 6009 6010 unsigned int i; 6011 6012 cpu_regwptr = tcg_global_mem_new_ptr(cpu_env, 6013 offsetof(CPUSPARCState, regwptr), 6014 "regwptr"); 6015 6016 for (i = 0; i < ARRAY_SIZE(r32); ++i) { 6017 *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name); 6018 } 6019 6020 for (i = 0; i < ARRAY_SIZE(rtl); ++i) { 6021 *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name); 6022 } 6023 6024 cpu_regs[0] = NULL; 6025 for (i = 1; i < 8; ++i) { 6026 cpu_regs[i] = tcg_global_mem_new(cpu_env, 6027 offsetof(CPUSPARCState, gregs[i]), 6028 gregnames[i]); 6029 } 6030 6031 for (i = 8; i < 32; ++i) { 6032 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr, 6033 (i - 8) * sizeof(target_ulong), 6034 gregnames[i]); 6035 } 6036 6037 for (i = 0; i < TARGET_DPREGS; i++) { 6038 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 6039 offsetof(CPUSPARCState, fpr[i]), 6040 fregnames[i]); 6041 } 6042 } 6043 6044 void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb, 6045 target_ulong *data) 6046 { 6047 target_ulong pc = data[0]; 6048 target_ulong npc = data[1]; 6049 6050 env->pc = pc; 6051 if (npc == DYNAMIC_PC) { 6052 /* dynamic NPC: already stored */ 6053 } else if (npc & JUMP_PC) { 6054 /* jump PC: use 'cond' and the jump targets of the translation */ 6055 if (env->cond) { 6056 env->npc = npc & ~3; 6057 } else { 6058 env->npc = pc + 4; 6059 } 6060 } else { 6061 env->npc = npc; 6062 } 6063 } 6064