1 /* 2 * QEMU monitor 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "cpu.h" 26 #include "monitor/monitor.h" 27 #include "monitor/hmp-target.h" 28 #include "monitor/hmp.h" 29 30 31 void hmp_info_tlb(Monitor *mon, const QDict *qdict) 32 { 33 CPUArchState *env1 = mon_get_cpu_env(mon); 34 35 if (!env1) { 36 monitor_printf(mon, "No CPU available\n"); 37 return; 38 } 39 dump_mmu(env1); 40 } 41 42 #ifndef TARGET_SPARC64 43 static target_long monitor_get_psr(Monitor *mon, const struct MonitorDef *md, 44 int val) 45 { 46 CPUArchState *env = mon_get_cpu_env(mon); 47 48 return cpu_get_psr(env); 49 } 50 #endif 51 52 static target_long monitor_get_reg(Monitor *mon, const struct MonitorDef *md, 53 int val) 54 { 55 CPUArchState *env = mon_get_cpu_env(mon); 56 return env->regwptr[val]; 57 } 58 59 const MonitorDef monitor_defs[] = { 60 { "g0", offsetof(CPUSPARCState, gregs[0]) }, 61 { "g1", offsetof(CPUSPARCState, gregs[1]) }, 62 { "g2", offsetof(CPUSPARCState, gregs[2]) }, 63 { "g3", offsetof(CPUSPARCState, gregs[3]) }, 64 { "g4", offsetof(CPUSPARCState, gregs[4]) }, 65 { "g5", offsetof(CPUSPARCState, gregs[5]) }, 66 { "g6", offsetof(CPUSPARCState, gregs[6]) }, 67 { "g7", offsetof(CPUSPARCState, gregs[7]) }, 68 { "o0", 0, monitor_get_reg }, 69 { "o1", 1, monitor_get_reg }, 70 { "o2", 2, monitor_get_reg }, 71 { "o3", 3, monitor_get_reg }, 72 { "o4", 4, monitor_get_reg }, 73 { "o5", 5, monitor_get_reg }, 74 { "o6", 6, monitor_get_reg }, 75 { "o7", 7, monitor_get_reg }, 76 { "l0", 8, monitor_get_reg }, 77 { "l1", 9, monitor_get_reg }, 78 { "l2", 10, monitor_get_reg }, 79 { "l3", 11, monitor_get_reg }, 80 { "l4", 12, monitor_get_reg }, 81 { "l5", 13, monitor_get_reg }, 82 { "l6", 14, monitor_get_reg }, 83 { "l7", 15, monitor_get_reg }, 84 { "i0", 16, monitor_get_reg }, 85 { "i1", 17, monitor_get_reg }, 86 { "i2", 18, monitor_get_reg }, 87 { "i3", 19, monitor_get_reg }, 88 { "i4", 20, monitor_get_reg }, 89 { "i5", 21, monitor_get_reg }, 90 { "i6", 22, monitor_get_reg }, 91 { "i7", 23, monitor_get_reg }, 92 { "pc", offsetof(CPUSPARCState, pc) }, 93 { "npc", offsetof(CPUSPARCState, npc) }, 94 { "y", offsetof(CPUSPARCState, y) }, 95 #ifndef TARGET_SPARC64 96 { "psr", 0, &monitor_get_psr, }, 97 { "wim", offsetof(CPUSPARCState, wim) }, 98 #endif 99 { "tbr", offsetof(CPUSPARCState, tbr) }, 100 { "fsr", offsetof(CPUSPARCState, fsr) }, 101 { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) }, 102 { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) }, 103 { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) }, 104 { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) }, 105 { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) }, 106 { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) }, 107 { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) }, 108 { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) }, 109 { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) }, 110 { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) }, 111 { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) }, 112 { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) }, 113 { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) }, 114 { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) }, 115 { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) }, 116 { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) }, 117 { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) }, 118 { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) }, 119 { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) }, 120 { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) }, 121 { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) }, 122 { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) }, 123 { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) }, 124 { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) }, 125 { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) }, 126 { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) }, 127 { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) }, 128 { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) }, 129 { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) }, 130 { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) }, 131 { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) }, 132 { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) }, 133 #ifdef TARGET_SPARC64 134 { "f32", offsetof(CPUSPARCState, fpr[16]) }, 135 { "f34", offsetof(CPUSPARCState, fpr[17]) }, 136 { "f36", offsetof(CPUSPARCState, fpr[18]) }, 137 { "f38", offsetof(CPUSPARCState, fpr[19]) }, 138 { "f40", offsetof(CPUSPARCState, fpr[20]) }, 139 { "f42", offsetof(CPUSPARCState, fpr[21]) }, 140 { "f44", offsetof(CPUSPARCState, fpr[22]) }, 141 { "f46", offsetof(CPUSPARCState, fpr[23]) }, 142 { "f48", offsetof(CPUSPARCState, fpr[24]) }, 143 { "f50", offsetof(CPUSPARCState, fpr[25]) }, 144 { "f52", offsetof(CPUSPARCState, fpr[26]) }, 145 { "f54", offsetof(CPUSPARCState, fpr[27]) }, 146 { "f56", offsetof(CPUSPARCState, fpr[28]) }, 147 { "f58", offsetof(CPUSPARCState, fpr[29]) }, 148 { "f60", offsetof(CPUSPARCState, fpr[30]) }, 149 { "f62", offsetof(CPUSPARCState, fpr[31]) }, 150 { "asi", offsetof(CPUSPARCState, asi) }, 151 { "pstate", offsetof(CPUSPARCState, pstate) }, 152 { "cansave", offsetof(CPUSPARCState, cansave) }, 153 { "canrestore", offsetof(CPUSPARCState, canrestore) }, 154 { "otherwin", offsetof(CPUSPARCState, otherwin) }, 155 { "wstate", offsetof(CPUSPARCState, wstate) }, 156 { "cleanwin", offsetof(CPUSPARCState, cleanwin) }, 157 { "fprs", offsetof(CPUSPARCState, fprs), NULL, MD_I32 }, 158 #endif 159 { NULL }, 160 }; 161 162 const MonitorDef *target_monitor_defs(void) 163 { 164 return monitor_defs; 165 } 166