1 /* 2 * Helpers for loads and stores 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "tcg/tcg.h" 24 #include "exec/helper-proto.h" 25 #include "exec/exec-all.h" 26 #include "exec/cpu_ldst.h" 27 #include "asi.h" 28 29 //#define DEBUG_MMU 30 //#define DEBUG_MXCC 31 //#define DEBUG_UNASSIGNED 32 //#define DEBUG_ASI 33 //#define DEBUG_CACHE_CONTROL 34 35 #ifdef DEBUG_MMU 36 #define DPRINTF_MMU(fmt, ...) \ 37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) 38 #else 39 #define DPRINTF_MMU(fmt, ...) do {} while (0) 40 #endif 41 42 #ifdef DEBUG_MXCC 43 #define DPRINTF_MXCC(fmt, ...) \ 44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) 45 #else 46 #define DPRINTF_MXCC(fmt, ...) do {} while (0) 47 #endif 48 49 #ifdef DEBUG_ASI 50 #define DPRINTF_ASI(fmt, ...) \ 51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) 52 #endif 53 54 #ifdef DEBUG_CACHE_CONTROL 55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \ 56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) 57 #else 58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) 59 #endif 60 61 #ifdef TARGET_SPARC64 62 #ifndef TARGET_ABI32 63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM) 64 #else 65 #define AM_CHECK(env1) (1) 66 #endif 67 #endif 68 69 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 70 /* Calculates TSB pointer value for fault page size 71 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers 72 * UA2005 holds the page size configuration in mmu_ctx registers */ 73 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, 74 const SparcV9MMU *mmu, const int idx) 75 { 76 uint64_t tsb_register; 77 int page_size; 78 if (cpu_has_hypervisor(env)) { 79 int tsb_index = 0; 80 int ctx = mmu->tag_access & 0x1fffULL; 81 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; 82 tsb_index = idx; 83 tsb_index |= ctx ? 2 : 0; 84 page_size = idx ? ctx_register >> 8 : ctx_register; 85 page_size &= 7; 86 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; 87 } else { 88 page_size = idx; 89 tsb_register = mmu->tsb; 90 } 91 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; 92 int tsb_size = tsb_register & 0xf; 93 94 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size; 95 96 /* move va bits to correct position, 97 * the context bits will be masked out later */ 98 uint64_t va = mmu->tag_access >> (3 * page_size + 9); 99 100 /* calculate tsb_base mask and adjust va if split is in use */ 101 if (tsb_split) { 102 if (idx == 0) { 103 va &= ~(1ULL << (13 + tsb_size)); 104 } else { 105 va |= (1ULL << (13 + tsb_size)); 106 } 107 tsb_base_mask <<= 1; 108 } 109 110 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; 111 } 112 113 /* Calculates tag target register value by reordering bits 114 in tag access register */ 115 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) 116 { 117 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); 118 } 119 120 static void replace_tlb_entry(SparcTLBEntry *tlb, 121 uint64_t tlb_tag, uint64_t tlb_tte, 122 CPUSPARCState *env) 123 { 124 target_ulong mask, size, va, offset; 125 126 /* flush page range if translation is valid */ 127 if (TTE_IS_VALID(tlb->tte)) { 128 CPUState *cs = env_cpu(env); 129 130 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); 131 mask = 1ULL + ~size; 132 133 va = tlb->tag & mask; 134 135 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { 136 tlb_flush_page(cs, va + offset); 137 } 138 } 139 140 tlb->tag = tlb_tag; 141 tlb->tte = tlb_tte; 142 } 143 144 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, 145 const char *strmmu, CPUSPARCState *env1) 146 { 147 unsigned int i; 148 target_ulong mask; 149 uint64_t context; 150 151 int is_demap_context = (demap_addr >> 6) & 1; 152 153 /* demap context */ 154 switch ((demap_addr >> 4) & 3) { 155 case 0: /* primary */ 156 context = env1->dmmu.mmu_primary_context; 157 break; 158 case 1: /* secondary */ 159 context = env1->dmmu.mmu_secondary_context; 160 break; 161 case 2: /* nucleus */ 162 context = 0; 163 break; 164 case 3: /* reserved */ 165 default: 166 return; 167 } 168 169 for (i = 0; i < 64; i++) { 170 if (TTE_IS_VALID(tlb[i].tte)) { 171 172 if (is_demap_context) { 173 /* will remove non-global entries matching context value */ 174 if (TTE_IS_GLOBAL(tlb[i].tte) || 175 !tlb_compare_context(&tlb[i], context)) { 176 continue; 177 } 178 } else { 179 /* demap page 180 will remove any entry matching VA */ 181 mask = 0xffffffffffffe000ULL; 182 mask <<= 3 * ((tlb[i].tte >> 61) & 3); 183 184 if (!compare_masked(demap_addr, tlb[i].tag, mask)) { 185 continue; 186 } 187 188 /* entry should be global or matching context value */ 189 if (!TTE_IS_GLOBAL(tlb[i].tte) && 190 !tlb_compare_context(&tlb[i], context)) { 191 continue; 192 } 193 } 194 195 replace_tlb_entry(&tlb[i], 0, 0, env1); 196 #ifdef DEBUG_MMU 197 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); 198 dump_mmu(env1); 199 #endif 200 } 201 } 202 } 203 204 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState *env, uint64_t tag, 205 uint64_t sun4v_tte) 206 { 207 uint64_t sun4u_tte; 208 if (!(cpu_has_hypervisor(env) && (tag & TLB_UST1_IS_SUN4V_BIT))) { 209 /* is already in the sun4u format */ 210 return sun4v_tte; 211 } 212 sun4u_tte = TTE_PA(sun4v_tte) | (sun4v_tte & TTE_VALID_BIT); 213 sun4u_tte |= (sun4v_tte & 3ULL) << 61; /* TTE_PGSIZE */ 214 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_NFO_BIT_UA2005, TTE_NFO_BIT); 215 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_USED_BIT_UA2005, TTE_USED_BIT); 216 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_W_OK_BIT_UA2005, TTE_W_OK_BIT); 217 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_SIDEEFFECT_BIT_UA2005, 218 TTE_SIDEEFFECT_BIT); 219 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_PRIV_BIT_UA2005, TTE_PRIV_BIT); 220 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_LOCKED_BIT_UA2005, TTE_LOCKED_BIT); 221 return sun4u_tte; 222 } 223 224 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, 225 uint64_t tlb_tag, uint64_t tlb_tte, 226 const char *strmmu, CPUSPARCState *env1, 227 uint64_t addr) 228 { 229 unsigned int i, replace_used; 230 231 tlb_tte = sun4v_tte_to_sun4u(env1, addr, tlb_tte); 232 if (cpu_has_hypervisor(env1)) { 233 uint64_t new_vaddr = tlb_tag & ~0x1fffULL; 234 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte); 235 uint32_t new_ctx = tlb_tag & 0x1fffU; 236 for (i = 0; i < 64; i++) { 237 uint32_t ctx = tlb[i].tag & 0x1fffU; 238 /* check if new mapping overlaps an existing one */ 239 if (new_ctx == ctx) { 240 uint64_t vaddr = tlb[i].tag & ~0x1fffULL; 241 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte); 242 if (new_vaddr == vaddr 243 || (new_vaddr < vaddr + size 244 && vaddr < new_vaddr + new_size)) { 245 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, 246 new_vaddr); 247 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 248 return; 249 } 250 } 251 252 } 253 } 254 /* Try replacing invalid entry */ 255 for (i = 0; i < 64; i++) { 256 if (!TTE_IS_VALID(tlb[i].tte)) { 257 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 258 #ifdef DEBUG_MMU 259 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); 260 dump_mmu(env1); 261 #endif 262 return; 263 } 264 } 265 266 /* All entries are valid, try replacing unlocked entry */ 267 268 for (replace_used = 0; replace_used < 2; ++replace_used) { 269 270 /* Used entries are not replaced on first pass */ 271 272 for (i = 0; i < 64; i++) { 273 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) { 274 275 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 276 #ifdef DEBUG_MMU 277 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", 278 strmmu, (replace_used ? "used" : "unused"), i); 279 dump_mmu(env1); 280 #endif 281 return; 282 } 283 } 284 285 /* Now reset used bit and search for unused entries again */ 286 287 for (i = 0; i < 64; i++) { 288 TTE_SET_UNUSED(tlb[i].tte); 289 } 290 } 291 292 #ifdef DEBUG_MMU 293 DPRINTF_MMU("%s lru replacement: no free entries available, " 294 "replacing the last one\n", strmmu); 295 #endif 296 /* corner case: the last entry is replaced anyway */ 297 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1); 298 } 299 300 #endif 301 302 #ifdef TARGET_SPARC64 303 /* returns true if access using this ASI is to have address translated by MMU 304 otherwise access is to raw physical address */ 305 /* TODO: check sparc32 bits */ 306 static inline int is_translating_asi(int asi) 307 { 308 /* Ultrasparc IIi translating asi 309 - note this list is defined by cpu implementation 310 */ 311 switch (asi) { 312 case 0x04 ... 0x11: 313 case 0x16 ... 0x19: 314 case 0x1E ... 0x1F: 315 case 0x24 ... 0x2C: 316 case 0x70 ... 0x73: 317 case 0x78 ... 0x79: 318 case 0x80 ... 0xFF: 319 return 1; 320 321 default: 322 return 0; 323 } 324 } 325 326 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr) 327 { 328 if (AM_CHECK(env1)) { 329 addr &= 0xffffffffULL; 330 } 331 return addr; 332 } 333 334 static inline target_ulong asi_address_mask(CPUSPARCState *env, 335 int asi, target_ulong addr) 336 { 337 if (is_translating_asi(asi)) { 338 addr = address_mask(env, addr); 339 } 340 return addr; 341 } 342 343 #ifndef CONFIG_USER_ONLY 344 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra) 345 { 346 /* ASIs >= 0x80 are user mode. 347 * ASIs >= 0x30 are hyper mode (or super if hyper is not available). 348 * ASIs <= 0x2f are super mode. 349 */ 350 if (asi < 0x80 351 && !cpu_hypervisor_mode(env) 352 && (!cpu_supervisor_mode(env) 353 || (asi >= 0x30 && cpu_has_hypervisor(env)))) { 354 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra); 355 } 356 } 357 #endif /* !CONFIG_USER_ONLY */ 358 #endif 359 360 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) 361 static void do_check_align(CPUSPARCState *env, target_ulong addr, 362 uint32_t align, uintptr_t ra) 363 { 364 if (addr & align) { 365 cpu_raise_exception_ra(env, TT_UNALIGNED, ra); 366 } 367 } 368 #endif 369 370 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ 371 defined(DEBUG_MXCC) 372 static void dump_mxcc(CPUSPARCState *env) 373 { 374 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 375 "\n", 376 env->mxccdata[0], env->mxccdata[1], 377 env->mxccdata[2], env->mxccdata[3]); 378 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 379 "\n" 380 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 381 "\n", 382 env->mxccregs[0], env->mxccregs[1], 383 env->mxccregs[2], env->mxccregs[3], 384 env->mxccregs[4], env->mxccregs[5], 385 env->mxccregs[6], env->mxccregs[7]); 386 } 387 #endif 388 389 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \ 390 && defined(DEBUG_ASI) 391 static void dump_asi(const char *txt, target_ulong addr, int asi, int size, 392 uint64_t r1) 393 { 394 switch (size) { 395 case 1: 396 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, 397 addr, asi, r1 & 0xff); 398 break; 399 case 2: 400 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, 401 addr, asi, r1 & 0xffff); 402 break; 403 case 4: 404 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, 405 addr, asi, r1 & 0xffffffff); 406 break; 407 case 8: 408 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, 409 addr, asi, r1); 410 break; 411 } 412 } 413 #endif 414 415 #ifndef CONFIG_USER_ONLY 416 #ifndef TARGET_SPARC64 417 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 418 bool is_write, bool is_exec, int is_asi, 419 unsigned size, uintptr_t retaddr) 420 { 421 CPUSPARCState *env = cpu_env(cs); 422 int fault_type; 423 424 #ifdef DEBUG_UNASSIGNED 425 if (is_asi) { 426 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 427 " asi 0x%02x from " TARGET_FMT_lx "\n", 428 is_exec ? "exec" : is_write ? "write" : "read", size, 429 size == 1 ? "" : "s", addr, is_asi, env->pc); 430 } else { 431 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 432 " from " TARGET_FMT_lx "\n", 433 is_exec ? "exec" : is_write ? "write" : "read", size, 434 size == 1 ? "" : "s", addr, env->pc); 435 } 436 #endif 437 /* Don't overwrite translation and access faults */ 438 fault_type = (env->mmuregs[3] & 0x1c) >> 2; 439 if ((fault_type > 4) || (fault_type == 0)) { 440 env->mmuregs[3] = 0; /* Fault status register */ 441 if (is_asi) { 442 env->mmuregs[3] |= 1 << 16; 443 } 444 if (env->psrs) { 445 env->mmuregs[3] |= 1 << 5; 446 } 447 if (is_exec) { 448 env->mmuregs[3] |= 1 << 6; 449 } 450 if (is_write) { 451 env->mmuregs[3] |= 1 << 7; 452 } 453 env->mmuregs[3] |= (5 << 2) | 2; 454 /* SuperSPARC will never place instruction fault addresses in the FAR */ 455 if (!is_exec) { 456 env->mmuregs[4] = addr; /* Fault address register */ 457 } 458 } 459 /* overflow (same type fault was not read before another fault) */ 460 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { 461 env->mmuregs[3] |= 1; 462 } 463 464 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { 465 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS; 466 cpu_raise_exception_ra(env, tt, retaddr); 467 } 468 469 /* 470 * flush neverland mappings created during no-fault mode, 471 * so the sequential MMU faults report proper fault types 472 */ 473 if (env->mmuregs[0] & MMU_NF) { 474 tlb_flush(cs); 475 } 476 } 477 #else 478 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 479 bool is_write, bool is_exec, int is_asi, 480 unsigned size, uintptr_t retaddr) 481 { 482 CPUSPARCState *env = cpu_env(cs); 483 484 #ifdef DEBUG_UNASSIGNED 485 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx 486 "\n", addr, env->pc); 487 #endif 488 489 if (is_exec) { /* XXX has_hypervisor */ 490 if (env->lsu & (IMMU_E)) { 491 cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr); 492 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 493 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr); 494 } 495 } else { 496 if (env->lsu & (DMMU_E)) { 497 cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr); 498 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 499 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr); 500 } 501 } 502 } 503 #endif 504 #endif 505 506 #ifndef TARGET_SPARC64 507 #ifndef CONFIG_USER_ONLY 508 509 510 /* Leon3 cache control */ 511 512 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr, 513 uint64_t val, int size) 514 { 515 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", 516 addr, val, size); 517 518 if (size != 4) { 519 DPRINTF_CACHE_CONTROL("32bits only\n"); 520 return; 521 } 522 523 switch (addr) { 524 case 0x00: /* Cache control */ 525 526 /* These values must always be read as zeros */ 527 val &= ~CACHE_CTRL_FD; 528 val &= ~CACHE_CTRL_FI; 529 val &= ~CACHE_CTRL_IB; 530 val &= ~CACHE_CTRL_IP; 531 val &= ~CACHE_CTRL_DP; 532 533 env->cache_control = val; 534 break; 535 case 0x04: /* Instruction cache configuration */ 536 case 0x08: /* Data cache configuration */ 537 /* Read Only */ 538 break; 539 default: 540 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr); 541 break; 542 }; 543 } 544 545 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr, 546 int size) 547 { 548 uint64_t ret = 0; 549 550 if (size != 4) { 551 DPRINTF_CACHE_CONTROL("32bits only\n"); 552 return 0; 553 } 554 555 switch (addr) { 556 case 0x00: /* Cache control */ 557 ret = env->cache_control; 558 break; 559 560 /* Configuration registers are read and only always keep those 561 predefined values */ 562 563 case 0x04: /* Instruction cache configuration */ 564 ret = 0x10220000; 565 break; 566 case 0x08: /* Data cache configuration */ 567 ret = 0x18220000; 568 break; 569 default: 570 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr); 571 break; 572 }; 573 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", 574 addr, ret, size); 575 return ret; 576 } 577 578 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 579 int asi, uint32_t memop) 580 { 581 int size = 1 << (memop & MO_SIZE); 582 int sign = memop & MO_SIGN; 583 CPUState *cs = env_cpu(env); 584 uint64_t ret = 0; 585 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) 586 uint32_t last_addr = addr; 587 #endif 588 589 do_check_align(env, addr, size - 1, GETPC()); 590 switch (asi) { 591 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 592 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 593 switch (addr) { 594 case 0x00: /* Leon3 Cache Control */ 595 case 0x08: /* Leon3 Instruction Cache config */ 596 case 0x0C: /* Leon3 Date Cache config */ 597 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 598 ret = leon3_cache_control_ld(env, addr, size); 599 } 600 break; 601 case 0x01c00a00: /* MXCC control register */ 602 if (size == 8) { 603 ret = env->mxccregs[3]; 604 } else { 605 qemu_log_mask(LOG_UNIMP, 606 "%08x: unimplemented access size: %d\n", addr, 607 size); 608 } 609 break; 610 case 0x01c00a04: /* MXCC control register */ 611 if (size == 4) { 612 ret = env->mxccregs[3]; 613 } else { 614 qemu_log_mask(LOG_UNIMP, 615 "%08x: unimplemented access size: %d\n", addr, 616 size); 617 } 618 break; 619 case 0x01c00c00: /* Module reset register */ 620 if (size == 8) { 621 ret = env->mxccregs[5]; 622 /* should we do something here? */ 623 } else { 624 qemu_log_mask(LOG_UNIMP, 625 "%08x: unimplemented access size: %d\n", addr, 626 size); 627 } 628 break; 629 case 0x01c00f00: /* MBus port address register */ 630 if (size == 8) { 631 ret = env->mxccregs[7]; 632 } else { 633 qemu_log_mask(LOG_UNIMP, 634 "%08x: unimplemented access size: %d\n", addr, 635 size); 636 } 637 break; 638 default: 639 qemu_log_mask(LOG_UNIMP, 640 "%08x: unimplemented address, size: %d\n", addr, 641 size); 642 break; 643 } 644 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " 645 "addr = %08x -> ret = %" PRIx64 "," 646 "addr = %08x\n", asi, size, sign, last_addr, ret, addr); 647 #ifdef DEBUG_MXCC 648 dump_mxcc(env); 649 #endif 650 break; 651 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */ 652 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */ 653 { 654 int mmulev; 655 656 mmulev = (addr >> 8) & 15; 657 if (mmulev > 4) { 658 ret = 0; 659 } else { 660 ret = mmu_probe(env, addr, mmulev); 661 } 662 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", 663 addr, mmulev, ret); 664 } 665 break; 666 case ASI_M_MMUREGS: /* SuperSparc MMU regs */ 667 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */ 668 { 669 int reg = (addr >> 8) & 0x1f; 670 671 ret = env->mmuregs[reg]; 672 if (reg == 3) { /* Fault status cleared on read */ 673 env->mmuregs[3] = 0; 674 } else if (reg == 0x13) { /* Fault status read */ 675 ret = env->mmuregs[3]; 676 } else if (reg == 0x14) { /* Fault address read */ 677 ret = env->mmuregs[4]; 678 } 679 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); 680 } 681 break; 682 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 683 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 684 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 685 break; 686 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */ 687 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */ 688 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */ 689 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ 690 break; 691 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 692 { 693 MemTxResult result; 694 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 695 696 switch (size) { 697 case 1: 698 ret = address_space_ldub(cs->as, access_addr, 699 MEMTXATTRS_UNSPECIFIED, &result); 700 break; 701 case 2: 702 ret = address_space_lduw(cs->as, access_addr, 703 MEMTXATTRS_UNSPECIFIED, &result); 704 break; 705 default: 706 case 4: 707 ret = address_space_ldl(cs->as, access_addr, 708 MEMTXATTRS_UNSPECIFIED, &result); 709 break; 710 case 8: 711 ret = address_space_ldq(cs->as, access_addr, 712 MEMTXATTRS_UNSPECIFIED, &result); 713 break; 714 } 715 716 if (result != MEMTX_OK) { 717 sparc_raise_mmu_fault(cs, access_addr, false, false, false, 718 size, GETPC()); 719 } 720 break; 721 } 722 case 0x30: /* Turbosparc secondary cache diagnostic */ 723 case 0x31: /* Turbosparc RAM snoop */ 724 case 0x32: /* Turbosparc page table descriptor diagnostic */ 725 case 0x39: /* data cache diagnostic register */ 726 ret = 0; 727 break; 728 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ 729 { 730 int reg = (addr >> 8) & 3; 731 732 switch (reg) { 733 case 0: /* Breakpoint Value (Addr) */ 734 ret = env->mmubpregs[reg]; 735 break; 736 case 1: /* Breakpoint Mask */ 737 ret = env->mmubpregs[reg]; 738 break; 739 case 2: /* Breakpoint Control */ 740 ret = env->mmubpregs[reg]; 741 break; 742 case 3: /* Breakpoint Status */ 743 ret = env->mmubpregs[reg]; 744 env->mmubpregs[reg] = 0ULL; 745 break; 746 } 747 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, 748 ret); 749 } 750 break; 751 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 752 ret = env->mmubpctrv; 753 break; 754 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 755 ret = env->mmubpctrc; 756 break; 757 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 758 ret = env->mmubpctrs; 759 break; 760 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 761 ret = env->mmubpaction; 762 break; 763 default: 764 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); 765 ret = 0; 766 break; 767 768 case ASI_USERDATA: /* User data access */ 769 case ASI_KERNELDATA: /* Supervisor data access */ 770 case ASI_USERTXT: /* User code access */ 771 case ASI_KERNELTXT: /* Supervisor code access */ 772 case ASI_P: /* Implicit primary context data access (v9 only?) */ 773 case ASI_M_BYPASS: /* MMU passthrough */ 774 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 775 /* These are always handled inline. */ 776 g_assert_not_reached(); 777 } 778 if (sign) { 779 switch (size) { 780 case 1: 781 ret = (int8_t) ret; 782 break; 783 case 2: 784 ret = (int16_t) ret; 785 break; 786 case 4: 787 ret = (int32_t) ret; 788 break; 789 default: 790 break; 791 } 792 } 793 #ifdef DEBUG_ASI 794 dump_asi("read ", last_addr, asi, size, ret); 795 #endif 796 return ret; 797 } 798 799 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, 800 int asi, uint32_t memop) 801 { 802 int size = 1 << (memop & MO_SIZE); 803 CPUState *cs = env_cpu(env); 804 805 do_check_align(env, addr, size - 1, GETPC()); 806 switch (asi) { 807 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 808 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 809 switch (addr) { 810 case 0x00: /* Leon3 Cache Control */ 811 case 0x08: /* Leon3 Instruction Cache config */ 812 case 0x0C: /* Leon3 Date Cache config */ 813 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 814 leon3_cache_control_st(env, addr, val, size); 815 } 816 break; 817 818 case 0x01c00000: /* MXCC stream data register 0 */ 819 if (size == 8) { 820 env->mxccdata[0] = val; 821 } else { 822 qemu_log_mask(LOG_UNIMP, 823 "%08x: unimplemented access size: %d\n", addr, 824 size); 825 } 826 break; 827 case 0x01c00008: /* MXCC stream data register 1 */ 828 if (size == 8) { 829 env->mxccdata[1] = val; 830 } else { 831 qemu_log_mask(LOG_UNIMP, 832 "%08x: unimplemented access size: %d\n", addr, 833 size); 834 } 835 break; 836 case 0x01c00010: /* MXCC stream data register 2 */ 837 if (size == 8) { 838 env->mxccdata[2] = val; 839 } else { 840 qemu_log_mask(LOG_UNIMP, 841 "%08x: unimplemented access size: %d\n", addr, 842 size); 843 } 844 break; 845 case 0x01c00018: /* MXCC stream data register 3 */ 846 if (size == 8) { 847 env->mxccdata[3] = val; 848 } else { 849 qemu_log_mask(LOG_UNIMP, 850 "%08x: unimplemented access size: %d\n", addr, 851 size); 852 } 853 break; 854 case 0x01c00100: /* MXCC stream source */ 855 { 856 int i; 857 858 if (size == 8) { 859 env->mxccregs[0] = val; 860 } else { 861 qemu_log_mask(LOG_UNIMP, 862 "%08x: unimplemented access size: %d\n", addr, 863 size); 864 } 865 866 for (i = 0; i < 4; i++) { 867 MemTxResult result; 868 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; 869 870 env->mxccdata[i] = address_space_ldq(cs->as, 871 access_addr, 872 MEMTXATTRS_UNSPECIFIED, 873 &result); 874 if (result != MEMTX_OK) { 875 /* TODO: investigate whether this is the right behaviour */ 876 sparc_raise_mmu_fault(cs, access_addr, false, false, 877 false, size, GETPC()); 878 } 879 } 880 break; 881 } 882 case 0x01c00200: /* MXCC stream destination */ 883 { 884 int i; 885 886 if (size == 8) { 887 env->mxccregs[1] = val; 888 } else { 889 qemu_log_mask(LOG_UNIMP, 890 "%08x: unimplemented access size: %d\n", addr, 891 size); 892 } 893 894 for (i = 0; i < 4; i++) { 895 MemTxResult result; 896 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; 897 898 address_space_stq(cs->as, access_addr, env->mxccdata[i], 899 MEMTXATTRS_UNSPECIFIED, &result); 900 901 if (result != MEMTX_OK) { 902 /* TODO: investigate whether this is the right behaviour */ 903 sparc_raise_mmu_fault(cs, access_addr, true, false, 904 false, size, GETPC()); 905 } 906 } 907 break; 908 } 909 case 0x01c00a00: /* MXCC control register */ 910 if (size == 8) { 911 env->mxccregs[3] = val; 912 } else { 913 qemu_log_mask(LOG_UNIMP, 914 "%08x: unimplemented access size: %d\n", addr, 915 size); 916 } 917 break; 918 case 0x01c00a04: /* MXCC control register */ 919 if (size == 4) { 920 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) 921 | val; 922 } else { 923 qemu_log_mask(LOG_UNIMP, 924 "%08x: unimplemented access size: %d\n", addr, 925 size); 926 } 927 break; 928 case 0x01c00e00: /* MXCC error register */ 929 /* writing a 1 bit clears the error */ 930 if (size == 8) { 931 env->mxccregs[6] &= ~val; 932 } else { 933 qemu_log_mask(LOG_UNIMP, 934 "%08x: unimplemented access size: %d\n", addr, 935 size); 936 } 937 break; 938 case 0x01c00f00: /* MBus port address register */ 939 if (size == 8) { 940 env->mxccregs[7] = val; 941 } else { 942 qemu_log_mask(LOG_UNIMP, 943 "%08x: unimplemented access size: %d\n", addr, 944 size); 945 } 946 break; 947 default: 948 qemu_log_mask(LOG_UNIMP, 949 "%08x: unimplemented address, size: %d\n", addr, 950 size); 951 break; 952 } 953 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", 954 asi, size, addr, val); 955 #ifdef DEBUG_MXCC 956 dump_mxcc(env); 957 #endif 958 break; 959 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */ 960 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */ 961 { 962 int mmulev; 963 964 mmulev = (addr >> 8) & 15; 965 DPRINTF_MMU("mmu flush level %d\n", mmulev); 966 switch (mmulev) { 967 case 0: /* flush page */ 968 tlb_flush_page(cs, addr & 0xfffff000); 969 break; 970 case 1: /* flush segment (256k) */ 971 case 2: /* flush region (16M) */ 972 case 3: /* flush context (4G) */ 973 case 4: /* flush entire */ 974 tlb_flush(cs); 975 break; 976 default: 977 break; 978 } 979 #ifdef DEBUG_MMU 980 dump_mmu(env); 981 #endif 982 } 983 break; 984 case ASI_M_MMUREGS: /* write MMU regs */ 985 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */ 986 { 987 int reg = (addr >> 8) & 0x1f; 988 uint32_t oldreg; 989 990 oldreg = env->mmuregs[reg]; 991 switch (reg) { 992 case 0: /* Control Register */ 993 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | 994 (val & 0x00ffffff); 995 /* Mappings generated during no-fault mode 996 are invalid in normal mode. */ 997 if ((oldreg ^ env->mmuregs[reg]) 998 & (MMU_NF | env->def.mmu_bm)) { 999 tlb_flush(cs); 1000 } 1001 break; 1002 case 1: /* Context Table Pointer Register */ 1003 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; 1004 break; 1005 case 2: /* Context Register */ 1006 env->mmuregs[reg] = val & env->def.mmu_cxr_mask; 1007 if (oldreg != env->mmuregs[reg]) { 1008 /* we flush when the MMU context changes because 1009 QEMU has no MMU context support */ 1010 tlb_flush(cs); 1011 } 1012 break; 1013 case 3: /* Synchronous Fault Status Register with Clear */ 1014 case 4: /* Synchronous Fault Address Register */ 1015 break; 1016 case 0x10: /* TLB Replacement Control Register */ 1017 env->mmuregs[reg] = val & env->def.mmu_trcr_mask; 1018 break; 1019 case 0x13: /* Synchronous Fault Status Register with Read 1020 and Clear */ 1021 env->mmuregs[3] = val & env->def.mmu_sfsr_mask; 1022 break; 1023 case 0x14: /* Synchronous Fault Address Register */ 1024 env->mmuregs[4] = val; 1025 break; 1026 default: 1027 env->mmuregs[reg] = val; 1028 break; 1029 } 1030 if (oldreg != env->mmuregs[reg]) { 1031 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", 1032 reg, oldreg, env->mmuregs[reg]); 1033 } 1034 #ifdef DEBUG_MMU 1035 dump_mmu(env); 1036 #endif 1037 } 1038 break; 1039 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 1040 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 1041 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 1042 break; 1043 case ASI_M_TXTC_TAG: /* I-cache tag */ 1044 case ASI_M_TXTC_DATA: /* I-cache data */ 1045 case ASI_M_DATAC_TAG: /* D-cache tag */ 1046 case ASI_M_DATAC_DATA: /* D-cache data */ 1047 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */ 1048 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */ 1049 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */ 1050 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */ 1051 case ASI_M_FLUSH_USER: /* I/D-cache flush user */ 1052 break; 1053 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 1054 { 1055 MemTxResult result; 1056 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 1057 1058 switch (size) { 1059 case 1: 1060 address_space_stb(cs->as, access_addr, val, 1061 MEMTXATTRS_UNSPECIFIED, &result); 1062 break; 1063 case 2: 1064 address_space_stw(cs->as, access_addr, val, 1065 MEMTXATTRS_UNSPECIFIED, &result); 1066 break; 1067 case 4: 1068 default: 1069 address_space_stl(cs->as, access_addr, val, 1070 MEMTXATTRS_UNSPECIFIED, &result); 1071 break; 1072 case 8: 1073 address_space_stq(cs->as, access_addr, val, 1074 MEMTXATTRS_UNSPECIFIED, &result); 1075 break; 1076 } 1077 if (result != MEMTX_OK) { 1078 sparc_raise_mmu_fault(cs, access_addr, true, false, false, 1079 size, GETPC()); 1080 } 1081 } 1082 break; 1083 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ 1084 case 0x31: /* store buffer data, Ross RT620 I-cache flush or 1085 Turbosparc snoop RAM */ 1086 case 0x32: /* store buffer control or Turbosparc page table 1087 descriptor diagnostic */ 1088 case 0x36: /* I-cache flash clear */ 1089 case 0x37: /* D-cache flash clear */ 1090 break; 1091 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ 1092 { 1093 int reg = (addr >> 8) & 3; 1094 1095 switch (reg) { 1096 case 0: /* Breakpoint Value (Addr) */ 1097 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1098 break; 1099 case 1: /* Breakpoint Mask */ 1100 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1101 break; 1102 case 2: /* Breakpoint Control */ 1103 env->mmubpregs[reg] = (val & 0x7fULL); 1104 break; 1105 case 3: /* Breakpoint Status */ 1106 env->mmubpregs[reg] = (val & 0xfULL); 1107 break; 1108 } 1109 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg, 1110 env->mmuregs[reg]); 1111 } 1112 break; 1113 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 1114 env->mmubpctrv = val & 0xffffffff; 1115 break; 1116 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 1117 env->mmubpctrc = val & 0x3; 1118 break; 1119 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 1120 env->mmubpctrs = val & 0x3; 1121 break; 1122 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 1123 env->mmubpaction = val & 0x1fff; 1124 break; 1125 case ASI_USERTXT: /* User code access, XXX */ 1126 case ASI_KERNELTXT: /* Supervisor code access, XXX */ 1127 default: 1128 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); 1129 break; 1130 1131 case ASI_USERDATA: /* User data access */ 1132 case ASI_KERNELDATA: /* Supervisor data access */ 1133 case ASI_P: 1134 case ASI_M_BYPASS: /* MMU passthrough */ 1135 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 1136 case ASI_M_BCOPY: /* Block copy, sta access */ 1137 case ASI_M_BFILL: /* Block fill, stda access */ 1138 /* These are always handled inline. */ 1139 g_assert_not_reached(); 1140 } 1141 #ifdef DEBUG_ASI 1142 dump_asi("write", addr, asi, size, val); 1143 #endif 1144 } 1145 1146 uint64_t helper_ld_code(CPUSPARCState *env, target_ulong addr, uint32_t oi) 1147 { 1148 MemOp mop = get_memop(oi); 1149 uintptr_t ra = GETPC(); 1150 uint64_t ret; 1151 1152 switch (mop & MO_SIZE) { 1153 case MO_8: 1154 ret = cpu_ldb_code_mmu(env, addr, oi, ra); 1155 if (mop & MO_SIGN) { 1156 ret = (int8_t)ret; 1157 } 1158 break; 1159 case MO_16: 1160 ret = cpu_ldw_code_mmu(env, addr, oi, ra); 1161 if ((mop & MO_BSWAP) != MO_TE) { 1162 ret = bswap16(ret); 1163 } 1164 if (mop & MO_SIGN) { 1165 ret = (int16_t)ret; 1166 } 1167 break; 1168 case MO_32: 1169 ret = cpu_ldl_code_mmu(env, addr, oi, ra); 1170 if ((mop & MO_BSWAP) != MO_TE) { 1171 ret = bswap32(ret); 1172 } 1173 if (mop & MO_SIGN) { 1174 ret = (int32_t)ret; 1175 } 1176 break; 1177 case MO_64: 1178 ret = cpu_ldq_code_mmu(env, addr, oi, ra); 1179 if ((mop & MO_BSWAP) != MO_TE) { 1180 ret = bswap64(ret); 1181 } 1182 break; 1183 default: 1184 g_assert_not_reached(); 1185 } 1186 return ret; 1187 } 1188 1189 #endif /* CONFIG_USER_ONLY */ 1190 #else /* TARGET_SPARC64 */ 1191 1192 #ifdef CONFIG_USER_ONLY 1193 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1194 int asi, uint32_t memop) 1195 { 1196 int size = 1 << (memop & MO_SIZE); 1197 int sign = memop & MO_SIGN; 1198 uint64_t ret = 0; 1199 1200 if (asi < 0x80) { 1201 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1202 } 1203 do_check_align(env, addr, size - 1, GETPC()); 1204 addr = asi_address_mask(env, asi, addr); 1205 1206 switch (asi) { 1207 case ASI_PNF: /* Primary no-fault */ 1208 case ASI_PNFL: /* Primary no-fault LE */ 1209 case ASI_SNF: /* Secondary no-fault */ 1210 case ASI_SNFL: /* Secondary no-fault LE */ 1211 if (!page_check_range(addr, size, PAGE_READ)) { 1212 ret = 0; 1213 break; 1214 } 1215 switch (size) { 1216 case 1: 1217 ret = cpu_ldub_data(env, addr); 1218 break; 1219 case 2: 1220 ret = cpu_lduw_data(env, addr); 1221 break; 1222 case 4: 1223 ret = cpu_ldl_data(env, addr); 1224 break; 1225 case 8: 1226 ret = cpu_ldq_data(env, addr); 1227 break; 1228 default: 1229 g_assert_not_reached(); 1230 } 1231 break; 1232 break; 1233 1234 case ASI_P: /* Primary */ 1235 case ASI_PL: /* Primary LE */ 1236 case ASI_S: /* Secondary */ 1237 case ASI_SL: /* Secondary LE */ 1238 /* These are always handled inline. */ 1239 g_assert_not_reached(); 1240 1241 default: 1242 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1243 } 1244 1245 /* Convert from little endian */ 1246 switch (asi) { 1247 case ASI_PNFL: /* Primary no-fault LE */ 1248 case ASI_SNFL: /* Secondary no-fault LE */ 1249 switch (size) { 1250 case 2: 1251 ret = bswap16(ret); 1252 break; 1253 case 4: 1254 ret = bswap32(ret); 1255 break; 1256 case 8: 1257 ret = bswap64(ret); 1258 break; 1259 } 1260 } 1261 1262 /* Convert to signed number */ 1263 if (sign) { 1264 switch (size) { 1265 case 1: 1266 ret = (int8_t) ret; 1267 break; 1268 case 2: 1269 ret = (int16_t) ret; 1270 break; 1271 case 4: 1272 ret = (int32_t) ret; 1273 break; 1274 } 1275 } 1276 #ifdef DEBUG_ASI 1277 dump_asi("read", addr, asi, size, ret); 1278 #endif 1279 return ret; 1280 } 1281 1282 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1283 int asi, uint32_t memop) 1284 { 1285 int size = 1 << (memop & MO_SIZE); 1286 #ifdef DEBUG_ASI 1287 dump_asi("write", addr, asi, size, val); 1288 #endif 1289 if (asi < 0x80) { 1290 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1291 } 1292 do_check_align(env, addr, size - 1, GETPC()); 1293 1294 switch (asi) { 1295 case ASI_P: /* Primary */ 1296 case ASI_PL: /* Primary LE */ 1297 case ASI_S: /* Secondary */ 1298 case ASI_SL: /* Secondary LE */ 1299 /* These are always handled inline. */ 1300 g_assert_not_reached(); 1301 1302 case ASI_PNF: /* Primary no-fault, RO */ 1303 case ASI_SNF: /* Secondary no-fault, RO */ 1304 case ASI_PNFL: /* Primary no-fault LE, RO */ 1305 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1306 default: 1307 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1308 } 1309 } 1310 1311 #else /* CONFIG_USER_ONLY */ 1312 1313 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1314 int asi, uint32_t memop) 1315 { 1316 int size = 1 << (memop & MO_SIZE); 1317 int sign = memop & MO_SIGN; 1318 CPUState *cs = env_cpu(env); 1319 uint64_t ret = 0; 1320 #if defined(DEBUG_ASI) 1321 target_ulong last_addr = addr; 1322 #endif 1323 1324 asi &= 0xff; 1325 1326 do_check_asi(env, asi, GETPC()); 1327 do_check_align(env, addr, size - 1, GETPC()); 1328 addr = asi_address_mask(env, asi, addr); 1329 1330 switch (asi) { 1331 case ASI_PNF: 1332 case ASI_PNFL: 1333 case ASI_SNF: 1334 case ASI_SNFL: 1335 { 1336 MemOpIdx oi; 1337 int idx = (env->pstate & PS_PRIV 1338 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX) 1339 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX)); 1340 1341 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) { 1342 #ifdef DEBUG_ASI 1343 dump_asi("read ", last_addr, asi, size, ret); 1344 #endif 1345 /* exception_index is set in get_physical_address_data. */ 1346 cpu_raise_exception_ra(env, cs->exception_index, GETPC()); 1347 } 1348 oi = make_memop_idx(memop, idx); 1349 switch (size) { 1350 case 1: 1351 ret = cpu_ldb_mmu(env, addr, oi, GETPC()); 1352 break; 1353 case 2: 1354 ret = cpu_ldw_mmu(env, addr, oi, GETPC()); 1355 break; 1356 case 4: 1357 ret = cpu_ldl_mmu(env, addr, oi, GETPC()); 1358 break; 1359 case 8: 1360 ret = cpu_ldq_mmu(env, addr, oi, GETPC()); 1361 break; 1362 default: 1363 g_assert_not_reached(); 1364 } 1365 } 1366 break; 1367 1368 case ASI_AIUP: /* As if user primary */ 1369 case ASI_AIUS: /* As if user secondary */ 1370 case ASI_AIUPL: /* As if user primary LE */ 1371 case ASI_AIUSL: /* As if user secondary LE */ 1372 case ASI_P: /* Primary */ 1373 case ASI_S: /* Secondary */ 1374 case ASI_PL: /* Primary LE */ 1375 case ASI_SL: /* Secondary LE */ 1376 case ASI_REAL: /* Bypass */ 1377 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1378 case ASI_REAL_L: /* Bypass LE */ 1379 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1380 case ASI_N: /* Nucleus */ 1381 case ASI_NL: /* Nucleus Little Endian (LE) */ 1382 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1383 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1384 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1385 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1386 case ASI_TWINX_REAL: /* Real address, twinx */ 1387 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1388 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1389 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1390 case ASI_TWINX_N: /* Nucleus, twinx */ 1391 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1392 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1393 case ASI_TWINX_P: /* Primary, twinx */ 1394 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1395 case ASI_TWINX_S: /* Secondary, twinx */ 1396 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1397 /* These are always handled inline. */ 1398 g_assert_not_reached(); 1399 1400 case ASI_UPA_CONFIG: /* UPA config */ 1401 /* XXX */ 1402 break; 1403 case ASI_LSU_CONTROL: /* LSU */ 1404 ret = env->lsu; 1405 break; 1406 case ASI_IMMU: /* I-MMU regs */ 1407 { 1408 int reg = (addr >> 3) & 0xf; 1409 switch (reg) { 1410 case 0: 1411 /* 0x00 I-TSB Tag Target register */ 1412 ret = ultrasparc_tag_target(env->immu.tag_access); 1413 break; 1414 case 3: /* SFSR */ 1415 ret = env->immu.sfsr; 1416 break; 1417 case 5: /* TSB access */ 1418 ret = env->immu.tsb; 1419 break; 1420 case 6: 1421 /* 0x30 I-TSB Tag Access register */ 1422 ret = env->immu.tag_access; 1423 break; 1424 default: 1425 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1426 ret = 0; 1427 } 1428 break; 1429 } 1430 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */ 1431 { 1432 /* env->immuregs[5] holds I-MMU TSB register value 1433 env->immuregs[6] holds I-MMU Tag Access register value */ 1434 ret = ultrasparc_tsb_pointer(env, &env->immu, 0); 1435 break; 1436 } 1437 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ 1438 { 1439 /* env->immuregs[5] holds I-MMU TSB register value 1440 env->immuregs[6] holds I-MMU Tag Access register value */ 1441 ret = ultrasparc_tsb_pointer(env, &env->immu, 1); 1442 break; 1443 } 1444 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1445 { 1446 int reg = (addr >> 3) & 0x3f; 1447 1448 ret = env->itlb[reg].tte; 1449 break; 1450 } 1451 case ASI_ITLB_TAG_READ: /* I-MMU tag read */ 1452 { 1453 int reg = (addr >> 3) & 0x3f; 1454 1455 ret = env->itlb[reg].tag; 1456 break; 1457 } 1458 case ASI_DMMU: /* D-MMU regs */ 1459 { 1460 int reg = (addr >> 3) & 0xf; 1461 switch (reg) { 1462 case 0: 1463 /* 0x00 D-TSB Tag Target register */ 1464 ret = ultrasparc_tag_target(env->dmmu.tag_access); 1465 break; 1466 case 1: /* 0x08 Primary Context */ 1467 ret = env->dmmu.mmu_primary_context; 1468 break; 1469 case 2: /* 0x10 Secondary Context */ 1470 ret = env->dmmu.mmu_secondary_context; 1471 break; 1472 case 3: /* SFSR */ 1473 ret = env->dmmu.sfsr; 1474 break; 1475 case 4: /* 0x20 SFAR */ 1476 ret = env->dmmu.sfar; 1477 break; 1478 case 5: /* 0x28 TSB access */ 1479 ret = env->dmmu.tsb; 1480 break; 1481 case 6: /* 0x30 D-TSB Tag Access register */ 1482 ret = env->dmmu.tag_access; 1483 break; 1484 case 7: 1485 ret = env->dmmu.virtual_watchpoint; 1486 break; 1487 case 8: 1488 ret = env->dmmu.physical_watchpoint; 1489 break; 1490 default: 1491 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1492 ret = 0; 1493 } 1494 break; 1495 } 1496 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */ 1497 { 1498 /* env->dmmuregs[5] holds D-MMU TSB register value 1499 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1500 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); 1501 break; 1502 } 1503 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ 1504 { 1505 /* env->dmmuregs[5] holds D-MMU TSB register value 1506 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1507 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); 1508 break; 1509 } 1510 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1511 { 1512 int reg = (addr >> 3) & 0x3f; 1513 1514 ret = env->dtlb[reg].tte; 1515 break; 1516 } 1517 case ASI_DTLB_TAG_READ: /* D-MMU tag read */ 1518 { 1519 int reg = (addr >> 3) & 0x3f; 1520 1521 ret = env->dtlb[reg].tag; 1522 break; 1523 } 1524 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1525 break; 1526 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1527 ret = env->ivec_status; 1528 break; 1529 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1530 { 1531 int reg = (addr >> 4) & 0x3; 1532 if (reg < 3) { 1533 ret = env->ivec_data[reg]; 1534 } 1535 break; 1536 } 1537 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1538 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1539 /* Hyperprivileged access only */ 1540 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1541 } 1542 /* fall through */ 1543 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1544 { 1545 unsigned int i = (addr >> 3) & 0x7; 1546 ret = env->scratch[i]; 1547 break; 1548 } 1549 case ASI_MMU: /* UA2005 Context ID registers */ 1550 switch ((addr >> 3) & 0x3) { 1551 case 1: 1552 ret = env->dmmu.mmu_primary_context; 1553 break; 1554 case 2: 1555 ret = env->dmmu.mmu_secondary_context; 1556 break; 1557 default: 1558 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1559 } 1560 break; 1561 case ASI_DCACHE_DATA: /* D-cache data */ 1562 case ASI_DCACHE_TAG: /* D-cache tag access */ 1563 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1564 case ASI_AFSR: /* E-cache asynchronous fault status */ 1565 case ASI_AFAR: /* E-cache asynchronous fault address */ 1566 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1567 case ASI_IC_INSTR: /* I-cache instruction access */ 1568 case ASI_IC_TAG: /* I-cache tag access */ 1569 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1570 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1571 case ASI_EC_W: /* E-cache tag */ 1572 case ASI_EC_R: /* E-cache tag */ 1573 break; 1574 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */ 1575 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */ 1576 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */ 1577 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */ 1578 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ 1579 case ASI_INTR_W: /* Interrupt vector, WO */ 1580 default: 1581 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1582 ret = 0; 1583 break; 1584 } 1585 1586 /* Convert to signed number */ 1587 if (sign) { 1588 switch (size) { 1589 case 1: 1590 ret = (int8_t) ret; 1591 break; 1592 case 2: 1593 ret = (int16_t) ret; 1594 break; 1595 case 4: 1596 ret = (int32_t) ret; 1597 break; 1598 default: 1599 break; 1600 } 1601 } 1602 #ifdef DEBUG_ASI 1603 dump_asi("read ", last_addr, asi, size, ret); 1604 #endif 1605 return ret; 1606 } 1607 1608 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1609 int asi, uint32_t memop) 1610 { 1611 int size = 1 << (memop & MO_SIZE); 1612 CPUState *cs = env_cpu(env); 1613 1614 #ifdef DEBUG_ASI 1615 dump_asi("write", addr, asi, size, val); 1616 #endif 1617 1618 asi &= 0xff; 1619 1620 do_check_asi(env, asi, GETPC()); 1621 do_check_align(env, addr, size - 1, GETPC()); 1622 addr = asi_address_mask(env, asi, addr); 1623 1624 switch (asi) { 1625 case ASI_AIUP: /* As if user primary */ 1626 case ASI_AIUS: /* As if user secondary */ 1627 case ASI_AIUPL: /* As if user primary LE */ 1628 case ASI_AIUSL: /* As if user secondary LE */ 1629 case ASI_P: /* Primary */ 1630 case ASI_S: /* Secondary */ 1631 case ASI_PL: /* Primary LE */ 1632 case ASI_SL: /* Secondary LE */ 1633 case ASI_REAL: /* Bypass */ 1634 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1635 case ASI_REAL_L: /* Bypass LE */ 1636 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1637 case ASI_N: /* Nucleus */ 1638 case ASI_NL: /* Nucleus Little Endian (LE) */ 1639 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1640 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1641 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1642 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1643 case ASI_TWINX_REAL: /* Real address, twinx */ 1644 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1645 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1646 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1647 case ASI_TWINX_N: /* Nucleus, twinx */ 1648 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1649 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1650 case ASI_TWINX_P: /* Primary, twinx */ 1651 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1652 case ASI_TWINX_S: /* Secondary, twinx */ 1653 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1654 /* These are always handled inline. */ 1655 g_assert_not_reached(); 1656 /* these ASIs have different functions on UltraSPARC-IIIi 1657 * and UA2005 CPUs. Use the explicit numbers to avoid confusion 1658 */ 1659 case 0x31: 1660 case 0x32: 1661 case 0x39: 1662 case 0x3a: 1663 if (cpu_has_hypervisor(env)) { 1664 /* UA2005 1665 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0 1666 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1 1667 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0 1668 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1 1669 */ 1670 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1671 env->dmmu.sun4v_tsb_pointers[idx] = val; 1672 } else { 1673 goto illegal_insn; 1674 } 1675 break; 1676 case 0x33: 1677 case 0x3b: 1678 if (cpu_has_hypervisor(env)) { 1679 /* UA2005 1680 * ASI_DMMU_CTX_ZERO_CONFIG 1681 * ASI_DMMU_CTX_NONZERO_CONFIG 1682 */ 1683 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1684 } else { 1685 goto illegal_insn; 1686 } 1687 break; 1688 case 0x35: 1689 case 0x36: 1690 case 0x3d: 1691 case 0x3e: 1692 if (cpu_has_hypervisor(env)) { 1693 /* UA2005 1694 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0 1695 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1 1696 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0 1697 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1 1698 */ 1699 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1700 env->immu.sun4v_tsb_pointers[idx] = val; 1701 } else { 1702 goto illegal_insn; 1703 } 1704 break; 1705 case 0x37: 1706 case 0x3f: 1707 if (cpu_has_hypervisor(env)) { 1708 /* UA2005 1709 * ASI_IMMU_CTX_ZERO_CONFIG 1710 * ASI_IMMU_CTX_NONZERO_CONFIG 1711 */ 1712 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1713 } else { 1714 goto illegal_insn; 1715 } 1716 break; 1717 case ASI_UPA_CONFIG: /* UPA config */ 1718 /* XXX */ 1719 return; 1720 case ASI_LSU_CONTROL: /* LSU */ 1721 env->lsu = val & (DMMU_E | IMMU_E); 1722 return; 1723 case ASI_IMMU: /* I-MMU regs */ 1724 { 1725 int reg = (addr >> 3) & 0xf; 1726 uint64_t oldreg; 1727 1728 oldreg = env->immu.mmuregs[reg]; 1729 switch (reg) { 1730 case 0: /* RO */ 1731 return; 1732 case 1: /* Not in I-MMU */ 1733 case 2: 1734 return; 1735 case 3: /* SFSR */ 1736 if ((val & 1) == 0) { 1737 val = 0; /* Clear SFSR */ 1738 } 1739 env->immu.sfsr = val; 1740 break; 1741 case 4: /* RO */ 1742 return; 1743 case 5: /* TSB access */ 1744 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" 1745 PRIx64 "\n", env->immu.tsb, val); 1746 env->immu.tsb = val; 1747 break; 1748 case 6: /* Tag access */ 1749 env->immu.tag_access = val; 1750 break; 1751 case 7: 1752 case 8: 1753 return; 1754 default: 1755 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1756 break; 1757 } 1758 1759 if (oldreg != env->immu.mmuregs[reg]) { 1760 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1761 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); 1762 } 1763 #ifdef DEBUG_MMU 1764 dump_mmu(env); 1765 #endif 1766 return; 1767 } 1768 case ASI_ITLB_DATA_IN: /* I-MMU data in */ 1769 /* ignore real translation entries */ 1770 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1771 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, 1772 val, "immu", env, addr); 1773 } 1774 return; 1775 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1776 { 1777 /* TODO: auto demap */ 1778 1779 unsigned int i = (addr >> 3) & 0x3f; 1780 1781 /* ignore real translation entries */ 1782 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1783 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, 1784 sun4v_tte_to_sun4u(env, addr, val), env); 1785 } 1786 #ifdef DEBUG_MMU 1787 DPRINTF_MMU("immu data access replaced entry [%i]\n", i); 1788 dump_mmu(env); 1789 #endif 1790 return; 1791 } 1792 case ASI_IMMU_DEMAP: /* I-MMU demap */ 1793 demap_tlb(env->itlb, addr, "immu", env); 1794 return; 1795 case ASI_DMMU: /* D-MMU regs */ 1796 { 1797 int reg = (addr >> 3) & 0xf; 1798 uint64_t oldreg; 1799 1800 oldreg = env->dmmu.mmuregs[reg]; 1801 switch (reg) { 1802 case 0: /* RO */ 1803 case 4: 1804 return; 1805 case 3: /* SFSR */ 1806 if ((val & 1) == 0) { 1807 val = 0; /* Clear SFSR, Fault address */ 1808 env->dmmu.sfar = 0; 1809 } 1810 env->dmmu.sfsr = val; 1811 break; 1812 case 1: /* Primary context */ 1813 env->dmmu.mmu_primary_context = val; 1814 /* can be optimized to only flush MMU_USER_IDX 1815 and MMU_KERNEL_IDX entries */ 1816 tlb_flush(cs); 1817 break; 1818 case 2: /* Secondary context */ 1819 env->dmmu.mmu_secondary_context = val; 1820 /* can be optimized to only flush MMU_USER_SECONDARY_IDX 1821 and MMU_KERNEL_SECONDARY_IDX entries */ 1822 tlb_flush(cs); 1823 break; 1824 case 5: /* TSB access */ 1825 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" 1826 PRIx64 "\n", env->dmmu.tsb, val); 1827 env->dmmu.tsb = val; 1828 break; 1829 case 6: /* Tag access */ 1830 env->dmmu.tag_access = val; 1831 break; 1832 case 7: /* Virtual Watchpoint */ 1833 env->dmmu.virtual_watchpoint = val; 1834 break; 1835 case 8: /* Physical Watchpoint */ 1836 env->dmmu.physical_watchpoint = val; 1837 break; 1838 default: 1839 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1840 break; 1841 } 1842 1843 if (oldreg != env->dmmu.mmuregs[reg]) { 1844 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1845 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); 1846 } 1847 #ifdef DEBUG_MMU 1848 dump_mmu(env); 1849 #endif 1850 return; 1851 } 1852 case ASI_DTLB_DATA_IN: /* D-MMU data in */ 1853 /* ignore real translation entries */ 1854 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1855 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, 1856 val, "dmmu", env, addr); 1857 } 1858 return; 1859 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1860 { 1861 unsigned int i = (addr >> 3) & 0x3f; 1862 1863 /* ignore real translation entries */ 1864 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1865 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, 1866 sun4v_tte_to_sun4u(env, addr, val), env); 1867 } 1868 #ifdef DEBUG_MMU 1869 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); 1870 dump_mmu(env); 1871 #endif 1872 return; 1873 } 1874 case ASI_DMMU_DEMAP: /* D-MMU demap */ 1875 demap_tlb(env->dtlb, addr, "dmmu", env); 1876 return; 1877 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1878 env->ivec_status = val & 0x20; 1879 return; 1880 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1881 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1882 /* Hyperprivileged access only */ 1883 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1884 } 1885 /* fall through */ 1886 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1887 { 1888 unsigned int i = (addr >> 3) & 0x7; 1889 env->scratch[i] = val; 1890 return; 1891 } 1892 case ASI_MMU: /* UA2005 Context ID registers */ 1893 { 1894 switch ((addr >> 3) & 0x3) { 1895 case 1: 1896 env->dmmu.mmu_primary_context = val; 1897 env->immu.mmu_primary_context = val; 1898 tlb_flush_by_mmuidx(cs, 1899 (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX)); 1900 break; 1901 case 2: 1902 env->dmmu.mmu_secondary_context = val; 1903 env->immu.mmu_secondary_context = val; 1904 tlb_flush_by_mmuidx(cs, 1905 (1 << MMU_USER_SECONDARY_IDX) | 1906 (1 << MMU_KERNEL_SECONDARY_IDX)); 1907 break; 1908 default: 1909 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1910 } 1911 } 1912 return; 1913 case ASI_QUEUE: /* UA2005 CPU mondo queue */ 1914 case ASI_DCACHE_DATA: /* D-cache data */ 1915 case ASI_DCACHE_TAG: /* D-cache tag access */ 1916 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1917 case ASI_AFSR: /* E-cache asynchronous fault status */ 1918 case ASI_AFAR: /* E-cache asynchronous fault address */ 1919 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1920 case ASI_IC_INSTR: /* I-cache instruction access */ 1921 case ASI_IC_TAG: /* I-cache tag access */ 1922 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1923 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1924 case ASI_EC_W: /* E-cache tag */ 1925 case ASI_EC_R: /* E-cache tag */ 1926 return; 1927 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */ 1928 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */ 1929 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */ 1930 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */ 1931 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */ 1932 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */ 1933 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */ 1934 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1935 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1936 case ASI_PNF: /* Primary no-fault, RO */ 1937 case ASI_SNF: /* Secondary no-fault, RO */ 1938 case ASI_PNFL: /* Primary no-fault LE, RO */ 1939 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1940 default: 1941 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1942 return; 1943 illegal_insn: 1944 cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC()); 1945 } 1946 } 1947 #endif /* CONFIG_USER_ONLY */ 1948 #endif /* TARGET_SPARC64 */ 1949 1950 #if !defined(CONFIG_USER_ONLY) 1951 1952 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1953 vaddr addr, unsigned size, 1954 MMUAccessType access_type, 1955 int mmu_idx, MemTxAttrs attrs, 1956 MemTxResult response, uintptr_t retaddr) 1957 { 1958 bool is_write = access_type == MMU_DATA_STORE; 1959 bool is_exec = access_type == MMU_INST_FETCH; 1960 bool is_asi = false; 1961 1962 sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec, 1963 is_asi, size, retaddr); 1964 } 1965 #endif 1966