1 /* 2 * Helpers for loads and stores 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "tcg/tcg.h" 24 #include "exec/helper-proto.h" 25 #include "exec/exec-all.h" 26 #include "exec/cpu_ldst.h" 27 #include "asi.h" 28 29 //#define DEBUG_MMU 30 //#define DEBUG_MXCC 31 //#define DEBUG_UNASSIGNED 32 //#define DEBUG_ASI 33 //#define DEBUG_CACHE_CONTROL 34 35 #ifdef DEBUG_MMU 36 #define DPRINTF_MMU(fmt, ...) \ 37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) 38 #else 39 #define DPRINTF_MMU(fmt, ...) do {} while (0) 40 #endif 41 42 #ifdef DEBUG_MXCC 43 #define DPRINTF_MXCC(fmt, ...) \ 44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) 45 #else 46 #define DPRINTF_MXCC(fmt, ...) do {} while (0) 47 #endif 48 49 #ifdef DEBUG_ASI 50 #define DPRINTF_ASI(fmt, ...) \ 51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) 52 #endif 53 54 #ifdef DEBUG_CACHE_CONTROL 55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \ 56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) 57 #else 58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) 59 #endif 60 61 #ifdef TARGET_SPARC64 62 #ifndef TARGET_ABI32 63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM) 64 #else 65 #define AM_CHECK(env1) (1) 66 #endif 67 #endif 68 69 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 70 /* Calculates TSB pointer value for fault page size 71 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers 72 * UA2005 holds the page size configuration in mmu_ctx registers */ 73 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, 74 const SparcV9MMU *mmu, const int idx) 75 { 76 uint64_t tsb_register; 77 int page_size; 78 if (cpu_has_hypervisor(env)) { 79 int tsb_index = 0; 80 int ctx = mmu->tag_access & 0x1fffULL; 81 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; 82 tsb_index = idx; 83 tsb_index |= ctx ? 2 : 0; 84 page_size = idx ? ctx_register >> 8 : ctx_register; 85 page_size &= 7; 86 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; 87 } else { 88 page_size = idx; 89 tsb_register = mmu->tsb; 90 } 91 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; 92 int tsb_size = tsb_register & 0xf; 93 94 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size; 95 96 /* move va bits to correct position, 97 * the context bits will be masked out later */ 98 uint64_t va = mmu->tag_access >> (3 * page_size + 9); 99 100 /* calculate tsb_base mask and adjust va if split is in use */ 101 if (tsb_split) { 102 if (idx == 0) { 103 va &= ~(1ULL << (13 + tsb_size)); 104 } else { 105 va |= (1ULL << (13 + tsb_size)); 106 } 107 tsb_base_mask <<= 1; 108 } 109 110 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; 111 } 112 113 /* Calculates tag target register value by reordering bits 114 in tag access register */ 115 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) 116 { 117 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); 118 } 119 120 static void replace_tlb_entry(SparcTLBEntry *tlb, 121 uint64_t tlb_tag, uint64_t tlb_tte, 122 CPUSPARCState *env) 123 { 124 target_ulong mask, size, va, offset; 125 126 /* flush page range if translation is valid */ 127 if (TTE_IS_VALID(tlb->tte)) { 128 CPUState *cs = env_cpu(env); 129 130 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); 131 mask = 1ULL + ~size; 132 133 va = tlb->tag & mask; 134 135 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { 136 tlb_flush_page(cs, va + offset); 137 } 138 } 139 140 tlb->tag = tlb_tag; 141 tlb->tte = tlb_tte; 142 } 143 144 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, 145 const char *strmmu, CPUSPARCState *env1) 146 { 147 unsigned int i; 148 target_ulong mask; 149 uint64_t context; 150 151 int is_demap_context = (demap_addr >> 6) & 1; 152 153 /* demap context */ 154 switch ((demap_addr >> 4) & 3) { 155 case 0: /* primary */ 156 context = env1->dmmu.mmu_primary_context; 157 break; 158 case 1: /* secondary */ 159 context = env1->dmmu.mmu_secondary_context; 160 break; 161 case 2: /* nucleus */ 162 context = 0; 163 break; 164 case 3: /* reserved */ 165 default: 166 return; 167 } 168 169 for (i = 0; i < 64; i++) { 170 if (TTE_IS_VALID(tlb[i].tte)) { 171 172 if (is_demap_context) { 173 /* will remove non-global entries matching context value */ 174 if (TTE_IS_GLOBAL(tlb[i].tte) || 175 !tlb_compare_context(&tlb[i], context)) { 176 continue; 177 } 178 } else { 179 /* demap page 180 will remove any entry matching VA */ 181 mask = 0xffffffffffffe000ULL; 182 mask <<= 3 * ((tlb[i].tte >> 61) & 3); 183 184 if (!compare_masked(demap_addr, tlb[i].tag, mask)) { 185 continue; 186 } 187 188 /* entry should be global or matching context value */ 189 if (!TTE_IS_GLOBAL(tlb[i].tte) && 190 !tlb_compare_context(&tlb[i], context)) { 191 continue; 192 } 193 } 194 195 replace_tlb_entry(&tlb[i], 0, 0, env1); 196 #ifdef DEBUG_MMU 197 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); 198 dump_mmu(env1); 199 #endif 200 } 201 } 202 } 203 204 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState *env, uint64_t tag, 205 uint64_t sun4v_tte) 206 { 207 uint64_t sun4u_tte; 208 if (!(cpu_has_hypervisor(env) && (tag & TLB_UST1_IS_SUN4V_BIT))) { 209 /* is already in the sun4u format */ 210 return sun4v_tte; 211 } 212 sun4u_tte = TTE_PA(sun4v_tte) | (sun4v_tte & TTE_VALID_BIT); 213 sun4u_tte |= (sun4v_tte & 3ULL) << 61; /* TTE_PGSIZE */ 214 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_NFO_BIT_UA2005, TTE_NFO_BIT); 215 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_USED_BIT_UA2005, TTE_USED_BIT); 216 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_W_OK_BIT_UA2005, TTE_W_OK_BIT); 217 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_SIDEEFFECT_BIT_UA2005, 218 TTE_SIDEEFFECT_BIT); 219 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_PRIV_BIT_UA2005, TTE_PRIV_BIT); 220 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_LOCKED_BIT_UA2005, TTE_LOCKED_BIT); 221 return sun4u_tte; 222 } 223 224 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, 225 uint64_t tlb_tag, uint64_t tlb_tte, 226 const char *strmmu, CPUSPARCState *env1, 227 uint64_t addr) 228 { 229 unsigned int i, replace_used; 230 231 tlb_tte = sun4v_tte_to_sun4u(env1, addr, tlb_tte); 232 if (cpu_has_hypervisor(env1)) { 233 uint64_t new_vaddr = tlb_tag & ~0x1fffULL; 234 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte); 235 uint32_t new_ctx = tlb_tag & 0x1fffU; 236 for (i = 0; i < 64; i++) { 237 uint32_t ctx = tlb[i].tag & 0x1fffU; 238 /* check if new mapping overlaps an existing one */ 239 if (new_ctx == ctx) { 240 uint64_t vaddr = tlb[i].tag & ~0x1fffULL; 241 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte); 242 if (new_vaddr == vaddr 243 || (new_vaddr < vaddr + size 244 && vaddr < new_vaddr + new_size)) { 245 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, 246 new_vaddr); 247 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 248 return; 249 } 250 } 251 252 } 253 } 254 /* Try replacing invalid entry */ 255 for (i = 0; i < 64; i++) { 256 if (!TTE_IS_VALID(tlb[i].tte)) { 257 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 258 #ifdef DEBUG_MMU 259 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); 260 dump_mmu(env1); 261 #endif 262 return; 263 } 264 } 265 266 /* All entries are valid, try replacing unlocked entry */ 267 268 for (replace_used = 0; replace_used < 2; ++replace_used) { 269 270 /* Used entries are not replaced on first pass */ 271 272 for (i = 0; i < 64; i++) { 273 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) { 274 275 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 276 #ifdef DEBUG_MMU 277 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", 278 strmmu, (replace_used ? "used" : "unused"), i); 279 dump_mmu(env1); 280 #endif 281 return; 282 } 283 } 284 285 /* Now reset used bit and search for unused entries again */ 286 287 for (i = 0; i < 64; i++) { 288 TTE_SET_UNUSED(tlb[i].tte); 289 } 290 } 291 292 #ifdef DEBUG_MMU 293 DPRINTF_MMU("%s lru replacement: no free entries available, " 294 "replacing the last one\n", strmmu); 295 #endif 296 /* corner case: the last entry is replaced anyway */ 297 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1); 298 } 299 300 #endif 301 302 #ifdef TARGET_SPARC64 303 /* returns true if access using this ASI is to have address translated by MMU 304 otherwise access is to raw physical address */ 305 /* TODO: check sparc32 bits */ 306 static inline int is_translating_asi(int asi) 307 { 308 /* Ultrasparc IIi translating asi 309 - note this list is defined by cpu implementation 310 */ 311 switch (asi) { 312 case 0x04 ... 0x11: 313 case 0x16 ... 0x19: 314 case 0x1E ... 0x1F: 315 case 0x24 ... 0x2C: 316 case 0x70 ... 0x73: 317 case 0x78 ... 0x79: 318 case 0x80 ... 0xFF: 319 return 1; 320 321 default: 322 return 0; 323 } 324 } 325 326 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr) 327 { 328 if (AM_CHECK(env1)) { 329 addr &= 0xffffffffULL; 330 } 331 return addr; 332 } 333 334 static inline target_ulong asi_address_mask(CPUSPARCState *env, 335 int asi, target_ulong addr) 336 { 337 if (is_translating_asi(asi)) { 338 addr = address_mask(env, addr); 339 } 340 return addr; 341 } 342 343 #ifndef CONFIG_USER_ONLY 344 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra) 345 { 346 /* ASIs >= 0x80 are user mode. 347 * ASIs >= 0x30 are hyper mode (or super if hyper is not available). 348 * ASIs <= 0x2f are super mode. 349 */ 350 if (asi < 0x80 351 && !cpu_hypervisor_mode(env) 352 && (!cpu_supervisor_mode(env) 353 || (asi >= 0x30 && cpu_has_hypervisor(env)))) { 354 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra); 355 } 356 } 357 #endif /* !CONFIG_USER_ONLY */ 358 #endif 359 360 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) 361 static void do_check_align(CPUSPARCState *env, target_ulong addr, 362 uint32_t align, uintptr_t ra) 363 { 364 if (addr & align) { 365 cpu_raise_exception_ra(env, TT_UNALIGNED, ra); 366 } 367 } 368 #endif 369 370 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ 371 defined(DEBUG_MXCC) 372 static void dump_mxcc(CPUSPARCState *env) 373 { 374 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 375 "\n", 376 env->mxccdata[0], env->mxccdata[1], 377 env->mxccdata[2], env->mxccdata[3]); 378 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 379 "\n" 380 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 381 "\n", 382 env->mxccregs[0], env->mxccregs[1], 383 env->mxccregs[2], env->mxccregs[3], 384 env->mxccregs[4], env->mxccregs[5], 385 env->mxccregs[6], env->mxccregs[7]); 386 } 387 #endif 388 389 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \ 390 && defined(DEBUG_ASI) 391 static void dump_asi(const char *txt, target_ulong addr, int asi, int size, 392 uint64_t r1) 393 { 394 switch (size) { 395 case 1: 396 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, 397 addr, asi, r1 & 0xff); 398 break; 399 case 2: 400 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, 401 addr, asi, r1 & 0xffff); 402 break; 403 case 4: 404 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, 405 addr, asi, r1 & 0xffffffff); 406 break; 407 case 8: 408 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, 409 addr, asi, r1); 410 break; 411 } 412 } 413 #endif 414 415 #ifndef CONFIG_USER_ONLY 416 #ifndef TARGET_SPARC64 417 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 418 bool is_write, bool is_exec, int is_asi, 419 unsigned size, uintptr_t retaddr) 420 { 421 CPUSPARCState *env = cpu_env(cs); 422 int fault_type; 423 424 #ifdef DEBUG_UNASSIGNED 425 if (is_asi) { 426 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 427 " asi 0x%02x from " TARGET_FMT_lx "\n", 428 is_exec ? "exec" : is_write ? "write" : "read", size, 429 size == 1 ? "" : "s", addr, is_asi, env->pc); 430 } else { 431 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 432 " from " TARGET_FMT_lx "\n", 433 is_exec ? "exec" : is_write ? "write" : "read", size, 434 size == 1 ? "" : "s", addr, env->pc); 435 } 436 #endif 437 /* Don't overwrite translation and access faults */ 438 fault_type = (env->mmuregs[3] & 0x1c) >> 2; 439 if ((fault_type > 4) || (fault_type == 0)) { 440 env->mmuregs[3] = 0; /* Fault status register */ 441 if (is_asi) { 442 env->mmuregs[3] |= 1 << 16; 443 } 444 if (env->psrs) { 445 env->mmuregs[3] |= 1 << 5; 446 } 447 if (is_exec) { 448 env->mmuregs[3] |= 1 << 6; 449 } 450 if (is_write) { 451 env->mmuregs[3] |= 1 << 7; 452 } 453 env->mmuregs[3] |= (5 << 2) | 2; 454 /* SuperSPARC will never place instruction fault addresses in the FAR */ 455 if (!is_exec) { 456 env->mmuregs[4] = addr; /* Fault address register */ 457 } 458 } 459 /* overflow (same type fault was not read before another fault) */ 460 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { 461 env->mmuregs[3] |= 1; 462 } 463 464 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { 465 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS; 466 cpu_raise_exception_ra(env, tt, retaddr); 467 } 468 469 /* 470 * flush neverland mappings created during no-fault mode, 471 * so the sequential MMU faults report proper fault types 472 */ 473 if (env->mmuregs[0] & MMU_NF) { 474 tlb_flush(cs); 475 } 476 } 477 #else 478 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 479 bool is_write, bool is_exec, int is_asi, 480 unsigned size, uintptr_t retaddr) 481 { 482 CPUSPARCState *env = cpu_env(cs); 483 484 #ifdef DEBUG_UNASSIGNED 485 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx 486 "\n", addr, env->pc); 487 #endif 488 489 if (is_exec) { /* XXX has_hypervisor */ 490 if (env->lsu & (IMMU_E)) { 491 cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr); 492 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 493 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr); 494 } 495 } else { 496 if (env->lsu & (DMMU_E)) { 497 cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr); 498 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 499 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr); 500 } 501 } 502 } 503 #endif 504 #endif 505 506 #ifndef TARGET_SPARC64 507 #ifndef CONFIG_USER_ONLY 508 509 510 /* Leon3 cache control */ 511 512 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr, 513 uint64_t val, int size) 514 { 515 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", 516 addr, val, size); 517 518 if (size != 4) { 519 DPRINTF_CACHE_CONTROL("32bits only\n"); 520 return; 521 } 522 523 switch (addr) { 524 case 0x00: /* Cache control */ 525 526 /* These values must always be read as zeros */ 527 val &= ~CACHE_CTRL_FD; 528 val &= ~CACHE_CTRL_FI; 529 val &= ~CACHE_CTRL_IB; 530 val &= ~CACHE_CTRL_IP; 531 val &= ~CACHE_CTRL_DP; 532 533 env->cache_control = val; 534 break; 535 case 0x04: /* Instruction cache configuration */ 536 case 0x08: /* Data cache configuration */ 537 /* Read Only */ 538 break; 539 default: 540 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr); 541 break; 542 }; 543 } 544 545 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr, 546 int size) 547 { 548 uint64_t ret = 0; 549 550 if (size != 4) { 551 DPRINTF_CACHE_CONTROL("32bits only\n"); 552 return 0; 553 } 554 555 switch (addr) { 556 case 0x00: /* Cache control */ 557 ret = env->cache_control; 558 break; 559 560 /* Configuration registers are read and only always keep those 561 predefined values */ 562 563 case 0x04: /* Instruction cache configuration */ 564 ret = 0x10220000; 565 break; 566 case 0x08: /* Data cache configuration */ 567 ret = 0x18220000; 568 break; 569 default: 570 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr); 571 break; 572 }; 573 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", 574 addr, ret, size); 575 return ret; 576 } 577 578 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 579 int asi, uint32_t memop) 580 { 581 int size = 1 << (memop & MO_SIZE); 582 int sign = memop & MO_SIGN; 583 CPUState *cs = env_cpu(env); 584 uint64_t ret = 0; 585 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) 586 uint32_t last_addr = addr; 587 #endif 588 MemOpIdx oi; 589 590 do_check_align(env, addr, size - 1, GETPC()); 591 switch (asi) { 592 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 593 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 594 switch (addr) { 595 case 0x00: /* Leon3 Cache Control */ 596 case 0x08: /* Leon3 Instruction Cache config */ 597 case 0x0C: /* Leon3 Date Cache config */ 598 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 599 ret = leon3_cache_control_ld(env, addr, size); 600 } 601 break; 602 case 0x01c00a00: /* MXCC control register */ 603 if (size == 8) { 604 ret = env->mxccregs[3]; 605 } else { 606 qemu_log_mask(LOG_UNIMP, 607 "%08x: unimplemented access size: %d\n", addr, 608 size); 609 } 610 break; 611 case 0x01c00a04: /* MXCC control register */ 612 if (size == 4) { 613 ret = env->mxccregs[3]; 614 } else { 615 qemu_log_mask(LOG_UNIMP, 616 "%08x: unimplemented access size: %d\n", addr, 617 size); 618 } 619 break; 620 case 0x01c00c00: /* Module reset register */ 621 if (size == 8) { 622 ret = env->mxccregs[5]; 623 /* should we do something here? */ 624 } else { 625 qemu_log_mask(LOG_UNIMP, 626 "%08x: unimplemented access size: %d\n", addr, 627 size); 628 } 629 break; 630 case 0x01c00f00: /* MBus port address register */ 631 if (size == 8) { 632 ret = env->mxccregs[7]; 633 } else { 634 qemu_log_mask(LOG_UNIMP, 635 "%08x: unimplemented access size: %d\n", addr, 636 size); 637 } 638 break; 639 default: 640 qemu_log_mask(LOG_UNIMP, 641 "%08x: unimplemented address, size: %d\n", addr, 642 size); 643 break; 644 } 645 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " 646 "addr = %08x -> ret = %" PRIx64 "," 647 "addr = %08x\n", asi, size, sign, last_addr, ret, addr); 648 #ifdef DEBUG_MXCC 649 dump_mxcc(env); 650 #endif 651 break; 652 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */ 653 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */ 654 { 655 int mmulev; 656 657 mmulev = (addr >> 8) & 15; 658 if (mmulev > 4) { 659 ret = 0; 660 } else { 661 ret = mmu_probe(env, addr, mmulev); 662 } 663 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", 664 addr, mmulev, ret); 665 } 666 break; 667 case ASI_M_MMUREGS: /* SuperSparc MMU regs */ 668 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */ 669 { 670 int reg = (addr >> 8) & 0x1f; 671 672 ret = env->mmuregs[reg]; 673 if (reg == 3) { /* Fault status cleared on read */ 674 env->mmuregs[3] = 0; 675 } else if (reg == 0x13) { /* Fault status read */ 676 ret = env->mmuregs[3]; 677 } else if (reg == 0x14) { /* Fault address read */ 678 ret = env->mmuregs[4]; 679 } 680 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); 681 } 682 break; 683 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 684 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 685 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 686 break; 687 case ASI_KERNELTXT: /* Supervisor code access */ 688 oi = make_memop_idx(memop, cpu_mmu_index(env_cpu(env), true)); 689 switch (size) { 690 case 1: 691 ret = cpu_ldb_code_mmu(env, addr, oi, GETPC()); 692 break; 693 case 2: 694 ret = cpu_ldw_code_mmu(env, addr, oi, GETPC()); 695 break; 696 default: 697 case 4: 698 ret = cpu_ldl_code_mmu(env, addr, oi, GETPC()); 699 break; 700 case 8: 701 ret = cpu_ldq_code_mmu(env, addr, oi, GETPC()); 702 break; 703 } 704 break; 705 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */ 706 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */ 707 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */ 708 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ 709 break; 710 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 711 { 712 MemTxResult result; 713 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 714 715 switch (size) { 716 case 1: 717 ret = address_space_ldub(cs->as, access_addr, 718 MEMTXATTRS_UNSPECIFIED, &result); 719 break; 720 case 2: 721 ret = address_space_lduw(cs->as, access_addr, 722 MEMTXATTRS_UNSPECIFIED, &result); 723 break; 724 default: 725 case 4: 726 ret = address_space_ldl(cs->as, access_addr, 727 MEMTXATTRS_UNSPECIFIED, &result); 728 break; 729 case 8: 730 ret = address_space_ldq(cs->as, access_addr, 731 MEMTXATTRS_UNSPECIFIED, &result); 732 break; 733 } 734 735 if (result != MEMTX_OK) { 736 sparc_raise_mmu_fault(cs, access_addr, false, false, false, 737 size, GETPC()); 738 } 739 break; 740 } 741 case 0x30: /* Turbosparc secondary cache diagnostic */ 742 case 0x31: /* Turbosparc RAM snoop */ 743 case 0x32: /* Turbosparc page table descriptor diagnostic */ 744 case 0x39: /* data cache diagnostic register */ 745 ret = 0; 746 break; 747 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ 748 { 749 int reg = (addr >> 8) & 3; 750 751 switch (reg) { 752 case 0: /* Breakpoint Value (Addr) */ 753 ret = env->mmubpregs[reg]; 754 break; 755 case 1: /* Breakpoint Mask */ 756 ret = env->mmubpregs[reg]; 757 break; 758 case 2: /* Breakpoint Control */ 759 ret = env->mmubpregs[reg]; 760 break; 761 case 3: /* Breakpoint Status */ 762 ret = env->mmubpregs[reg]; 763 env->mmubpregs[reg] = 0ULL; 764 break; 765 } 766 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, 767 ret); 768 } 769 break; 770 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 771 ret = env->mmubpctrv; 772 break; 773 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 774 ret = env->mmubpctrc; 775 break; 776 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 777 ret = env->mmubpctrs; 778 break; 779 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 780 ret = env->mmubpaction; 781 break; 782 case ASI_USERTXT: /* User code access, XXX */ 783 default: 784 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); 785 ret = 0; 786 break; 787 788 case ASI_USERDATA: /* User data access */ 789 case ASI_KERNELDATA: /* Supervisor data access */ 790 case ASI_P: /* Implicit primary context data access (v9 only?) */ 791 case ASI_M_BYPASS: /* MMU passthrough */ 792 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 793 /* These are always handled inline. */ 794 g_assert_not_reached(); 795 } 796 if (sign) { 797 switch (size) { 798 case 1: 799 ret = (int8_t) ret; 800 break; 801 case 2: 802 ret = (int16_t) ret; 803 break; 804 case 4: 805 ret = (int32_t) ret; 806 break; 807 default: 808 break; 809 } 810 } 811 #ifdef DEBUG_ASI 812 dump_asi("read ", last_addr, asi, size, ret); 813 #endif 814 return ret; 815 } 816 817 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, 818 int asi, uint32_t memop) 819 { 820 int size = 1 << (memop & MO_SIZE); 821 CPUState *cs = env_cpu(env); 822 823 do_check_align(env, addr, size - 1, GETPC()); 824 switch (asi) { 825 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 826 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 827 switch (addr) { 828 case 0x00: /* Leon3 Cache Control */ 829 case 0x08: /* Leon3 Instruction Cache config */ 830 case 0x0C: /* Leon3 Date Cache config */ 831 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 832 leon3_cache_control_st(env, addr, val, size); 833 } 834 break; 835 836 case 0x01c00000: /* MXCC stream data register 0 */ 837 if (size == 8) { 838 env->mxccdata[0] = val; 839 } else { 840 qemu_log_mask(LOG_UNIMP, 841 "%08x: unimplemented access size: %d\n", addr, 842 size); 843 } 844 break; 845 case 0x01c00008: /* MXCC stream data register 1 */ 846 if (size == 8) { 847 env->mxccdata[1] = val; 848 } else { 849 qemu_log_mask(LOG_UNIMP, 850 "%08x: unimplemented access size: %d\n", addr, 851 size); 852 } 853 break; 854 case 0x01c00010: /* MXCC stream data register 2 */ 855 if (size == 8) { 856 env->mxccdata[2] = val; 857 } else { 858 qemu_log_mask(LOG_UNIMP, 859 "%08x: unimplemented access size: %d\n", addr, 860 size); 861 } 862 break; 863 case 0x01c00018: /* MXCC stream data register 3 */ 864 if (size == 8) { 865 env->mxccdata[3] = val; 866 } else { 867 qemu_log_mask(LOG_UNIMP, 868 "%08x: unimplemented access size: %d\n", addr, 869 size); 870 } 871 break; 872 case 0x01c00100: /* MXCC stream source */ 873 { 874 int i; 875 876 if (size == 8) { 877 env->mxccregs[0] = val; 878 } else { 879 qemu_log_mask(LOG_UNIMP, 880 "%08x: unimplemented access size: %d\n", addr, 881 size); 882 } 883 884 for (i = 0; i < 4; i++) { 885 MemTxResult result; 886 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; 887 888 env->mxccdata[i] = address_space_ldq(cs->as, 889 access_addr, 890 MEMTXATTRS_UNSPECIFIED, 891 &result); 892 if (result != MEMTX_OK) { 893 /* TODO: investigate whether this is the right behaviour */ 894 sparc_raise_mmu_fault(cs, access_addr, false, false, 895 false, size, GETPC()); 896 } 897 } 898 break; 899 } 900 case 0x01c00200: /* MXCC stream destination */ 901 { 902 int i; 903 904 if (size == 8) { 905 env->mxccregs[1] = val; 906 } else { 907 qemu_log_mask(LOG_UNIMP, 908 "%08x: unimplemented access size: %d\n", addr, 909 size); 910 } 911 912 for (i = 0; i < 4; i++) { 913 MemTxResult result; 914 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; 915 916 address_space_stq(cs->as, access_addr, env->mxccdata[i], 917 MEMTXATTRS_UNSPECIFIED, &result); 918 919 if (result != MEMTX_OK) { 920 /* TODO: investigate whether this is the right behaviour */ 921 sparc_raise_mmu_fault(cs, access_addr, true, false, 922 false, size, GETPC()); 923 } 924 } 925 break; 926 } 927 case 0x01c00a00: /* MXCC control register */ 928 if (size == 8) { 929 env->mxccregs[3] = val; 930 } else { 931 qemu_log_mask(LOG_UNIMP, 932 "%08x: unimplemented access size: %d\n", addr, 933 size); 934 } 935 break; 936 case 0x01c00a04: /* MXCC control register */ 937 if (size == 4) { 938 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) 939 | val; 940 } else { 941 qemu_log_mask(LOG_UNIMP, 942 "%08x: unimplemented access size: %d\n", addr, 943 size); 944 } 945 break; 946 case 0x01c00e00: /* MXCC error register */ 947 /* writing a 1 bit clears the error */ 948 if (size == 8) { 949 env->mxccregs[6] &= ~val; 950 } else { 951 qemu_log_mask(LOG_UNIMP, 952 "%08x: unimplemented access size: %d\n", addr, 953 size); 954 } 955 break; 956 case 0x01c00f00: /* MBus port address register */ 957 if (size == 8) { 958 env->mxccregs[7] = val; 959 } else { 960 qemu_log_mask(LOG_UNIMP, 961 "%08x: unimplemented access size: %d\n", addr, 962 size); 963 } 964 break; 965 default: 966 qemu_log_mask(LOG_UNIMP, 967 "%08x: unimplemented address, size: %d\n", addr, 968 size); 969 break; 970 } 971 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", 972 asi, size, addr, val); 973 #ifdef DEBUG_MXCC 974 dump_mxcc(env); 975 #endif 976 break; 977 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */ 978 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */ 979 { 980 int mmulev; 981 982 mmulev = (addr >> 8) & 15; 983 DPRINTF_MMU("mmu flush level %d\n", mmulev); 984 switch (mmulev) { 985 case 0: /* flush page */ 986 tlb_flush_page(cs, addr & 0xfffff000); 987 break; 988 case 1: /* flush segment (256k) */ 989 case 2: /* flush region (16M) */ 990 case 3: /* flush context (4G) */ 991 case 4: /* flush entire */ 992 tlb_flush(cs); 993 break; 994 default: 995 break; 996 } 997 #ifdef DEBUG_MMU 998 dump_mmu(env); 999 #endif 1000 } 1001 break; 1002 case ASI_M_MMUREGS: /* write MMU regs */ 1003 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */ 1004 { 1005 int reg = (addr >> 8) & 0x1f; 1006 uint32_t oldreg; 1007 1008 oldreg = env->mmuregs[reg]; 1009 switch (reg) { 1010 case 0: /* Control Register */ 1011 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | 1012 (val & 0x00ffffff); 1013 /* Mappings generated during no-fault mode 1014 are invalid in normal mode. */ 1015 if ((oldreg ^ env->mmuregs[reg]) 1016 & (MMU_NF | env->def.mmu_bm)) { 1017 tlb_flush(cs); 1018 } 1019 break; 1020 case 1: /* Context Table Pointer Register */ 1021 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; 1022 break; 1023 case 2: /* Context Register */ 1024 env->mmuregs[reg] = val & env->def.mmu_cxr_mask; 1025 if (oldreg != env->mmuregs[reg]) { 1026 /* we flush when the MMU context changes because 1027 QEMU has no MMU context support */ 1028 tlb_flush(cs); 1029 } 1030 break; 1031 case 3: /* Synchronous Fault Status Register with Clear */ 1032 case 4: /* Synchronous Fault Address Register */ 1033 break; 1034 case 0x10: /* TLB Replacement Control Register */ 1035 env->mmuregs[reg] = val & env->def.mmu_trcr_mask; 1036 break; 1037 case 0x13: /* Synchronous Fault Status Register with Read 1038 and Clear */ 1039 env->mmuregs[3] = val & env->def.mmu_sfsr_mask; 1040 break; 1041 case 0x14: /* Synchronous Fault Address Register */ 1042 env->mmuregs[4] = val; 1043 break; 1044 default: 1045 env->mmuregs[reg] = val; 1046 break; 1047 } 1048 if (oldreg != env->mmuregs[reg]) { 1049 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", 1050 reg, oldreg, env->mmuregs[reg]); 1051 } 1052 #ifdef DEBUG_MMU 1053 dump_mmu(env); 1054 #endif 1055 } 1056 break; 1057 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 1058 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 1059 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 1060 break; 1061 case ASI_M_TXTC_TAG: /* I-cache tag */ 1062 case ASI_M_TXTC_DATA: /* I-cache data */ 1063 case ASI_M_DATAC_TAG: /* D-cache tag */ 1064 case ASI_M_DATAC_DATA: /* D-cache data */ 1065 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */ 1066 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */ 1067 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */ 1068 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */ 1069 case ASI_M_FLUSH_USER: /* I/D-cache flush user */ 1070 break; 1071 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 1072 { 1073 MemTxResult result; 1074 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 1075 1076 switch (size) { 1077 case 1: 1078 address_space_stb(cs->as, access_addr, val, 1079 MEMTXATTRS_UNSPECIFIED, &result); 1080 break; 1081 case 2: 1082 address_space_stw(cs->as, access_addr, val, 1083 MEMTXATTRS_UNSPECIFIED, &result); 1084 break; 1085 case 4: 1086 default: 1087 address_space_stl(cs->as, access_addr, val, 1088 MEMTXATTRS_UNSPECIFIED, &result); 1089 break; 1090 case 8: 1091 address_space_stq(cs->as, access_addr, val, 1092 MEMTXATTRS_UNSPECIFIED, &result); 1093 break; 1094 } 1095 if (result != MEMTX_OK) { 1096 sparc_raise_mmu_fault(cs, access_addr, true, false, false, 1097 size, GETPC()); 1098 } 1099 } 1100 break; 1101 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ 1102 case 0x31: /* store buffer data, Ross RT620 I-cache flush or 1103 Turbosparc snoop RAM */ 1104 case 0x32: /* store buffer control or Turbosparc page table 1105 descriptor diagnostic */ 1106 case 0x36: /* I-cache flash clear */ 1107 case 0x37: /* D-cache flash clear */ 1108 break; 1109 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ 1110 { 1111 int reg = (addr >> 8) & 3; 1112 1113 switch (reg) { 1114 case 0: /* Breakpoint Value (Addr) */ 1115 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1116 break; 1117 case 1: /* Breakpoint Mask */ 1118 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1119 break; 1120 case 2: /* Breakpoint Control */ 1121 env->mmubpregs[reg] = (val & 0x7fULL); 1122 break; 1123 case 3: /* Breakpoint Status */ 1124 env->mmubpregs[reg] = (val & 0xfULL); 1125 break; 1126 } 1127 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg, 1128 env->mmuregs[reg]); 1129 } 1130 break; 1131 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 1132 env->mmubpctrv = val & 0xffffffff; 1133 break; 1134 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 1135 env->mmubpctrc = val & 0x3; 1136 break; 1137 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 1138 env->mmubpctrs = val & 0x3; 1139 break; 1140 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 1141 env->mmubpaction = val & 0x1fff; 1142 break; 1143 case ASI_USERTXT: /* User code access, XXX */ 1144 case ASI_KERNELTXT: /* Supervisor code access, XXX */ 1145 default: 1146 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); 1147 break; 1148 1149 case ASI_USERDATA: /* User data access */ 1150 case ASI_KERNELDATA: /* Supervisor data access */ 1151 case ASI_P: 1152 case ASI_M_BYPASS: /* MMU passthrough */ 1153 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 1154 case ASI_M_BCOPY: /* Block copy, sta access */ 1155 case ASI_M_BFILL: /* Block fill, stda access */ 1156 /* These are always handled inline. */ 1157 g_assert_not_reached(); 1158 } 1159 #ifdef DEBUG_ASI 1160 dump_asi("write", addr, asi, size, val); 1161 #endif 1162 } 1163 1164 #endif /* CONFIG_USER_ONLY */ 1165 #else /* TARGET_SPARC64 */ 1166 1167 #ifdef CONFIG_USER_ONLY 1168 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1169 int asi, uint32_t memop) 1170 { 1171 int size = 1 << (memop & MO_SIZE); 1172 int sign = memop & MO_SIGN; 1173 uint64_t ret = 0; 1174 1175 if (asi < 0x80) { 1176 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1177 } 1178 do_check_align(env, addr, size - 1, GETPC()); 1179 addr = asi_address_mask(env, asi, addr); 1180 1181 switch (asi) { 1182 case ASI_PNF: /* Primary no-fault */ 1183 case ASI_PNFL: /* Primary no-fault LE */ 1184 case ASI_SNF: /* Secondary no-fault */ 1185 case ASI_SNFL: /* Secondary no-fault LE */ 1186 if (!page_check_range(addr, size, PAGE_READ)) { 1187 ret = 0; 1188 break; 1189 } 1190 switch (size) { 1191 case 1: 1192 ret = cpu_ldub_data(env, addr); 1193 break; 1194 case 2: 1195 ret = cpu_lduw_data(env, addr); 1196 break; 1197 case 4: 1198 ret = cpu_ldl_data(env, addr); 1199 break; 1200 case 8: 1201 ret = cpu_ldq_data(env, addr); 1202 break; 1203 default: 1204 g_assert_not_reached(); 1205 } 1206 break; 1207 break; 1208 1209 case ASI_P: /* Primary */ 1210 case ASI_PL: /* Primary LE */ 1211 case ASI_S: /* Secondary */ 1212 case ASI_SL: /* Secondary LE */ 1213 /* These are always handled inline. */ 1214 g_assert_not_reached(); 1215 1216 default: 1217 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1218 } 1219 1220 /* Convert from little endian */ 1221 switch (asi) { 1222 case ASI_PNFL: /* Primary no-fault LE */ 1223 case ASI_SNFL: /* Secondary no-fault LE */ 1224 switch (size) { 1225 case 2: 1226 ret = bswap16(ret); 1227 break; 1228 case 4: 1229 ret = bswap32(ret); 1230 break; 1231 case 8: 1232 ret = bswap64(ret); 1233 break; 1234 } 1235 } 1236 1237 /* Convert to signed number */ 1238 if (sign) { 1239 switch (size) { 1240 case 1: 1241 ret = (int8_t) ret; 1242 break; 1243 case 2: 1244 ret = (int16_t) ret; 1245 break; 1246 case 4: 1247 ret = (int32_t) ret; 1248 break; 1249 } 1250 } 1251 #ifdef DEBUG_ASI 1252 dump_asi("read", addr, asi, size, ret); 1253 #endif 1254 return ret; 1255 } 1256 1257 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1258 int asi, uint32_t memop) 1259 { 1260 int size = 1 << (memop & MO_SIZE); 1261 #ifdef DEBUG_ASI 1262 dump_asi("write", addr, asi, size, val); 1263 #endif 1264 if (asi < 0x80) { 1265 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1266 } 1267 do_check_align(env, addr, size - 1, GETPC()); 1268 1269 switch (asi) { 1270 case ASI_P: /* Primary */ 1271 case ASI_PL: /* Primary LE */ 1272 case ASI_S: /* Secondary */ 1273 case ASI_SL: /* Secondary LE */ 1274 /* These are always handled inline. */ 1275 g_assert_not_reached(); 1276 1277 case ASI_PNF: /* Primary no-fault, RO */ 1278 case ASI_SNF: /* Secondary no-fault, RO */ 1279 case ASI_PNFL: /* Primary no-fault LE, RO */ 1280 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1281 default: 1282 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1283 } 1284 } 1285 1286 #else /* CONFIG_USER_ONLY */ 1287 1288 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1289 int asi, uint32_t memop) 1290 { 1291 int size = 1 << (memop & MO_SIZE); 1292 int sign = memop & MO_SIGN; 1293 CPUState *cs = env_cpu(env); 1294 uint64_t ret = 0; 1295 #if defined(DEBUG_ASI) 1296 target_ulong last_addr = addr; 1297 #endif 1298 1299 asi &= 0xff; 1300 1301 do_check_asi(env, asi, GETPC()); 1302 do_check_align(env, addr, size - 1, GETPC()); 1303 addr = asi_address_mask(env, asi, addr); 1304 1305 switch (asi) { 1306 case ASI_PNF: 1307 case ASI_PNFL: 1308 case ASI_SNF: 1309 case ASI_SNFL: 1310 { 1311 MemOpIdx oi; 1312 int idx = (env->pstate & PS_PRIV 1313 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX) 1314 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX)); 1315 1316 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) { 1317 #ifdef DEBUG_ASI 1318 dump_asi("read ", last_addr, asi, size, ret); 1319 #endif 1320 /* exception_index is set in get_physical_address_data. */ 1321 cpu_raise_exception_ra(env, cs->exception_index, GETPC()); 1322 } 1323 oi = make_memop_idx(memop, idx); 1324 switch (size) { 1325 case 1: 1326 ret = cpu_ldb_mmu(env, addr, oi, GETPC()); 1327 break; 1328 case 2: 1329 ret = cpu_ldw_mmu(env, addr, oi, GETPC()); 1330 break; 1331 case 4: 1332 ret = cpu_ldl_mmu(env, addr, oi, GETPC()); 1333 break; 1334 case 8: 1335 ret = cpu_ldq_mmu(env, addr, oi, GETPC()); 1336 break; 1337 default: 1338 g_assert_not_reached(); 1339 } 1340 } 1341 break; 1342 1343 case ASI_AIUP: /* As if user primary */ 1344 case ASI_AIUS: /* As if user secondary */ 1345 case ASI_AIUPL: /* As if user primary LE */ 1346 case ASI_AIUSL: /* As if user secondary LE */ 1347 case ASI_P: /* Primary */ 1348 case ASI_S: /* Secondary */ 1349 case ASI_PL: /* Primary LE */ 1350 case ASI_SL: /* Secondary LE */ 1351 case ASI_REAL: /* Bypass */ 1352 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1353 case ASI_REAL_L: /* Bypass LE */ 1354 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1355 case ASI_N: /* Nucleus */ 1356 case ASI_NL: /* Nucleus Little Endian (LE) */ 1357 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1358 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1359 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1360 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1361 case ASI_TWINX_REAL: /* Real address, twinx */ 1362 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1363 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1364 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1365 case ASI_TWINX_N: /* Nucleus, twinx */ 1366 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1367 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1368 case ASI_TWINX_P: /* Primary, twinx */ 1369 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1370 case ASI_TWINX_S: /* Secondary, twinx */ 1371 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1372 /* These are always handled inline. */ 1373 g_assert_not_reached(); 1374 1375 case ASI_UPA_CONFIG: /* UPA config */ 1376 /* XXX */ 1377 break; 1378 case ASI_LSU_CONTROL: /* LSU */ 1379 ret = env->lsu; 1380 break; 1381 case ASI_IMMU: /* I-MMU regs */ 1382 { 1383 int reg = (addr >> 3) & 0xf; 1384 switch (reg) { 1385 case 0: 1386 /* 0x00 I-TSB Tag Target register */ 1387 ret = ultrasparc_tag_target(env->immu.tag_access); 1388 break; 1389 case 3: /* SFSR */ 1390 ret = env->immu.sfsr; 1391 break; 1392 case 5: /* TSB access */ 1393 ret = env->immu.tsb; 1394 break; 1395 case 6: 1396 /* 0x30 I-TSB Tag Access register */ 1397 ret = env->immu.tag_access; 1398 break; 1399 default: 1400 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1401 ret = 0; 1402 } 1403 break; 1404 } 1405 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */ 1406 { 1407 /* env->immuregs[5] holds I-MMU TSB register value 1408 env->immuregs[6] holds I-MMU Tag Access register value */ 1409 ret = ultrasparc_tsb_pointer(env, &env->immu, 0); 1410 break; 1411 } 1412 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ 1413 { 1414 /* env->immuregs[5] holds I-MMU TSB register value 1415 env->immuregs[6] holds I-MMU Tag Access register value */ 1416 ret = ultrasparc_tsb_pointer(env, &env->immu, 1); 1417 break; 1418 } 1419 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1420 { 1421 int reg = (addr >> 3) & 0x3f; 1422 1423 ret = env->itlb[reg].tte; 1424 break; 1425 } 1426 case ASI_ITLB_TAG_READ: /* I-MMU tag read */ 1427 { 1428 int reg = (addr >> 3) & 0x3f; 1429 1430 ret = env->itlb[reg].tag; 1431 break; 1432 } 1433 case ASI_DMMU: /* D-MMU regs */ 1434 { 1435 int reg = (addr >> 3) & 0xf; 1436 switch (reg) { 1437 case 0: 1438 /* 0x00 D-TSB Tag Target register */ 1439 ret = ultrasparc_tag_target(env->dmmu.tag_access); 1440 break; 1441 case 1: /* 0x08 Primary Context */ 1442 ret = env->dmmu.mmu_primary_context; 1443 break; 1444 case 2: /* 0x10 Secondary Context */ 1445 ret = env->dmmu.mmu_secondary_context; 1446 break; 1447 case 3: /* SFSR */ 1448 ret = env->dmmu.sfsr; 1449 break; 1450 case 4: /* 0x20 SFAR */ 1451 ret = env->dmmu.sfar; 1452 break; 1453 case 5: /* 0x28 TSB access */ 1454 ret = env->dmmu.tsb; 1455 break; 1456 case 6: /* 0x30 D-TSB Tag Access register */ 1457 ret = env->dmmu.tag_access; 1458 break; 1459 case 7: 1460 ret = env->dmmu.virtual_watchpoint; 1461 break; 1462 case 8: 1463 ret = env->dmmu.physical_watchpoint; 1464 break; 1465 default: 1466 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1467 ret = 0; 1468 } 1469 break; 1470 } 1471 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */ 1472 { 1473 /* env->dmmuregs[5] holds D-MMU TSB register value 1474 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1475 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); 1476 break; 1477 } 1478 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ 1479 { 1480 /* env->dmmuregs[5] holds D-MMU TSB register value 1481 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1482 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); 1483 break; 1484 } 1485 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1486 { 1487 int reg = (addr >> 3) & 0x3f; 1488 1489 ret = env->dtlb[reg].tte; 1490 break; 1491 } 1492 case ASI_DTLB_TAG_READ: /* D-MMU tag read */ 1493 { 1494 int reg = (addr >> 3) & 0x3f; 1495 1496 ret = env->dtlb[reg].tag; 1497 break; 1498 } 1499 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1500 break; 1501 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1502 ret = env->ivec_status; 1503 break; 1504 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1505 { 1506 int reg = (addr >> 4) & 0x3; 1507 if (reg < 3) { 1508 ret = env->ivec_data[reg]; 1509 } 1510 break; 1511 } 1512 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1513 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1514 /* Hyperprivileged access only */ 1515 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1516 } 1517 /* fall through */ 1518 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1519 { 1520 unsigned int i = (addr >> 3) & 0x7; 1521 ret = env->scratch[i]; 1522 break; 1523 } 1524 case ASI_MMU: /* UA2005 Context ID registers */ 1525 switch ((addr >> 3) & 0x3) { 1526 case 1: 1527 ret = env->dmmu.mmu_primary_context; 1528 break; 1529 case 2: 1530 ret = env->dmmu.mmu_secondary_context; 1531 break; 1532 default: 1533 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1534 } 1535 break; 1536 case ASI_DCACHE_DATA: /* D-cache data */ 1537 case ASI_DCACHE_TAG: /* D-cache tag access */ 1538 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1539 case ASI_AFSR: /* E-cache asynchronous fault status */ 1540 case ASI_AFAR: /* E-cache asynchronous fault address */ 1541 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1542 case ASI_IC_INSTR: /* I-cache instruction access */ 1543 case ASI_IC_TAG: /* I-cache tag access */ 1544 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1545 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1546 case ASI_EC_W: /* E-cache tag */ 1547 case ASI_EC_R: /* E-cache tag */ 1548 break; 1549 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */ 1550 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */ 1551 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */ 1552 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */ 1553 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ 1554 case ASI_INTR_W: /* Interrupt vector, WO */ 1555 default: 1556 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1557 ret = 0; 1558 break; 1559 } 1560 1561 /* Convert to signed number */ 1562 if (sign) { 1563 switch (size) { 1564 case 1: 1565 ret = (int8_t) ret; 1566 break; 1567 case 2: 1568 ret = (int16_t) ret; 1569 break; 1570 case 4: 1571 ret = (int32_t) ret; 1572 break; 1573 default: 1574 break; 1575 } 1576 } 1577 #ifdef DEBUG_ASI 1578 dump_asi("read ", last_addr, asi, size, ret); 1579 #endif 1580 return ret; 1581 } 1582 1583 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1584 int asi, uint32_t memop) 1585 { 1586 int size = 1 << (memop & MO_SIZE); 1587 CPUState *cs = env_cpu(env); 1588 1589 #ifdef DEBUG_ASI 1590 dump_asi("write", addr, asi, size, val); 1591 #endif 1592 1593 asi &= 0xff; 1594 1595 do_check_asi(env, asi, GETPC()); 1596 do_check_align(env, addr, size - 1, GETPC()); 1597 addr = asi_address_mask(env, asi, addr); 1598 1599 switch (asi) { 1600 case ASI_AIUP: /* As if user primary */ 1601 case ASI_AIUS: /* As if user secondary */ 1602 case ASI_AIUPL: /* As if user primary LE */ 1603 case ASI_AIUSL: /* As if user secondary LE */ 1604 case ASI_P: /* Primary */ 1605 case ASI_S: /* Secondary */ 1606 case ASI_PL: /* Primary LE */ 1607 case ASI_SL: /* Secondary LE */ 1608 case ASI_REAL: /* Bypass */ 1609 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1610 case ASI_REAL_L: /* Bypass LE */ 1611 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1612 case ASI_N: /* Nucleus */ 1613 case ASI_NL: /* Nucleus Little Endian (LE) */ 1614 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1615 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1616 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1617 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1618 case ASI_TWINX_REAL: /* Real address, twinx */ 1619 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1620 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1621 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1622 case ASI_TWINX_N: /* Nucleus, twinx */ 1623 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1624 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1625 case ASI_TWINX_P: /* Primary, twinx */ 1626 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1627 case ASI_TWINX_S: /* Secondary, twinx */ 1628 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1629 /* These are always handled inline. */ 1630 g_assert_not_reached(); 1631 /* these ASIs have different functions on UltraSPARC-IIIi 1632 * and UA2005 CPUs. Use the explicit numbers to avoid confusion 1633 */ 1634 case 0x31: 1635 case 0x32: 1636 case 0x39: 1637 case 0x3a: 1638 if (cpu_has_hypervisor(env)) { 1639 /* UA2005 1640 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0 1641 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1 1642 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0 1643 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1 1644 */ 1645 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1646 env->dmmu.sun4v_tsb_pointers[idx] = val; 1647 } else { 1648 goto illegal_insn; 1649 } 1650 break; 1651 case 0x33: 1652 case 0x3b: 1653 if (cpu_has_hypervisor(env)) { 1654 /* UA2005 1655 * ASI_DMMU_CTX_ZERO_CONFIG 1656 * ASI_DMMU_CTX_NONZERO_CONFIG 1657 */ 1658 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1659 } else { 1660 goto illegal_insn; 1661 } 1662 break; 1663 case 0x35: 1664 case 0x36: 1665 case 0x3d: 1666 case 0x3e: 1667 if (cpu_has_hypervisor(env)) { 1668 /* UA2005 1669 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0 1670 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1 1671 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0 1672 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1 1673 */ 1674 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1675 env->immu.sun4v_tsb_pointers[idx] = val; 1676 } else { 1677 goto illegal_insn; 1678 } 1679 break; 1680 case 0x37: 1681 case 0x3f: 1682 if (cpu_has_hypervisor(env)) { 1683 /* UA2005 1684 * ASI_IMMU_CTX_ZERO_CONFIG 1685 * ASI_IMMU_CTX_NONZERO_CONFIG 1686 */ 1687 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1688 } else { 1689 goto illegal_insn; 1690 } 1691 break; 1692 case ASI_UPA_CONFIG: /* UPA config */ 1693 /* XXX */ 1694 return; 1695 case ASI_LSU_CONTROL: /* LSU */ 1696 env->lsu = val & (DMMU_E | IMMU_E); 1697 return; 1698 case ASI_IMMU: /* I-MMU regs */ 1699 { 1700 int reg = (addr >> 3) & 0xf; 1701 uint64_t oldreg; 1702 1703 oldreg = env->immu.mmuregs[reg]; 1704 switch (reg) { 1705 case 0: /* RO */ 1706 return; 1707 case 1: /* Not in I-MMU */ 1708 case 2: 1709 return; 1710 case 3: /* SFSR */ 1711 if ((val & 1) == 0) { 1712 val = 0; /* Clear SFSR */ 1713 } 1714 env->immu.sfsr = val; 1715 break; 1716 case 4: /* RO */ 1717 return; 1718 case 5: /* TSB access */ 1719 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" 1720 PRIx64 "\n", env->immu.tsb, val); 1721 env->immu.tsb = val; 1722 break; 1723 case 6: /* Tag access */ 1724 env->immu.tag_access = val; 1725 break; 1726 case 7: 1727 case 8: 1728 return; 1729 default: 1730 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1731 break; 1732 } 1733 1734 if (oldreg != env->immu.mmuregs[reg]) { 1735 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1736 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); 1737 } 1738 #ifdef DEBUG_MMU 1739 dump_mmu(env); 1740 #endif 1741 return; 1742 } 1743 case ASI_ITLB_DATA_IN: /* I-MMU data in */ 1744 /* ignore real translation entries */ 1745 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1746 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, 1747 val, "immu", env, addr); 1748 } 1749 return; 1750 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1751 { 1752 /* TODO: auto demap */ 1753 1754 unsigned int i = (addr >> 3) & 0x3f; 1755 1756 /* ignore real translation entries */ 1757 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1758 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, 1759 sun4v_tte_to_sun4u(env, addr, val), env); 1760 } 1761 #ifdef DEBUG_MMU 1762 DPRINTF_MMU("immu data access replaced entry [%i]\n", i); 1763 dump_mmu(env); 1764 #endif 1765 return; 1766 } 1767 case ASI_IMMU_DEMAP: /* I-MMU demap */ 1768 demap_tlb(env->itlb, addr, "immu", env); 1769 return; 1770 case ASI_DMMU: /* D-MMU regs */ 1771 { 1772 int reg = (addr >> 3) & 0xf; 1773 uint64_t oldreg; 1774 1775 oldreg = env->dmmu.mmuregs[reg]; 1776 switch (reg) { 1777 case 0: /* RO */ 1778 case 4: 1779 return; 1780 case 3: /* SFSR */ 1781 if ((val & 1) == 0) { 1782 val = 0; /* Clear SFSR, Fault address */ 1783 env->dmmu.sfar = 0; 1784 } 1785 env->dmmu.sfsr = val; 1786 break; 1787 case 1: /* Primary context */ 1788 env->dmmu.mmu_primary_context = val; 1789 /* can be optimized to only flush MMU_USER_IDX 1790 and MMU_KERNEL_IDX entries */ 1791 tlb_flush(cs); 1792 break; 1793 case 2: /* Secondary context */ 1794 env->dmmu.mmu_secondary_context = val; 1795 /* can be optimized to only flush MMU_USER_SECONDARY_IDX 1796 and MMU_KERNEL_SECONDARY_IDX entries */ 1797 tlb_flush(cs); 1798 break; 1799 case 5: /* TSB access */ 1800 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" 1801 PRIx64 "\n", env->dmmu.tsb, val); 1802 env->dmmu.tsb = val; 1803 break; 1804 case 6: /* Tag access */ 1805 env->dmmu.tag_access = val; 1806 break; 1807 case 7: /* Virtual Watchpoint */ 1808 env->dmmu.virtual_watchpoint = val; 1809 break; 1810 case 8: /* Physical Watchpoint */ 1811 env->dmmu.physical_watchpoint = val; 1812 break; 1813 default: 1814 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1815 break; 1816 } 1817 1818 if (oldreg != env->dmmu.mmuregs[reg]) { 1819 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1820 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); 1821 } 1822 #ifdef DEBUG_MMU 1823 dump_mmu(env); 1824 #endif 1825 return; 1826 } 1827 case ASI_DTLB_DATA_IN: /* D-MMU data in */ 1828 /* ignore real translation entries */ 1829 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1830 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, 1831 val, "dmmu", env, addr); 1832 } 1833 return; 1834 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1835 { 1836 unsigned int i = (addr >> 3) & 0x3f; 1837 1838 /* ignore real translation entries */ 1839 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1840 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, 1841 sun4v_tte_to_sun4u(env, addr, val), env); 1842 } 1843 #ifdef DEBUG_MMU 1844 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); 1845 dump_mmu(env); 1846 #endif 1847 return; 1848 } 1849 case ASI_DMMU_DEMAP: /* D-MMU demap */ 1850 demap_tlb(env->dtlb, addr, "dmmu", env); 1851 return; 1852 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1853 env->ivec_status = val & 0x20; 1854 return; 1855 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1856 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1857 /* Hyperprivileged access only */ 1858 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1859 } 1860 /* fall through */ 1861 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1862 { 1863 unsigned int i = (addr >> 3) & 0x7; 1864 env->scratch[i] = val; 1865 return; 1866 } 1867 case ASI_MMU: /* UA2005 Context ID registers */ 1868 { 1869 switch ((addr >> 3) & 0x3) { 1870 case 1: 1871 env->dmmu.mmu_primary_context = val; 1872 env->immu.mmu_primary_context = val; 1873 tlb_flush_by_mmuidx(cs, 1874 (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX)); 1875 break; 1876 case 2: 1877 env->dmmu.mmu_secondary_context = val; 1878 env->immu.mmu_secondary_context = val; 1879 tlb_flush_by_mmuidx(cs, 1880 (1 << MMU_USER_SECONDARY_IDX) | 1881 (1 << MMU_KERNEL_SECONDARY_IDX)); 1882 break; 1883 default: 1884 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1885 } 1886 } 1887 return; 1888 case ASI_QUEUE: /* UA2005 CPU mondo queue */ 1889 case ASI_DCACHE_DATA: /* D-cache data */ 1890 case ASI_DCACHE_TAG: /* D-cache tag access */ 1891 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1892 case ASI_AFSR: /* E-cache asynchronous fault status */ 1893 case ASI_AFAR: /* E-cache asynchronous fault address */ 1894 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1895 case ASI_IC_INSTR: /* I-cache instruction access */ 1896 case ASI_IC_TAG: /* I-cache tag access */ 1897 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1898 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1899 case ASI_EC_W: /* E-cache tag */ 1900 case ASI_EC_R: /* E-cache tag */ 1901 return; 1902 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */ 1903 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */ 1904 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */ 1905 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */ 1906 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */ 1907 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */ 1908 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */ 1909 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1910 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1911 case ASI_PNF: /* Primary no-fault, RO */ 1912 case ASI_SNF: /* Secondary no-fault, RO */ 1913 case ASI_PNFL: /* Primary no-fault LE, RO */ 1914 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1915 default: 1916 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1917 return; 1918 illegal_insn: 1919 cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC()); 1920 } 1921 } 1922 #endif /* CONFIG_USER_ONLY */ 1923 #endif /* TARGET_SPARC64 */ 1924 1925 #if !defined(CONFIG_USER_ONLY) 1926 1927 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1928 vaddr addr, unsigned size, 1929 MMUAccessType access_type, 1930 int mmu_idx, MemTxAttrs attrs, 1931 MemTxResult response, uintptr_t retaddr) 1932 { 1933 bool is_write = access_type == MMU_DATA_STORE; 1934 bool is_exec = access_type == MMU_INST_FETCH; 1935 bool is_asi = false; 1936 1937 sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec, 1938 is_asi, size, retaddr); 1939 } 1940 #endif 1941