1 /* 2 * Helpers for loads and stores 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "tcg/tcg.h" 24 #include "exec/helper-proto.h" 25 #include "exec/exec-all.h" 26 #include "exec/cpu_ldst.h" 27 #include "asi.h" 28 29 //#define DEBUG_MMU 30 //#define DEBUG_MXCC 31 //#define DEBUG_UNASSIGNED 32 //#define DEBUG_ASI 33 //#define DEBUG_CACHE_CONTROL 34 35 #ifdef DEBUG_MMU 36 #define DPRINTF_MMU(fmt, ...) \ 37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) 38 #else 39 #define DPRINTF_MMU(fmt, ...) do {} while (0) 40 #endif 41 42 #ifdef DEBUG_MXCC 43 #define DPRINTF_MXCC(fmt, ...) \ 44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) 45 #else 46 #define DPRINTF_MXCC(fmt, ...) do {} while (0) 47 #endif 48 49 #ifdef DEBUG_ASI 50 #define DPRINTF_ASI(fmt, ...) \ 51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) 52 #endif 53 54 #ifdef DEBUG_CACHE_CONTROL 55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \ 56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) 57 #else 58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) 59 #endif 60 61 #ifdef TARGET_SPARC64 62 #ifndef TARGET_ABI32 63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM) 64 #else 65 #define AM_CHECK(env1) (1) 66 #endif 67 #endif 68 69 #define QT0 (env->qt0) 70 #define QT1 (env->qt1) 71 72 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 73 /* Calculates TSB pointer value for fault page size 74 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers 75 * UA2005 holds the page size configuration in mmu_ctx registers */ 76 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, 77 const SparcV9MMU *mmu, const int idx) 78 { 79 uint64_t tsb_register; 80 int page_size; 81 if (cpu_has_hypervisor(env)) { 82 int tsb_index = 0; 83 int ctx = mmu->tag_access & 0x1fffULL; 84 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; 85 tsb_index = idx; 86 tsb_index |= ctx ? 2 : 0; 87 page_size = idx ? ctx_register >> 8 : ctx_register; 88 page_size &= 7; 89 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; 90 } else { 91 page_size = idx; 92 tsb_register = mmu->tsb; 93 } 94 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; 95 int tsb_size = tsb_register & 0xf; 96 97 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size; 98 99 /* move va bits to correct position, 100 * the context bits will be masked out later */ 101 uint64_t va = mmu->tag_access >> (3 * page_size + 9); 102 103 /* calculate tsb_base mask and adjust va if split is in use */ 104 if (tsb_split) { 105 if (idx == 0) { 106 va &= ~(1ULL << (13 + tsb_size)); 107 } else { 108 va |= (1ULL << (13 + tsb_size)); 109 } 110 tsb_base_mask <<= 1; 111 } 112 113 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; 114 } 115 116 /* Calculates tag target register value by reordering bits 117 in tag access register */ 118 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) 119 { 120 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); 121 } 122 123 static void replace_tlb_entry(SparcTLBEntry *tlb, 124 uint64_t tlb_tag, uint64_t tlb_tte, 125 CPUSPARCState *env) 126 { 127 target_ulong mask, size, va, offset; 128 129 /* flush page range if translation is valid */ 130 if (TTE_IS_VALID(tlb->tte)) { 131 CPUState *cs = env_cpu(env); 132 133 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); 134 mask = 1ULL + ~size; 135 136 va = tlb->tag & mask; 137 138 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { 139 tlb_flush_page(cs, va + offset); 140 } 141 } 142 143 tlb->tag = tlb_tag; 144 tlb->tte = tlb_tte; 145 } 146 147 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, 148 const char *strmmu, CPUSPARCState *env1) 149 { 150 unsigned int i; 151 target_ulong mask; 152 uint64_t context; 153 154 int is_demap_context = (demap_addr >> 6) & 1; 155 156 /* demap context */ 157 switch ((demap_addr >> 4) & 3) { 158 case 0: /* primary */ 159 context = env1->dmmu.mmu_primary_context; 160 break; 161 case 1: /* secondary */ 162 context = env1->dmmu.mmu_secondary_context; 163 break; 164 case 2: /* nucleus */ 165 context = 0; 166 break; 167 case 3: /* reserved */ 168 default: 169 return; 170 } 171 172 for (i = 0; i < 64; i++) { 173 if (TTE_IS_VALID(tlb[i].tte)) { 174 175 if (is_demap_context) { 176 /* will remove non-global entries matching context value */ 177 if (TTE_IS_GLOBAL(tlb[i].tte) || 178 !tlb_compare_context(&tlb[i], context)) { 179 continue; 180 } 181 } else { 182 /* demap page 183 will remove any entry matching VA */ 184 mask = 0xffffffffffffe000ULL; 185 mask <<= 3 * ((tlb[i].tte >> 61) & 3); 186 187 if (!compare_masked(demap_addr, tlb[i].tag, mask)) { 188 continue; 189 } 190 191 /* entry should be global or matching context value */ 192 if (!TTE_IS_GLOBAL(tlb[i].tte) && 193 !tlb_compare_context(&tlb[i], context)) { 194 continue; 195 } 196 } 197 198 replace_tlb_entry(&tlb[i], 0, 0, env1); 199 #ifdef DEBUG_MMU 200 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); 201 dump_mmu(env1); 202 #endif 203 } 204 } 205 } 206 207 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState *env, uint64_t tag, 208 uint64_t sun4v_tte) 209 { 210 uint64_t sun4u_tte; 211 if (!(cpu_has_hypervisor(env) && (tag & TLB_UST1_IS_SUN4V_BIT))) { 212 /* is already in the sun4u format */ 213 return sun4v_tte; 214 } 215 sun4u_tte = TTE_PA(sun4v_tte) | (sun4v_tte & TTE_VALID_BIT); 216 sun4u_tte |= (sun4v_tte & 3ULL) << 61; /* TTE_PGSIZE */ 217 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_NFO_BIT_UA2005, TTE_NFO_BIT); 218 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_USED_BIT_UA2005, TTE_USED_BIT); 219 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_W_OK_BIT_UA2005, TTE_W_OK_BIT); 220 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_SIDEEFFECT_BIT_UA2005, 221 TTE_SIDEEFFECT_BIT); 222 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_PRIV_BIT_UA2005, TTE_PRIV_BIT); 223 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_LOCKED_BIT_UA2005, TTE_LOCKED_BIT); 224 return sun4u_tte; 225 } 226 227 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, 228 uint64_t tlb_tag, uint64_t tlb_tte, 229 const char *strmmu, CPUSPARCState *env1, 230 uint64_t addr) 231 { 232 unsigned int i, replace_used; 233 234 tlb_tte = sun4v_tte_to_sun4u(env1, addr, tlb_tte); 235 if (cpu_has_hypervisor(env1)) { 236 uint64_t new_vaddr = tlb_tag & ~0x1fffULL; 237 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte); 238 uint32_t new_ctx = tlb_tag & 0x1fffU; 239 for (i = 0; i < 64; i++) { 240 uint32_t ctx = tlb[i].tag & 0x1fffU; 241 /* check if new mapping overlaps an existing one */ 242 if (new_ctx == ctx) { 243 uint64_t vaddr = tlb[i].tag & ~0x1fffULL; 244 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte); 245 if (new_vaddr == vaddr 246 || (new_vaddr < vaddr + size 247 && vaddr < new_vaddr + new_size)) { 248 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, 249 new_vaddr); 250 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 251 return; 252 } 253 } 254 255 } 256 } 257 /* Try replacing invalid entry */ 258 for (i = 0; i < 64; i++) { 259 if (!TTE_IS_VALID(tlb[i].tte)) { 260 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 261 #ifdef DEBUG_MMU 262 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); 263 dump_mmu(env1); 264 #endif 265 return; 266 } 267 } 268 269 /* All entries are valid, try replacing unlocked entry */ 270 271 for (replace_used = 0; replace_used < 2; ++replace_used) { 272 273 /* Used entries are not replaced on first pass */ 274 275 for (i = 0; i < 64; i++) { 276 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) { 277 278 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 279 #ifdef DEBUG_MMU 280 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", 281 strmmu, (replace_used ? "used" : "unused"), i); 282 dump_mmu(env1); 283 #endif 284 return; 285 } 286 } 287 288 /* Now reset used bit and search for unused entries again */ 289 290 for (i = 0; i < 64; i++) { 291 TTE_SET_UNUSED(tlb[i].tte); 292 } 293 } 294 295 #ifdef DEBUG_MMU 296 DPRINTF_MMU("%s lru replacement: no free entries available, " 297 "replacing the last one\n", strmmu); 298 #endif 299 /* corner case: the last entry is replaced anyway */ 300 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1); 301 } 302 303 #endif 304 305 #ifdef TARGET_SPARC64 306 /* returns true if access using this ASI is to have address translated by MMU 307 otherwise access is to raw physical address */ 308 /* TODO: check sparc32 bits */ 309 static inline int is_translating_asi(int asi) 310 { 311 /* Ultrasparc IIi translating asi 312 - note this list is defined by cpu implementation 313 */ 314 switch (asi) { 315 case 0x04 ... 0x11: 316 case 0x16 ... 0x19: 317 case 0x1E ... 0x1F: 318 case 0x24 ... 0x2C: 319 case 0x70 ... 0x73: 320 case 0x78 ... 0x79: 321 case 0x80 ... 0xFF: 322 return 1; 323 324 default: 325 return 0; 326 } 327 } 328 329 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr) 330 { 331 if (AM_CHECK(env1)) { 332 addr &= 0xffffffffULL; 333 } 334 return addr; 335 } 336 337 static inline target_ulong asi_address_mask(CPUSPARCState *env, 338 int asi, target_ulong addr) 339 { 340 if (is_translating_asi(asi)) { 341 addr = address_mask(env, addr); 342 } 343 return addr; 344 } 345 346 #ifndef CONFIG_USER_ONLY 347 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra) 348 { 349 /* ASIs >= 0x80 are user mode. 350 * ASIs >= 0x30 are hyper mode (or super if hyper is not available). 351 * ASIs <= 0x2f are super mode. 352 */ 353 if (asi < 0x80 354 && !cpu_hypervisor_mode(env) 355 && (!cpu_supervisor_mode(env) 356 || (asi >= 0x30 && cpu_has_hypervisor(env)))) { 357 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra); 358 } 359 } 360 #endif /* !CONFIG_USER_ONLY */ 361 #endif 362 363 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) 364 static void do_check_align(CPUSPARCState *env, target_ulong addr, 365 uint32_t align, uintptr_t ra) 366 { 367 if (addr & align) { 368 cpu_raise_exception_ra(env, TT_UNALIGNED, ra); 369 } 370 } 371 #endif 372 373 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ 374 defined(DEBUG_MXCC) 375 static void dump_mxcc(CPUSPARCState *env) 376 { 377 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 378 "\n", 379 env->mxccdata[0], env->mxccdata[1], 380 env->mxccdata[2], env->mxccdata[3]); 381 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 382 "\n" 383 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 384 "\n", 385 env->mxccregs[0], env->mxccregs[1], 386 env->mxccregs[2], env->mxccregs[3], 387 env->mxccregs[4], env->mxccregs[5], 388 env->mxccregs[6], env->mxccregs[7]); 389 } 390 #endif 391 392 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \ 393 && defined(DEBUG_ASI) 394 static void dump_asi(const char *txt, target_ulong addr, int asi, int size, 395 uint64_t r1) 396 { 397 switch (size) { 398 case 1: 399 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, 400 addr, asi, r1 & 0xff); 401 break; 402 case 2: 403 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, 404 addr, asi, r1 & 0xffff); 405 break; 406 case 4: 407 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, 408 addr, asi, r1 & 0xffffffff); 409 break; 410 case 8: 411 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, 412 addr, asi, r1); 413 break; 414 } 415 } 416 #endif 417 418 #ifndef CONFIG_USER_ONLY 419 #ifndef TARGET_SPARC64 420 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 421 bool is_write, bool is_exec, int is_asi, 422 unsigned size, uintptr_t retaddr) 423 { 424 SPARCCPU *cpu = SPARC_CPU(cs); 425 CPUSPARCState *env = &cpu->env; 426 int fault_type; 427 428 #ifdef DEBUG_UNASSIGNED 429 if (is_asi) { 430 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 431 " asi 0x%02x from " TARGET_FMT_lx "\n", 432 is_exec ? "exec" : is_write ? "write" : "read", size, 433 size == 1 ? "" : "s", addr, is_asi, env->pc); 434 } else { 435 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx 436 " from " TARGET_FMT_lx "\n", 437 is_exec ? "exec" : is_write ? "write" : "read", size, 438 size == 1 ? "" : "s", addr, env->pc); 439 } 440 #endif 441 /* Don't overwrite translation and access faults */ 442 fault_type = (env->mmuregs[3] & 0x1c) >> 2; 443 if ((fault_type > 4) || (fault_type == 0)) { 444 env->mmuregs[3] = 0; /* Fault status register */ 445 if (is_asi) { 446 env->mmuregs[3] |= 1 << 16; 447 } 448 if (env->psrs) { 449 env->mmuregs[3] |= 1 << 5; 450 } 451 if (is_exec) { 452 env->mmuregs[3] |= 1 << 6; 453 } 454 if (is_write) { 455 env->mmuregs[3] |= 1 << 7; 456 } 457 env->mmuregs[3] |= (5 << 2) | 2; 458 /* SuperSPARC will never place instruction fault addresses in the FAR */ 459 if (!is_exec) { 460 env->mmuregs[4] = addr; /* Fault address register */ 461 } 462 } 463 /* overflow (same type fault was not read before another fault) */ 464 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { 465 env->mmuregs[3] |= 1; 466 } 467 468 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { 469 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS; 470 cpu_raise_exception_ra(env, tt, retaddr); 471 } 472 473 /* 474 * flush neverland mappings created during no-fault mode, 475 * so the sequential MMU faults report proper fault types 476 */ 477 if (env->mmuregs[0] & MMU_NF) { 478 tlb_flush(cs); 479 } 480 } 481 #else 482 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, 483 bool is_write, bool is_exec, int is_asi, 484 unsigned size, uintptr_t retaddr) 485 { 486 SPARCCPU *cpu = SPARC_CPU(cs); 487 CPUSPARCState *env = &cpu->env; 488 489 #ifdef DEBUG_UNASSIGNED 490 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx 491 "\n", addr, env->pc); 492 #endif 493 494 if (is_exec) { /* XXX has_hypervisor */ 495 if (env->lsu & (IMMU_E)) { 496 cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr); 497 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 498 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr); 499 } 500 } else { 501 if (env->lsu & (DMMU_E)) { 502 cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr); 503 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { 504 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr); 505 } 506 } 507 } 508 #endif 509 #endif 510 511 #ifndef TARGET_SPARC64 512 #ifndef CONFIG_USER_ONLY 513 514 515 /* Leon3 cache control */ 516 517 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr, 518 uint64_t val, int size) 519 { 520 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", 521 addr, val, size); 522 523 if (size != 4) { 524 DPRINTF_CACHE_CONTROL("32bits only\n"); 525 return; 526 } 527 528 switch (addr) { 529 case 0x00: /* Cache control */ 530 531 /* These values must always be read as zeros */ 532 val &= ~CACHE_CTRL_FD; 533 val &= ~CACHE_CTRL_FI; 534 val &= ~CACHE_CTRL_IB; 535 val &= ~CACHE_CTRL_IP; 536 val &= ~CACHE_CTRL_DP; 537 538 env->cache_control = val; 539 break; 540 case 0x04: /* Instruction cache configuration */ 541 case 0x08: /* Data cache configuration */ 542 /* Read Only */ 543 break; 544 default: 545 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr); 546 break; 547 }; 548 } 549 550 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr, 551 int size) 552 { 553 uint64_t ret = 0; 554 555 if (size != 4) { 556 DPRINTF_CACHE_CONTROL("32bits only\n"); 557 return 0; 558 } 559 560 switch (addr) { 561 case 0x00: /* Cache control */ 562 ret = env->cache_control; 563 break; 564 565 /* Configuration registers are read and only always keep those 566 predefined values */ 567 568 case 0x04: /* Instruction cache configuration */ 569 ret = 0x10220000; 570 break; 571 case 0x08: /* Data cache configuration */ 572 ret = 0x18220000; 573 break; 574 default: 575 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr); 576 break; 577 }; 578 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", 579 addr, ret, size); 580 return ret; 581 } 582 583 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 584 int asi, uint32_t memop) 585 { 586 int size = 1 << (memop & MO_SIZE); 587 int sign = memop & MO_SIGN; 588 CPUState *cs = env_cpu(env); 589 uint64_t ret = 0; 590 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) 591 uint32_t last_addr = addr; 592 #endif 593 MemOpIdx oi; 594 595 do_check_align(env, addr, size - 1, GETPC()); 596 switch (asi) { 597 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 598 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 599 switch (addr) { 600 case 0x00: /* Leon3 Cache Control */ 601 case 0x08: /* Leon3 Instruction Cache config */ 602 case 0x0C: /* Leon3 Date Cache config */ 603 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 604 ret = leon3_cache_control_ld(env, addr, size); 605 } 606 break; 607 case 0x01c00a00: /* MXCC control register */ 608 if (size == 8) { 609 ret = env->mxccregs[3]; 610 } else { 611 qemu_log_mask(LOG_UNIMP, 612 "%08x: unimplemented access size: %d\n", addr, 613 size); 614 } 615 break; 616 case 0x01c00a04: /* MXCC control register */ 617 if (size == 4) { 618 ret = env->mxccregs[3]; 619 } else { 620 qemu_log_mask(LOG_UNIMP, 621 "%08x: unimplemented access size: %d\n", addr, 622 size); 623 } 624 break; 625 case 0x01c00c00: /* Module reset register */ 626 if (size == 8) { 627 ret = env->mxccregs[5]; 628 /* should we do something here? */ 629 } else { 630 qemu_log_mask(LOG_UNIMP, 631 "%08x: unimplemented access size: %d\n", addr, 632 size); 633 } 634 break; 635 case 0x01c00f00: /* MBus port address register */ 636 if (size == 8) { 637 ret = env->mxccregs[7]; 638 } else { 639 qemu_log_mask(LOG_UNIMP, 640 "%08x: unimplemented access size: %d\n", addr, 641 size); 642 } 643 break; 644 default: 645 qemu_log_mask(LOG_UNIMP, 646 "%08x: unimplemented address, size: %d\n", addr, 647 size); 648 break; 649 } 650 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " 651 "addr = %08x -> ret = %" PRIx64 "," 652 "addr = %08x\n", asi, size, sign, last_addr, ret, addr); 653 #ifdef DEBUG_MXCC 654 dump_mxcc(env); 655 #endif 656 break; 657 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */ 658 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */ 659 { 660 int mmulev; 661 662 mmulev = (addr >> 8) & 15; 663 if (mmulev > 4) { 664 ret = 0; 665 } else { 666 ret = mmu_probe(env, addr, mmulev); 667 } 668 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", 669 addr, mmulev, ret); 670 } 671 break; 672 case ASI_M_MMUREGS: /* SuperSparc MMU regs */ 673 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */ 674 { 675 int reg = (addr >> 8) & 0x1f; 676 677 ret = env->mmuregs[reg]; 678 if (reg == 3) { /* Fault status cleared on read */ 679 env->mmuregs[3] = 0; 680 } else if (reg == 0x13) { /* Fault status read */ 681 ret = env->mmuregs[3]; 682 } else if (reg == 0x14) { /* Fault address read */ 683 ret = env->mmuregs[4]; 684 } 685 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); 686 } 687 break; 688 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 689 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 690 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 691 break; 692 case ASI_KERNELTXT: /* Supervisor code access */ 693 oi = make_memop_idx(memop, cpu_mmu_index(env, true)); 694 switch (size) { 695 case 1: 696 ret = cpu_ldb_code_mmu(env, addr, oi, GETPC()); 697 break; 698 case 2: 699 ret = cpu_ldw_code_mmu(env, addr, oi, GETPC()); 700 break; 701 default: 702 case 4: 703 ret = cpu_ldl_code_mmu(env, addr, oi, GETPC()); 704 break; 705 case 8: 706 ret = cpu_ldq_code_mmu(env, addr, oi, GETPC()); 707 break; 708 } 709 break; 710 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */ 711 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */ 712 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */ 713 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ 714 break; 715 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 716 { 717 MemTxResult result; 718 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 719 720 switch (size) { 721 case 1: 722 ret = address_space_ldub(cs->as, access_addr, 723 MEMTXATTRS_UNSPECIFIED, &result); 724 break; 725 case 2: 726 ret = address_space_lduw(cs->as, access_addr, 727 MEMTXATTRS_UNSPECIFIED, &result); 728 break; 729 default: 730 case 4: 731 ret = address_space_ldl(cs->as, access_addr, 732 MEMTXATTRS_UNSPECIFIED, &result); 733 break; 734 case 8: 735 ret = address_space_ldq(cs->as, access_addr, 736 MEMTXATTRS_UNSPECIFIED, &result); 737 break; 738 } 739 740 if (result != MEMTX_OK) { 741 sparc_raise_mmu_fault(cs, access_addr, false, false, false, 742 size, GETPC()); 743 } 744 break; 745 } 746 case 0x30: /* Turbosparc secondary cache diagnostic */ 747 case 0x31: /* Turbosparc RAM snoop */ 748 case 0x32: /* Turbosparc page table descriptor diagnostic */ 749 case 0x39: /* data cache diagnostic register */ 750 ret = 0; 751 break; 752 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ 753 { 754 int reg = (addr >> 8) & 3; 755 756 switch (reg) { 757 case 0: /* Breakpoint Value (Addr) */ 758 ret = env->mmubpregs[reg]; 759 break; 760 case 1: /* Breakpoint Mask */ 761 ret = env->mmubpregs[reg]; 762 break; 763 case 2: /* Breakpoint Control */ 764 ret = env->mmubpregs[reg]; 765 break; 766 case 3: /* Breakpoint Status */ 767 ret = env->mmubpregs[reg]; 768 env->mmubpregs[reg] = 0ULL; 769 break; 770 } 771 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, 772 ret); 773 } 774 break; 775 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 776 ret = env->mmubpctrv; 777 break; 778 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 779 ret = env->mmubpctrc; 780 break; 781 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 782 ret = env->mmubpctrs; 783 break; 784 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 785 ret = env->mmubpaction; 786 break; 787 case ASI_USERTXT: /* User code access, XXX */ 788 default: 789 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); 790 ret = 0; 791 break; 792 793 case ASI_USERDATA: /* User data access */ 794 case ASI_KERNELDATA: /* Supervisor data access */ 795 case ASI_P: /* Implicit primary context data access (v9 only?) */ 796 case ASI_M_BYPASS: /* MMU passthrough */ 797 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 798 /* These are always handled inline. */ 799 g_assert_not_reached(); 800 } 801 if (sign) { 802 switch (size) { 803 case 1: 804 ret = (int8_t) ret; 805 break; 806 case 2: 807 ret = (int16_t) ret; 808 break; 809 case 4: 810 ret = (int32_t) ret; 811 break; 812 default: 813 break; 814 } 815 } 816 #ifdef DEBUG_ASI 817 dump_asi("read ", last_addr, asi, size, ret); 818 #endif 819 return ret; 820 } 821 822 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, 823 int asi, uint32_t memop) 824 { 825 int size = 1 << (memop & MO_SIZE); 826 CPUState *cs = env_cpu(env); 827 828 do_check_align(env, addr, size - 1, GETPC()); 829 switch (asi) { 830 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */ 831 /* case ASI_LEON_CACHEREGS: Leon3 cache control */ 832 switch (addr) { 833 case 0x00: /* Leon3 Cache Control */ 834 case 0x08: /* Leon3 Instruction Cache config */ 835 case 0x0C: /* Leon3 Date Cache config */ 836 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { 837 leon3_cache_control_st(env, addr, val, size); 838 } 839 break; 840 841 case 0x01c00000: /* MXCC stream data register 0 */ 842 if (size == 8) { 843 env->mxccdata[0] = val; 844 } else { 845 qemu_log_mask(LOG_UNIMP, 846 "%08x: unimplemented access size: %d\n", addr, 847 size); 848 } 849 break; 850 case 0x01c00008: /* MXCC stream data register 1 */ 851 if (size == 8) { 852 env->mxccdata[1] = val; 853 } else { 854 qemu_log_mask(LOG_UNIMP, 855 "%08x: unimplemented access size: %d\n", addr, 856 size); 857 } 858 break; 859 case 0x01c00010: /* MXCC stream data register 2 */ 860 if (size == 8) { 861 env->mxccdata[2] = val; 862 } else { 863 qemu_log_mask(LOG_UNIMP, 864 "%08x: unimplemented access size: %d\n", addr, 865 size); 866 } 867 break; 868 case 0x01c00018: /* MXCC stream data register 3 */ 869 if (size == 8) { 870 env->mxccdata[3] = val; 871 } else { 872 qemu_log_mask(LOG_UNIMP, 873 "%08x: unimplemented access size: %d\n", addr, 874 size); 875 } 876 break; 877 case 0x01c00100: /* MXCC stream source */ 878 { 879 int i; 880 881 if (size == 8) { 882 env->mxccregs[0] = val; 883 } else { 884 qemu_log_mask(LOG_UNIMP, 885 "%08x: unimplemented access size: %d\n", addr, 886 size); 887 } 888 889 for (i = 0; i < 4; i++) { 890 MemTxResult result; 891 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; 892 893 env->mxccdata[i] = address_space_ldq(cs->as, 894 access_addr, 895 MEMTXATTRS_UNSPECIFIED, 896 &result); 897 if (result != MEMTX_OK) { 898 /* TODO: investigate whether this is the right behaviour */ 899 sparc_raise_mmu_fault(cs, access_addr, false, false, 900 false, size, GETPC()); 901 } 902 } 903 break; 904 } 905 case 0x01c00200: /* MXCC stream destination */ 906 { 907 int i; 908 909 if (size == 8) { 910 env->mxccregs[1] = val; 911 } else { 912 qemu_log_mask(LOG_UNIMP, 913 "%08x: unimplemented access size: %d\n", addr, 914 size); 915 } 916 917 for (i = 0; i < 4; i++) { 918 MemTxResult result; 919 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; 920 921 address_space_stq(cs->as, access_addr, env->mxccdata[i], 922 MEMTXATTRS_UNSPECIFIED, &result); 923 924 if (result != MEMTX_OK) { 925 /* TODO: investigate whether this is the right behaviour */ 926 sparc_raise_mmu_fault(cs, access_addr, true, false, 927 false, size, GETPC()); 928 } 929 } 930 break; 931 } 932 case 0x01c00a00: /* MXCC control register */ 933 if (size == 8) { 934 env->mxccregs[3] = val; 935 } else { 936 qemu_log_mask(LOG_UNIMP, 937 "%08x: unimplemented access size: %d\n", addr, 938 size); 939 } 940 break; 941 case 0x01c00a04: /* MXCC control register */ 942 if (size == 4) { 943 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) 944 | val; 945 } else { 946 qemu_log_mask(LOG_UNIMP, 947 "%08x: unimplemented access size: %d\n", addr, 948 size); 949 } 950 break; 951 case 0x01c00e00: /* MXCC error register */ 952 /* writing a 1 bit clears the error */ 953 if (size == 8) { 954 env->mxccregs[6] &= ~val; 955 } else { 956 qemu_log_mask(LOG_UNIMP, 957 "%08x: unimplemented access size: %d\n", addr, 958 size); 959 } 960 break; 961 case 0x01c00f00: /* MBus port address register */ 962 if (size == 8) { 963 env->mxccregs[7] = val; 964 } else { 965 qemu_log_mask(LOG_UNIMP, 966 "%08x: unimplemented access size: %d\n", addr, 967 size); 968 } 969 break; 970 default: 971 qemu_log_mask(LOG_UNIMP, 972 "%08x: unimplemented address, size: %d\n", addr, 973 size); 974 break; 975 } 976 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", 977 asi, size, addr, val); 978 #ifdef DEBUG_MXCC 979 dump_mxcc(env); 980 #endif 981 break; 982 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */ 983 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */ 984 { 985 int mmulev; 986 987 mmulev = (addr >> 8) & 15; 988 DPRINTF_MMU("mmu flush level %d\n", mmulev); 989 switch (mmulev) { 990 case 0: /* flush page */ 991 tlb_flush_page(cs, addr & 0xfffff000); 992 break; 993 case 1: /* flush segment (256k) */ 994 case 2: /* flush region (16M) */ 995 case 3: /* flush context (4G) */ 996 case 4: /* flush entire */ 997 tlb_flush(cs); 998 break; 999 default: 1000 break; 1001 } 1002 #ifdef DEBUG_MMU 1003 dump_mmu(env); 1004 #endif 1005 } 1006 break; 1007 case ASI_M_MMUREGS: /* write MMU regs */ 1008 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */ 1009 { 1010 int reg = (addr >> 8) & 0x1f; 1011 uint32_t oldreg; 1012 1013 oldreg = env->mmuregs[reg]; 1014 switch (reg) { 1015 case 0: /* Control Register */ 1016 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | 1017 (val & 0x00ffffff); 1018 /* Mappings generated during no-fault mode 1019 are invalid in normal mode. */ 1020 if ((oldreg ^ env->mmuregs[reg]) 1021 & (MMU_NF | env->def.mmu_bm)) { 1022 tlb_flush(cs); 1023 } 1024 break; 1025 case 1: /* Context Table Pointer Register */ 1026 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; 1027 break; 1028 case 2: /* Context Register */ 1029 env->mmuregs[reg] = val & env->def.mmu_cxr_mask; 1030 if (oldreg != env->mmuregs[reg]) { 1031 /* we flush when the MMU context changes because 1032 QEMU has no MMU context support */ 1033 tlb_flush(cs); 1034 } 1035 break; 1036 case 3: /* Synchronous Fault Status Register with Clear */ 1037 case 4: /* Synchronous Fault Address Register */ 1038 break; 1039 case 0x10: /* TLB Replacement Control Register */ 1040 env->mmuregs[reg] = val & env->def.mmu_trcr_mask; 1041 break; 1042 case 0x13: /* Synchronous Fault Status Register with Read 1043 and Clear */ 1044 env->mmuregs[3] = val & env->def.mmu_sfsr_mask; 1045 break; 1046 case 0x14: /* Synchronous Fault Address Register */ 1047 env->mmuregs[4] = val; 1048 break; 1049 default: 1050 env->mmuregs[reg] = val; 1051 break; 1052 } 1053 if (oldreg != env->mmuregs[reg]) { 1054 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", 1055 reg, oldreg, env->mmuregs[reg]); 1056 } 1057 #ifdef DEBUG_MMU 1058 dump_mmu(env); 1059 #endif 1060 } 1061 break; 1062 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */ 1063 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */ 1064 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ 1065 break; 1066 case ASI_M_TXTC_TAG: /* I-cache tag */ 1067 case ASI_M_TXTC_DATA: /* I-cache data */ 1068 case ASI_M_DATAC_TAG: /* D-cache tag */ 1069 case ASI_M_DATAC_DATA: /* D-cache data */ 1070 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */ 1071 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */ 1072 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */ 1073 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */ 1074 case ASI_M_FLUSH_USER: /* I/D-cache flush user */ 1075 break; 1076 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ 1077 { 1078 MemTxResult result; 1079 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); 1080 1081 switch (size) { 1082 case 1: 1083 address_space_stb(cs->as, access_addr, val, 1084 MEMTXATTRS_UNSPECIFIED, &result); 1085 break; 1086 case 2: 1087 address_space_stw(cs->as, access_addr, val, 1088 MEMTXATTRS_UNSPECIFIED, &result); 1089 break; 1090 case 4: 1091 default: 1092 address_space_stl(cs->as, access_addr, val, 1093 MEMTXATTRS_UNSPECIFIED, &result); 1094 break; 1095 case 8: 1096 address_space_stq(cs->as, access_addr, val, 1097 MEMTXATTRS_UNSPECIFIED, &result); 1098 break; 1099 } 1100 if (result != MEMTX_OK) { 1101 sparc_raise_mmu_fault(cs, access_addr, true, false, false, 1102 size, GETPC()); 1103 } 1104 } 1105 break; 1106 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ 1107 case 0x31: /* store buffer data, Ross RT620 I-cache flush or 1108 Turbosparc snoop RAM */ 1109 case 0x32: /* store buffer control or Turbosparc page table 1110 descriptor diagnostic */ 1111 case 0x36: /* I-cache flash clear */ 1112 case 0x37: /* D-cache flash clear */ 1113 break; 1114 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ 1115 { 1116 int reg = (addr >> 8) & 3; 1117 1118 switch (reg) { 1119 case 0: /* Breakpoint Value (Addr) */ 1120 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1121 break; 1122 case 1: /* Breakpoint Mask */ 1123 env->mmubpregs[reg] = (val & 0xfffffffffULL); 1124 break; 1125 case 2: /* Breakpoint Control */ 1126 env->mmubpregs[reg] = (val & 0x7fULL); 1127 break; 1128 case 3: /* Breakpoint Status */ 1129 env->mmubpregs[reg] = (val & 0xfULL); 1130 break; 1131 } 1132 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg, 1133 env->mmuregs[reg]); 1134 } 1135 break; 1136 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ 1137 env->mmubpctrv = val & 0xffffffff; 1138 break; 1139 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ 1140 env->mmubpctrc = val & 0x3; 1141 break; 1142 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ 1143 env->mmubpctrs = val & 0x3; 1144 break; 1145 case 0x4c: /* SuperSPARC MMU Breakpoint Action */ 1146 env->mmubpaction = val & 0x1fff; 1147 break; 1148 case ASI_USERTXT: /* User code access, XXX */ 1149 case ASI_KERNELTXT: /* Supervisor code access, XXX */ 1150 default: 1151 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); 1152 break; 1153 1154 case ASI_USERDATA: /* User data access */ 1155 case ASI_KERNELDATA: /* Supervisor data access */ 1156 case ASI_P: 1157 case ASI_M_BYPASS: /* MMU passthrough */ 1158 case ASI_LEON_BYPASS: /* LEON MMU passthrough */ 1159 case ASI_M_BCOPY: /* Block copy, sta access */ 1160 case ASI_M_BFILL: /* Block fill, stda access */ 1161 /* These are always handled inline. */ 1162 g_assert_not_reached(); 1163 } 1164 #ifdef DEBUG_ASI 1165 dump_asi("write", addr, asi, size, val); 1166 #endif 1167 } 1168 1169 #endif /* CONFIG_USER_ONLY */ 1170 #else /* TARGET_SPARC64 */ 1171 1172 #ifdef CONFIG_USER_ONLY 1173 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1174 int asi, uint32_t memop) 1175 { 1176 int size = 1 << (memop & MO_SIZE); 1177 int sign = memop & MO_SIGN; 1178 uint64_t ret = 0; 1179 1180 if (asi < 0x80) { 1181 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1182 } 1183 do_check_align(env, addr, size - 1, GETPC()); 1184 addr = asi_address_mask(env, asi, addr); 1185 1186 switch (asi) { 1187 case ASI_PNF: /* Primary no-fault */ 1188 case ASI_PNFL: /* Primary no-fault LE */ 1189 case ASI_SNF: /* Secondary no-fault */ 1190 case ASI_SNFL: /* Secondary no-fault LE */ 1191 if (!page_check_range(addr, size, PAGE_READ)) { 1192 ret = 0; 1193 break; 1194 } 1195 switch (size) { 1196 case 1: 1197 ret = cpu_ldub_data(env, addr); 1198 break; 1199 case 2: 1200 ret = cpu_lduw_data(env, addr); 1201 break; 1202 case 4: 1203 ret = cpu_ldl_data(env, addr); 1204 break; 1205 case 8: 1206 ret = cpu_ldq_data(env, addr); 1207 break; 1208 default: 1209 g_assert_not_reached(); 1210 } 1211 break; 1212 break; 1213 1214 case ASI_P: /* Primary */ 1215 case ASI_PL: /* Primary LE */ 1216 case ASI_S: /* Secondary */ 1217 case ASI_SL: /* Secondary LE */ 1218 /* These are always handled inline. */ 1219 g_assert_not_reached(); 1220 1221 default: 1222 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1223 } 1224 1225 /* Convert from little endian */ 1226 switch (asi) { 1227 case ASI_PNFL: /* Primary no-fault LE */ 1228 case ASI_SNFL: /* Secondary no-fault LE */ 1229 switch (size) { 1230 case 2: 1231 ret = bswap16(ret); 1232 break; 1233 case 4: 1234 ret = bswap32(ret); 1235 break; 1236 case 8: 1237 ret = bswap64(ret); 1238 break; 1239 } 1240 } 1241 1242 /* Convert to signed number */ 1243 if (sign) { 1244 switch (size) { 1245 case 1: 1246 ret = (int8_t) ret; 1247 break; 1248 case 2: 1249 ret = (int16_t) ret; 1250 break; 1251 case 4: 1252 ret = (int32_t) ret; 1253 break; 1254 } 1255 } 1256 #ifdef DEBUG_ASI 1257 dump_asi("read", addr, asi, size, ret); 1258 #endif 1259 return ret; 1260 } 1261 1262 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1263 int asi, uint32_t memop) 1264 { 1265 int size = 1 << (memop & MO_SIZE); 1266 #ifdef DEBUG_ASI 1267 dump_asi("write", addr, asi, size, val); 1268 #endif 1269 if (asi < 0x80) { 1270 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC()); 1271 } 1272 do_check_align(env, addr, size - 1, GETPC()); 1273 1274 switch (asi) { 1275 case ASI_P: /* Primary */ 1276 case ASI_PL: /* Primary LE */ 1277 case ASI_S: /* Secondary */ 1278 case ASI_SL: /* Secondary LE */ 1279 /* These are always handled inline. */ 1280 g_assert_not_reached(); 1281 1282 case ASI_PNF: /* Primary no-fault, RO */ 1283 case ASI_SNF: /* Secondary no-fault, RO */ 1284 case ASI_PNFL: /* Primary no-fault LE, RO */ 1285 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1286 default: 1287 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); 1288 } 1289 } 1290 1291 #else /* CONFIG_USER_ONLY */ 1292 1293 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, 1294 int asi, uint32_t memop) 1295 { 1296 int size = 1 << (memop & MO_SIZE); 1297 int sign = memop & MO_SIGN; 1298 CPUState *cs = env_cpu(env); 1299 uint64_t ret = 0; 1300 #if defined(DEBUG_ASI) 1301 target_ulong last_addr = addr; 1302 #endif 1303 1304 asi &= 0xff; 1305 1306 do_check_asi(env, asi, GETPC()); 1307 do_check_align(env, addr, size - 1, GETPC()); 1308 addr = asi_address_mask(env, asi, addr); 1309 1310 switch (asi) { 1311 case ASI_PNF: 1312 case ASI_PNFL: 1313 case ASI_SNF: 1314 case ASI_SNFL: 1315 { 1316 MemOpIdx oi; 1317 int idx = (env->pstate & PS_PRIV 1318 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX) 1319 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX)); 1320 1321 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) { 1322 #ifdef DEBUG_ASI 1323 dump_asi("read ", last_addr, asi, size, ret); 1324 #endif 1325 /* exception_index is set in get_physical_address_data. */ 1326 cpu_raise_exception_ra(env, cs->exception_index, GETPC()); 1327 } 1328 oi = make_memop_idx(memop, idx); 1329 switch (size) { 1330 case 1: 1331 ret = cpu_ldb_mmu(env, addr, oi, GETPC()); 1332 break; 1333 case 2: 1334 ret = cpu_ldw_mmu(env, addr, oi, GETPC()); 1335 break; 1336 case 4: 1337 ret = cpu_ldl_mmu(env, addr, oi, GETPC()); 1338 break; 1339 case 8: 1340 ret = cpu_ldq_mmu(env, addr, oi, GETPC()); 1341 break; 1342 default: 1343 g_assert_not_reached(); 1344 } 1345 } 1346 break; 1347 1348 case ASI_AIUP: /* As if user primary */ 1349 case ASI_AIUS: /* As if user secondary */ 1350 case ASI_AIUPL: /* As if user primary LE */ 1351 case ASI_AIUSL: /* As if user secondary LE */ 1352 case ASI_P: /* Primary */ 1353 case ASI_S: /* Secondary */ 1354 case ASI_PL: /* Primary LE */ 1355 case ASI_SL: /* Secondary LE */ 1356 case ASI_REAL: /* Bypass */ 1357 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1358 case ASI_REAL_L: /* Bypass LE */ 1359 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1360 case ASI_N: /* Nucleus */ 1361 case ASI_NL: /* Nucleus Little Endian (LE) */ 1362 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1363 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1364 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1365 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1366 case ASI_TWINX_REAL: /* Real address, twinx */ 1367 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1368 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1369 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1370 case ASI_TWINX_N: /* Nucleus, twinx */ 1371 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1372 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1373 case ASI_TWINX_P: /* Primary, twinx */ 1374 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1375 case ASI_TWINX_S: /* Secondary, twinx */ 1376 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1377 /* These are always handled inline. */ 1378 g_assert_not_reached(); 1379 1380 case ASI_UPA_CONFIG: /* UPA config */ 1381 /* XXX */ 1382 break; 1383 case ASI_LSU_CONTROL: /* LSU */ 1384 ret = env->lsu; 1385 break; 1386 case ASI_IMMU: /* I-MMU regs */ 1387 { 1388 int reg = (addr >> 3) & 0xf; 1389 switch (reg) { 1390 case 0: 1391 /* 0x00 I-TSB Tag Target register */ 1392 ret = ultrasparc_tag_target(env->immu.tag_access); 1393 break; 1394 case 3: /* SFSR */ 1395 ret = env->immu.sfsr; 1396 break; 1397 case 5: /* TSB access */ 1398 ret = env->immu.tsb; 1399 break; 1400 case 6: 1401 /* 0x30 I-TSB Tag Access register */ 1402 ret = env->immu.tag_access; 1403 break; 1404 default: 1405 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1406 ret = 0; 1407 } 1408 break; 1409 } 1410 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */ 1411 { 1412 /* env->immuregs[5] holds I-MMU TSB register value 1413 env->immuregs[6] holds I-MMU Tag Access register value */ 1414 ret = ultrasparc_tsb_pointer(env, &env->immu, 0); 1415 break; 1416 } 1417 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ 1418 { 1419 /* env->immuregs[5] holds I-MMU TSB register value 1420 env->immuregs[6] holds I-MMU Tag Access register value */ 1421 ret = ultrasparc_tsb_pointer(env, &env->immu, 1); 1422 break; 1423 } 1424 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1425 { 1426 int reg = (addr >> 3) & 0x3f; 1427 1428 ret = env->itlb[reg].tte; 1429 break; 1430 } 1431 case ASI_ITLB_TAG_READ: /* I-MMU tag read */ 1432 { 1433 int reg = (addr >> 3) & 0x3f; 1434 1435 ret = env->itlb[reg].tag; 1436 break; 1437 } 1438 case ASI_DMMU: /* D-MMU regs */ 1439 { 1440 int reg = (addr >> 3) & 0xf; 1441 switch (reg) { 1442 case 0: 1443 /* 0x00 D-TSB Tag Target register */ 1444 ret = ultrasparc_tag_target(env->dmmu.tag_access); 1445 break; 1446 case 1: /* 0x08 Primary Context */ 1447 ret = env->dmmu.mmu_primary_context; 1448 break; 1449 case 2: /* 0x10 Secondary Context */ 1450 ret = env->dmmu.mmu_secondary_context; 1451 break; 1452 case 3: /* SFSR */ 1453 ret = env->dmmu.sfsr; 1454 break; 1455 case 4: /* 0x20 SFAR */ 1456 ret = env->dmmu.sfar; 1457 break; 1458 case 5: /* 0x28 TSB access */ 1459 ret = env->dmmu.tsb; 1460 break; 1461 case 6: /* 0x30 D-TSB Tag Access register */ 1462 ret = env->dmmu.tag_access; 1463 break; 1464 case 7: 1465 ret = env->dmmu.virtual_watchpoint; 1466 break; 1467 case 8: 1468 ret = env->dmmu.physical_watchpoint; 1469 break; 1470 default: 1471 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1472 ret = 0; 1473 } 1474 break; 1475 } 1476 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */ 1477 { 1478 /* env->dmmuregs[5] holds D-MMU TSB register value 1479 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1480 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); 1481 break; 1482 } 1483 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ 1484 { 1485 /* env->dmmuregs[5] holds D-MMU TSB register value 1486 env->dmmuregs[6] holds D-MMU Tag Access register value */ 1487 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); 1488 break; 1489 } 1490 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1491 { 1492 int reg = (addr >> 3) & 0x3f; 1493 1494 ret = env->dtlb[reg].tte; 1495 break; 1496 } 1497 case ASI_DTLB_TAG_READ: /* D-MMU tag read */ 1498 { 1499 int reg = (addr >> 3) & 0x3f; 1500 1501 ret = env->dtlb[reg].tag; 1502 break; 1503 } 1504 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1505 break; 1506 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1507 ret = env->ivec_status; 1508 break; 1509 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1510 { 1511 int reg = (addr >> 4) & 0x3; 1512 if (reg < 3) { 1513 ret = env->ivec_data[reg]; 1514 } 1515 break; 1516 } 1517 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1518 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1519 /* Hyperprivileged access only */ 1520 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1521 } 1522 /* fall through */ 1523 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1524 { 1525 unsigned int i = (addr >> 3) & 0x7; 1526 ret = env->scratch[i]; 1527 break; 1528 } 1529 case ASI_MMU: /* UA2005 Context ID registers */ 1530 switch ((addr >> 3) & 0x3) { 1531 case 1: 1532 ret = env->dmmu.mmu_primary_context; 1533 break; 1534 case 2: 1535 ret = env->dmmu.mmu_secondary_context; 1536 break; 1537 default: 1538 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1539 } 1540 break; 1541 case ASI_DCACHE_DATA: /* D-cache data */ 1542 case ASI_DCACHE_TAG: /* D-cache tag access */ 1543 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1544 case ASI_AFSR: /* E-cache asynchronous fault status */ 1545 case ASI_AFAR: /* E-cache asynchronous fault address */ 1546 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1547 case ASI_IC_INSTR: /* I-cache instruction access */ 1548 case ASI_IC_TAG: /* I-cache tag access */ 1549 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1550 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1551 case ASI_EC_W: /* E-cache tag */ 1552 case ASI_EC_R: /* E-cache tag */ 1553 break; 1554 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */ 1555 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */ 1556 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */ 1557 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */ 1558 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ 1559 case ASI_INTR_W: /* Interrupt vector, WO */ 1560 default: 1561 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); 1562 ret = 0; 1563 break; 1564 } 1565 1566 /* Convert to signed number */ 1567 if (sign) { 1568 switch (size) { 1569 case 1: 1570 ret = (int8_t) ret; 1571 break; 1572 case 2: 1573 ret = (int16_t) ret; 1574 break; 1575 case 4: 1576 ret = (int32_t) ret; 1577 break; 1578 default: 1579 break; 1580 } 1581 } 1582 #ifdef DEBUG_ASI 1583 dump_asi("read ", last_addr, asi, size, ret); 1584 #endif 1585 return ret; 1586 } 1587 1588 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, 1589 int asi, uint32_t memop) 1590 { 1591 int size = 1 << (memop & MO_SIZE); 1592 CPUState *cs = env_cpu(env); 1593 1594 #ifdef DEBUG_ASI 1595 dump_asi("write", addr, asi, size, val); 1596 #endif 1597 1598 asi &= 0xff; 1599 1600 do_check_asi(env, asi, GETPC()); 1601 do_check_align(env, addr, size - 1, GETPC()); 1602 addr = asi_address_mask(env, asi, addr); 1603 1604 switch (asi) { 1605 case ASI_AIUP: /* As if user primary */ 1606 case ASI_AIUS: /* As if user secondary */ 1607 case ASI_AIUPL: /* As if user primary LE */ 1608 case ASI_AIUSL: /* As if user secondary LE */ 1609 case ASI_P: /* Primary */ 1610 case ASI_S: /* Secondary */ 1611 case ASI_PL: /* Primary LE */ 1612 case ASI_SL: /* Secondary LE */ 1613 case ASI_REAL: /* Bypass */ 1614 case ASI_REAL_IO: /* Bypass, non-cacheable */ 1615 case ASI_REAL_L: /* Bypass LE */ 1616 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ 1617 case ASI_N: /* Nucleus */ 1618 case ASI_NL: /* Nucleus Little Endian (LE) */ 1619 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */ 1620 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */ 1621 case ASI_TWINX_AIUP: /* As if user primary, twinx */ 1622 case ASI_TWINX_AIUS: /* As if user secondary, twinx */ 1623 case ASI_TWINX_REAL: /* Real address, twinx */ 1624 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */ 1625 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */ 1626 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */ 1627 case ASI_TWINX_N: /* Nucleus, twinx */ 1628 case ASI_TWINX_NL: /* Nucleus, twinx, LE */ 1629 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */ 1630 case ASI_TWINX_P: /* Primary, twinx */ 1631 case ASI_TWINX_PL: /* Primary, twinx, LE */ 1632 case ASI_TWINX_S: /* Secondary, twinx */ 1633 case ASI_TWINX_SL: /* Secondary, twinx, LE */ 1634 /* These are always handled inline. */ 1635 g_assert_not_reached(); 1636 /* these ASIs have different functions on UltraSPARC-IIIi 1637 * and UA2005 CPUs. Use the explicit numbers to avoid confusion 1638 */ 1639 case 0x31: 1640 case 0x32: 1641 case 0x39: 1642 case 0x3a: 1643 if (cpu_has_hypervisor(env)) { 1644 /* UA2005 1645 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0 1646 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1 1647 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0 1648 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1 1649 */ 1650 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1651 env->dmmu.sun4v_tsb_pointers[idx] = val; 1652 } else { 1653 goto illegal_insn; 1654 } 1655 break; 1656 case 0x33: 1657 case 0x3b: 1658 if (cpu_has_hypervisor(env)) { 1659 /* UA2005 1660 * ASI_DMMU_CTX_ZERO_CONFIG 1661 * ASI_DMMU_CTX_NONZERO_CONFIG 1662 */ 1663 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1664 } else { 1665 goto illegal_insn; 1666 } 1667 break; 1668 case 0x35: 1669 case 0x36: 1670 case 0x3d: 1671 case 0x3e: 1672 if (cpu_has_hypervisor(env)) { 1673 /* UA2005 1674 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0 1675 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1 1676 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0 1677 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1 1678 */ 1679 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); 1680 env->immu.sun4v_tsb_pointers[idx] = val; 1681 } else { 1682 goto illegal_insn; 1683 } 1684 break; 1685 case 0x37: 1686 case 0x3f: 1687 if (cpu_has_hypervisor(env)) { 1688 /* UA2005 1689 * ASI_IMMU_CTX_ZERO_CONFIG 1690 * ASI_IMMU_CTX_NONZERO_CONFIG 1691 */ 1692 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val; 1693 } else { 1694 goto illegal_insn; 1695 } 1696 break; 1697 case ASI_UPA_CONFIG: /* UPA config */ 1698 /* XXX */ 1699 return; 1700 case ASI_LSU_CONTROL: /* LSU */ 1701 env->lsu = val & (DMMU_E | IMMU_E); 1702 return; 1703 case ASI_IMMU: /* I-MMU regs */ 1704 { 1705 int reg = (addr >> 3) & 0xf; 1706 uint64_t oldreg; 1707 1708 oldreg = env->immu.mmuregs[reg]; 1709 switch (reg) { 1710 case 0: /* RO */ 1711 return; 1712 case 1: /* Not in I-MMU */ 1713 case 2: 1714 return; 1715 case 3: /* SFSR */ 1716 if ((val & 1) == 0) { 1717 val = 0; /* Clear SFSR */ 1718 } 1719 env->immu.sfsr = val; 1720 break; 1721 case 4: /* RO */ 1722 return; 1723 case 5: /* TSB access */ 1724 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" 1725 PRIx64 "\n", env->immu.tsb, val); 1726 env->immu.tsb = val; 1727 break; 1728 case 6: /* Tag access */ 1729 env->immu.tag_access = val; 1730 break; 1731 case 7: 1732 case 8: 1733 return; 1734 default: 1735 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1736 break; 1737 } 1738 1739 if (oldreg != env->immu.mmuregs[reg]) { 1740 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1741 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); 1742 } 1743 #ifdef DEBUG_MMU 1744 dump_mmu(env); 1745 #endif 1746 return; 1747 } 1748 case ASI_ITLB_DATA_IN: /* I-MMU data in */ 1749 /* ignore real translation entries */ 1750 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1751 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, 1752 val, "immu", env, addr); 1753 } 1754 return; 1755 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ 1756 { 1757 /* TODO: auto demap */ 1758 1759 unsigned int i = (addr >> 3) & 0x3f; 1760 1761 /* ignore real translation entries */ 1762 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1763 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, 1764 sun4v_tte_to_sun4u(env, addr, val), env); 1765 } 1766 #ifdef DEBUG_MMU 1767 DPRINTF_MMU("immu data access replaced entry [%i]\n", i); 1768 dump_mmu(env); 1769 #endif 1770 return; 1771 } 1772 case ASI_IMMU_DEMAP: /* I-MMU demap */ 1773 demap_tlb(env->itlb, addr, "immu", env); 1774 return; 1775 case ASI_DMMU: /* D-MMU regs */ 1776 { 1777 int reg = (addr >> 3) & 0xf; 1778 uint64_t oldreg; 1779 1780 oldreg = env->dmmu.mmuregs[reg]; 1781 switch (reg) { 1782 case 0: /* RO */ 1783 case 4: 1784 return; 1785 case 3: /* SFSR */ 1786 if ((val & 1) == 0) { 1787 val = 0; /* Clear SFSR, Fault address */ 1788 env->dmmu.sfar = 0; 1789 } 1790 env->dmmu.sfsr = val; 1791 break; 1792 case 1: /* Primary context */ 1793 env->dmmu.mmu_primary_context = val; 1794 /* can be optimized to only flush MMU_USER_IDX 1795 and MMU_KERNEL_IDX entries */ 1796 tlb_flush(cs); 1797 break; 1798 case 2: /* Secondary context */ 1799 env->dmmu.mmu_secondary_context = val; 1800 /* can be optimized to only flush MMU_USER_SECONDARY_IDX 1801 and MMU_KERNEL_SECONDARY_IDX entries */ 1802 tlb_flush(cs); 1803 break; 1804 case 5: /* TSB access */ 1805 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" 1806 PRIx64 "\n", env->dmmu.tsb, val); 1807 env->dmmu.tsb = val; 1808 break; 1809 case 6: /* Tag access */ 1810 env->dmmu.tag_access = val; 1811 break; 1812 case 7: /* Virtual Watchpoint */ 1813 env->dmmu.virtual_watchpoint = val; 1814 break; 1815 case 8: /* Physical Watchpoint */ 1816 env->dmmu.physical_watchpoint = val; 1817 break; 1818 default: 1819 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1820 break; 1821 } 1822 1823 if (oldreg != env->dmmu.mmuregs[reg]) { 1824 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" 1825 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); 1826 } 1827 #ifdef DEBUG_MMU 1828 dump_mmu(env); 1829 #endif 1830 return; 1831 } 1832 case ASI_DTLB_DATA_IN: /* D-MMU data in */ 1833 /* ignore real translation entries */ 1834 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1835 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, 1836 val, "dmmu", env, addr); 1837 } 1838 return; 1839 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ 1840 { 1841 unsigned int i = (addr >> 3) & 0x3f; 1842 1843 /* ignore real translation entries */ 1844 if (!(addr & TLB_UST1_IS_REAL_BIT)) { 1845 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, 1846 sun4v_tte_to_sun4u(env, addr, val), env); 1847 } 1848 #ifdef DEBUG_MMU 1849 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); 1850 dump_mmu(env); 1851 #endif 1852 return; 1853 } 1854 case ASI_DMMU_DEMAP: /* D-MMU demap */ 1855 demap_tlb(env->dtlb, addr, "dmmu", env); 1856 return; 1857 case ASI_INTR_RECEIVE: /* Interrupt data receive */ 1858 env->ivec_status = val & 0x20; 1859 return; 1860 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ 1861 if (unlikely((addr >= 0x20) && (addr < 0x30))) { 1862 /* Hyperprivileged access only */ 1863 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1864 } 1865 /* fall through */ 1866 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ 1867 { 1868 unsigned int i = (addr >> 3) & 0x7; 1869 env->scratch[i] = val; 1870 return; 1871 } 1872 case ASI_MMU: /* UA2005 Context ID registers */ 1873 { 1874 switch ((addr >> 3) & 0x3) { 1875 case 1: 1876 env->dmmu.mmu_primary_context = val; 1877 env->immu.mmu_primary_context = val; 1878 tlb_flush_by_mmuidx(cs, 1879 (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX)); 1880 break; 1881 case 2: 1882 env->dmmu.mmu_secondary_context = val; 1883 env->immu.mmu_secondary_context = val; 1884 tlb_flush_by_mmuidx(cs, 1885 (1 << MMU_USER_SECONDARY_IDX) | 1886 (1 << MMU_KERNEL_SECONDARY_IDX)); 1887 break; 1888 default: 1889 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1890 } 1891 } 1892 return; 1893 case ASI_QUEUE: /* UA2005 CPU mondo queue */ 1894 case ASI_DCACHE_DATA: /* D-cache data */ 1895 case ASI_DCACHE_TAG: /* D-cache tag access */ 1896 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ 1897 case ASI_AFSR: /* E-cache asynchronous fault status */ 1898 case ASI_AFAR: /* E-cache asynchronous fault address */ 1899 case ASI_EC_TAG_DATA: /* E-cache tag data */ 1900 case ASI_IC_INSTR: /* I-cache instruction access */ 1901 case ASI_IC_TAG: /* I-cache tag access */ 1902 case ASI_IC_PRE_DECODE: /* I-cache predecode */ 1903 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ 1904 case ASI_EC_W: /* E-cache tag */ 1905 case ASI_EC_R: /* E-cache tag */ 1906 return; 1907 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */ 1908 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */ 1909 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */ 1910 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */ 1911 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */ 1912 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */ 1913 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */ 1914 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */ 1915 case ASI_INTR_R: /* Incoming interrupt vector, RO */ 1916 case ASI_PNF: /* Primary no-fault, RO */ 1917 case ASI_SNF: /* Secondary no-fault, RO */ 1918 case ASI_PNFL: /* Primary no-fault LE, RO */ 1919 case ASI_SNFL: /* Secondary no-fault LE, RO */ 1920 default: 1921 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); 1922 return; 1923 illegal_insn: 1924 cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC()); 1925 } 1926 } 1927 #endif /* CONFIG_USER_ONLY */ 1928 #endif /* TARGET_SPARC64 */ 1929 1930 #if !defined(CONFIG_USER_ONLY) 1931 1932 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1933 vaddr addr, unsigned size, 1934 MMUAccessType access_type, 1935 int mmu_idx, MemTxAttrs attrs, 1936 MemTxResult response, uintptr_t retaddr) 1937 { 1938 bool is_write = access_type == MMU_DATA_STORE; 1939 bool is_exec = access_type == MMU_INST_FETCH; 1940 bool is_asi = false; 1941 1942 sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec, 1943 is_asi, size, retaddr); 1944 } 1945 #endif 1946