1 /* 2 * Sparc64 interrupt helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/main-loop.h" 22 #include "cpu.h" 23 #include "exec/helper-proto.h" 24 #include "exec/log.h" 25 #include "trace.h" 26 27 #define DEBUG_PCALL 28 29 #ifdef DEBUG_PCALL 30 static const char * const excp_names[0x80] = { 31 [TT_TFAULT] = "Instruction Access Fault", 32 [TT_TMISS] = "Instruction Access MMU Miss", 33 [TT_CODE_ACCESS] = "Instruction Access Error", 34 [TT_ILL_INSN] = "Illegal Instruction", 35 [TT_PRIV_INSN] = "Privileged Instruction", 36 [TT_NFPU_INSN] = "FPU Disabled", 37 [TT_FP_EXCP] = "FPU Exception", 38 [TT_TOVF] = "Tag Overflow", 39 [TT_CLRWIN] = "Clean Windows", 40 [TT_DIV_ZERO] = "Division By Zero", 41 [TT_DFAULT] = "Data Access Fault", 42 [TT_DMISS] = "Data Access MMU Miss", 43 [TT_DATA_ACCESS] = "Data Access Error", 44 [TT_DPROT] = "Data Protection Error", 45 [TT_UNALIGNED] = "Unaligned Memory Access", 46 [TT_PRIV_ACT] = "Privileged Action", 47 [TT_EXTINT | 0x1] = "External Interrupt 1", 48 [TT_EXTINT | 0x2] = "External Interrupt 2", 49 [TT_EXTINT | 0x3] = "External Interrupt 3", 50 [TT_EXTINT | 0x4] = "External Interrupt 4", 51 [TT_EXTINT | 0x5] = "External Interrupt 5", 52 [TT_EXTINT | 0x6] = "External Interrupt 6", 53 [TT_EXTINT | 0x7] = "External Interrupt 7", 54 [TT_EXTINT | 0x8] = "External Interrupt 8", 55 [TT_EXTINT | 0x9] = "External Interrupt 9", 56 [TT_EXTINT | 0xa] = "External Interrupt 10", 57 [TT_EXTINT | 0xb] = "External Interrupt 11", 58 [TT_EXTINT | 0xc] = "External Interrupt 12", 59 [TT_EXTINT | 0xd] = "External Interrupt 13", 60 [TT_EXTINT | 0xe] = "External Interrupt 14", 61 [TT_EXTINT | 0xf] = "External Interrupt 15", 62 }; 63 #endif 64 65 void sparc_cpu_do_interrupt(CPUState *cs) 66 { 67 SPARCCPU *cpu = SPARC_CPU(cs); 68 CPUSPARCState *env = &cpu->env; 69 int intno = cs->exception_index; 70 trap_state *tsptr; 71 72 /* Compute PSR before exposing state. */ 73 if (env->cc_op != CC_OP_FLAGS) { 74 cpu_get_psr(env); 75 } 76 77 #ifdef DEBUG_PCALL 78 if (qemu_loglevel_mask(CPU_LOG_INT)) { 79 static int count; 80 const char *name; 81 82 if (intno < 0 || intno >= 0x1ff) { 83 name = "Unknown"; 84 } else if (intno >= 0x180) { 85 name = "Hyperprivileged Trap Instruction"; 86 } else if (intno >= 0x100) { 87 name = "Trap Instruction"; 88 } else if (intno >= 0xc0) { 89 name = "Window Fill"; 90 } else if (intno >= 0x80) { 91 name = "Window Spill"; 92 } else { 93 name = excp_names[intno]; 94 if (!name) { 95 name = "Unknown"; 96 } 97 } 98 99 qemu_log("%6d: %s (v=%04x)\n", count, name, intno); 100 log_cpu_state(cs, 0); 101 #if 0 102 { 103 int i; 104 uint8_t *ptr; 105 106 qemu_log(" code="); 107 ptr = (uint8_t *)env->pc; 108 for (i = 0; i < 16; i++) { 109 qemu_log(" %02x", ldub(ptr + i)); 110 } 111 qemu_log("\n"); 112 } 113 #endif 114 count++; 115 } 116 #endif 117 #if !defined(CONFIG_USER_ONLY) 118 if (env->tl >= env->maxtl) { 119 cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," 120 " Error state", cs->exception_index, env->tl, env->maxtl); 121 return; 122 } 123 #endif 124 if (env->tl < env->maxtl - 1) { 125 env->tl++; 126 } else { 127 env->pstate |= PS_RED; 128 if (env->tl < env->maxtl) { 129 env->tl++; 130 } 131 } 132 tsptr = cpu_tsptr(env); 133 134 tsptr->tstate = (cpu_get_ccr(env) << 32) | 135 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 136 cpu_get_cwp64(env); 137 tsptr->tpc = env->pc; 138 tsptr->tnpc = env->npc; 139 tsptr->tt = intno; 140 141 if (cpu_has_hypervisor(env)) { 142 env->htstate[env->tl] = env->hpstate; 143 /* XXX OpenSPARC T1 - UltraSPARC T3 have MAXPTL=2 144 but this may change in the future */ 145 if (env->tl > 2) { 146 env->hpstate |= HS_PRIV; 147 } 148 } 149 150 if (env->def.features & CPU_FEATURE_GL) { 151 tsptr->tstate |= (env->gl & 7ULL) << 40; 152 cpu_gl_switch_gregs(env, env->gl + 1); 153 env->gl++; 154 } 155 156 switch (intno) { 157 case TT_IVEC: 158 if (!cpu_has_hypervisor(env)) { 159 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG); 160 } 161 break; 162 case TT_TFAULT: 163 case TT_DFAULT: 164 case TT_TMISS ... TT_TMISS + 3: 165 case TT_DMISS ... TT_DMISS + 3: 166 case TT_DPROT ... TT_DPROT + 3: 167 if (cpu_has_hypervisor(env)) { 168 env->hpstate |= HS_PRIV; 169 env->pstate = PS_PEF | PS_PRIV; 170 } else { 171 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG); 172 } 173 break; 174 case TT_INSN_REAL_TRANSLATION_MISS ... TT_DATA_REAL_TRANSLATION_MISS: 175 case TT_HTRAP ... TT_HTRAP + 127: 176 env->hpstate |= HS_PRIV; 177 break; 178 default: 179 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG); 180 break; 181 } 182 183 if (intno == TT_CLRWIN) { 184 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); 185 } else if ((intno & 0x1c0) == TT_SPILL) { 186 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); 187 } else if ((intno & 0x1c0) == TT_FILL) { 188 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); 189 } 190 191 if (cpu_hypervisor_mode(env)) { 192 env->pc = (env->htba & ~0x3fffULL) | (intno << 5); 193 } else { 194 env->pc = env->tbr & ~0x7fffULL; 195 env->pc |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); 196 } 197 env->npc = env->pc + 4; 198 cs->exception_index = -1; 199 } 200 201 trap_state *cpu_tsptr(CPUSPARCState* env) 202 { 203 return &env->ts[env->tl & MAXTL_MASK]; 204 } 205 206 static bool do_modify_softint(CPUSPARCState *env, uint32_t value) 207 { 208 if (env->softint != value) { 209 env->softint = value; 210 #if !defined(CONFIG_USER_ONLY) 211 if (cpu_interrupts_enabled(env)) { 212 qemu_mutex_lock_iothread(); 213 cpu_check_irqs(env); 214 qemu_mutex_unlock_iothread(); 215 } 216 #endif 217 return true; 218 } 219 return false; 220 } 221 222 void helper_set_softint(CPUSPARCState *env, uint64_t value) 223 { 224 if (do_modify_softint(env, env->softint | (uint32_t)value)) { 225 trace_int_helper_set_softint(env->softint); 226 } 227 } 228 229 void helper_clear_softint(CPUSPARCState *env, uint64_t value) 230 { 231 if (do_modify_softint(env, env->softint & (uint32_t)~value)) { 232 trace_int_helper_clear_softint(env->softint); 233 } 234 } 235 236 void helper_write_softint(CPUSPARCState *env, uint64_t value) 237 { 238 if (do_modify_softint(env, (uint32_t)value)) { 239 trace_int_helper_write_softint(env->softint); 240 } 241 } 242