1 /* 2 * Sparc32 interrupt helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "trace.h" 23 #include "exec/log.h" 24 #include "sysemu/runstate.h" 25 26 27 static const char * const excp_names[0x80] = { 28 [TT_TFAULT] = "Instruction Access Fault", 29 [TT_ILL_INSN] = "Illegal Instruction", 30 [TT_PRIV_INSN] = "Privileged Instruction", 31 [TT_NFPU_INSN] = "FPU Disabled", 32 [TT_WIN_OVF] = "Window Overflow", 33 [TT_WIN_UNF] = "Window Underflow", 34 [TT_UNALIGNED] = "Unaligned Memory Access", 35 [TT_FP_EXCP] = "FPU Exception", 36 [TT_DFAULT] = "Data Access Fault", 37 [TT_TOVF] = "Tag Overflow", 38 [TT_EXTINT | 0x1] = "External Interrupt 1", 39 [TT_EXTINT | 0x2] = "External Interrupt 2", 40 [TT_EXTINT | 0x3] = "External Interrupt 3", 41 [TT_EXTINT | 0x4] = "External Interrupt 4", 42 [TT_EXTINT | 0x5] = "External Interrupt 5", 43 [TT_EXTINT | 0x6] = "External Interrupt 6", 44 [TT_EXTINT | 0x7] = "External Interrupt 7", 45 [TT_EXTINT | 0x8] = "External Interrupt 8", 46 [TT_EXTINT | 0x9] = "External Interrupt 9", 47 [TT_EXTINT | 0xa] = "External Interrupt 10", 48 [TT_EXTINT | 0xb] = "External Interrupt 11", 49 [TT_EXTINT | 0xc] = "External Interrupt 12", 50 [TT_EXTINT | 0xd] = "External Interrupt 13", 51 [TT_EXTINT | 0xe] = "External Interrupt 14", 52 [TT_EXTINT | 0xf] = "External Interrupt 15", 53 [TT_TOVF] = "Tag Overflow", 54 [TT_CODE_ACCESS] = "Instruction Access Error", 55 [TT_DATA_ACCESS] = "Data Access Error", 56 [TT_DIV_ZERO] = "Division By Zero", 57 [TT_NCP_INSN] = "Coprocessor Disabled", 58 }; 59 60 static const char *excp_name_str(int32_t exception_index) 61 { 62 if (exception_index < 0 || exception_index >= ARRAY_SIZE(excp_names)) { 63 return "Unknown"; 64 } 65 return excp_names[exception_index]; 66 } 67 68 void sparc_cpu_do_interrupt(CPUState *cs) 69 { 70 SPARCCPU *cpu = SPARC_CPU(cs); 71 CPUSPARCState *env = &cpu->env; 72 int cwp, intno = cs->exception_index; 73 74 /* Compute PSR before exposing state. */ 75 if (env->cc_op != CC_OP_FLAGS) { 76 cpu_get_psr(env); 77 } 78 79 if (qemu_loglevel_mask(CPU_LOG_INT)) { 80 static int count; 81 const char *name; 82 83 if (intno < 0 || intno >= 0x100) { 84 name = "Unknown"; 85 } else if (intno >= 0x80) { 86 name = "Trap Instruction"; 87 } else { 88 name = excp_name_str(intno); 89 } 90 91 qemu_log("%6d: %s (v=%02x)\n", count, name, intno); 92 log_cpu_state(cs, 0); 93 #if 0 94 { 95 int i; 96 uint8_t *ptr; 97 98 qemu_log(" code="); 99 ptr = (uint8_t *)env->pc; 100 for (i = 0; i < 16; i++) { 101 qemu_log(" %02x", ldub(ptr + i)); 102 } 103 qemu_log("\n"); 104 } 105 #endif 106 count++; 107 } 108 #if !defined(CONFIG_USER_ONLY) 109 if (env->psret == 0) { 110 if (cs->exception_index == 0x80 && 111 env->def.features & CPU_FEATURE_TA0_SHUTDOWN) { 112 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 113 } else { 114 cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, " 115 "Error state", 116 cs->exception_index, excp_name_str(cs->exception_index)); 117 } 118 return; 119 } 120 #endif 121 env->psret = 0; 122 cwp = cpu_cwp_dec(env, env->cwp - 1); 123 cpu_set_cwp(env, cwp); 124 env->regwptr[9] = env->pc; 125 env->regwptr[10] = env->npc; 126 env->psrps = env->psrs; 127 env->psrs = 1; 128 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); 129 env->pc = env->tbr; 130 env->npc = env->pc + 4; 131 cs->exception_index = -1; 132 133 #if !defined(CONFIG_USER_ONLY) 134 /* IRQ acknowledgment */ 135 if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { 136 env->qemu_irq_ack(env, env->irq_manager, intno); 137 } 138 #endif 139 } 140 141 #if !defined(CONFIG_USER_ONLY) 142 static void leon3_cache_control_int(CPUSPARCState *env) 143 { 144 uint32_t state = 0; 145 146 if (env->cache_control & CACHE_CTRL_IF) { 147 /* Instruction cache state */ 148 state = env->cache_control & CACHE_STATE_MASK; 149 if (state == CACHE_ENABLED) { 150 state = CACHE_FROZEN; 151 trace_int_helper_icache_freeze(); 152 } 153 154 env->cache_control &= ~CACHE_STATE_MASK; 155 env->cache_control |= state; 156 } 157 158 if (env->cache_control & CACHE_CTRL_DF) { 159 /* Data cache state */ 160 state = (env->cache_control >> 2) & CACHE_STATE_MASK; 161 if (state == CACHE_ENABLED) { 162 state = CACHE_FROZEN; 163 trace_int_helper_dcache_freeze(); 164 } 165 166 env->cache_control &= ~(CACHE_STATE_MASK << 2); 167 env->cache_control |= (state << 2); 168 } 169 } 170 171 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno) 172 { 173 leon3_irq_ack(irq_manager, intno); 174 leon3_cache_control_int(env); 175 } 176 #endif 177