1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu/bswap.h" 5 #include "cpu-qom.h" 6 #include "exec/cpu-defs.h" 7 #include "qemu/cpu-float.h" 8 9 /* 10 * From Oracle SPARC Architecture 2015: 11 * 12 * Compatibility notes: The PSO memory model described in SPARC V8 and 13 * SPARC V9 compatibility architecture specifications was never implemented 14 * in a SPARC V9 implementation and is not included in the Oracle SPARC 15 * Architecture specification. 16 * 17 * The RMO memory model described in the SPARC V9 specification was 18 * implemented in some non-Sun SPARC V9 implementations, but is not 19 * directly supported in Oracle SPARC Architecture 2015 implementations. 20 * 21 * Therefore always use TSO in QEMU. 22 * 23 * D.5 Specification of Partial Store Order (PSO) 24 * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. 25 * 26 * D.6 Specification of Total Store Order (TSO) 27 * ... PSO with the additional requirement that all [stores] are followed 28 * by an implied MEMBAR #StoreStore. 29 */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) 31 32 #if !defined(TARGET_SPARC64) 33 #define TARGET_DPREGS 16 34 #else 35 #define TARGET_DPREGS 32 36 #endif 37 38 /*#define EXCP_INTERRUPT 0x100*/ 39 40 /* Windowed register indexes. */ 41 enum { 42 WREG_O0, 43 WREG_O1, 44 WREG_O2, 45 WREG_O3, 46 WREG_O4, 47 WREG_O5, 48 WREG_O6, 49 WREG_O7, 50 51 WREG_L0, 52 WREG_L1, 53 WREG_L2, 54 WREG_L3, 55 WREG_L4, 56 WREG_L5, 57 WREG_L6, 58 WREG_L7, 59 60 WREG_I0, 61 WREG_I1, 62 WREG_I2, 63 WREG_I3, 64 WREG_I4, 65 WREG_I5, 66 WREG_I6, 67 WREG_I7, 68 69 WREG_SP = WREG_O6, 70 WREG_FP = WREG_I6, 71 }; 72 73 /* trap definitions */ 74 #ifndef TARGET_SPARC64 75 #define TT_TFAULT 0x01 76 #define TT_ILL_INSN 0x02 77 #define TT_PRIV_INSN 0x03 78 #define TT_NFPU_INSN 0x04 79 #define TT_WIN_OVF 0x05 80 #define TT_WIN_UNF 0x06 81 #define TT_UNALIGNED 0x07 82 #define TT_FP_EXCP 0x08 83 #define TT_DFAULT 0x09 84 #define TT_TOVF 0x0a 85 #define TT_EXTINT 0x10 86 #define TT_CODE_ACCESS 0x21 87 #define TT_UNIMP_FLUSH 0x25 88 #define TT_DATA_ACCESS 0x29 89 #define TT_DIV_ZERO 0x2a 90 #define TT_NCP_INSN 0x24 91 #define TT_TRAP 0x80 92 #else 93 #define TT_POWER_ON_RESET 0x01 94 #define TT_TFAULT 0x08 95 #define TT_CODE_ACCESS 0x0a 96 #define TT_ILL_INSN 0x10 97 #define TT_UNIMP_FLUSH TT_ILL_INSN 98 #define TT_PRIV_INSN 0x11 99 #define TT_NFPU_INSN 0x20 100 #define TT_FP_EXCP 0x21 101 #define TT_TOVF 0x23 102 #define TT_CLRWIN 0x24 103 #define TT_DIV_ZERO 0x28 104 #define TT_DFAULT 0x30 105 #define TT_DATA_ACCESS 0x32 106 #define TT_UNALIGNED 0x34 107 #define TT_PRIV_ACT 0x37 108 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 109 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 110 #define TT_EXTINT 0x40 111 #define TT_IVEC 0x60 112 #define TT_TMISS 0x64 113 #define TT_DMISS 0x68 114 #define TT_DPROT 0x6c 115 #define TT_SPILL 0x80 116 #define TT_FILL 0xc0 117 #define TT_WOTHER (1 << 5) 118 #define TT_TRAP 0x100 119 #define TT_HTRAP 0x180 120 #endif 121 122 #define PSR_NEG_SHIFT 23 123 #define PSR_NEG (1 << PSR_NEG_SHIFT) 124 #define PSR_ZERO_SHIFT 22 125 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 126 #define PSR_OVF_SHIFT 21 127 #define PSR_OVF (1 << PSR_OVF_SHIFT) 128 #define PSR_CARRY_SHIFT 20 129 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 130 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 131 #if !defined(TARGET_SPARC64) 132 #define PSR_EF (1<<12) 133 #define PSR_PIL 0xf00 134 #define PSR_S (1<<7) 135 #define PSR_PS (1<<6) 136 #define PSR_ET (1<<5) 137 #define PSR_CWP 0x1f 138 #endif 139 140 /* Trap base register */ 141 #define TBR_BASE_MASK 0xfffff000 142 143 #if defined(TARGET_SPARC64) 144 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 145 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 146 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 147 #define PS_CLE (1<<9) /* UA2007 */ 148 #define PS_TLE (1<<8) /* UA2007 */ 149 #define PS_RMO (1<<7) 150 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 151 #define PS_PEF (1<<4) /* enable fpu */ 152 #define PS_AM (1<<3) /* address mask */ 153 #define PS_PRIV (1<<2) 154 #define PS_IE (1<<1) 155 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 156 157 #define FPRS_DL (1 << 0) 158 #define FPRS_DU (1 << 1) 159 #define FPRS_FEF (1 << 2) 160 161 #define HS_PRIV (1<<2) 162 #endif 163 164 /* Fcc */ 165 #define FSR_RD1 (1ULL << 31) 166 #define FSR_RD0 (1ULL << 30) 167 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 168 #define FSR_RD_NEAREST 0 169 #define FSR_RD_ZERO FSR_RD0 170 #define FSR_RD_POS FSR_RD1 171 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 172 173 #define FSR_NVM (1ULL << 27) 174 #define FSR_OFM (1ULL << 26) 175 #define FSR_UFM (1ULL << 25) 176 #define FSR_DZM (1ULL << 24) 177 #define FSR_NXM (1ULL << 23) 178 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 179 180 #define FSR_NVA (1ULL << 9) 181 #define FSR_OFA (1ULL << 8) 182 #define FSR_UFA (1ULL << 7) 183 #define FSR_DZA (1ULL << 6) 184 #define FSR_NXA (1ULL << 5) 185 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 186 187 #define FSR_NVC (1ULL << 4) 188 #define FSR_OFC (1ULL << 3) 189 #define FSR_UFC (1ULL << 2) 190 #define FSR_DZC (1ULL << 1) 191 #define FSR_NXC (1ULL << 0) 192 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 193 194 #define FSR_FTT2 (1ULL << 16) 195 #define FSR_FTT1 (1ULL << 15) 196 #define FSR_FTT0 (1ULL << 14) 197 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 198 #ifdef TARGET_SPARC64 199 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL 200 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL 201 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL 202 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL 203 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL 204 #else 205 #define FSR_FTT_NMASK 0xfffe3fffULL 206 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL 207 #define FSR_LDFSR_OLDMASK 0x000fc000ULL 208 #endif 209 #define FSR_LDFSR_MASK 0xcfc00fffULL 210 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 211 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 212 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 213 #define FSR_FTT_INVAL_FPR (6ULL << 14) 214 215 #define FSR_FCC1_SHIFT 11 216 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) 217 #define FSR_FCC0_SHIFT 10 218 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) 219 220 /* MMU */ 221 #define MMU_E (1<<0) 222 #define MMU_NF (1<<1) 223 224 #define PTE_ENTRYTYPE_MASK 3 225 #define PTE_ACCESS_MASK 0x1c 226 #define PTE_ACCESS_SHIFT 2 227 #define PTE_PPN_SHIFT 7 228 #define PTE_ADDR_MASK 0xffffff00 229 230 #define PG_ACCESSED_BIT 5 231 #define PG_MODIFIED_BIT 6 232 #define PG_CACHE_BIT 7 233 234 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 235 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 236 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 237 238 /* 3 <= NWINDOWS <= 32. */ 239 #define MIN_NWINDOWS 3 240 #define MAX_NWINDOWS 32 241 242 #ifdef TARGET_SPARC64 243 typedef struct trap_state { 244 uint64_t tpc; 245 uint64_t tnpc; 246 uint64_t tstate; 247 uint32_t tt; 248 } trap_state; 249 #endif 250 #define TARGET_INSN_START_EXTRA_WORDS 1 251 252 typedef struct sparc_def_t { 253 const char *name; 254 target_ulong iu_version; 255 uint32_t fpu_version; 256 uint32_t mmu_version; 257 uint32_t mmu_bm; 258 uint32_t mmu_ctpr_mask; 259 uint32_t mmu_cxr_mask; 260 uint32_t mmu_sfsr_mask; 261 uint32_t mmu_trcr_mask; 262 uint32_t mxcc_version; 263 uint32_t features; 264 uint32_t nwindows; 265 uint32_t maxtl; 266 } sparc_def_t; 267 268 #define FEATURE(X) CPU_FEATURE_BIT_##X, 269 enum { 270 #include "cpu-feature.h.inc" 271 }; 272 273 #undef FEATURE 274 #define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X, 275 276 enum { 277 #include "cpu-feature.h.inc" 278 }; 279 280 #undef FEATURE 281 282 #ifndef TARGET_SPARC64 283 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 284 CPU_FEATURE_FSMULD) 285 #else 286 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 287 CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ 288 CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) 289 enum { 290 mmu_us_12, // Ultrasparc < III (64 entry TLB) 291 mmu_us_3, // Ultrasparc III (512 entry TLB) 292 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 293 mmu_sun4v, // T1, T2 294 }; 295 #endif 296 297 #define TTE_VALID_BIT (1ULL << 63) 298 #define TTE_NFO_BIT (1ULL << 60) 299 #define TTE_IE_BIT (1ULL << 59) 300 #define TTE_USED_BIT (1ULL << 41) 301 #define TTE_LOCKED_BIT (1ULL << 6) 302 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 303 #define TTE_PRIV_BIT (1ULL << 2) 304 #define TTE_W_OK_BIT (1ULL << 1) 305 #define TTE_GLOBAL_BIT (1ULL << 0) 306 307 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 308 #define TTE_USED_BIT_UA2005 (1ULL << 47) 309 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 310 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 311 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 312 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 313 314 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 315 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 316 #define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) 317 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 318 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 319 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 320 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 321 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 322 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 323 324 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 325 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 326 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 327 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 328 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 329 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 330 331 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 332 333 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 334 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 335 336 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 337 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 338 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 339 340 /* UltraSPARC T1 specific */ 341 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 342 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 343 344 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 345 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 346 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 347 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 348 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 349 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 350 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 351 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 352 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 353 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 354 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 355 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 356 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 357 358 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 359 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 360 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 361 #define SFSR_CT_SECONDARY (1ULL << 4) 362 #define SFSR_CT_NUCLEUS (2ULL << 4) 363 #define SFSR_CT_NOTRANS (3ULL << 4) 364 #define SFSR_CT_MASK (3ULL << 4) 365 366 /* Leon3 cache control */ 367 368 /* Cache control: emulate the behavior of cache control registers but without 369 any effect on the emulated */ 370 371 #define CACHE_STATE_MASK 0x3 372 #define CACHE_DISABLED 0x0 373 #define CACHE_FROZEN 0x1 374 #define CACHE_ENABLED 0x3 375 376 /* Cache Control register fields */ 377 378 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 379 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 380 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 381 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 382 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 383 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 384 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 385 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 386 387 #define CONVERT_BIT(X, SRC, DST) \ 388 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 389 390 typedef struct SparcTLBEntry { 391 uint64_t tag; 392 uint64_t tte; 393 } SparcTLBEntry; 394 395 struct CPUTimer 396 { 397 const char *name; 398 uint32_t frequency; 399 uint32_t disabled; 400 uint64_t disabled_mask; 401 uint32_t npt; 402 uint64_t npt_mask; 403 int64_t clock_offset; 404 QEMUTimer *qtimer; 405 }; 406 407 typedef struct CPUTimer CPUTimer; 408 409 typedef struct CPUArchState CPUSPARCState; 410 #if defined(TARGET_SPARC64) 411 typedef union { 412 uint64_t mmuregs[16]; 413 struct { 414 uint64_t tsb_tag_target; 415 uint64_t mmu_primary_context; 416 uint64_t mmu_secondary_context; 417 uint64_t sfsr; 418 uint64_t sfar; 419 uint64_t tsb; 420 uint64_t tag_access; 421 uint64_t virtual_watchpoint; 422 uint64_t physical_watchpoint; 423 uint64_t sun4v_ctx_config[2]; 424 uint64_t sun4v_tsb_pointers[4]; 425 }; 426 } SparcV9MMU; 427 #endif 428 struct CPUArchState { 429 target_ulong gregs[8]; /* general registers */ 430 target_ulong *regwptr; /* pointer to current register window */ 431 target_ulong pc; /* program counter */ 432 target_ulong npc; /* next program counter */ 433 target_ulong y; /* multiply/divide register */ 434 435 /* 436 * Bit 31 is for icc, bit 63 for xcc. 437 * Other bits are garbage. 438 */ 439 target_long cc_N; 440 target_long cc_V; 441 442 /* 443 * Z is represented as == 0; any non-zero value is !Z. 444 * For sparc64, the high 32-bits of icc.Z are garbage. 445 */ 446 target_ulong icc_Z; 447 #ifdef TARGET_SPARC64 448 target_ulong xcc_Z; 449 #endif 450 451 /* 452 * For sparc32, icc.C is boolean. 453 * For sparc64, xcc.C is boolean; 454 * icc.C is bit 32 with other bits garbage. 455 */ 456 target_ulong icc_C; 457 #ifdef TARGET_SPARC64 458 target_ulong xcc_C; 459 #endif 460 461 target_ulong cond; /* conditional branch result (XXX: save it in a 462 temporary register when possible) */ 463 464 target_ulong fsr; /* FPU state register */ 465 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 466 uint32_t cwp; /* index of current register window (extracted 467 from PSR) */ 468 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 469 uint32_t wim; /* window invalid mask */ 470 #endif 471 target_ulong tbr; /* trap base register */ 472 #if !defined(TARGET_SPARC64) 473 int psrs; /* supervisor mode (extracted from PSR) */ 474 int psrps; /* previous supervisor mode */ 475 int psret; /* enable traps */ 476 #endif 477 uint32_t psrpil; /* interrupt blocking level */ 478 uint32_t pil_in; /* incoming interrupt level bitmap */ 479 #if !defined(TARGET_SPARC64) 480 int psref; /* enable fpu */ 481 #endif 482 int interrupt_index; 483 /* NOTE: we allow 8 more registers to handle wrapping */ 484 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 485 486 /* Fields up to this point are cleared by a CPU reset */ 487 struct {} end_reset_fields; 488 489 /* Fields from here on are preserved across CPU reset. */ 490 target_ulong version; 491 uint32_t nwindows; 492 493 /* MMU regs */ 494 #if defined(TARGET_SPARC64) 495 uint64_t lsu; 496 #define DMMU_E 0x8 497 #define IMMU_E 0x4 498 SparcV9MMU immu; 499 SparcV9MMU dmmu; 500 SparcTLBEntry itlb[64]; 501 SparcTLBEntry dtlb[64]; 502 uint32_t mmu_version; 503 #else 504 uint32_t mmuregs[32]; 505 uint64_t mxccdata[4]; 506 uint64_t mxccregs[8]; 507 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 508 uint64_t mmubpaction; 509 uint64_t mmubpregs[4]; 510 uint64_t prom_addr; 511 #endif 512 /* temporary float registers */ 513 float128 qt0, qt1; 514 float_status fp_status; 515 #if defined(TARGET_SPARC64) 516 #define MAXTL_MAX 8 517 #define MAXTL_MASK (MAXTL_MAX - 1) 518 trap_state ts[MAXTL_MAX]; 519 uint32_t asi; 520 uint32_t pstate; 521 uint32_t tl; 522 uint32_t maxtl; 523 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 524 uint64_t agregs[8]; /* alternate general registers */ 525 uint64_t bgregs[8]; /* backup for normal global registers */ 526 uint64_t igregs[8]; /* interrupt general registers */ 527 uint64_t mgregs[8]; /* mmu general registers */ 528 uint64_t glregs[8 * MAXTL_MAX]; 529 uint32_t fprs; 530 uint64_t tick_cmpr, stick_cmpr; 531 CPUTimer *tick, *stick; 532 #define TICK_NPT_MASK 0x8000000000000000ULL 533 #define TICK_INT_DIS 0x8000000000000000ULL 534 uint64_t gsr; 535 uint32_t gl; // UA2005 536 /* UA 2005 hyperprivileged registers */ 537 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 538 uint64_t scratch[8]; 539 CPUTimer *hstick; // UA 2005 540 /* Interrupt vector registers */ 541 uint64_t ivec_status; 542 uint64_t ivec_data[3]; 543 uint32_t softint; 544 #define SOFTINT_TIMER 1 545 #define SOFTINT_STIMER (1 << 16) 546 #define SOFTINT_INTRMASK (0xFFFE) 547 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 548 #endif 549 sparc_def_t def; 550 551 void *irq_manager; 552 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); 553 554 /* Leon3 cache control */ 555 uint32_t cache_control; 556 }; 557 558 /** 559 * SPARCCPU: 560 * @env: #CPUSPARCState 561 * 562 * A SPARC CPU. 563 */ 564 struct ArchCPU { 565 CPUState parent_obj; 566 567 CPUSPARCState env; 568 }; 569 570 /** 571 * SPARCCPUClass: 572 * @parent_realize: The parent class' realize handler. 573 * @parent_phases: The parent class' reset phase handlers. 574 * 575 * A SPARC CPU model. 576 */ 577 struct SPARCCPUClass { 578 CPUClass parent_class; 579 580 DeviceRealize parent_realize; 581 ResettablePhases parent_phases; 582 sparc_def_t *cpu_def; 583 }; 584 585 #ifndef CONFIG_USER_ONLY 586 extern const VMStateDescription vmstate_sparc_cpu; 587 588 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 589 #endif 590 591 void sparc_cpu_do_interrupt(CPUState *cpu); 592 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 593 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 594 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 595 MMUAccessType access_type, 596 int mmu_idx, 597 uintptr_t retaddr); 598 G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); 599 600 /* cpu_init.c */ 601 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 602 void sparc_cpu_list(void); 603 /* mmu_helper.c */ 604 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 605 MMUAccessType access_type, int mmu_idx, 606 bool probe, uintptr_t retaddr); 607 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 608 void dump_mmu(CPUSPARCState *env); 609 610 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 611 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 612 uint8_t *buf, int len, bool is_write); 613 #endif 614 615 616 /* translate.c */ 617 void sparc_tcg_init(void); 618 void sparc_restore_state_to_opc(CPUState *cs, 619 const TranslationBlock *tb, 620 const uint64_t *data); 621 622 /* cpu-exec.c */ 623 624 /* win_helper.c */ 625 target_ulong cpu_get_psr(CPUSPARCState *env1); 626 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 627 void cpu_put_psr_icc(CPUSPARCState *env1, target_ulong val); 628 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 629 #ifdef TARGET_SPARC64 630 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 631 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 632 #endif 633 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 634 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 635 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 636 637 /* sun4m.c, sun4u.c */ 638 void cpu_check_irqs(CPUSPARCState *env); 639 640 #if defined (TARGET_SPARC64) 641 642 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 643 { 644 return (x & mask) == (y & mask); 645 } 646 647 #define MMU_CONTEXT_BITS 13 648 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 649 650 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 651 uint64_t context) 652 { 653 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 654 } 655 656 #endif 657 658 /* cpu-exec.c */ 659 #if !defined(CONFIG_USER_ONLY) 660 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 661 vaddr addr, unsigned size, 662 MMUAccessType access_type, 663 int mmu_idx, MemTxAttrs attrs, 664 MemTxResult response, uintptr_t retaddr); 665 #if defined(TARGET_SPARC64) 666 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 667 int mmu_idx); 668 #endif 669 #endif 670 671 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 672 673 #define cpu_list sparc_cpu_list 674 675 /* MMU modes definitions */ 676 #if defined (TARGET_SPARC64) 677 #define MMU_USER_IDX 0 678 #define MMU_USER_SECONDARY_IDX 1 679 #define MMU_KERNEL_IDX 2 680 #define MMU_KERNEL_SECONDARY_IDX 3 681 #define MMU_NUCLEUS_IDX 4 682 #define MMU_PHYS_IDX 5 683 #else 684 #define MMU_USER_IDX 0 685 #define MMU_KERNEL_IDX 1 686 #define MMU_PHYS_IDX 2 687 #endif 688 689 #if defined (TARGET_SPARC64) 690 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 691 { 692 return env1->def.features & CPU_FEATURE_HYPV; 693 } 694 695 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 696 { 697 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 698 } 699 700 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 701 { 702 return env1->pstate & PS_PRIV; 703 } 704 #else 705 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 706 { 707 return env1->psrs; 708 } 709 #endif 710 711 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) 712 { 713 #if defined(CONFIG_USER_ONLY) 714 return MMU_USER_IDX; 715 #elif !defined(TARGET_SPARC64) 716 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ 717 return MMU_PHYS_IDX; 718 } else { 719 return env->psrs; 720 } 721 #else 722 /* IMMU or DMMU disabled. */ 723 if (ifetch 724 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 725 : (env->lsu & DMMU_E) == 0) { 726 return MMU_PHYS_IDX; 727 } else if (cpu_hypervisor_mode(env)) { 728 return MMU_PHYS_IDX; 729 } else if (env->tl > 0) { 730 return MMU_NUCLEUS_IDX; 731 } else if (cpu_supervisor_mode(env)) { 732 return MMU_KERNEL_IDX; 733 } else { 734 return MMU_USER_IDX; 735 } 736 #endif 737 } 738 739 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 740 { 741 #if !defined (TARGET_SPARC64) 742 if (env1->psret != 0) 743 return 1; 744 #else 745 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 746 return 1; 747 } 748 #endif 749 750 return 0; 751 } 752 753 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 754 { 755 #if !defined(TARGET_SPARC64) 756 /* level 15 is non-maskable on sparc v8 */ 757 return pil == 15 || pil > env1->psrpil; 758 #else 759 return pil > env1->psrpil; 760 #endif 761 } 762 763 #include "exec/cpu-all.h" 764 765 #ifdef TARGET_SPARC64 766 /* sun4u.c */ 767 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 768 uint64_t cpu_tick_get_count(CPUTimer *timer); 769 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 770 trap_state* cpu_tsptr(CPUSPARCState* env); 771 #endif 772 773 #define TB_FLAG_MMU_MASK 7 774 #define TB_FLAG_FPU_ENABLED (1 << 4) 775 #define TB_FLAG_AM_ENABLED (1 << 5) 776 #define TB_FLAG_SUPER (1 << 6) 777 #define TB_FLAG_HYPER (1 << 7) 778 #define TB_FLAG_ASI_SHIFT 24 779 780 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 781 uint64_t *cs_base, uint32_t *pflags) 782 { 783 uint32_t flags; 784 *pc = env->pc; 785 *cs_base = env->npc; 786 flags = cpu_mmu_index(env, false); 787 #ifndef CONFIG_USER_ONLY 788 if (cpu_supervisor_mode(env)) { 789 flags |= TB_FLAG_SUPER; 790 } 791 #endif 792 #ifdef TARGET_SPARC64 793 #ifndef CONFIG_USER_ONLY 794 if (cpu_hypervisor_mode(env)) { 795 flags |= TB_FLAG_HYPER; 796 } 797 #endif 798 if (env->pstate & PS_AM) { 799 flags |= TB_FLAG_AM_ENABLED; 800 } 801 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { 802 flags |= TB_FLAG_FPU_ENABLED; 803 } 804 flags |= env->asi << TB_FLAG_ASI_SHIFT; 805 #else 806 if (env->psref) { 807 flags |= TB_FLAG_FPU_ENABLED; 808 } 809 #endif 810 *pflags = flags; 811 } 812 813 static inline bool tb_fpu_enabled(int tb_flags) 814 { 815 #if defined(CONFIG_USER_ONLY) 816 return true; 817 #else 818 return tb_flags & TB_FLAG_FPU_ENABLED; 819 #endif 820 } 821 822 static inline bool tb_am_enabled(int tb_flags) 823 { 824 #ifndef TARGET_SPARC64 825 return false; 826 #else 827 return tb_flags & TB_FLAG_AM_ENABLED; 828 #endif 829 } 830 831 #ifdef TARGET_SPARC64 832 /* win_helper.c */ 833 target_ulong cpu_get_ccr(CPUSPARCState *env1); 834 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 835 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 836 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 837 838 static inline uint64_t sparc64_tstate(CPUSPARCState *env) 839 { 840 uint64_t tstate = (cpu_get_ccr(env) << 32) | 841 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 842 cpu_get_cwp64(env); 843 844 if (env->def.features & CPU_FEATURE_GL) { 845 tstate |= (env->gl & 7ULL) << 40; 846 } 847 return tstate; 848 } 849 #endif 850 851 #endif 852