1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu-common.h" 5 #include "qemu/bswap.h" 6 #include "cpu-qom.h" 7 #include "exec/cpu-defs.h" 8 9 #define ALIGNED_ONLY 10 11 #if !defined(TARGET_SPARC64) 12 #define TARGET_DPREGS 16 13 #else 14 #define TARGET_DPREGS 32 15 #endif 16 17 #define CPUArchState struct CPUSPARCState 18 19 /*#define EXCP_INTERRUPT 0x100*/ 20 21 /* trap definitions */ 22 #ifndef TARGET_SPARC64 23 #define TT_TFAULT 0x01 24 #define TT_ILL_INSN 0x02 25 #define TT_PRIV_INSN 0x03 26 #define TT_NFPU_INSN 0x04 27 #define TT_WIN_OVF 0x05 28 #define TT_WIN_UNF 0x06 29 #define TT_UNALIGNED 0x07 30 #define TT_FP_EXCP 0x08 31 #define TT_DFAULT 0x09 32 #define TT_TOVF 0x0a 33 #define TT_EXTINT 0x10 34 #define TT_CODE_ACCESS 0x21 35 #define TT_UNIMP_FLUSH 0x25 36 #define TT_DATA_ACCESS 0x29 37 #define TT_DIV_ZERO 0x2a 38 #define TT_NCP_INSN 0x24 39 #define TT_TRAP 0x80 40 #else 41 #define TT_POWER_ON_RESET 0x01 42 #define TT_TFAULT 0x08 43 #define TT_CODE_ACCESS 0x0a 44 #define TT_ILL_INSN 0x10 45 #define TT_UNIMP_FLUSH TT_ILL_INSN 46 #define TT_PRIV_INSN 0x11 47 #define TT_NFPU_INSN 0x20 48 #define TT_FP_EXCP 0x21 49 #define TT_TOVF 0x23 50 #define TT_CLRWIN 0x24 51 #define TT_DIV_ZERO 0x28 52 #define TT_DFAULT 0x30 53 #define TT_DATA_ACCESS 0x32 54 #define TT_UNALIGNED 0x34 55 #define TT_PRIV_ACT 0x37 56 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 57 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 58 #define TT_EXTINT 0x40 59 #define TT_IVEC 0x60 60 #define TT_TMISS 0x64 61 #define TT_DMISS 0x68 62 #define TT_DPROT 0x6c 63 #define TT_SPILL 0x80 64 #define TT_FILL 0xc0 65 #define TT_WOTHER (1 << 5) 66 #define TT_TRAP 0x100 67 #define TT_HTRAP 0x180 68 #endif 69 70 #define PSR_NEG_SHIFT 23 71 #define PSR_NEG (1 << PSR_NEG_SHIFT) 72 #define PSR_ZERO_SHIFT 22 73 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 74 #define PSR_OVF_SHIFT 21 75 #define PSR_OVF (1 << PSR_OVF_SHIFT) 76 #define PSR_CARRY_SHIFT 20 77 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 78 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 79 #if !defined(TARGET_SPARC64) 80 #define PSR_EF (1<<12) 81 #define PSR_PIL 0xf00 82 #define PSR_S (1<<7) 83 #define PSR_PS (1<<6) 84 #define PSR_ET (1<<5) 85 #define PSR_CWP 0x1f 86 #endif 87 88 #define CC_SRC (env->cc_src) 89 #define CC_SRC2 (env->cc_src2) 90 #define CC_DST (env->cc_dst) 91 #define CC_OP (env->cc_op) 92 93 /* Even though lazy evaluation of CPU condition codes tends to be less 94 * important on RISC systems where condition codes are only updated 95 * when explicitly requested, SPARC uses it to update 32-bit and 64-bit 96 * condition codes. 97 */ 98 enum { 99 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 100 CC_OP_FLAGS, /* all cc are back in status register */ 101 CC_OP_DIV, /* modify N, Z and V, C = 0*/ 102 CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 103 CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 104 CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 105 CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ 106 CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 107 CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 108 CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 109 CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ 110 CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */ 111 CC_OP_NB, 112 }; 113 114 /* Trap base register */ 115 #define TBR_BASE_MASK 0xfffff000 116 117 #if defined(TARGET_SPARC64) 118 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 119 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 120 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 121 #define PS_CLE (1<<9) /* UA2007 */ 122 #define PS_TLE (1<<8) /* UA2007 */ 123 #define PS_RMO (1<<7) 124 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 125 #define PS_PEF (1<<4) /* enable fpu */ 126 #define PS_AM (1<<3) /* address mask */ 127 #define PS_PRIV (1<<2) 128 #define PS_IE (1<<1) 129 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 130 131 #define FPRS_FEF (1<<2) 132 133 #define HS_PRIV (1<<2) 134 #endif 135 136 /* Fcc */ 137 #define FSR_RD1 (1ULL << 31) 138 #define FSR_RD0 (1ULL << 30) 139 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 140 #define FSR_RD_NEAREST 0 141 #define FSR_RD_ZERO FSR_RD0 142 #define FSR_RD_POS FSR_RD1 143 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 144 145 #define FSR_NVM (1ULL << 27) 146 #define FSR_OFM (1ULL << 26) 147 #define FSR_UFM (1ULL << 25) 148 #define FSR_DZM (1ULL << 24) 149 #define FSR_NXM (1ULL << 23) 150 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 151 152 #define FSR_NVA (1ULL << 9) 153 #define FSR_OFA (1ULL << 8) 154 #define FSR_UFA (1ULL << 7) 155 #define FSR_DZA (1ULL << 6) 156 #define FSR_NXA (1ULL << 5) 157 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 158 159 #define FSR_NVC (1ULL << 4) 160 #define FSR_OFC (1ULL << 3) 161 #define FSR_UFC (1ULL << 2) 162 #define FSR_DZC (1ULL << 1) 163 #define FSR_NXC (1ULL << 0) 164 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 165 166 #define FSR_FTT2 (1ULL << 16) 167 #define FSR_FTT1 (1ULL << 15) 168 #define FSR_FTT0 (1ULL << 14) 169 //gcc warns about constant overflow for ~FSR_FTT_MASK 170 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 171 #ifdef TARGET_SPARC64 172 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL 173 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL 174 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL 175 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL 176 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL 177 #else 178 #define FSR_FTT_NMASK 0xfffe3fffULL 179 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL 180 #define FSR_LDFSR_OLDMASK 0x000fc000ULL 181 #endif 182 #define FSR_LDFSR_MASK 0xcfc00fffULL 183 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 184 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 185 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 186 #define FSR_FTT_INVAL_FPR (6ULL << 14) 187 188 #define FSR_FCC1_SHIFT 11 189 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) 190 #define FSR_FCC0_SHIFT 10 191 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) 192 193 /* MMU */ 194 #define MMU_E (1<<0) 195 #define MMU_NF (1<<1) 196 197 #define PTE_ENTRYTYPE_MASK 3 198 #define PTE_ACCESS_MASK 0x1c 199 #define PTE_ACCESS_SHIFT 2 200 #define PTE_PPN_SHIFT 7 201 #define PTE_ADDR_MASK 0xffffff00 202 203 #define PG_ACCESSED_BIT 5 204 #define PG_MODIFIED_BIT 6 205 #define PG_CACHE_BIT 7 206 207 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 208 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 209 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 210 211 /* 3 <= NWINDOWS <= 32. */ 212 #define MIN_NWINDOWS 3 213 #define MAX_NWINDOWS 32 214 215 #ifdef TARGET_SPARC64 216 typedef struct trap_state { 217 uint64_t tpc; 218 uint64_t tnpc; 219 uint64_t tstate; 220 uint32_t tt; 221 } trap_state; 222 #endif 223 #define TARGET_INSN_START_EXTRA_WORDS 1 224 225 struct sparc_def_t { 226 const char *name; 227 target_ulong iu_version; 228 uint32_t fpu_version; 229 uint32_t mmu_version; 230 uint32_t mmu_bm; 231 uint32_t mmu_ctpr_mask; 232 uint32_t mmu_cxr_mask; 233 uint32_t mmu_sfsr_mask; 234 uint32_t mmu_trcr_mask; 235 uint32_t mxcc_version; 236 uint32_t features; 237 uint32_t nwindows; 238 uint32_t maxtl; 239 }; 240 241 #define CPU_FEATURE_FLOAT (1 << 0) 242 #define CPU_FEATURE_FLOAT128 (1 << 1) 243 #define CPU_FEATURE_SWAP (1 << 2) 244 #define CPU_FEATURE_MUL (1 << 3) 245 #define CPU_FEATURE_DIV (1 << 4) 246 #define CPU_FEATURE_FLUSH (1 << 5) 247 #define CPU_FEATURE_FSQRT (1 << 6) 248 #define CPU_FEATURE_FMUL (1 << 7) 249 #define CPU_FEATURE_VIS1 (1 << 8) 250 #define CPU_FEATURE_VIS2 (1 << 9) 251 #define CPU_FEATURE_FSMULD (1 << 10) 252 #define CPU_FEATURE_HYPV (1 << 11) 253 #define CPU_FEATURE_CMT (1 << 12) 254 #define CPU_FEATURE_GL (1 << 13) 255 #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ 256 #define CPU_FEATURE_ASR17 (1 << 15) 257 #define CPU_FEATURE_CACHE_CTRL (1 << 16) 258 #define CPU_FEATURE_POWERDOWN (1 << 17) 259 #define CPU_FEATURE_CASA (1 << 18) 260 261 #ifndef TARGET_SPARC64 262 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ 263 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 264 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ 265 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) 266 #else 267 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ 268 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 269 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ 270 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ 271 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ 272 CPU_FEATURE_CASA) 273 enum { 274 mmu_us_12, // Ultrasparc < III (64 entry TLB) 275 mmu_us_3, // Ultrasparc III (512 entry TLB) 276 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 277 mmu_sun4v, // T1, T2 278 }; 279 #endif 280 281 #define TTE_VALID_BIT (1ULL << 63) 282 #define TTE_NFO_BIT (1ULL << 60) 283 #define TTE_USED_BIT (1ULL << 41) 284 #define TTE_LOCKED_BIT (1ULL << 6) 285 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 286 #define TTE_PRIV_BIT (1ULL << 2) 287 #define TTE_W_OK_BIT (1ULL << 1) 288 #define TTE_GLOBAL_BIT (1ULL << 0) 289 290 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 291 #define TTE_USED_BIT_UA2005 (1ULL << 47) 292 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 293 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 294 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 295 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 296 297 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 298 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 299 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 300 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 301 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 302 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 303 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 304 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 305 306 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 307 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 308 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 309 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 310 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 311 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 312 313 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 314 315 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 316 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 317 318 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 319 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 320 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 321 322 /* UltraSPARC T1 specific */ 323 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 324 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 325 326 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 327 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 328 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 329 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 330 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 331 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 332 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 333 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 334 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 335 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 336 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 337 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 338 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 339 340 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 341 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 342 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 343 #define SFSR_CT_SECONDARY (1ULL << 4) 344 #define SFSR_CT_NUCLEUS (2ULL << 4) 345 #define SFSR_CT_NOTRANS (3ULL << 4) 346 #define SFSR_CT_MASK (3ULL << 4) 347 348 /* Leon3 cache control */ 349 350 /* Cache control: emulate the behavior of cache control registers but without 351 any effect on the emulated */ 352 353 #define CACHE_STATE_MASK 0x3 354 #define CACHE_DISABLED 0x0 355 #define CACHE_FROZEN 0x1 356 #define CACHE_ENABLED 0x3 357 358 /* Cache Control register fields */ 359 360 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 361 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 362 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 363 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 364 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 365 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 366 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 367 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 368 369 #define CONVERT_BIT(X, SRC, DST) \ 370 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 371 372 typedef struct SparcTLBEntry { 373 uint64_t tag; 374 uint64_t tte; 375 } SparcTLBEntry; 376 377 struct CPUTimer 378 { 379 const char *name; 380 uint32_t frequency; 381 uint32_t disabled; 382 uint64_t disabled_mask; 383 uint32_t npt; 384 uint64_t npt_mask; 385 int64_t clock_offset; 386 QEMUTimer *qtimer; 387 }; 388 389 typedef struct CPUTimer CPUTimer; 390 391 typedef struct CPUSPARCState CPUSPARCState; 392 #if defined(TARGET_SPARC64) 393 typedef union { 394 uint64_t mmuregs[16]; 395 struct { 396 uint64_t tsb_tag_target; 397 uint64_t mmu_primary_context; 398 uint64_t mmu_secondary_context; 399 uint64_t sfsr; 400 uint64_t sfar; 401 uint64_t tsb; 402 uint64_t tag_access; 403 uint64_t virtual_watchpoint; 404 uint64_t physical_watchpoint; 405 uint64_t sun4v_ctx_config[2]; 406 uint64_t sun4v_tsb_pointers[4]; 407 }; 408 } SparcV9MMU; 409 #endif 410 struct CPUSPARCState { 411 target_ulong gregs[8]; /* general registers */ 412 target_ulong *regwptr; /* pointer to current register window */ 413 target_ulong pc; /* program counter */ 414 target_ulong npc; /* next program counter */ 415 target_ulong y; /* multiply/divide register */ 416 417 /* emulator internal flags handling */ 418 target_ulong cc_src, cc_src2; 419 target_ulong cc_dst; 420 uint32_t cc_op; 421 422 target_ulong cond; /* conditional branch result (XXX: save it in a 423 temporary register when possible) */ 424 425 uint32_t psr; /* processor state register */ 426 target_ulong fsr; /* FPU state register */ 427 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 428 uint32_t cwp; /* index of current register window (extracted 429 from PSR) */ 430 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 431 uint32_t wim; /* window invalid mask */ 432 #endif 433 target_ulong tbr; /* trap base register */ 434 #if !defined(TARGET_SPARC64) 435 int psrs; /* supervisor mode (extracted from PSR) */ 436 int psrps; /* previous supervisor mode */ 437 int psret; /* enable traps */ 438 #endif 439 uint32_t psrpil; /* interrupt blocking level */ 440 uint32_t pil_in; /* incoming interrupt level bitmap */ 441 #if !defined(TARGET_SPARC64) 442 int psref; /* enable fpu */ 443 #endif 444 int interrupt_index; 445 /* NOTE: we allow 8 more registers to handle wrapping */ 446 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 447 448 /* Fields up to this point are cleared by a CPU reset */ 449 struct {} end_reset_fields; 450 451 CPU_COMMON 452 453 /* Fields from here on are preserved across CPU reset. */ 454 target_ulong version; 455 uint32_t nwindows; 456 457 /* MMU regs */ 458 #if defined(TARGET_SPARC64) 459 uint64_t lsu; 460 #define DMMU_E 0x8 461 #define IMMU_E 0x4 462 SparcV9MMU immu; 463 SparcV9MMU dmmu; 464 SparcTLBEntry itlb[64]; 465 SparcTLBEntry dtlb[64]; 466 uint32_t mmu_version; 467 #else 468 uint32_t mmuregs[32]; 469 uint64_t mxccdata[4]; 470 uint64_t mxccregs[8]; 471 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 472 uint64_t mmubpaction; 473 uint64_t mmubpregs[4]; 474 uint64_t prom_addr; 475 #endif 476 /* temporary float registers */ 477 float128 qt0, qt1; 478 float_status fp_status; 479 #if defined(TARGET_SPARC64) 480 #define MAXTL_MAX 8 481 #define MAXTL_MASK (MAXTL_MAX - 1) 482 trap_state ts[MAXTL_MAX]; 483 uint32_t xcc; /* Extended integer condition codes */ 484 uint32_t asi; 485 uint32_t pstate; 486 uint32_t tl; 487 uint32_t maxtl; 488 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 489 uint64_t agregs[8]; /* alternate general registers */ 490 uint64_t bgregs[8]; /* backup for normal global registers */ 491 uint64_t igregs[8]; /* interrupt general registers */ 492 uint64_t mgregs[8]; /* mmu general registers */ 493 uint64_t glregs[8 * MAXTL_MAX]; 494 uint64_t fprs; 495 uint64_t tick_cmpr, stick_cmpr; 496 CPUTimer *tick, *stick; 497 #define TICK_NPT_MASK 0x8000000000000000ULL 498 #define TICK_INT_DIS 0x8000000000000000ULL 499 uint64_t gsr; 500 uint32_t gl; // UA2005 501 /* UA 2005 hyperprivileged registers */ 502 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 503 uint64_t scratch[8]; 504 CPUTimer *hstick; // UA 2005 505 /* Interrupt vector registers */ 506 uint64_t ivec_status; 507 uint64_t ivec_data[3]; 508 uint32_t softint; 509 #define SOFTINT_TIMER 1 510 #define SOFTINT_STIMER (1 << 16) 511 #define SOFTINT_INTRMASK (0xFFFE) 512 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 513 #endif 514 sparc_def_t def; 515 516 void *irq_manager; 517 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); 518 519 /* Leon3 cache control */ 520 uint32_t cache_control; 521 }; 522 523 /** 524 * SPARCCPU: 525 * @env: #CPUSPARCState 526 * 527 * A SPARC CPU. 528 */ 529 struct SPARCCPU { 530 /*< private >*/ 531 CPUState parent_obj; 532 /*< public >*/ 533 534 CPUSPARCState env; 535 }; 536 537 static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) 538 { 539 return container_of(env, SPARCCPU, env); 540 } 541 542 #define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) 543 544 #define ENV_OFFSET offsetof(SPARCCPU, env) 545 546 #ifndef CONFIG_USER_ONLY 547 extern const struct VMStateDescription vmstate_sparc_cpu; 548 #endif 549 550 void sparc_cpu_do_interrupt(CPUState *cpu); 551 void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 552 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 553 int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 554 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 555 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 556 MMUAccessType access_type, 557 int mmu_idx, 558 uintptr_t retaddr); 559 void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; 560 561 #ifndef NO_CPU_IO_DEFS 562 /* cpu_init.c */ 563 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 564 void sparc_cpu_list(void); 565 /* mmu_helper.c */ 566 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 567 MMUAccessType access_type, int mmu_idx, 568 bool probe, uintptr_t retaddr); 569 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 570 void dump_mmu(CPUSPARCState *env); 571 572 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 573 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 574 uint8_t *buf, int len, bool is_write); 575 #endif 576 577 578 /* translate.c */ 579 void sparc_tcg_init(void); 580 581 /* cpu-exec.c */ 582 583 /* win_helper.c */ 584 target_ulong cpu_get_psr(CPUSPARCState *env1); 585 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 586 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 587 #ifdef TARGET_SPARC64 588 target_ulong cpu_get_ccr(CPUSPARCState *env1); 589 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 590 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 591 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 592 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 593 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 594 #endif 595 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 596 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 597 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 598 599 /* int_helper.c */ 600 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); 601 602 /* sun4m.c, sun4u.c */ 603 void cpu_check_irqs(CPUSPARCState *env); 604 605 /* leon3.c */ 606 void leon3_irq_ack(void *irq_manager, int intno); 607 608 #if defined (TARGET_SPARC64) 609 610 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 611 { 612 return (x & mask) == (y & mask); 613 } 614 615 #define MMU_CONTEXT_BITS 13 616 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 617 618 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 619 uint64_t context) 620 { 621 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 622 } 623 624 #endif 625 #endif 626 627 /* cpu-exec.c */ 628 #if !defined(CONFIG_USER_ONLY) 629 void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr, 630 bool is_write, bool is_exec, int is_asi, 631 unsigned size); 632 #if defined(TARGET_SPARC64) 633 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 634 int mmu_idx); 635 #endif 636 #endif 637 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); 638 639 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU 640 #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX 641 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 642 643 #define cpu_signal_handler cpu_sparc_signal_handler 644 #define cpu_list sparc_cpu_list 645 646 /* MMU modes definitions */ 647 #if defined (TARGET_SPARC64) 648 #define MMU_USER_IDX 0 649 #define MMU_USER_SECONDARY_IDX 1 650 #define MMU_KERNEL_IDX 2 651 #define MMU_KERNEL_SECONDARY_IDX 3 652 #define MMU_NUCLEUS_IDX 4 653 #define MMU_PHYS_IDX 5 654 #else 655 #define MMU_USER_IDX 0 656 #define MMU_KERNEL_IDX 1 657 #define MMU_PHYS_IDX 2 658 #endif 659 660 #if defined (TARGET_SPARC64) 661 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 662 { 663 return env1->def.features & CPU_FEATURE_HYPV; 664 } 665 666 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 667 { 668 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 669 } 670 671 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 672 { 673 return env1->pstate & PS_PRIV; 674 } 675 #else 676 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 677 { 678 return env1->psrs; 679 } 680 #endif 681 682 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) 683 { 684 #if defined(CONFIG_USER_ONLY) 685 return MMU_USER_IDX; 686 #elif !defined(TARGET_SPARC64) 687 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ 688 return MMU_PHYS_IDX; 689 } else { 690 return env->psrs; 691 } 692 #else 693 /* IMMU or DMMU disabled. */ 694 if (ifetch 695 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 696 : (env->lsu & DMMU_E) == 0) { 697 return MMU_PHYS_IDX; 698 } else if (cpu_hypervisor_mode(env)) { 699 return MMU_PHYS_IDX; 700 } else if (env->tl > 0) { 701 return MMU_NUCLEUS_IDX; 702 } else if (cpu_supervisor_mode(env)) { 703 return MMU_KERNEL_IDX; 704 } else { 705 return MMU_USER_IDX; 706 } 707 #endif 708 } 709 710 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 711 { 712 #if !defined (TARGET_SPARC64) 713 if (env1->psret != 0) 714 return 1; 715 #else 716 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 717 return 1; 718 } 719 #endif 720 721 return 0; 722 } 723 724 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 725 { 726 #if !defined(TARGET_SPARC64) 727 /* level 15 is non-maskable on sparc v8 */ 728 return pil == 15 || pil > env1->psrpil; 729 #else 730 return pil > env1->psrpil; 731 #endif 732 } 733 734 #include "exec/cpu-all.h" 735 736 #ifdef TARGET_SPARC64 737 /* sun4u.c */ 738 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 739 uint64_t cpu_tick_get_count(CPUTimer *timer); 740 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 741 trap_state* cpu_tsptr(CPUSPARCState* env); 742 #endif 743 744 #define TB_FLAG_MMU_MASK 7 745 #define TB_FLAG_FPU_ENABLED (1 << 4) 746 #define TB_FLAG_AM_ENABLED (1 << 5) 747 #define TB_FLAG_SUPER (1 << 6) 748 #define TB_FLAG_HYPER (1 << 7) 749 #define TB_FLAG_ASI_SHIFT 24 750 751 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, 752 target_ulong *cs_base, uint32_t *pflags) 753 { 754 uint32_t flags; 755 *pc = env->pc; 756 *cs_base = env->npc; 757 flags = cpu_mmu_index(env, false); 758 #ifndef CONFIG_USER_ONLY 759 if (cpu_supervisor_mode(env)) { 760 flags |= TB_FLAG_SUPER; 761 } 762 #endif 763 #ifdef TARGET_SPARC64 764 #ifndef CONFIG_USER_ONLY 765 if (cpu_hypervisor_mode(env)) { 766 flags |= TB_FLAG_HYPER; 767 } 768 #endif 769 if (env->pstate & PS_AM) { 770 flags |= TB_FLAG_AM_ENABLED; 771 } 772 if ((env->def.features & CPU_FEATURE_FLOAT) 773 && (env->pstate & PS_PEF) 774 && (env->fprs & FPRS_FEF)) { 775 flags |= TB_FLAG_FPU_ENABLED; 776 } 777 flags |= env->asi << TB_FLAG_ASI_SHIFT; 778 #else 779 if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { 780 flags |= TB_FLAG_FPU_ENABLED; 781 } 782 #endif 783 *pflags = flags; 784 } 785 786 static inline bool tb_fpu_enabled(int tb_flags) 787 { 788 #if defined(CONFIG_USER_ONLY) 789 return true; 790 #else 791 return tb_flags & TB_FLAG_FPU_ENABLED; 792 #endif 793 } 794 795 static inline bool tb_am_enabled(int tb_flags) 796 { 797 #ifndef TARGET_SPARC64 798 return false; 799 #else 800 return tb_flags & TB_FLAG_AM_ENABLED; 801 #endif 802 } 803 804 #endif 805