1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu/bswap.h" 5 #include "cpu-qom.h" 6 #include "exec/cpu-defs.h" 7 8 #if !defined(TARGET_SPARC64) 9 #define TARGET_DPREGS 16 10 #else 11 #define TARGET_DPREGS 32 12 #endif 13 14 /*#define EXCP_INTERRUPT 0x100*/ 15 16 /* trap definitions */ 17 #ifndef TARGET_SPARC64 18 #define TT_TFAULT 0x01 19 #define TT_ILL_INSN 0x02 20 #define TT_PRIV_INSN 0x03 21 #define TT_NFPU_INSN 0x04 22 #define TT_WIN_OVF 0x05 23 #define TT_WIN_UNF 0x06 24 #define TT_UNALIGNED 0x07 25 #define TT_FP_EXCP 0x08 26 #define TT_DFAULT 0x09 27 #define TT_TOVF 0x0a 28 #define TT_EXTINT 0x10 29 #define TT_CODE_ACCESS 0x21 30 #define TT_UNIMP_FLUSH 0x25 31 #define TT_DATA_ACCESS 0x29 32 #define TT_DIV_ZERO 0x2a 33 #define TT_NCP_INSN 0x24 34 #define TT_TRAP 0x80 35 #else 36 #define TT_POWER_ON_RESET 0x01 37 #define TT_TFAULT 0x08 38 #define TT_CODE_ACCESS 0x0a 39 #define TT_ILL_INSN 0x10 40 #define TT_UNIMP_FLUSH TT_ILL_INSN 41 #define TT_PRIV_INSN 0x11 42 #define TT_NFPU_INSN 0x20 43 #define TT_FP_EXCP 0x21 44 #define TT_TOVF 0x23 45 #define TT_CLRWIN 0x24 46 #define TT_DIV_ZERO 0x28 47 #define TT_DFAULT 0x30 48 #define TT_DATA_ACCESS 0x32 49 #define TT_UNALIGNED 0x34 50 #define TT_PRIV_ACT 0x37 51 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 52 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 53 #define TT_EXTINT 0x40 54 #define TT_IVEC 0x60 55 #define TT_TMISS 0x64 56 #define TT_DMISS 0x68 57 #define TT_DPROT 0x6c 58 #define TT_SPILL 0x80 59 #define TT_FILL 0xc0 60 #define TT_WOTHER (1 << 5) 61 #define TT_TRAP 0x100 62 #define TT_HTRAP 0x180 63 #endif 64 65 #define PSR_NEG_SHIFT 23 66 #define PSR_NEG (1 << PSR_NEG_SHIFT) 67 #define PSR_ZERO_SHIFT 22 68 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 69 #define PSR_OVF_SHIFT 21 70 #define PSR_OVF (1 << PSR_OVF_SHIFT) 71 #define PSR_CARRY_SHIFT 20 72 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 73 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 74 #if !defined(TARGET_SPARC64) 75 #define PSR_EF (1<<12) 76 #define PSR_PIL 0xf00 77 #define PSR_S (1<<7) 78 #define PSR_PS (1<<6) 79 #define PSR_ET (1<<5) 80 #define PSR_CWP 0x1f 81 #endif 82 83 #define CC_SRC (env->cc_src) 84 #define CC_SRC2 (env->cc_src2) 85 #define CC_DST (env->cc_dst) 86 #define CC_OP (env->cc_op) 87 88 /* Even though lazy evaluation of CPU condition codes tends to be less 89 * important on RISC systems where condition codes are only updated 90 * when explicitly requested, SPARC uses it to update 32-bit and 64-bit 91 * condition codes. 92 */ 93 enum { 94 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 95 CC_OP_FLAGS, /* all cc are back in status register */ 96 CC_OP_DIV, /* modify N, Z and V, C = 0*/ 97 CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 98 CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 99 CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 100 CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ 101 CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 102 CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 103 CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 104 CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ 105 CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */ 106 CC_OP_NB, 107 }; 108 109 /* Trap base register */ 110 #define TBR_BASE_MASK 0xfffff000 111 112 #if defined(TARGET_SPARC64) 113 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 114 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 115 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 116 #define PS_CLE (1<<9) /* UA2007 */ 117 #define PS_TLE (1<<8) /* UA2007 */ 118 #define PS_RMO (1<<7) 119 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 120 #define PS_PEF (1<<4) /* enable fpu */ 121 #define PS_AM (1<<3) /* address mask */ 122 #define PS_PRIV (1<<2) 123 #define PS_IE (1<<1) 124 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 125 126 #define FPRS_FEF (1<<2) 127 128 #define HS_PRIV (1<<2) 129 #endif 130 131 /* Fcc */ 132 #define FSR_RD1 (1ULL << 31) 133 #define FSR_RD0 (1ULL << 30) 134 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 135 #define FSR_RD_NEAREST 0 136 #define FSR_RD_ZERO FSR_RD0 137 #define FSR_RD_POS FSR_RD1 138 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 139 140 #define FSR_NVM (1ULL << 27) 141 #define FSR_OFM (1ULL << 26) 142 #define FSR_UFM (1ULL << 25) 143 #define FSR_DZM (1ULL << 24) 144 #define FSR_NXM (1ULL << 23) 145 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 146 147 #define FSR_NVA (1ULL << 9) 148 #define FSR_OFA (1ULL << 8) 149 #define FSR_UFA (1ULL << 7) 150 #define FSR_DZA (1ULL << 6) 151 #define FSR_NXA (1ULL << 5) 152 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 153 154 #define FSR_NVC (1ULL << 4) 155 #define FSR_OFC (1ULL << 3) 156 #define FSR_UFC (1ULL << 2) 157 #define FSR_DZC (1ULL << 1) 158 #define FSR_NXC (1ULL << 0) 159 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 160 161 #define FSR_FTT2 (1ULL << 16) 162 #define FSR_FTT1 (1ULL << 15) 163 #define FSR_FTT0 (1ULL << 14) 164 //gcc warns about constant overflow for ~FSR_FTT_MASK 165 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 166 #ifdef TARGET_SPARC64 167 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL 168 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL 169 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL 170 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL 171 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL 172 #else 173 #define FSR_FTT_NMASK 0xfffe3fffULL 174 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL 175 #define FSR_LDFSR_OLDMASK 0x000fc000ULL 176 #endif 177 #define FSR_LDFSR_MASK 0xcfc00fffULL 178 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 179 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 180 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 181 #define FSR_FTT_INVAL_FPR (6ULL << 14) 182 183 #define FSR_FCC1_SHIFT 11 184 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) 185 #define FSR_FCC0_SHIFT 10 186 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) 187 188 /* MMU */ 189 #define MMU_E (1<<0) 190 #define MMU_NF (1<<1) 191 192 #define PTE_ENTRYTYPE_MASK 3 193 #define PTE_ACCESS_MASK 0x1c 194 #define PTE_ACCESS_SHIFT 2 195 #define PTE_PPN_SHIFT 7 196 #define PTE_ADDR_MASK 0xffffff00 197 198 #define PG_ACCESSED_BIT 5 199 #define PG_MODIFIED_BIT 6 200 #define PG_CACHE_BIT 7 201 202 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 203 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 204 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 205 206 /* 3 <= NWINDOWS <= 32. */ 207 #define MIN_NWINDOWS 3 208 #define MAX_NWINDOWS 32 209 210 #ifdef TARGET_SPARC64 211 typedef struct trap_state { 212 uint64_t tpc; 213 uint64_t tnpc; 214 uint64_t tstate; 215 uint32_t tt; 216 } trap_state; 217 #endif 218 #define TARGET_INSN_START_EXTRA_WORDS 1 219 220 struct sparc_def_t { 221 const char *name; 222 target_ulong iu_version; 223 uint32_t fpu_version; 224 uint32_t mmu_version; 225 uint32_t mmu_bm; 226 uint32_t mmu_ctpr_mask; 227 uint32_t mmu_cxr_mask; 228 uint32_t mmu_sfsr_mask; 229 uint32_t mmu_trcr_mask; 230 uint32_t mxcc_version; 231 uint32_t features; 232 uint32_t nwindows; 233 uint32_t maxtl; 234 }; 235 236 #define CPU_FEATURE_FLOAT (1 << 0) 237 #define CPU_FEATURE_FLOAT128 (1 << 1) 238 #define CPU_FEATURE_SWAP (1 << 2) 239 #define CPU_FEATURE_MUL (1 << 3) 240 #define CPU_FEATURE_DIV (1 << 4) 241 #define CPU_FEATURE_FLUSH (1 << 5) 242 #define CPU_FEATURE_FSQRT (1 << 6) 243 #define CPU_FEATURE_FMUL (1 << 7) 244 #define CPU_FEATURE_VIS1 (1 << 8) 245 #define CPU_FEATURE_VIS2 (1 << 9) 246 #define CPU_FEATURE_FSMULD (1 << 10) 247 #define CPU_FEATURE_HYPV (1 << 11) 248 #define CPU_FEATURE_CMT (1 << 12) 249 #define CPU_FEATURE_GL (1 << 13) 250 #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ 251 #define CPU_FEATURE_ASR17 (1 << 15) 252 #define CPU_FEATURE_CACHE_CTRL (1 << 16) 253 #define CPU_FEATURE_POWERDOWN (1 << 17) 254 #define CPU_FEATURE_CASA (1 << 18) 255 256 #ifndef TARGET_SPARC64 257 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ 258 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 259 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ 260 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) 261 #else 262 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ 263 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 264 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ 265 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ 266 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ 267 CPU_FEATURE_CASA) 268 enum { 269 mmu_us_12, // Ultrasparc < III (64 entry TLB) 270 mmu_us_3, // Ultrasparc III (512 entry TLB) 271 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 272 mmu_sun4v, // T1, T2 273 }; 274 #endif 275 276 #define TTE_VALID_BIT (1ULL << 63) 277 #define TTE_NFO_BIT (1ULL << 60) 278 #define TTE_USED_BIT (1ULL << 41) 279 #define TTE_LOCKED_BIT (1ULL << 6) 280 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 281 #define TTE_PRIV_BIT (1ULL << 2) 282 #define TTE_W_OK_BIT (1ULL << 1) 283 #define TTE_GLOBAL_BIT (1ULL << 0) 284 285 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 286 #define TTE_USED_BIT_UA2005 (1ULL << 47) 287 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 288 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 289 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 290 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 291 292 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 293 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 294 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 295 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 296 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 297 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 298 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 299 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 300 301 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 302 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 303 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 304 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 305 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 306 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 307 308 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 309 310 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 311 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 312 313 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 314 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 315 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 316 317 /* UltraSPARC T1 specific */ 318 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 319 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 320 321 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 322 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 323 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 324 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 325 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 326 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 327 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 328 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 329 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 330 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 331 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 332 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 333 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 334 335 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 336 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 337 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 338 #define SFSR_CT_SECONDARY (1ULL << 4) 339 #define SFSR_CT_NUCLEUS (2ULL << 4) 340 #define SFSR_CT_NOTRANS (3ULL << 4) 341 #define SFSR_CT_MASK (3ULL << 4) 342 343 /* Leon3 cache control */ 344 345 /* Cache control: emulate the behavior of cache control registers but without 346 any effect on the emulated */ 347 348 #define CACHE_STATE_MASK 0x3 349 #define CACHE_DISABLED 0x0 350 #define CACHE_FROZEN 0x1 351 #define CACHE_ENABLED 0x3 352 353 /* Cache Control register fields */ 354 355 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 356 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 357 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 358 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 359 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 360 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 361 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 362 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 363 364 #define CONVERT_BIT(X, SRC, DST) \ 365 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 366 367 typedef struct SparcTLBEntry { 368 uint64_t tag; 369 uint64_t tte; 370 } SparcTLBEntry; 371 372 struct CPUTimer 373 { 374 const char *name; 375 uint32_t frequency; 376 uint32_t disabled; 377 uint64_t disabled_mask; 378 uint32_t npt; 379 uint64_t npt_mask; 380 int64_t clock_offset; 381 QEMUTimer *qtimer; 382 }; 383 384 typedef struct CPUTimer CPUTimer; 385 386 typedef struct CPUSPARCState CPUSPARCState; 387 #if defined(TARGET_SPARC64) 388 typedef union { 389 uint64_t mmuregs[16]; 390 struct { 391 uint64_t tsb_tag_target; 392 uint64_t mmu_primary_context; 393 uint64_t mmu_secondary_context; 394 uint64_t sfsr; 395 uint64_t sfar; 396 uint64_t tsb; 397 uint64_t tag_access; 398 uint64_t virtual_watchpoint; 399 uint64_t physical_watchpoint; 400 uint64_t sun4v_ctx_config[2]; 401 uint64_t sun4v_tsb_pointers[4]; 402 }; 403 } SparcV9MMU; 404 #endif 405 struct CPUSPARCState { 406 target_ulong gregs[8]; /* general registers */ 407 target_ulong *regwptr; /* pointer to current register window */ 408 target_ulong pc; /* program counter */ 409 target_ulong npc; /* next program counter */ 410 target_ulong y; /* multiply/divide register */ 411 412 /* emulator internal flags handling */ 413 target_ulong cc_src, cc_src2; 414 target_ulong cc_dst; 415 uint32_t cc_op; 416 417 target_ulong cond; /* conditional branch result (XXX: save it in a 418 temporary register when possible) */ 419 420 uint32_t psr; /* processor state register */ 421 target_ulong fsr; /* FPU state register */ 422 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 423 uint32_t cwp; /* index of current register window (extracted 424 from PSR) */ 425 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 426 uint32_t wim; /* window invalid mask */ 427 #endif 428 target_ulong tbr; /* trap base register */ 429 #if !defined(TARGET_SPARC64) 430 int psrs; /* supervisor mode (extracted from PSR) */ 431 int psrps; /* previous supervisor mode */ 432 int psret; /* enable traps */ 433 #endif 434 uint32_t psrpil; /* interrupt blocking level */ 435 uint32_t pil_in; /* incoming interrupt level bitmap */ 436 #if !defined(TARGET_SPARC64) 437 int psref; /* enable fpu */ 438 #endif 439 int interrupt_index; 440 /* NOTE: we allow 8 more registers to handle wrapping */ 441 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 442 443 /* Fields up to this point are cleared by a CPU reset */ 444 struct {} end_reset_fields; 445 446 /* Fields from here on are preserved across CPU reset. */ 447 target_ulong version; 448 uint32_t nwindows; 449 450 /* MMU regs */ 451 #if defined(TARGET_SPARC64) 452 uint64_t lsu; 453 #define DMMU_E 0x8 454 #define IMMU_E 0x4 455 SparcV9MMU immu; 456 SparcV9MMU dmmu; 457 SparcTLBEntry itlb[64]; 458 SparcTLBEntry dtlb[64]; 459 uint32_t mmu_version; 460 #else 461 uint32_t mmuregs[32]; 462 uint64_t mxccdata[4]; 463 uint64_t mxccregs[8]; 464 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 465 uint64_t mmubpaction; 466 uint64_t mmubpregs[4]; 467 uint64_t prom_addr; 468 #endif 469 /* temporary float registers */ 470 float128 qt0, qt1; 471 float_status fp_status; 472 #if defined(TARGET_SPARC64) 473 #define MAXTL_MAX 8 474 #define MAXTL_MASK (MAXTL_MAX - 1) 475 trap_state ts[MAXTL_MAX]; 476 uint32_t xcc; /* Extended integer condition codes */ 477 uint32_t asi; 478 uint32_t pstate; 479 uint32_t tl; 480 uint32_t maxtl; 481 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 482 uint64_t agregs[8]; /* alternate general registers */ 483 uint64_t bgregs[8]; /* backup for normal global registers */ 484 uint64_t igregs[8]; /* interrupt general registers */ 485 uint64_t mgregs[8]; /* mmu general registers */ 486 uint64_t glregs[8 * MAXTL_MAX]; 487 uint64_t fprs; 488 uint64_t tick_cmpr, stick_cmpr; 489 CPUTimer *tick, *stick; 490 #define TICK_NPT_MASK 0x8000000000000000ULL 491 #define TICK_INT_DIS 0x8000000000000000ULL 492 uint64_t gsr; 493 uint32_t gl; // UA2005 494 /* UA 2005 hyperprivileged registers */ 495 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 496 uint64_t scratch[8]; 497 CPUTimer *hstick; // UA 2005 498 /* Interrupt vector registers */ 499 uint64_t ivec_status; 500 uint64_t ivec_data[3]; 501 uint32_t softint; 502 #define SOFTINT_TIMER 1 503 #define SOFTINT_STIMER (1 << 16) 504 #define SOFTINT_INTRMASK (0xFFFE) 505 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 506 #endif 507 sparc_def_t def; 508 509 void *irq_manager; 510 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); 511 512 /* Leon3 cache control */ 513 uint32_t cache_control; 514 }; 515 516 /** 517 * SPARCCPU: 518 * @env: #CPUSPARCState 519 * 520 * A SPARC CPU. 521 */ 522 struct SPARCCPU { 523 /*< private >*/ 524 CPUState parent_obj; 525 /*< public >*/ 526 527 CPUNegativeOffsetState neg; 528 CPUSPARCState env; 529 }; 530 531 532 #ifndef CONFIG_USER_ONLY 533 extern const VMStateDescription vmstate_sparc_cpu; 534 #endif 535 536 void sparc_cpu_do_interrupt(CPUState *cpu); 537 void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 538 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 539 int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 540 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 541 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 542 MMUAccessType access_type, 543 int mmu_idx, 544 uintptr_t retaddr); 545 void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; 546 547 #ifndef NO_CPU_IO_DEFS 548 /* cpu_init.c */ 549 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 550 void sparc_cpu_list(void); 551 /* mmu_helper.c */ 552 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 553 MMUAccessType access_type, int mmu_idx, 554 bool probe, uintptr_t retaddr); 555 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 556 void dump_mmu(CPUSPARCState *env); 557 558 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 559 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 560 uint8_t *buf, int len, bool is_write); 561 #endif 562 563 564 /* translate.c */ 565 void sparc_tcg_init(void); 566 567 /* cpu-exec.c */ 568 569 /* win_helper.c */ 570 target_ulong cpu_get_psr(CPUSPARCState *env1); 571 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 572 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 573 #ifdef TARGET_SPARC64 574 target_ulong cpu_get_ccr(CPUSPARCState *env1); 575 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 576 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 577 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 578 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 579 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 580 #endif 581 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 582 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 583 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 584 585 /* int_helper.c */ 586 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); 587 588 /* sun4m.c, sun4u.c */ 589 void cpu_check_irqs(CPUSPARCState *env); 590 591 /* leon3.c */ 592 void leon3_irq_ack(void *irq_manager, int intno); 593 594 #if defined (TARGET_SPARC64) 595 596 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 597 { 598 return (x & mask) == (y & mask); 599 } 600 601 #define MMU_CONTEXT_BITS 13 602 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 603 604 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 605 uint64_t context) 606 { 607 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 608 } 609 610 #endif 611 #endif 612 613 /* cpu-exec.c */ 614 #if !defined(CONFIG_USER_ONLY) 615 void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr, 616 bool is_write, bool is_exec, int is_asi, 617 unsigned size); 618 #if defined(TARGET_SPARC64) 619 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 620 int mmu_idx); 621 #endif 622 #endif 623 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); 624 625 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU 626 #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX 627 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 628 629 #define cpu_signal_handler cpu_sparc_signal_handler 630 #define cpu_list sparc_cpu_list 631 632 /* MMU modes definitions */ 633 #if defined (TARGET_SPARC64) 634 #define MMU_USER_IDX 0 635 #define MMU_USER_SECONDARY_IDX 1 636 #define MMU_KERNEL_IDX 2 637 #define MMU_KERNEL_SECONDARY_IDX 3 638 #define MMU_NUCLEUS_IDX 4 639 #define MMU_PHYS_IDX 5 640 #else 641 #define MMU_USER_IDX 0 642 #define MMU_KERNEL_IDX 1 643 #define MMU_PHYS_IDX 2 644 #endif 645 646 #if defined (TARGET_SPARC64) 647 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 648 { 649 return env1->def.features & CPU_FEATURE_HYPV; 650 } 651 652 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 653 { 654 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 655 } 656 657 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 658 { 659 return env1->pstate & PS_PRIV; 660 } 661 #else 662 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 663 { 664 return env1->psrs; 665 } 666 #endif 667 668 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) 669 { 670 #if defined(CONFIG_USER_ONLY) 671 return MMU_USER_IDX; 672 #elif !defined(TARGET_SPARC64) 673 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ 674 return MMU_PHYS_IDX; 675 } else { 676 return env->psrs; 677 } 678 #else 679 /* IMMU or DMMU disabled. */ 680 if (ifetch 681 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 682 : (env->lsu & DMMU_E) == 0) { 683 return MMU_PHYS_IDX; 684 } else if (cpu_hypervisor_mode(env)) { 685 return MMU_PHYS_IDX; 686 } else if (env->tl > 0) { 687 return MMU_NUCLEUS_IDX; 688 } else if (cpu_supervisor_mode(env)) { 689 return MMU_KERNEL_IDX; 690 } else { 691 return MMU_USER_IDX; 692 } 693 #endif 694 } 695 696 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 697 { 698 #if !defined (TARGET_SPARC64) 699 if (env1->psret != 0) 700 return 1; 701 #else 702 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 703 return 1; 704 } 705 #endif 706 707 return 0; 708 } 709 710 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 711 { 712 #if !defined(TARGET_SPARC64) 713 /* level 15 is non-maskable on sparc v8 */ 714 return pil == 15 || pil > env1->psrpil; 715 #else 716 return pil > env1->psrpil; 717 #endif 718 } 719 720 typedef CPUSPARCState CPUArchState; 721 typedef SPARCCPU ArchCPU; 722 723 #include "exec/cpu-all.h" 724 725 #ifdef TARGET_SPARC64 726 /* sun4u.c */ 727 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 728 uint64_t cpu_tick_get_count(CPUTimer *timer); 729 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 730 trap_state* cpu_tsptr(CPUSPARCState* env); 731 #endif 732 733 #define TB_FLAG_MMU_MASK 7 734 #define TB_FLAG_FPU_ENABLED (1 << 4) 735 #define TB_FLAG_AM_ENABLED (1 << 5) 736 #define TB_FLAG_SUPER (1 << 6) 737 #define TB_FLAG_HYPER (1 << 7) 738 #define TB_FLAG_ASI_SHIFT 24 739 740 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, 741 target_ulong *cs_base, uint32_t *pflags) 742 { 743 uint32_t flags; 744 *pc = env->pc; 745 *cs_base = env->npc; 746 flags = cpu_mmu_index(env, false); 747 #ifndef CONFIG_USER_ONLY 748 if (cpu_supervisor_mode(env)) { 749 flags |= TB_FLAG_SUPER; 750 } 751 #endif 752 #ifdef TARGET_SPARC64 753 #ifndef CONFIG_USER_ONLY 754 if (cpu_hypervisor_mode(env)) { 755 flags |= TB_FLAG_HYPER; 756 } 757 #endif 758 if (env->pstate & PS_AM) { 759 flags |= TB_FLAG_AM_ENABLED; 760 } 761 if ((env->def.features & CPU_FEATURE_FLOAT) 762 && (env->pstate & PS_PEF) 763 && (env->fprs & FPRS_FEF)) { 764 flags |= TB_FLAG_FPU_ENABLED; 765 } 766 flags |= env->asi << TB_FLAG_ASI_SHIFT; 767 #else 768 if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { 769 flags |= TB_FLAG_FPU_ENABLED; 770 } 771 #endif 772 *pflags = flags; 773 } 774 775 static inline bool tb_fpu_enabled(int tb_flags) 776 { 777 #if defined(CONFIG_USER_ONLY) 778 return true; 779 #else 780 return tb_flags & TB_FLAG_FPU_ENABLED; 781 #endif 782 } 783 784 static inline bool tb_am_enabled(int tb_flags) 785 { 786 #ifndef TARGET_SPARC64 787 return false; 788 #else 789 return tb_flags & TB_FLAG_AM_ENABLED; 790 #endif 791 } 792 793 #endif 794