1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu/bswap.h" 5 #include "cpu-qom.h" 6 #include "exec/cpu-defs.h" 7 #include "qemu/cpu-float.h" 8 9 /* 10 * From Oracle SPARC Architecture 2015: 11 * 12 * Compatibility notes: The PSO memory model described in SPARC V8 and 13 * SPARC V9 compatibility architecture specifications was never implemented 14 * in a SPARC V9 implementation and is not included in the Oracle SPARC 15 * Architecture specification. 16 * 17 * The RMO memory model described in the SPARC V9 specification was 18 * implemented in some non-Sun SPARC V9 implementations, but is not 19 * directly supported in Oracle SPARC Architecture 2015 implementations. 20 * 21 * Therefore always use TSO in QEMU. 22 * 23 * D.5 Specification of Partial Store Order (PSO) 24 * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. 25 * 26 * D.6 Specification of Total Store Order (TSO) 27 * ... PSO with the additional requirement that all [stores] are followed 28 * by an implied MEMBAR #StoreStore. 29 */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) 31 32 #if !defined(TARGET_SPARC64) 33 #define TARGET_DPREGS 16 34 #define TARGET_FCCREGS 1 35 #else 36 #define TARGET_DPREGS 32 37 #define TARGET_FCCREGS 4 38 #endif 39 40 /*#define EXCP_INTERRUPT 0x100*/ 41 42 /* Windowed register indexes. */ 43 enum { 44 WREG_O0, 45 WREG_O1, 46 WREG_O2, 47 WREG_O3, 48 WREG_O4, 49 WREG_O5, 50 WREG_O6, 51 WREG_O7, 52 53 WREG_L0, 54 WREG_L1, 55 WREG_L2, 56 WREG_L3, 57 WREG_L4, 58 WREG_L5, 59 WREG_L6, 60 WREG_L7, 61 62 WREG_I0, 63 WREG_I1, 64 WREG_I2, 65 WREG_I3, 66 WREG_I4, 67 WREG_I5, 68 WREG_I6, 69 WREG_I7, 70 71 WREG_SP = WREG_O6, 72 WREG_FP = WREG_I6, 73 }; 74 75 /* trap definitions */ 76 #ifndef TARGET_SPARC64 77 #define TT_TFAULT 0x01 78 #define TT_ILL_INSN 0x02 79 #define TT_PRIV_INSN 0x03 80 #define TT_NFPU_INSN 0x04 81 #define TT_WIN_OVF 0x05 82 #define TT_WIN_UNF 0x06 83 #define TT_UNALIGNED 0x07 84 #define TT_FP_EXCP 0x08 85 #define TT_DFAULT 0x09 86 #define TT_TOVF 0x0a 87 #define TT_EXTINT 0x10 88 #define TT_CODE_ACCESS 0x21 89 #define TT_UNIMP_FLUSH 0x25 90 #define TT_DATA_ACCESS 0x29 91 #define TT_DIV_ZERO 0x2a 92 #define TT_NCP_INSN 0x24 93 #define TT_TRAP 0x80 94 #else 95 #define TT_POWER_ON_RESET 0x01 96 #define TT_TFAULT 0x08 97 #define TT_CODE_ACCESS 0x0a 98 #define TT_ILL_INSN 0x10 99 #define TT_UNIMP_FLUSH TT_ILL_INSN 100 #define TT_PRIV_INSN 0x11 101 #define TT_NFPU_INSN 0x20 102 #define TT_FP_EXCP 0x21 103 #define TT_TOVF 0x23 104 #define TT_CLRWIN 0x24 105 #define TT_DIV_ZERO 0x28 106 #define TT_DFAULT 0x30 107 #define TT_DATA_ACCESS 0x32 108 #define TT_UNALIGNED 0x34 109 #define TT_PRIV_ACT 0x37 110 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 111 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 112 #define TT_EXTINT 0x40 113 #define TT_IVEC 0x60 114 #define TT_TMISS 0x64 115 #define TT_DMISS 0x68 116 #define TT_DPROT 0x6c 117 #define TT_SPILL 0x80 118 #define TT_FILL 0xc0 119 #define TT_WOTHER (1 << 5) 120 #define TT_TRAP 0x100 121 #define TT_HTRAP 0x180 122 #endif 123 124 #define PSR_NEG_SHIFT 23 125 #define PSR_NEG (1 << PSR_NEG_SHIFT) 126 #define PSR_ZERO_SHIFT 22 127 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 128 #define PSR_OVF_SHIFT 21 129 #define PSR_OVF (1 << PSR_OVF_SHIFT) 130 #define PSR_CARRY_SHIFT 20 131 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 132 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 133 #if !defined(TARGET_SPARC64) 134 #define PSR_EF (1<<12) 135 #define PSR_PIL 0xf00 136 #define PSR_S (1<<7) 137 #define PSR_PS (1<<6) 138 #define PSR_ET (1<<5) 139 #define PSR_CWP 0x1f 140 #endif 141 142 /* Trap base register */ 143 #define TBR_BASE_MASK 0xfffff000 144 145 #if defined(TARGET_SPARC64) 146 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 147 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 148 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 149 #define PS_CLE (1<<9) /* UA2007 */ 150 #define PS_TLE (1<<8) /* UA2007 */ 151 #define PS_RMO (1<<7) 152 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 153 #define PS_PEF (1<<4) /* enable fpu */ 154 #define PS_AM (1<<3) /* address mask */ 155 #define PS_PRIV (1<<2) 156 #define PS_IE (1<<1) 157 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 158 159 #define FPRS_DL (1 << 0) 160 #define FPRS_DU (1 << 1) 161 #define FPRS_FEF (1 << 2) 162 163 #define HS_PRIV (1<<2) 164 #endif 165 166 /* Fcc */ 167 #define FSR_RD1 (1ULL << 31) 168 #define FSR_RD0 (1ULL << 30) 169 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 170 #define FSR_RD_NEAREST 0 171 #define FSR_RD_ZERO FSR_RD0 172 #define FSR_RD_POS FSR_RD1 173 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 174 175 #define FSR_NVM (1ULL << 27) 176 #define FSR_OFM (1ULL << 26) 177 #define FSR_UFM (1ULL << 25) 178 #define FSR_DZM (1ULL << 24) 179 #define FSR_NXM (1ULL << 23) 180 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 181 #define FSR_TEM_SHIFT 23 182 183 #define FSR_NVA (1ULL << 9) 184 #define FSR_OFA (1ULL << 8) 185 #define FSR_UFA (1ULL << 7) 186 #define FSR_DZA (1ULL << 6) 187 #define FSR_NXA (1ULL << 5) 188 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 189 #define FSR_AEXC_SHIFT 5 190 191 #define FSR_NVC (1ULL << 4) 192 #define FSR_OFC (1ULL << 3) 193 #define FSR_UFC (1ULL << 2) 194 #define FSR_DZC (1ULL << 1) 195 #define FSR_NXC (1ULL << 0) 196 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 197 198 #define FSR_VER_SHIFT 17 199 #define FSR_VER_MASK (7 << FSR_VER_SHIFT) 200 201 #define FSR_FTT2 (1ULL << 16) 202 #define FSR_FTT1 (1ULL << 15) 203 #define FSR_FTT0 (1ULL << 14) 204 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 205 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 206 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 207 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 208 #define FSR_FTT_INVAL_FPR (6ULL << 14) 209 210 #define FSR_FCC0_SHIFT 10 211 #define FSR_FCC1_SHIFT 32 212 #define FSR_FCC2_SHIFT 34 213 #define FSR_FCC3_SHIFT 36 214 215 /* MMU */ 216 #define MMU_E (1<<0) 217 #define MMU_NF (1<<1) 218 219 #define PTE_ENTRYTYPE_MASK 3 220 #define PTE_ACCESS_MASK 0x1c 221 #define PTE_ACCESS_SHIFT 2 222 #define PTE_PPN_SHIFT 7 223 #define PTE_ADDR_MASK 0xffffff00 224 225 #define PG_ACCESSED_BIT 5 226 #define PG_MODIFIED_BIT 6 227 #define PG_CACHE_BIT 7 228 229 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 230 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 231 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 232 233 /* 3 <= NWINDOWS <= 32. */ 234 #define MIN_NWINDOWS 3 235 #define MAX_NWINDOWS 32 236 237 #ifdef TARGET_SPARC64 238 typedef struct trap_state { 239 uint64_t tpc; 240 uint64_t tnpc; 241 uint64_t tstate; 242 uint32_t tt; 243 } trap_state; 244 #endif 245 #define TARGET_INSN_START_EXTRA_WORDS 1 246 247 typedef struct sparc_def_t { 248 const char *name; 249 target_ulong iu_version; 250 uint32_t fpu_version; 251 uint32_t mmu_version; 252 uint32_t mmu_bm; 253 uint32_t mmu_ctpr_mask; 254 uint32_t mmu_cxr_mask; 255 uint32_t mmu_sfsr_mask; 256 uint32_t mmu_trcr_mask; 257 uint32_t mxcc_version; 258 uint32_t features; 259 uint32_t nwindows; 260 uint32_t maxtl; 261 } sparc_def_t; 262 263 #define FEATURE(X) CPU_FEATURE_BIT_##X, 264 enum { 265 #include "cpu-feature.h.inc" 266 }; 267 268 #undef FEATURE 269 #define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X, 270 271 enum { 272 #include "cpu-feature.h.inc" 273 }; 274 275 #undef FEATURE 276 277 #ifndef TARGET_SPARC64 278 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 279 CPU_FEATURE_FSMULD) 280 #else 281 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 282 CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ 283 CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) 284 enum { 285 mmu_us_12, // Ultrasparc < III (64 entry TLB) 286 mmu_us_3, // Ultrasparc III (512 entry TLB) 287 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 288 mmu_sun4v, // T1, T2 289 }; 290 #endif 291 292 #define TTE_VALID_BIT (1ULL << 63) 293 #define TTE_NFO_BIT (1ULL << 60) 294 #define TTE_IE_BIT (1ULL << 59) 295 #define TTE_USED_BIT (1ULL << 41) 296 #define TTE_LOCKED_BIT (1ULL << 6) 297 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 298 #define TTE_PRIV_BIT (1ULL << 2) 299 #define TTE_W_OK_BIT (1ULL << 1) 300 #define TTE_GLOBAL_BIT (1ULL << 0) 301 302 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 303 #define TTE_USED_BIT_UA2005 (1ULL << 47) 304 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 305 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 306 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 307 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 308 309 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 310 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 311 #define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) 312 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 313 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 314 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 315 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 316 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 317 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 318 319 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 320 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 321 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 322 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 323 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 324 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 325 326 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 327 328 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 329 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 330 331 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 332 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 333 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 334 335 /* UltraSPARC T1 specific */ 336 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 337 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 338 339 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 340 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 341 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 342 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 343 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 344 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 345 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 346 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 347 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 348 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 349 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 350 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 351 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 352 353 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 354 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 355 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 356 #define SFSR_CT_SECONDARY (1ULL << 4) 357 #define SFSR_CT_NUCLEUS (2ULL << 4) 358 #define SFSR_CT_NOTRANS (3ULL << 4) 359 #define SFSR_CT_MASK (3ULL << 4) 360 361 /* Leon3 cache control */ 362 363 /* Cache control: emulate the behavior of cache control registers but without 364 any effect on the emulated */ 365 366 #define CACHE_STATE_MASK 0x3 367 #define CACHE_DISABLED 0x0 368 #define CACHE_FROZEN 0x1 369 #define CACHE_ENABLED 0x3 370 371 /* Cache Control register fields */ 372 373 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 374 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 375 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 376 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 377 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 378 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 379 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 380 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 381 382 #define CONVERT_BIT(X, SRC, DST) \ 383 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 384 385 typedef struct SparcTLBEntry { 386 uint64_t tag; 387 uint64_t tte; 388 } SparcTLBEntry; 389 390 struct CPUTimer 391 { 392 const char *name; 393 uint32_t frequency; 394 uint32_t disabled; 395 uint64_t disabled_mask; 396 uint32_t npt; 397 uint64_t npt_mask; 398 int64_t clock_offset; 399 QEMUTimer *qtimer; 400 }; 401 402 typedef struct CPUTimer CPUTimer; 403 404 typedef struct CPUArchState CPUSPARCState; 405 #if defined(TARGET_SPARC64) 406 typedef union { 407 uint64_t mmuregs[16]; 408 struct { 409 uint64_t tsb_tag_target; 410 uint64_t mmu_primary_context; 411 uint64_t mmu_secondary_context; 412 uint64_t sfsr; 413 uint64_t sfar; 414 uint64_t tsb; 415 uint64_t tag_access; 416 uint64_t virtual_watchpoint; 417 uint64_t physical_watchpoint; 418 uint64_t sun4v_ctx_config[2]; 419 uint64_t sun4v_tsb_pointers[4]; 420 }; 421 } SparcV9MMU; 422 #endif 423 struct CPUArchState { 424 target_ulong gregs[8]; /* general registers */ 425 target_ulong *regwptr; /* pointer to current register window */ 426 target_ulong pc; /* program counter */ 427 target_ulong npc; /* next program counter */ 428 target_ulong y; /* multiply/divide register */ 429 430 /* 431 * Bit 31 is for icc, bit 63 for xcc. 432 * Other bits are garbage. 433 */ 434 target_long cc_N; 435 target_long cc_V; 436 437 /* 438 * Z is represented as == 0; any non-zero value is !Z. 439 * For sparc64, the high 32-bits of icc.Z are garbage. 440 */ 441 target_ulong icc_Z; 442 #ifdef TARGET_SPARC64 443 target_ulong xcc_Z; 444 #endif 445 446 /* 447 * For sparc32, icc.C is boolean. 448 * For sparc64, xcc.C is boolean; 449 * icc.C is bit 32 with other bits garbage. 450 */ 451 target_ulong icc_C; 452 #ifdef TARGET_SPARC64 453 target_ulong xcc_C; 454 #endif 455 456 target_ulong cond; /* conditional branch result (XXX: save it in a 457 temporary register when possible) */ 458 459 /* FPU State Register, in parts */ 460 uint32_t fsr; /* rm, tem, aexc */ 461 uint32_t fsr_cexc_ftt; /* cexc, ftt */ 462 uint32_t fcc[TARGET_FCCREGS]; /* fcc* */ 463 464 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 465 uint32_t cwp; /* index of current register window (extracted 466 from PSR) */ 467 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 468 uint32_t wim; /* window invalid mask */ 469 #endif 470 target_ulong tbr; /* trap base register */ 471 #if !defined(TARGET_SPARC64) 472 int psrs; /* supervisor mode (extracted from PSR) */ 473 int psrps; /* previous supervisor mode */ 474 int psret; /* enable traps */ 475 #endif 476 uint32_t psrpil; /* interrupt blocking level */ 477 uint32_t pil_in; /* incoming interrupt level bitmap */ 478 #if !defined(TARGET_SPARC64) 479 int psref; /* enable fpu */ 480 #endif 481 int interrupt_index; 482 /* NOTE: we allow 8 more registers to handle wrapping */ 483 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 484 485 /* Fields up to this point are cleared by a CPU reset */ 486 struct {} end_reset_fields; 487 488 /* Fields from here on are preserved across CPU reset. */ 489 target_ulong version; 490 uint32_t nwindows; 491 492 /* MMU regs */ 493 #if defined(TARGET_SPARC64) 494 uint64_t lsu; 495 #define DMMU_E 0x8 496 #define IMMU_E 0x4 497 SparcV9MMU immu; 498 SparcV9MMU dmmu; 499 SparcTLBEntry itlb[64]; 500 SparcTLBEntry dtlb[64]; 501 uint32_t mmu_version; 502 #else 503 uint32_t mmuregs[32]; 504 uint64_t mxccdata[4]; 505 uint64_t mxccregs[8]; 506 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 507 uint64_t mmubpaction; 508 uint64_t mmubpregs[4]; 509 uint64_t prom_addr; 510 #endif 511 float_status fp_status; 512 #if defined(TARGET_SPARC64) 513 #define MAXTL_MAX 8 514 #define MAXTL_MASK (MAXTL_MAX - 1) 515 trap_state ts[MAXTL_MAX]; 516 uint32_t asi; 517 uint32_t pstate; 518 uint32_t tl; 519 uint32_t maxtl; 520 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 521 uint64_t agregs[8]; /* alternate general registers */ 522 uint64_t bgregs[8]; /* backup for normal global registers */ 523 uint64_t igregs[8]; /* interrupt general registers */ 524 uint64_t mgregs[8]; /* mmu general registers */ 525 uint64_t glregs[8 * MAXTL_MAX]; 526 uint32_t fprs; 527 uint64_t tick_cmpr, stick_cmpr; 528 CPUTimer *tick, *stick; 529 #define TICK_NPT_MASK 0x8000000000000000ULL 530 #define TICK_INT_DIS 0x8000000000000000ULL 531 uint64_t gsr; 532 uint32_t gl; // UA2005 533 /* UA 2005 hyperprivileged registers */ 534 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 535 uint64_t scratch[8]; 536 CPUTimer *hstick; // UA 2005 537 /* Interrupt vector registers */ 538 uint64_t ivec_status; 539 uint64_t ivec_data[3]; 540 uint32_t softint; 541 #define SOFTINT_TIMER 1 542 #define SOFTINT_STIMER (1 << 16) 543 #define SOFTINT_INTRMASK (0xFFFE) 544 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 545 #endif 546 sparc_def_t def; 547 548 void *irq_manager; 549 void (*qemu_irq_ack)(CPUSPARCState *env, int intno); 550 551 /* Leon3 cache control */ 552 uint32_t cache_control; 553 }; 554 555 /** 556 * SPARCCPU: 557 * @env: #CPUSPARCState 558 * 559 * A SPARC CPU. 560 */ 561 struct ArchCPU { 562 CPUState parent_obj; 563 564 CPUSPARCState env; 565 }; 566 567 /** 568 * SPARCCPUClass: 569 * @parent_realize: The parent class' realize handler. 570 * @parent_phases: The parent class' reset phase handlers. 571 * 572 * A SPARC CPU model. 573 */ 574 struct SPARCCPUClass { 575 CPUClass parent_class; 576 577 DeviceRealize parent_realize; 578 ResettablePhases parent_phases; 579 sparc_def_t *cpu_def; 580 }; 581 582 #ifndef CONFIG_USER_ONLY 583 extern const VMStateDescription vmstate_sparc_cpu; 584 585 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 586 #endif 587 588 void sparc_cpu_do_interrupt(CPUState *cpu); 589 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 590 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 591 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 592 MMUAccessType access_type, 593 int mmu_idx, 594 uintptr_t retaddr); 595 G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); 596 597 /* cpu_init.c */ 598 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 599 void sparc_cpu_list(void); 600 /* mmu_helper.c */ 601 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 602 MMUAccessType access_type, int mmu_idx, 603 bool probe, uintptr_t retaddr); 604 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 605 void dump_mmu(CPUSPARCState *env); 606 607 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 608 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 609 uint8_t *buf, int len, bool is_write); 610 #endif 611 612 613 /* translate.c */ 614 void sparc_tcg_init(void); 615 void sparc_restore_state_to_opc(CPUState *cs, 616 const TranslationBlock *tb, 617 const uint64_t *data); 618 619 /* fop_helper.c */ 620 target_ulong cpu_get_fsr(CPUSPARCState *); 621 void cpu_put_fsr(CPUSPARCState *, target_ulong); 622 623 /* win_helper.c */ 624 target_ulong cpu_get_psr(CPUSPARCState *env1); 625 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 626 void cpu_put_psr_icc(CPUSPARCState *env1, target_ulong val); 627 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 628 #ifdef TARGET_SPARC64 629 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 630 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 631 #endif 632 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 633 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 634 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 635 636 /* sun4m.c, sun4u.c */ 637 void cpu_check_irqs(CPUSPARCState *env); 638 639 #if defined (TARGET_SPARC64) 640 641 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 642 { 643 return (x & mask) == (y & mask); 644 } 645 646 #define MMU_CONTEXT_BITS 13 647 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 648 649 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 650 uint64_t context) 651 { 652 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 653 } 654 655 #endif 656 657 /* cpu-exec.c */ 658 #if !defined(CONFIG_USER_ONLY) 659 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 660 vaddr addr, unsigned size, 661 MMUAccessType access_type, 662 int mmu_idx, MemTxAttrs attrs, 663 MemTxResult response, uintptr_t retaddr); 664 #if defined(TARGET_SPARC64) 665 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 666 int mmu_idx); 667 #endif 668 #endif 669 670 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 671 672 #define cpu_list sparc_cpu_list 673 674 /* MMU modes definitions */ 675 #if defined (TARGET_SPARC64) 676 #define MMU_USER_IDX 0 677 #define MMU_USER_SECONDARY_IDX 1 678 #define MMU_KERNEL_IDX 2 679 #define MMU_KERNEL_SECONDARY_IDX 3 680 #define MMU_NUCLEUS_IDX 4 681 #define MMU_PHYS_IDX 5 682 #else 683 #define MMU_USER_IDX 0 684 #define MMU_KERNEL_IDX 1 685 #define MMU_PHYS_IDX 2 686 #endif 687 688 #if defined (TARGET_SPARC64) 689 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 690 { 691 return env1->def.features & CPU_FEATURE_HYPV; 692 } 693 694 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 695 { 696 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 697 } 698 699 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 700 { 701 return env1->pstate & PS_PRIV; 702 } 703 #else 704 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 705 { 706 return env1->psrs; 707 } 708 #endif 709 710 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 711 { 712 #if !defined (TARGET_SPARC64) 713 if (env1->psret != 0) 714 return 1; 715 #else 716 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 717 return 1; 718 } 719 #endif 720 721 return 0; 722 } 723 724 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 725 { 726 #if !defined(TARGET_SPARC64) 727 /* level 15 is non-maskable on sparc v8 */ 728 return pil == 15 || pil > env1->psrpil; 729 #else 730 return pil > env1->psrpil; 731 #endif 732 } 733 734 #include "exec/cpu-all.h" 735 736 #ifdef TARGET_SPARC64 737 /* sun4u.c */ 738 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 739 uint64_t cpu_tick_get_count(CPUTimer *timer); 740 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 741 trap_state* cpu_tsptr(CPUSPARCState* env); 742 #endif 743 744 #define TB_FLAG_MMU_MASK 7 745 #define TB_FLAG_FPU_ENABLED (1 << 4) 746 #define TB_FLAG_AM_ENABLED (1 << 5) 747 #define TB_FLAG_SUPER (1 << 6) 748 #define TB_FLAG_HYPER (1 << 7) 749 #define TB_FLAG_ASI_SHIFT 24 750 751 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 752 uint64_t *cs_base, uint32_t *pflags) 753 { 754 uint32_t flags; 755 *pc = env->pc; 756 *cs_base = env->npc; 757 flags = cpu_mmu_index(env_cpu(env), false); 758 #ifndef CONFIG_USER_ONLY 759 if (cpu_supervisor_mode(env)) { 760 flags |= TB_FLAG_SUPER; 761 } 762 #endif 763 #ifdef TARGET_SPARC64 764 #ifndef CONFIG_USER_ONLY 765 if (cpu_hypervisor_mode(env)) { 766 flags |= TB_FLAG_HYPER; 767 } 768 #endif 769 if (env->pstate & PS_AM) { 770 flags |= TB_FLAG_AM_ENABLED; 771 } 772 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { 773 flags |= TB_FLAG_FPU_ENABLED; 774 } 775 flags |= env->asi << TB_FLAG_ASI_SHIFT; 776 #else 777 if (env->psref) { 778 flags |= TB_FLAG_FPU_ENABLED; 779 } 780 #endif 781 *pflags = flags; 782 } 783 784 static inline bool tb_fpu_enabled(int tb_flags) 785 { 786 #if defined(CONFIG_USER_ONLY) 787 return true; 788 #else 789 return tb_flags & TB_FLAG_FPU_ENABLED; 790 #endif 791 } 792 793 static inline bool tb_am_enabled(int tb_flags) 794 { 795 #ifndef TARGET_SPARC64 796 return false; 797 #else 798 return tb_flags & TB_FLAG_AM_ENABLED; 799 #endif 800 } 801 802 #ifdef TARGET_SPARC64 803 /* win_helper.c */ 804 target_ulong cpu_get_ccr(CPUSPARCState *env1); 805 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 806 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 807 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 808 809 static inline uint64_t sparc64_tstate(CPUSPARCState *env) 810 { 811 uint64_t tstate = (cpu_get_ccr(env) << 32) | 812 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 813 cpu_get_cwp64(env); 814 815 if (env->def.features & CPU_FEATURE_GL) { 816 tstate |= (env->gl & 7ULL) << 40; 817 } 818 return tstate; 819 } 820 #endif 821 822 #endif 823