1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu/bswap.h" 5 #include "cpu-qom.h" 6 #include "exec/cpu-defs.h" 7 #include "qemu/cpu-float.h" 8 9 #if !defined(TARGET_SPARC64) 10 #define TARGET_DPREGS 16 11 #define TARGET_FCCREGS 1 12 #else 13 #define TARGET_DPREGS 32 14 #define TARGET_FCCREGS 4 15 #endif 16 17 /*#define EXCP_INTERRUPT 0x100*/ 18 19 /* Windowed register indexes. */ 20 enum { 21 WREG_O0, 22 WREG_O1, 23 WREG_O2, 24 WREG_O3, 25 WREG_O4, 26 WREG_O5, 27 WREG_O6, 28 WREG_O7, 29 30 WREG_L0, 31 WREG_L1, 32 WREG_L2, 33 WREG_L3, 34 WREG_L4, 35 WREG_L5, 36 WREG_L6, 37 WREG_L7, 38 39 WREG_I0, 40 WREG_I1, 41 WREG_I2, 42 WREG_I3, 43 WREG_I4, 44 WREG_I5, 45 WREG_I6, 46 WREG_I7, 47 48 WREG_SP = WREG_O6, 49 WREG_FP = WREG_I6, 50 }; 51 52 /* trap definitions */ 53 #ifndef TARGET_SPARC64 54 #define TT_TFAULT 0x01 55 #define TT_ILL_INSN 0x02 56 #define TT_PRIV_INSN 0x03 57 #define TT_NFPU_INSN 0x04 58 #define TT_WIN_OVF 0x05 59 #define TT_WIN_UNF 0x06 60 #define TT_UNALIGNED 0x07 61 #define TT_FP_EXCP 0x08 62 #define TT_DFAULT 0x09 63 #define TT_TOVF 0x0a 64 #define TT_EXTINT 0x10 65 #define TT_CODE_ACCESS 0x21 66 #define TT_UNIMP_FLUSH 0x25 67 #define TT_DATA_ACCESS 0x29 68 #define TT_DIV_ZERO 0x2a 69 #define TT_NCP_INSN 0x24 70 #define TT_TRAP 0x80 71 #else 72 #define TT_POWER_ON_RESET 0x01 73 #define TT_TFAULT 0x08 74 #define TT_CODE_ACCESS 0x0a 75 #define TT_ILL_INSN 0x10 76 #define TT_UNIMP_FLUSH TT_ILL_INSN 77 #define TT_PRIV_INSN 0x11 78 #define TT_NFPU_INSN 0x20 79 #define TT_FP_EXCP 0x21 80 #define TT_TOVF 0x23 81 #define TT_CLRWIN 0x24 82 #define TT_DIV_ZERO 0x28 83 #define TT_DFAULT 0x30 84 #define TT_DATA_ACCESS 0x32 85 #define TT_UNALIGNED 0x34 86 #define TT_PRIV_ACT 0x37 87 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 88 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 89 #define TT_EXTINT 0x40 90 #define TT_IVEC 0x60 91 #define TT_TMISS 0x64 92 #define TT_DMISS 0x68 93 #define TT_DPROT 0x6c 94 #define TT_SPILL 0x80 95 #define TT_FILL 0xc0 96 #define TT_WOTHER (1 << 5) 97 #define TT_TRAP 0x100 98 #define TT_HTRAP 0x180 99 #endif 100 101 #define PSR_NEG_SHIFT 23 102 #define PSR_NEG (1 << PSR_NEG_SHIFT) 103 #define PSR_ZERO_SHIFT 22 104 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 105 #define PSR_OVF_SHIFT 21 106 #define PSR_OVF (1 << PSR_OVF_SHIFT) 107 #define PSR_CARRY_SHIFT 20 108 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 109 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 110 #if !defined(TARGET_SPARC64) 111 #define PSR_EF (1<<12) 112 #define PSR_PIL 0xf00 113 #define PSR_S (1<<7) 114 #define PSR_PS (1<<6) 115 #define PSR_ET (1<<5) 116 #define PSR_CWP 0x1f 117 #endif 118 119 /* Trap base register */ 120 #define TBR_BASE_MASK 0xfffff000 121 122 #if defined(TARGET_SPARC64) 123 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 124 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 125 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 126 #define PS_CLE (1<<9) /* UA2007 */ 127 #define PS_TLE (1<<8) /* UA2007 */ 128 #define PS_RMO (1<<7) 129 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 130 #define PS_PEF (1<<4) /* enable fpu */ 131 #define PS_AM (1<<3) /* address mask */ 132 #define PS_PRIV (1<<2) 133 #define PS_IE (1<<1) 134 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 135 136 #define FPRS_DL (1 << 0) 137 #define FPRS_DU (1 << 1) 138 #define FPRS_FEF (1 << 2) 139 140 #define HS_PRIV (1<<2) 141 #endif 142 143 /* Fcc */ 144 #define FSR_RD1 (1ULL << 31) 145 #define FSR_RD0 (1ULL << 30) 146 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 147 #define FSR_RD_NEAREST 0 148 #define FSR_RD_ZERO FSR_RD0 149 #define FSR_RD_POS FSR_RD1 150 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 151 152 #define FSR_NVM (1ULL << 27) 153 #define FSR_OFM (1ULL << 26) 154 #define FSR_UFM (1ULL << 25) 155 #define FSR_DZM (1ULL << 24) 156 #define FSR_NXM (1ULL << 23) 157 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 158 #define FSR_TEM_SHIFT 23 159 160 #define FSR_NVA (1ULL << 9) 161 #define FSR_OFA (1ULL << 8) 162 #define FSR_UFA (1ULL << 7) 163 #define FSR_DZA (1ULL << 6) 164 #define FSR_NXA (1ULL << 5) 165 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 166 #define FSR_AEXC_SHIFT 5 167 168 #define FSR_NVC (1ULL << 4) 169 #define FSR_OFC (1ULL << 3) 170 #define FSR_UFC (1ULL << 2) 171 #define FSR_DZC (1ULL << 1) 172 #define FSR_NXC (1ULL << 0) 173 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 174 175 #define FSR_VER_SHIFT 17 176 #define FSR_VER_MASK (7 << FSR_VER_SHIFT) 177 178 #define FSR_FTT2 (1ULL << 16) 179 #define FSR_FTT1 (1ULL << 15) 180 #define FSR_FTT0 (1ULL << 14) 181 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 182 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 183 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 184 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 185 #define FSR_FTT_INVAL_FPR (6ULL << 14) 186 187 #define FSR_FCC0_SHIFT 10 188 #define FSR_FCC1_SHIFT 32 189 #define FSR_FCC2_SHIFT 34 190 #define FSR_FCC3_SHIFT 36 191 192 /* MMU */ 193 #define MMU_E (1<<0) 194 #define MMU_NF (1<<1) 195 196 #define PTE_ENTRYTYPE_MASK 3 197 #define PTE_ACCESS_MASK 0x1c 198 #define PTE_ACCESS_SHIFT 2 199 #define PTE_PPN_SHIFT 7 200 #define PTE_ADDR_MASK 0xffffff00 201 202 #define PG_ACCESSED_BIT 5 203 #define PG_MODIFIED_BIT 6 204 #define PG_CACHE_BIT 7 205 206 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 207 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 208 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 209 210 /* 3 <= NWINDOWS <= 32. */ 211 #define MIN_NWINDOWS 3 212 #define MAX_NWINDOWS 32 213 214 #ifdef TARGET_SPARC64 215 typedef struct trap_state { 216 uint64_t tpc; 217 uint64_t tnpc; 218 uint64_t tstate; 219 uint32_t tt; 220 } trap_state; 221 #endif 222 #define TARGET_INSN_START_EXTRA_WORDS 1 223 224 typedef struct sparc_def_t { 225 const char *name; 226 target_ulong iu_version; 227 uint32_t fpu_version; 228 uint32_t mmu_version; 229 uint32_t mmu_bm; 230 uint32_t mmu_ctpr_mask; 231 uint32_t mmu_cxr_mask; 232 uint32_t mmu_sfsr_mask; 233 uint32_t mmu_trcr_mask; 234 uint32_t mxcc_version; 235 uint32_t features; 236 uint32_t nwindows; 237 uint32_t maxtl; 238 } sparc_def_t; 239 240 #define FEATURE(X) CPU_FEATURE_BIT_##X, 241 enum { 242 #include "cpu-feature.h.inc" 243 }; 244 245 #undef FEATURE 246 #define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X, 247 248 enum { 249 #include "cpu-feature.h.inc" 250 }; 251 252 #undef FEATURE 253 254 #ifndef TARGET_SPARC64 255 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 256 CPU_FEATURE_FSMULD) 257 #else 258 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 259 CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ 260 CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) 261 enum { 262 mmu_us_12, // Ultrasparc < III (64 entry TLB) 263 mmu_us_3, // Ultrasparc III (512 entry TLB) 264 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 265 mmu_sun4v, // T1, T2 266 }; 267 #endif 268 269 #define TTE_VALID_BIT (1ULL << 63) 270 #define TTE_NFO_BIT (1ULL << 60) 271 #define TTE_IE_BIT (1ULL << 59) 272 #define TTE_USED_BIT (1ULL << 41) 273 #define TTE_LOCKED_BIT (1ULL << 6) 274 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 275 #define TTE_PRIV_BIT (1ULL << 2) 276 #define TTE_W_OK_BIT (1ULL << 1) 277 #define TTE_GLOBAL_BIT (1ULL << 0) 278 279 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 280 #define TTE_USED_BIT_UA2005 (1ULL << 47) 281 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 282 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 283 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 284 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 285 286 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 287 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 288 #define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) 289 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 290 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 291 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 292 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 293 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 294 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 295 296 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 297 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 298 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 299 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 300 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 301 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 302 303 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 304 305 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 306 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 307 308 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 309 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 310 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 311 312 /* UltraSPARC T1 specific */ 313 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 314 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 315 316 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 317 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 318 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 319 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 320 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 321 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 322 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 323 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 324 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 325 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 326 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 327 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 328 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 329 330 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 331 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 332 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 333 #define SFSR_CT_SECONDARY (1ULL << 4) 334 #define SFSR_CT_NUCLEUS (2ULL << 4) 335 #define SFSR_CT_NOTRANS (3ULL << 4) 336 #define SFSR_CT_MASK (3ULL << 4) 337 338 /* Leon3 cache control */ 339 340 /* Cache control: emulate the behavior of cache control registers but without 341 any effect on the emulated */ 342 343 #define CACHE_STATE_MASK 0x3 344 #define CACHE_DISABLED 0x0 345 #define CACHE_FROZEN 0x1 346 #define CACHE_ENABLED 0x3 347 348 /* Cache Control register fields */ 349 350 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 351 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 352 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 353 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 354 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 355 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 356 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 357 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 358 359 #define CONVERT_BIT(X, SRC, DST) \ 360 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 361 362 typedef struct SparcTLBEntry { 363 uint64_t tag; 364 uint64_t tte; 365 } SparcTLBEntry; 366 367 struct CPUTimer 368 { 369 const char *name; 370 uint32_t frequency; 371 uint32_t disabled; 372 uint64_t disabled_mask; 373 uint32_t npt; 374 uint64_t npt_mask; 375 int64_t clock_offset; 376 QEMUTimer *qtimer; 377 }; 378 379 typedef struct CPUTimer CPUTimer; 380 381 typedef struct CPUArchState CPUSPARCState; 382 #if defined(TARGET_SPARC64) 383 typedef union { 384 uint64_t mmuregs[16]; 385 struct { 386 uint64_t tsb_tag_target; 387 uint64_t mmu_primary_context; 388 uint64_t mmu_secondary_context; 389 uint64_t sfsr; 390 uint64_t sfar; 391 uint64_t tsb; 392 uint64_t tag_access; 393 uint64_t virtual_watchpoint; 394 uint64_t physical_watchpoint; 395 uint64_t sun4v_ctx_config[2]; 396 uint64_t sun4v_tsb_pointers[4]; 397 }; 398 } SparcV9MMU; 399 #endif 400 struct CPUArchState { 401 target_ulong gregs[8]; /* general registers */ 402 target_ulong *regwptr; /* pointer to current register window */ 403 target_ulong pc; /* program counter */ 404 target_ulong npc; /* next program counter */ 405 target_ulong y; /* multiply/divide register */ 406 407 /* 408 * Bit 31 is for icc, bit 63 for xcc. 409 * Other bits are garbage. 410 */ 411 target_long cc_N; 412 target_long cc_V; 413 414 /* 415 * Z is represented as == 0; any non-zero value is !Z. 416 * For sparc64, the high 32-bits of icc.Z are garbage. 417 */ 418 target_ulong icc_Z; 419 #ifdef TARGET_SPARC64 420 target_ulong xcc_Z; 421 #endif 422 423 /* 424 * For sparc32, icc.C is boolean. 425 * For sparc64, xcc.C is boolean; 426 * icc.C is bit 32 with other bits garbage. 427 */ 428 target_ulong icc_C; 429 #ifdef TARGET_SPARC64 430 target_ulong xcc_C; 431 #endif 432 433 target_ulong cond; /* conditional branch result (XXX: save it in a 434 temporary register when possible) */ 435 436 /* FPU State Register, in parts */ 437 uint32_t fsr; /* rm, tem, aexc */ 438 uint32_t fsr_cexc_ftt; /* cexc, ftt */ 439 uint32_t fcc[TARGET_FCCREGS]; /* fcc* */ 440 441 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 442 uint32_t cwp; /* index of current register window (extracted 443 from PSR) */ 444 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 445 uint32_t wim; /* window invalid mask */ 446 #endif 447 target_ulong tbr; /* trap base register */ 448 #if !defined(TARGET_SPARC64) 449 int psrs; /* supervisor mode (extracted from PSR) */ 450 int psrps; /* previous supervisor mode */ 451 int psret; /* enable traps */ 452 #endif 453 uint32_t psrpil; /* interrupt blocking level */ 454 uint32_t pil_in; /* incoming interrupt level bitmap */ 455 #if !defined(TARGET_SPARC64) 456 int psref; /* enable fpu */ 457 #endif 458 int interrupt_index; 459 /* NOTE: we allow 8 more registers to handle wrapping */ 460 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 461 462 /* Fields up to this point are cleared by a CPU reset */ 463 struct {} end_reset_fields; 464 465 /* Fields from here on are preserved across CPU reset. */ 466 target_ulong version; 467 uint32_t nwindows; 468 469 /* MMU regs */ 470 #if defined(TARGET_SPARC64) 471 uint64_t lsu; 472 #define DMMU_E 0x8 473 #define IMMU_E 0x4 474 SparcV9MMU immu; 475 SparcV9MMU dmmu; 476 SparcTLBEntry itlb[64]; 477 SparcTLBEntry dtlb[64]; 478 uint32_t mmu_version; 479 #else 480 uint32_t mmuregs[32]; 481 uint64_t mxccdata[4]; 482 uint64_t mxccregs[8]; 483 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 484 uint64_t mmubpaction; 485 uint64_t mmubpregs[4]; 486 uint64_t prom_addr; 487 #endif 488 float_status fp_status; 489 #if defined(TARGET_SPARC64) 490 #define MAXTL_MAX 8 491 #define MAXTL_MASK (MAXTL_MAX - 1) 492 trap_state ts[MAXTL_MAX]; 493 uint32_t asi; 494 uint32_t pstate; 495 uint32_t tl; 496 uint32_t maxtl; 497 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 498 uint64_t agregs[8]; /* alternate general registers */ 499 uint64_t bgregs[8]; /* backup for normal global registers */ 500 uint64_t igregs[8]; /* interrupt general registers */ 501 uint64_t mgregs[8]; /* mmu general registers */ 502 uint64_t glregs[8 * MAXTL_MAX]; 503 uint32_t fprs; 504 uint64_t tick_cmpr, stick_cmpr; 505 CPUTimer *tick, *stick; 506 #define TICK_NPT_MASK 0x8000000000000000ULL 507 #define TICK_INT_DIS 0x8000000000000000ULL 508 uint64_t gsr; 509 uint32_t gl; // UA2005 510 /* UA 2005 hyperprivileged registers */ 511 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 512 uint64_t scratch[8]; 513 CPUTimer *hstick; // UA 2005 514 /* Interrupt vector registers */ 515 uint64_t ivec_status; 516 uint64_t ivec_data[3]; 517 uint32_t softint; 518 #define SOFTINT_TIMER 1 519 #define SOFTINT_STIMER (1 << 16) 520 #define SOFTINT_INTRMASK (0xFFFE) 521 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 522 #endif 523 sparc_def_t def; 524 525 /* Leon3 */ 526 DeviceState *irq_manager; 527 void (*qemu_irq_ack)(CPUSPARCState *env, int intno); 528 uint32_t cache_control; 529 }; 530 531 /** 532 * SPARCCPU: 533 * @env: #CPUSPARCState 534 * 535 * A SPARC CPU. 536 */ 537 struct ArchCPU { 538 CPUState parent_obj; 539 540 CPUSPARCState env; 541 }; 542 543 /** 544 * SPARCCPUClass: 545 * @parent_realize: The parent class' realize handler. 546 * @parent_phases: The parent class' reset phase handlers. 547 * 548 * A SPARC CPU model. 549 */ 550 struct SPARCCPUClass { 551 CPUClass parent_class; 552 553 DeviceRealize parent_realize; 554 ResettablePhases parent_phases; 555 sparc_def_t *cpu_def; 556 }; 557 558 #ifndef CONFIG_USER_ONLY 559 extern const VMStateDescription vmstate_sparc_cpu; 560 561 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 562 #endif 563 564 void sparc_cpu_do_interrupt(CPUState *cpu); 565 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 566 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 567 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 568 MMUAccessType access_type, 569 int mmu_idx, 570 uintptr_t retaddr); 571 G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); 572 573 /* cpu_init.c */ 574 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 575 void sparc_cpu_list(void); 576 /* mmu_helper.c */ 577 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 578 MMUAccessType access_type, int mmu_idx, 579 bool probe, uintptr_t retaddr); 580 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 581 void dump_mmu(CPUSPARCState *env); 582 583 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 584 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 585 uint8_t *buf, int len, bool is_write); 586 #endif 587 588 589 /* translate.c */ 590 void sparc_tcg_init(void); 591 void sparc_restore_state_to_opc(CPUState *cs, 592 const TranslationBlock *tb, 593 const uint64_t *data); 594 595 /* fop_helper.c */ 596 target_ulong cpu_get_fsr(CPUSPARCState *); 597 void cpu_put_fsr(CPUSPARCState *, target_ulong); 598 599 /* win_helper.c */ 600 target_ulong cpu_get_psr(CPUSPARCState *env1); 601 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 602 void cpu_put_psr_icc(CPUSPARCState *env1, target_ulong val); 603 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 604 #ifdef TARGET_SPARC64 605 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 606 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 607 #endif 608 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 609 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 610 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 611 612 /* sun4m.c, sun4u.c */ 613 void cpu_check_irqs(CPUSPARCState *env); 614 615 #if defined (TARGET_SPARC64) 616 617 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 618 { 619 return (x & mask) == (y & mask); 620 } 621 622 #define MMU_CONTEXT_BITS 13 623 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 624 625 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 626 uint64_t context) 627 { 628 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 629 } 630 631 #endif 632 633 /* cpu-exec.c */ 634 #if !defined(CONFIG_USER_ONLY) 635 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 636 vaddr addr, unsigned size, 637 MMUAccessType access_type, 638 int mmu_idx, MemTxAttrs attrs, 639 MemTxResult response, uintptr_t retaddr); 640 #if defined(TARGET_SPARC64) 641 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 642 int mmu_idx); 643 #endif 644 #endif 645 646 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 647 648 #define cpu_list sparc_cpu_list 649 650 /* MMU modes definitions */ 651 #if defined (TARGET_SPARC64) 652 #define MMU_USER_IDX 0 653 #define MMU_USER_SECONDARY_IDX 1 654 #define MMU_KERNEL_IDX 2 655 #define MMU_KERNEL_SECONDARY_IDX 3 656 #define MMU_NUCLEUS_IDX 4 657 #define MMU_PHYS_IDX 5 658 #else 659 #define MMU_USER_IDX 0 660 #define MMU_KERNEL_IDX 1 661 #define MMU_PHYS_IDX 2 662 #endif 663 664 #if defined (TARGET_SPARC64) 665 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 666 { 667 return env1->def.features & CPU_FEATURE_HYPV; 668 } 669 670 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 671 { 672 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 673 } 674 675 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 676 { 677 return env1->pstate & PS_PRIV; 678 } 679 #else 680 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 681 { 682 return env1->psrs; 683 } 684 #endif 685 686 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 687 { 688 #if !defined (TARGET_SPARC64) 689 if (env1->psret != 0) 690 return 1; 691 #else 692 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 693 return 1; 694 } 695 #endif 696 697 return 0; 698 } 699 700 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 701 { 702 #if !defined(TARGET_SPARC64) 703 /* level 15 is non-maskable on sparc v8 */ 704 return pil == 15 || pil > env1->psrpil; 705 #else 706 return pil > env1->psrpil; 707 #endif 708 } 709 710 #include "exec/cpu-all.h" 711 712 #ifdef TARGET_SPARC64 713 /* sun4u.c */ 714 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 715 uint64_t cpu_tick_get_count(CPUTimer *timer); 716 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 717 trap_state* cpu_tsptr(CPUSPARCState* env); 718 #endif 719 720 #define TB_FLAG_MMU_MASK 7 721 #define TB_FLAG_FPU_ENABLED (1 << 4) 722 #define TB_FLAG_AM_ENABLED (1 << 5) 723 #define TB_FLAG_SUPER (1 << 6) 724 #define TB_FLAG_HYPER (1 << 7) 725 #define TB_FLAG_ASI_SHIFT 24 726 727 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 728 uint64_t *cs_base, uint32_t *pflags) 729 { 730 uint32_t flags; 731 *pc = env->pc; 732 *cs_base = env->npc; 733 flags = cpu_mmu_index(env_cpu(env), false); 734 #ifndef CONFIG_USER_ONLY 735 if (cpu_supervisor_mode(env)) { 736 flags |= TB_FLAG_SUPER; 737 } 738 #endif 739 #ifdef TARGET_SPARC64 740 #ifndef CONFIG_USER_ONLY 741 if (cpu_hypervisor_mode(env)) { 742 flags |= TB_FLAG_HYPER; 743 } 744 #endif 745 if (env->pstate & PS_AM) { 746 flags |= TB_FLAG_AM_ENABLED; 747 } 748 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { 749 flags |= TB_FLAG_FPU_ENABLED; 750 } 751 flags |= env->asi << TB_FLAG_ASI_SHIFT; 752 #else 753 if (env->psref) { 754 flags |= TB_FLAG_FPU_ENABLED; 755 } 756 #endif 757 *pflags = flags; 758 } 759 760 static inline bool tb_fpu_enabled(int tb_flags) 761 { 762 #if defined(CONFIG_USER_ONLY) 763 return true; 764 #else 765 return tb_flags & TB_FLAG_FPU_ENABLED; 766 #endif 767 } 768 769 static inline bool tb_am_enabled(int tb_flags) 770 { 771 #ifndef TARGET_SPARC64 772 return false; 773 #else 774 return tb_flags & TB_FLAG_AM_ENABLED; 775 #endif 776 } 777 778 #ifdef TARGET_SPARC64 779 /* win_helper.c */ 780 target_ulong cpu_get_ccr(CPUSPARCState *env1); 781 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 782 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 783 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 784 785 static inline uint64_t sparc64_tstate(CPUSPARCState *env) 786 { 787 uint64_t tstate = (cpu_get_ccr(env) << 32) | 788 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 789 cpu_get_cwp64(env); 790 791 if (env->def.features & CPU_FEATURE_GL) { 792 tstate |= (env->gl & 7ULL) << 40; 793 } 794 return tstate; 795 } 796 #endif 797 798 #endif 799