1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu/bswap.h" 5 #include "cpu-qom.h" 6 #include "exec/cpu-common.h" 7 #include "exec/cpu-defs.h" 8 #include "exec/cpu-interrupt.h" 9 #include "qemu/cpu-float.h" 10 11 #if !defined(TARGET_SPARC64) 12 #define TARGET_DPREGS 16 13 #define TARGET_FCCREGS 1 14 #else 15 #define TARGET_DPREGS 32 16 #define TARGET_FCCREGS 4 17 #endif 18 19 /*#define EXCP_INTERRUPT 0x100*/ 20 21 /* Windowed register indexes. */ 22 enum { 23 WREG_O0, 24 WREG_O1, 25 WREG_O2, 26 WREG_O3, 27 WREG_O4, 28 WREG_O5, 29 WREG_O6, 30 WREG_O7, 31 32 WREG_L0, 33 WREG_L1, 34 WREG_L2, 35 WREG_L3, 36 WREG_L4, 37 WREG_L5, 38 WREG_L6, 39 WREG_L7, 40 41 WREG_I0, 42 WREG_I1, 43 WREG_I2, 44 WREG_I3, 45 WREG_I4, 46 WREG_I5, 47 WREG_I6, 48 WREG_I7, 49 50 WREG_SP = WREG_O6, 51 WREG_FP = WREG_I6, 52 }; 53 54 /* trap definitions */ 55 #ifndef TARGET_SPARC64 56 #define TT_TFAULT 0x01 57 #define TT_ILL_INSN 0x02 58 #define TT_PRIV_INSN 0x03 59 #define TT_NFPU_INSN 0x04 60 #define TT_WIN_OVF 0x05 61 #define TT_WIN_UNF 0x06 62 #define TT_UNALIGNED 0x07 63 #define TT_FP_EXCP 0x08 64 #define TT_DFAULT 0x09 65 #define TT_TOVF 0x0a 66 #define TT_EXTINT 0x10 67 #define TT_CODE_ACCESS 0x21 68 #define TT_UNIMP_FLUSH 0x25 69 #define TT_DATA_ACCESS 0x29 70 #define TT_DIV_ZERO 0x2a 71 #define TT_NCP_INSN 0x24 72 #define TT_TRAP 0x80 73 #else 74 #define TT_POWER_ON_RESET 0x01 75 #define TT_TFAULT 0x08 76 #define TT_CODE_ACCESS 0x0a 77 #define TT_ILL_INSN 0x10 78 #define TT_UNIMP_FLUSH TT_ILL_INSN 79 #define TT_PRIV_INSN 0x11 80 #define TT_NFPU_INSN 0x20 81 #define TT_FP_EXCP 0x21 82 #define TT_TOVF 0x23 83 #define TT_CLRWIN 0x24 84 #define TT_DIV_ZERO 0x28 85 #define TT_DFAULT 0x30 86 #define TT_DATA_ACCESS 0x32 87 #define TT_UNALIGNED 0x34 88 #define TT_PRIV_ACT 0x37 89 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 90 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 91 #define TT_EXTINT 0x40 92 #define TT_IVEC 0x60 93 #define TT_TMISS 0x64 94 #define TT_DMISS 0x68 95 #define TT_DPROT 0x6c 96 #define TT_SPILL 0x80 97 #define TT_FILL 0xc0 98 #define TT_WOTHER (1 << 5) 99 #define TT_TRAP 0x100 100 #define TT_HTRAP 0x180 101 #endif 102 103 #define PSR_NEG_SHIFT 23 104 #define PSR_NEG (1 << PSR_NEG_SHIFT) 105 #define PSR_ZERO_SHIFT 22 106 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 107 #define PSR_OVF_SHIFT 21 108 #define PSR_OVF (1 << PSR_OVF_SHIFT) 109 #define PSR_CARRY_SHIFT 20 110 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 111 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 112 #if !defined(TARGET_SPARC64) 113 #define PSR_EF (1<<12) 114 #define PSR_PIL 0xf00 115 #define PSR_S (1<<7) 116 #define PSR_PS (1<<6) 117 #define PSR_ET (1<<5) 118 #define PSR_CWP 0x1f 119 #endif 120 121 /* Trap base register */ 122 #define TBR_BASE_MASK 0xfffff000 123 124 #if defined(TARGET_SPARC64) 125 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 126 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 127 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 128 #define PS_CLE (1<<9) /* UA2007 */ 129 #define PS_TLE (1<<8) /* UA2007 */ 130 #define PS_RMO (1<<7) 131 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 132 #define PS_PEF (1<<4) /* enable fpu */ 133 #define PS_AM (1<<3) /* address mask */ 134 #define PS_PRIV (1<<2) 135 #define PS_IE (1<<1) 136 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 137 138 #define FPRS_DL (1 << 0) 139 #define FPRS_DU (1 << 1) 140 #define FPRS_FEF (1 << 2) 141 142 #define HS_PRIV (1<<2) 143 #endif 144 145 /* Fcc */ 146 #define FSR_RD1 (1ULL << 31) 147 #define FSR_RD0 (1ULL << 30) 148 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 149 #define FSR_RD_NEAREST 0 150 #define FSR_RD_ZERO FSR_RD0 151 #define FSR_RD_POS FSR_RD1 152 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 153 154 #define FSR_NVM (1ULL << 27) 155 #define FSR_OFM (1ULL << 26) 156 #define FSR_UFM (1ULL << 25) 157 #define FSR_DZM (1ULL << 24) 158 #define FSR_NXM (1ULL << 23) 159 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 160 #define FSR_TEM_SHIFT 23 161 162 #define FSR_NVA (1ULL << 9) 163 #define FSR_OFA (1ULL << 8) 164 #define FSR_UFA (1ULL << 7) 165 #define FSR_DZA (1ULL << 6) 166 #define FSR_NXA (1ULL << 5) 167 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 168 #define FSR_AEXC_SHIFT 5 169 170 #define FSR_NVC (1ULL << 4) 171 #define FSR_OFC (1ULL << 3) 172 #define FSR_UFC (1ULL << 2) 173 #define FSR_DZC (1ULL << 1) 174 #define FSR_NXC (1ULL << 0) 175 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 176 177 #define FSR_VER_SHIFT 17 178 #define FSR_VER_MASK (7 << FSR_VER_SHIFT) 179 180 #define FSR_FTT2 (1ULL << 16) 181 #define FSR_FTT1 (1ULL << 15) 182 #define FSR_FTT0 (1ULL << 14) 183 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 184 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 185 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 186 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 187 #define FSR_FTT_INVAL_FPR (6ULL << 14) 188 189 #define FSR_QNE (1ULL << 13) 190 191 #define FSR_FCC0_SHIFT 10 192 #define FSR_FCC1_SHIFT 32 193 #define FSR_FCC2_SHIFT 34 194 #define FSR_FCC3_SHIFT 36 195 196 /* MMU */ 197 #define MMU_E (1<<0) 198 #define MMU_NF (1<<1) 199 200 #define PTE_ENTRYTYPE_MASK 3 201 #define PTE_ACCESS_MASK 0x1c 202 #define PTE_ACCESS_SHIFT 2 203 #define PTE_PPN_SHIFT 7 204 #define PTE_ADDR_MASK 0xffffff00 205 206 #define PG_ACCESSED_BIT 5 207 #define PG_MODIFIED_BIT 6 208 #define PG_CACHE_BIT 7 209 210 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 211 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 212 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 213 214 /* 3 <= NWINDOWS <= 32. */ 215 #define MIN_NWINDOWS 3 216 #define MAX_NWINDOWS 32 217 218 #ifdef TARGET_SPARC64 219 typedef struct trap_state { 220 uint64_t tpc; 221 uint64_t tnpc; 222 uint64_t tstate; 223 uint32_t tt; 224 } trap_state; 225 #endif 226 #define TARGET_INSN_START_EXTRA_WORDS 1 227 228 typedef struct sparc_def_t { 229 const char *name; 230 target_ulong iu_version; 231 uint32_t fpu_version; 232 uint32_t mmu_version; 233 uint32_t mmu_bm; 234 uint32_t mmu_ctpr_mask; 235 uint32_t mmu_cxr_mask; 236 uint32_t mmu_sfsr_mask; 237 uint32_t mmu_trcr_mask; 238 uint32_t mxcc_version; 239 uint32_t features; 240 uint32_t nwindows; 241 uint32_t maxtl; 242 } sparc_def_t; 243 244 #define FEATURE(X) CPU_FEATURE_BIT_##X, 245 enum { 246 #include "cpu-feature.h.inc" 247 }; 248 249 #undef FEATURE 250 #define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X, 251 252 enum { 253 #include "cpu-feature.h.inc" 254 }; 255 256 #undef FEATURE 257 258 #ifndef TARGET_SPARC64 259 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 260 CPU_FEATURE_FSMULD) 261 #else 262 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 263 CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ 264 CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) 265 enum { 266 mmu_us_12, // Ultrasparc < III (64 entry TLB) 267 mmu_us_3, // Ultrasparc III (512 entry TLB) 268 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 269 mmu_sun4v, // T1, T2 270 }; 271 #endif 272 273 #define TTE_VALID_BIT (1ULL << 63) 274 #define TTE_NFO_BIT (1ULL << 60) 275 #define TTE_IE_BIT (1ULL << 59) 276 #define TTE_USED_BIT (1ULL << 41) 277 #define TTE_LOCKED_BIT (1ULL << 6) 278 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 279 #define TTE_PRIV_BIT (1ULL << 2) 280 #define TTE_W_OK_BIT (1ULL << 1) 281 #define TTE_GLOBAL_BIT (1ULL << 0) 282 283 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 284 #define TTE_USED_BIT_UA2005 (1ULL << 47) 285 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 286 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 287 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 288 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 289 290 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 291 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 292 #define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) 293 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 294 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 295 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 296 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 297 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 298 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 299 300 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 301 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 302 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 303 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 304 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 305 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 306 307 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 308 309 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 310 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 311 312 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 313 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 314 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 315 316 /* UltraSPARC T1 specific */ 317 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 318 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 319 320 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 321 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 322 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 323 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 324 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 325 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 326 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 327 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 328 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 329 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 330 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 331 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 332 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 333 334 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 335 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 336 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 337 #define SFSR_CT_SECONDARY (1ULL << 4) 338 #define SFSR_CT_NUCLEUS (2ULL << 4) 339 #define SFSR_CT_NOTRANS (3ULL << 4) 340 #define SFSR_CT_MASK (3ULL << 4) 341 342 /* Leon3 cache control */ 343 344 /* Cache control: emulate the behavior of cache control registers but without 345 any effect on the emulated */ 346 347 #define CACHE_STATE_MASK 0x3 348 #define CACHE_DISABLED 0x0 349 #define CACHE_FROZEN 0x1 350 #define CACHE_ENABLED 0x3 351 352 /* Cache Control register fields */ 353 354 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 355 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 356 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 357 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 358 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 359 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 360 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 361 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 362 363 #define CONVERT_BIT(X, SRC, DST) \ 364 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 365 366 typedef struct SparcTLBEntry { 367 uint64_t tag; 368 uint64_t tte; 369 } SparcTLBEntry; 370 371 struct CPUTimer 372 { 373 const char *name; 374 uint32_t frequency; 375 uint32_t disabled; 376 uint64_t disabled_mask; 377 uint32_t npt; 378 uint64_t npt_mask; 379 int64_t clock_offset; 380 QEMUTimer *qtimer; 381 }; 382 383 typedef struct CPUTimer CPUTimer; 384 385 typedef struct CPUArchState CPUSPARCState; 386 #if defined(TARGET_SPARC64) 387 typedef union { 388 uint64_t mmuregs[16]; 389 struct { 390 uint64_t tsb_tag_target; 391 uint64_t mmu_primary_context; 392 uint64_t mmu_secondary_context; 393 uint64_t sfsr; 394 uint64_t sfar; 395 uint64_t tsb; 396 uint64_t tag_access; 397 uint64_t virtual_watchpoint; 398 uint64_t physical_watchpoint; 399 uint64_t sun4v_ctx_config[2]; 400 uint64_t sun4v_tsb_pointers[4]; 401 }; 402 } SparcV9MMU; 403 #endif 404 struct CPUArchState { 405 target_ulong gregs[8]; /* general registers */ 406 target_ulong *regwptr; /* pointer to current register window */ 407 target_ulong pc; /* program counter */ 408 target_ulong npc; /* next program counter */ 409 target_ulong y; /* multiply/divide register */ 410 411 /* 412 * Bit 31 is for icc, bit 63 for xcc. 413 * Other bits are garbage. 414 */ 415 target_long cc_N; 416 target_long cc_V; 417 418 /* 419 * Z is represented as == 0; any non-zero value is !Z. 420 * For sparc64, the high 32-bits of icc.Z are garbage. 421 */ 422 target_ulong icc_Z; 423 #ifdef TARGET_SPARC64 424 target_ulong xcc_Z; 425 #endif 426 427 /* 428 * For sparc32, icc.C is boolean. 429 * For sparc64, xcc.C is boolean; 430 * icc.C is bit 32 with other bits garbage. 431 */ 432 target_ulong icc_C; 433 #ifdef TARGET_SPARC64 434 target_ulong xcc_C; 435 #endif 436 437 target_ulong cond; /* conditional branch result (XXX: save it in a 438 temporary register when possible) */ 439 440 /* FPU State Register, in parts */ 441 uint32_t fsr; /* rm, tem, aexc */ 442 uint32_t fsr_cexc_ftt; /* cexc, ftt */ 443 uint32_t fcc[TARGET_FCCREGS]; /* fcc* */ 444 445 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 446 /* 447 * Single-element FPU fault queue, with address and insn, 448 * packaged into the double-word with which it is stored. 449 */ 450 uint32_t fsr_qne; /* qne */ 451 union { 452 uint64_t d; 453 struct { 454 #if HOST_BIG_ENDIAN 455 uint32_t addr; 456 uint32_t insn; 457 #else 458 uint32_t insn; 459 uint32_t addr; 460 #endif 461 } s; 462 } fq; 463 #endif 464 465 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 466 uint32_t cwp; /* index of current register window (extracted 467 from PSR) */ 468 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 469 uint32_t wim; /* window invalid mask */ 470 #endif 471 target_ulong tbr; /* trap base register */ 472 #if !defined(TARGET_SPARC64) 473 int psrs; /* supervisor mode (extracted from PSR) */ 474 int psrps; /* previous supervisor mode */ 475 int psret; /* enable traps */ 476 #endif 477 uint32_t psrpil; /* interrupt blocking level */ 478 uint32_t pil_in; /* incoming interrupt level bitmap */ 479 #if !defined(TARGET_SPARC64) 480 int psref; /* enable fpu */ 481 #endif 482 int interrupt_index; 483 /* NOTE: we allow 8 more registers to handle wrapping */ 484 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 485 486 /* Fields up to this point are cleared by a CPU reset */ 487 struct {} end_reset_fields; 488 489 /* Fields from here on are preserved across CPU reset. */ 490 target_ulong version; 491 uint32_t nwindows; 492 493 /* MMU regs */ 494 #if defined(TARGET_SPARC64) 495 uint64_t lsu; 496 #define DMMU_E 0x8 497 #define IMMU_E 0x4 498 SparcV9MMU immu; 499 SparcV9MMU dmmu; 500 SparcTLBEntry itlb[64]; 501 SparcTLBEntry dtlb[64]; 502 uint32_t mmu_version; 503 #else 504 uint32_t mmuregs[32]; 505 uint64_t mxccdata[4]; 506 uint64_t mxccregs[8]; 507 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 508 uint64_t mmubpaction; 509 uint64_t mmubpregs[4]; 510 uint64_t prom_addr; 511 #endif 512 float_status fp_status; 513 #if defined(TARGET_SPARC64) 514 #define MAXTL_MAX 8 515 #define MAXTL_MASK (MAXTL_MAX - 1) 516 trap_state ts[MAXTL_MAX]; 517 uint32_t asi; 518 uint32_t pstate; 519 uint32_t tl; 520 uint32_t maxtl; 521 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 522 uint64_t agregs[8]; /* alternate general registers */ 523 uint64_t bgregs[8]; /* backup for normal global registers */ 524 uint64_t igregs[8]; /* interrupt general registers */ 525 uint64_t mgregs[8]; /* mmu general registers */ 526 uint64_t glregs[8 * MAXTL_MAX]; 527 uint32_t fprs; 528 uint64_t tick_cmpr, stick_cmpr; 529 CPUTimer *tick, *stick; 530 #define TICK_NPT_MASK 0x8000000000000000ULL 531 #define TICK_INT_DIS 0x8000000000000000ULL 532 uint64_t gsr; 533 uint32_t gl; // UA2005 534 /* UA 2005 hyperprivileged registers */ 535 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 536 uint64_t scratch[8]; 537 CPUTimer *hstick; // UA 2005 538 /* Interrupt vector registers */ 539 uint64_t ivec_status; 540 uint64_t ivec_data[3]; 541 uint32_t softint; 542 #define SOFTINT_TIMER 1 543 #define SOFTINT_STIMER (1 << 16) 544 #define SOFTINT_INTRMASK (0xFFFE) 545 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 546 #endif 547 sparc_def_t def; 548 549 /* Leon3 */ 550 DeviceState *irq_manager; 551 void (*qemu_irq_ack)(CPUSPARCState *env, int intno); 552 uint32_t cache_control; 553 }; 554 555 /** 556 * SPARCCPU: 557 * @env: #CPUSPARCState 558 * 559 * A SPARC CPU. 560 */ 561 struct ArchCPU { 562 CPUState parent_obj; 563 564 CPUSPARCState env; 565 }; 566 567 /** 568 * SPARCCPUClass: 569 * @parent_realize: The parent class' realize handler. 570 * @parent_phases: The parent class' reset phase handlers. 571 * 572 * A SPARC CPU model. 573 */ 574 struct SPARCCPUClass { 575 CPUClass parent_class; 576 577 DeviceRealize parent_realize; 578 ResettablePhases parent_phases; 579 const sparc_def_t *cpu_def; 580 }; 581 582 #ifndef CONFIG_USER_ONLY 583 extern const VMStateDescription vmstate_sparc_cpu; 584 585 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 586 #endif 587 588 void sparc_cpu_do_interrupt(CPUState *cpu); 589 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 590 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 591 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 592 MMUAccessType access_type, 593 int mmu_idx, 594 uintptr_t retaddr); 595 G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); 596 597 /* cpu_init.c */ 598 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 599 void sparc_cpu_list(void); 600 /* mmu_helper.c */ 601 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 602 MMUAccessType access_type, int mmu_idx, 603 bool probe, uintptr_t retaddr); 604 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 605 void dump_mmu(CPUSPARCState *env); 606 607 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 608 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 609 uint8_t *buf, size_t len, bool is_write); 610 #endif 611 612 /* translate.c */ 613 void sparc_tcg_init(void); 614 void sparc_translate_code(CPUState *cs, TranslationBlock *tb, 615 int *max_insns, vaddr pc, void *host_pc); 616 617 /* fop_helper.c */ 618 target_ulong cpu_get_fsr(CPUSPARCState *); 619 void cpu_put_fsr(CPUSPARCState *, target_ulong); 620 621 /* win_helper.c */ 622 target_ulong cpu_get_psr(CPUSPARCState *env1); 623 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 624 void cpu_put_psr_icc(CPUSPARCState *env1, target_ulong val); 625 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 626 #ifdef TARGET_SPARC64 627 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 628 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 629 #endif 630 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 631 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 632 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 633 634 /* sun4m.c, sun4u.c */ 635 void cpu_check_irqs(CPUSPARCState *env); 636 637 #if defined (TARGET_SPARC64) 638 639 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 640 { 641 return (x & mask) == (y & mask); 642 } 643 644 #define MMU_CONTEXT_BITS 13 645 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 646 647 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 648 uint64_t context) 649 { 650 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 651 } 652 653 #endif 654 655 /* cpu-exec.c */ 656 #if !defined(CONFIG_USER_ONLY) 657 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 658 vaddr addr, unsigned size, 659 MMUAccessType access_type, 660 int mmu_idx, MemTxAttrs attrs, 661 MemTxResult response, uintptr_t retaddr); 662 #if defined(TARGET_SPARC64) 663 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 664 int mmu_idx); 665 #endif 666 #endif 667 668 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 669 670 #define cpu_list sparc_cpu_list 671 672 /* MMU modes definitions */ 673 #if defined (TARGET_SPARC64) 674 #define MMU_USER_IDX 0 675 #define MMU_USER_SECONDARY_IDX 1 676 #define MMU_KERNEL_IDX 2 677 #define MMU_KERNEL_SECONDARY_IDX 3 678 #define MMU_NUCLEUS_IDX 4 679 #define MMU_PHYS_IDX 5 680 #else 681 #define MMU_USER_IDX 0 682 #define MMU_KERNEL_IDX 1 683 #define MMU_PHYS_IDX 2 684 #endif 685 686 #if defined (TARGET_SPARC64) 687 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 688 { 689 return env1->def.features & CPU_FEATURE_HYPV; 690 } 691 692 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 693 { 694 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 695 } 696 697 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 698 { 699 return env1->pstate & PS_PRIV; 700 } 701 #else 702 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 703 { 704 return env1->psrs; 705 } 706 #endif 707 708 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 709 { 710 #if !defined (TARGET_SPARC64) 711 if (env1->psret != 0) 712 return 1; 713 #else 714 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 715 return 1; 716 } 717 #endif 718 719 return 0; 720 } 721 722 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 723 { 724 #if !defined(TARGET_SPARC64) 725 /* level 15 is non-maskable on sparc v8 */ 726 return pil == 15 || pil > env1->psrpil; 727 #else 728 return pil > env1->psrpil; 729 #endif 730 } 731 732 #ifdef TARGET_SPARC64 733 /* sun4u.c */ 734 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 735 uint64_t cpu_tick_get_count(CPUTimer *timer); 736 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 737 trap_state* cpu_tsptr(CPUSPARCState* env); 738 #endif 739 740 #define TB_FLAG_MMU_MASK 7 741 #define TB_FLAG_FPU_ENABLED (1 << 4) 742 #define TB_FLAG_AM_ENABLED (1 << 5) 743 #define TB_FLAG_SUPER (1 << 6) 744 #define TB_FLAG_HYPER (1 << 7) 745 #define TB_FLAG_FSR_QNE (1 << 8) 746 #define TB_FLAG_ASI_SHIFT 24 747 748 void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 749 uint64_t *cs_base, uint32_t *pflags); 750 751 static inline bool tb_fpu_enabled(int tb_flags) 752 { 753 #if defined(CONFIG_USER_ONLY) 754 return true; 755 #else 756 return tb_flags & TB_FLAG_FPU_ENABLED; 757 #endif 758 } 759 760 static inline bool tb_am_enabled(int tb_flags) 761 { 762 #ifndef TARGET_SPARC64 763 return false; 764 #else 765 return tb_flags & TB_FLAG_AM_ENABLED; 766 #endif 767 } 768 769 #ifdef TARGET_SPARC64 770 /* win_helper.c */ 771 target_ulong cpu_get_ccr(CPUSPARCState *env1); 772 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 773 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 774 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 775 776 static inline uint64_t sparc64_tstate(CPUSPARCState *env) 777 { 778 uint64_t tstate = (cpu_get_ccr(env) << 32) | 779 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 780 cpu_get_cwp64(env); 781 782 if (env->def.features & CPU_FEATURE_GL) { 783 tstate |= (env->gl & 7ULL) << 40; 784 } 785 return tstate; 786 } 787 #endif 788 789 #endif 790