1 /* 2 * Sparc CPU init helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu/module.h" 24 #include "qemu/qemu-print.h" 25 #include "exec/exec-all.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/visitor.h" 28 #include "tcg/tcg.h" 29 30 //#define DEBUG_FEATURES 31 32 static void sparc_cpu_reset_hold(Object *obj) 33 { 34 CPUState *s = CPU(obj); 35 SPARCCPU *cpu = SPARC_CPU(s); 36 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); 37 CPUSPARCState *env = &cpu->env; 38 39 if (scc->parent_phases.hold) { 40 scc->parent_phases.hold(obj); 41 } 42 43 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); 44 env->cwp = 0; 45 #ifndef TARGET_SPARC64 46 env->wim = 1; 47 #endif 48 env->regwptr = env->regbase + (env->cwp * 16); 49 CC_OP = CC_OP_FLAGS; 50 #if defined(CONFIG_USER_ONLY) 51 #ifdef TARGET_SPARC64 52 env->cleanwin = env->nwindows - 2; 53 env->cansave = env->nwindows - 2; 54 env->pstate = PS_RMO | PS_PEF | PS_IE; 55 env->asi = 0x82; /* Primary no-fault */ 56 #endif 57 #else 58 #if !defined(TARGET_SPARC64) 59 env->psret = 0; 60 env->psrs = 1; 61 env->psrps = 1; 62 #endif 63 #ifdef TARGET_SPARC64 64 env->pstate = PS_PRIV | PS_RED | PS_PEF; 65 if (!cpu_has_hypervisor(env)) { 66 env->pstate |= PS_AG; 67 } 68 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0; 69 env->tl = env->maxtl; 70 env->gl = 2; 71 cpu_tsptr(env)->tt = TT_POWER_ON_RESET; 72 env->lsu = 0; 73 #else 74 env->mmuregs[0] &= ~(MMU_E | MMU_NF); 75 env->mmuregs[0] |= env->def.mmu_bm; 76 #endif 77 env->pc = 0; 78 env->npc = env->pc + 4; 79 #endif 80 env->cache_control = 0; 81 } 82 83 #ifndef CONFIG_USER_ONLY 84 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 85 { 86 if (interrupt_request & CPU_INTERRUPT_HARD) { 87 SPARCCPU *cpu = SPARC_CPU(cs); 88 CPUSPARCState *env = &cpu->env; 89 90 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { 91 int pil = env->interrupt_index & 0xf; 92 int type = env->interrupt_index & 0xf0; 93 94 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) { 95 cs->exception_index = env->interrupt_index; 96 sparc_cpu_do_interrupt(cs); 97 return true; 98 } 99 } 100 } 101 return false; 102 } 103 #endif /* !CONFIG_USER_ONLY */ 104 105 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) 106 { 107 info->print_insn = print_insn_sparc; 108 #ifdef TARGET_SPARC64 109 info->mach = bfd_mach_sparc_v9b; 110 #endif 111 } 112 113 static void 114 cpu_add_feat_as_prop(const char *typename, const char *name, const char *val) 115 { 116 GlobalProperty *prop = g_new0(typeof(*prop), 1); 117 prop->driver = typename; 118 prop->property = g_strdup(name); 119 prop->value = g_strdup(val); 120 qdev_prop_register_global(prop); 121 } 122 123 /* Parse "+feature,-feature,feature=foo" CPU feature string */ 124 static void sparc_cpu_parse_features(const char *typename, char *features, 125 Error **errp) 126 { 127 GList *l, *plus_features = NULL, *minus_features = NULL; 128 char *featurestr; /* Single 'key=value" string being parsed */ 129 static bool cpu_globals_initialized; 130 131 if (cpu_globals_initialized) { 132 return; 133 } 134 cpu_globals_initialized = true; 135 136 if (!features) { 137 return; 138 } 139 140 for (featurestr = strtok(features, ","); 141 featurestr; 142 featurestr = strtok(NULL, ",")) { 143 const char *name; 144 const char *val = NULL; 145 char *eq = NULL; 146 147 /* Compatibility syntax: */ 148 if (featurestr[0] == '+') { 149 plus_features = g_list_append(plus_features, 150 g_strdup(featurestr + 1)); 151 continue; 152 } else if (featurestr[0] == '-') { 153 minus_features = g_list_append(minus_features, 154 g_strdup(featurestr + 1)); 155 continue; 156 } 157 158 eq = strchr(featurestr, '='); 159 name = featurestr; 160 if (eq) { 161 *eq++ = 0; 162 val = eq; 163 164 /* 165 * Temporarily, only +feat/-feat will be supported 166 * for boolean properties until we remove the 167 * minus-overrides-plus semantics and just follow 168 * the order options appear on the command-line. 169 * 170 * TODO: warn if user is relying on minus-override-plus semantics 171 * TODO: remove minus-override-plus semantics after 172 * warning for a few releases 173 */ 174 if (!strcasecmp(val, "on") || 175 !strcasecmp(val, "off") || 176 !strcasecmp(val, "true") || 177 !strcasecmp(val, "false")) { 178 error_setg(errp, "Boolean properties in format %s=%s" 179 " are not supported", name, val); 180 return; 181 } 182 } else { 183 error_setg(errp, "Unsupported property format: %s", name); 184 return; 185 } 186 cpu_add_feat_as_prop(typename, name, val); 187 } 188 189 for (l = plus_features; l; l = l->next) { 190 const char *name = l->data; 191 cpu_add_feat_as_prop(typename, name, "on"); 192 } 193 g_list_free_full(plus_features, g_free); 194 195 for (l = minus_features; l; l = l->next) { 196 const char *name = l->data; 197 cpu_add_feat_as_prop(typename, name, "off"); 198 } 199 g_list_free_full(minus_features, g_free); 200 } 201 202 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) 203 { 204 #if !defined(TARGET_SPARC64) 205 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; 206 #endif 207 } 208 209 static const sparc_def_t sparc_defs[] = { 210 #ifdef TARGET_SPARC64 211 { 212 .name = "Fujitsu Sparc64", 213 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), 214 .fpu_version = 0x00000000, 215 .mmu_version = mmu_us_12, 216 .nwindows = 4, 217 .maxtl = 4, 218 .features = CPU_DEFAULT_FEATURES, 219 }, 220 { 221 .name = "Fujitsu Sparc64 III", 222 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), 223 .fpu_version = 0x00000000, 224 .mmu_version = mmu_us_12, 225 .nwindows = 5, 226 .maxtl = 4, 227 .features = CPU_DEFAULT_FEATURES, 228 }, 229 { 230 .name = "Fujitsu Sparc64 IV", 231 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), 232 .fpu_version = 0x00000000, 233 .mmu_version = mmu_us_12, 234 .nwindows = 8, 235 .maxtl = 5, 236 .features = CPU_DEFAULT_FEATURES, 237 }, 238 { 239 .name = "Fujitsu Sparc64 V", 240 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), 241 .fpu_version = 0x00000000, 242 .mmu_version = mmu_us_12, 243 .nwindows = 8, 244 .maxtl = 5, 245 .features = CPU_DEFAULT_FEATURES, 246 }, 247 { 248 .name = "TI UltraSparc I", 249 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 250 .fpu_version = 0x00000000, 251 .mmu_version = mmu_us_12, 252 .nwindows = 8, 253 .maxtl = 5, 254 .features = CPU_DEFAULT_FEATURES, 255 }, 256 { 257 .name = "TI UltraSparc II", 258 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), 259 .fpu_version = 0x00000000, 260 .mmu_version = mmu_us_12, 261 .nwindows = 8, 262 .maxtl = 5, 263 .features = CPU_DEFAULT_FEATURES, 264 }, 265 { 266 .name = "TI UltraSparc IIi", 267 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), 268 .fpu_version = 0x00000000, 269 .mmu_version = mmu_us_12, 270 .nwindows = 8, 271 .maxtl = 5, 272 .features = CPU_DEFAULT_FEATURES, 273 }, 274 { 275 .name = "TI UltraSparc IIe", 276 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), 277 .fpu_version = 0x00000000, 278 .mmu_version = mmu_us_12, 279 .nwindows = 8, 280 .maxtl = 5, 281 .features = CPU_DEFAULT_FEATURES, 282 }, 283 { 284 .name = "Sun UltraSparc III", 285 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), 286 .fpu_version = 0x00000000, 287 .mmu_version = mmu_us_12, 288 .nwindows = 8, 289 .maxtl = 5, 290 .features = CPU_DEFAULT_FEATURES, 291 }, 292 { 293 .name = "Sun UltraSparc III Cu", 294 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), 295 .fpu_version = 0x00000000, 296 .mmu_version = mmu_us_3, 297 .nwindows = 8, 298 .maxtl = 5, 299 .features = CPU_DEFAULT_FEATURES, 300 }, 301 { 302 .name = "Sun UltraSparc IIIi", 303 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), 304 .fpu_version = 0x00000000, 305 .mmu_version = mmu_us_12, 306 .nwindows = 8, 307 .maxtl = 5, 308 .features = CPU_DEFAULT_FEATURES, 309 }, 310 { 311 .name = "Sun UltraSparc IV", 312 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), 313 .fpu_version = 0x00000000, 314 .mmu_version = mmu_us_4, 315 .nwindows = 8, 316 .maxtl = 5, 317 .features = CPU_DEFAULT_FEATURES, 318 }, 319 { 320 .name = "Sun UltraSparc IV+", 321 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), 322 .fpu_version = 0x00000000, 323 .mmu_version = mmu_us_12, 324 .nwindows = 8, 325 .maxtl = 5, 326 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, 327 }, 328 { 329 .name = "Sun UltraSparc IIIi+", 330 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), 331 .fpu_version = 0x00000000, 332 .mmu_version = mmu_us_3, 333 .nwindows = 8, 334 .maxtl = 5, 335 .features = CPU_DEFAULT_FEATURES, 336 }, 337 { 338 .name = "Sun UltraSparc T1", 339 /* defined in sparc_ifu_fdp.v and ctu.h */ 340 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), 341 .fpu_version = 0x00000000, 342 .mmu_version = mmu_sun4v, 343 .nwindows = 8, 344 .maxtl = 6, 345 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 346 | CPU_FEATURE_GL, 347 }, 348 { 349 .name = "Sun UltraSparc T2", 350 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ 351 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), 352 .fpu_version = 0x00000000, 353 .mmu_version = mmu_sun4v, 354 .nwindows = 8, 355 .maxtl = 6, 356 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 357 | CPU_FEATURE_GL, 358 }, 359 { 360 .name = "NEC UltraSparc I", 361 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 362 .fpu_version = 0x00000000, 363 .mmu_version = mmu_us_12, 364 .nwindows = 8, 365 .maxtl = 5, 366 .features = CPU_DEFAULT_FEATURES, 367 }, 368 #else 369 { 370 .name = "Fujitsu MB86904", 371 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ 372 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 373 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ 374 .mmu_bm = 0x00004000, 375 .mmu_ctpr_mask = 0x00ffffc0, 376 .mmu_cxr_mask = 0x000000ff, 377 .mmu_sfsr_mask = 0x00016fff, 378 .mmu_trcr_mask = 0x00ffffff, 379 .nwindows = 8, 380 .features = CPU_DEFAULT_FEATURES, 381 }, 382 { 383 .name = "Fujitsu MB86907", 384 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ 385 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 386 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ 387 .mmu_bm = 0x00004000, 388 .mmu_ctpr_mask = 0xffffffc0, 389 .mmu_cxr_mask = 0x000000ff, 390 .mmu_sfsr_mask = 0x00016fff, 391 .mmu_trcr_mask = 0xffffffff, 392 .nwindows = 8, 393 .features = CPU_DEFAULT_FEATURES, 394 }, 395 { 396 .name = "TI MicroSparc I", 397 .iu_version = 0x41000000, 398 .fpu_version = 4 << 17, 399 .mmu_version = 0x41000000, 400 .mmu_bm = 0x00004000, 401 .mmu_ctpr_mask = 0x007ffff0, 402 .mmu_cxr_mask = 0x0000003f, 403 .mmu_sfsr_mask = 0x00016fff, 404 .mmu_trcr_mask = 0x0000003f, 405 .nwindows = 7, 406 .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV, 407 }, 408 { 409 .name = "TI MicroSparc II", 410 .iu_version = 0x42000000, 411 .fpu_version = 4 << 17, 412 .mmu_version = 0x02000000, 413 .mmu_bm = 0x00004000, 414 .mmu_ctpr_mask = 0x00ffffc0, 415 .mmu_cxr_mask = 0x000000ff, 416 .mmu_sfsr_mask = 0x00016fff, 417 .mmu_trcr_mask = 0x00ffffff, 418 .nwindows = 8, 419 .features = CPU_DEFAULT_FEATURES, 420 }, 421 { 422 .name = "TI MicroSparc IIep", 423 .iu_version = 0x42000000, 424 .fpu_version = 4 << 17, 425 .mmu_version = 0x04000000, 426 .mmu_bm = 0x00004000, 427 .mmu_ctpr_mask = 0x00ffffc0, 428 .mmu_cxr_mask = 0x000000ff, 429 .mmu_sfsr_mask = 0x00016bff, 430 .mmu_trcr_mask = 0x00ffffff, 431 .nwindows = 8, 432 .features = CPU_DEFAULT_FEATURES, 433 }, 434 { 435 .name = "TI SuperSparc 40", /* STP1020NPGA */ 436 .iu_version = 0x41000000, /* SuperSPARC 2.x */ 437 .fpu_version = 0 << 17, 438 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ 439 .mmu_bm = 0x00002000, 440 .mmu_ctpr_mask = 0xffffffc0, 441 .mmu_cxr_mask = 0x0000ffff, 442 .mmu_sfsr_mask = 0xffffffff, 443 .mmu_trcr_mask = 0xffffffff, 444 .nwindows = 8, 445 .features = CPU_DEFAULT_FEATURES, 446 }, 447 { 448 .name = "TI SuperSparc 50", /* STP1020PGA */ 449 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 450 .fpu_version = 0 << 17, 451 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 452 .mmu_bm = 0x00002000, 453 .mmu_ctpr_mask = 0xffffffc0, 454 .mmu_cxr_mask = 0x0000ffff, 455 .mmu_sfsr_mask = 0xffffffff, 456 .mmu_trcr_mask = 0xffffffff, 457 .nwindows = 8, 458 .features = CPU_DEFAULT_FEATURES, 459 }, 460 { 461 .name = "TI SuperSparc 51", 462 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 463 .fpu_version = 0 << 17, 464 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 465 .mmu_bm = 0x00002000, 466 .mmu_ctpr_mask = 0xffffffc0, 467 .mmu_cxr_mask = 0x0000ffff, 468 .mmu_sfsr_mask = 0xffffffff, 469 .mmu_trcr_mask = 0xffffffff, 470 .mxcc_version = 0x00000104, 471 .nwindows = 8, 472 .features = CPU_DEFAULT_FEATURES, 473 }, 474 { 475 .name = "TI SuperSparc 60", /* STP1020APGA */ 476 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 477 .fpu_version = 0 << 17, 478 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 479 .mmu_bm = 0x00002000, 480 .mmu_ctpr_mask = 0xffffffc0, 481 .mmu_cxr_mask = 0x0000ffff, 482 .mmu_sfsr_mask = 0xffffffff, 483 .mmu_trcr_mask = 0xffffffff, 484 .nwindows = 8, 485 .features = CPU_DEFAULT_FEATURES, 486 }, 487 { 488 .name = "TI SuperSparc 61", 489 .iu_version = 0x44000000, /* SuperSPARC 3.x */ 490 .fpu_version = 0 << 17, 491 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 492 .mmu_bm = 0x00002000, 493 .mmu_ctpr_mask = 0xffffffc0, 494 .mmu_cxr_mask = 0x0000ffff, 495 .mmu_sfsr_mask = 0xffffffff, 496 .mmu_trcr_mask = 0xffffffff, 497 .mxcc_version = 0x00000104, 498 .nwindows = 8, 499 .features = CPU_DEFAULT_FEATURES, 500 }, 501 { 502 .name = "TI SuperSparc II", 503 .iu_version = 0x40000000, /* SuperSPARC II 1.x */ 504 .fpu_version = 0 << 17, 505 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ 506 .mmu_bm = 0x00002000, 507 .mmu_ctpr_mask = 0xffffffc0, 508 .mmu_cxr_mask = 0x0000ffff, 509 .mmu_sfsr_mask = 0xffffffff, 510 .mmu_trcr_mask = 0xffffffff, 511 .mxcc_version = 0x00000104, 512 .nwindows = 8, 513 .features = CPU_DEFAULT_FEATURES, 514 }, 515 { 516 .name = "LEON2", 517 .iu_version = 0xf2000000, 518 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 519 .mmu_version = 0xf2000000, 520 .mmu_bm = 0x00004000, 521 .mmu_ctpr_mask = 0x007ffff0, 522 .mmu_cxr_mask = 0x0000003f, 523 .mmu_sfsr_mask = 0xffffffff, 524 .mmu_trcr_mask = 0xffffffff, 525 .nwindows = 8, 526 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, 527 }, 528 { 529 .name = "LEON3", 530 .iu_version = 0xf3000000, 531 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 532 .mmu_version = 0xf3000000, 533 .mmu_bm = 0x00000000, 534 .mmu_ctpr_mask = 0xfffffffc, 535 .mmu_cxr_mask = 0x000000ff, 536 .mmu_sfsr_mask = 0xffffffff, 537 .mmu_trcr_mask = 0xffffffff, 538 .nwindows = 8, 539 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | 540 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | 541 CPU_FEATURE_CASA, 542 }, 543 #endif 544 }; 545 546 /* This must match sparc_cpu_properties[]. */ 547 static const char * const feature_name[] = { 548 [CPU_FEATURE_BIT_FLOAT128] = "float128", 549 #ifdef TARGET_SPARC64 550 [CPU_FEATURE_BIT_CMT] = "cmt", 551 [CPU_FEATURE_BIT_GL] = "gl", 552 [CPU_FEATURE_BIT_HYPV] = "hypv", 553 [CPU_FEATURE_BIT_VIS1] = "vis1", 554 [CPU_FEATURE_BIT_VIS2] = "vis2", 555 #else 556 [CPU_FEATURE_BIT_MUL] = "mul", 557 [CPU_FEATURE_BIT_DIV] = "div", 558 [CPU_FEATURE_BIT_FSMULD] = "fsmuld", 559 #endif 560 }; 561 562 static void print_features(uint32_t features, const char *prefix) 563 { 564 unsigned int i; 565 566 for (i = 0; i < ARRAY_SIZE(feature_name); i++) { 567 if (feature_name[i] && (features & (1 << i))) { 568 if (prefix) { 569 qemu_printf("%s", prefix); 570 } 571 qemu_printf("%s ", feature_name[i]); 572 } 573 } 574 } 575 576 void sparc_cpu_list(void) 577 { 578 unsigned int i; 579 580 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 581 qemu_printf("Sparc %16s IU " TARGET_FMT_lx 582 " FPU %08x MMU %08x NWINS %d ", 583 sparc_defs[i].name, 584 sparc_defs[i].iu_version, 585 sparc_defs[i].fpu_version, 586 sparc_defs[i].mmu_version, 587 sparc_defs[i].nwindows); 588 print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-"); 589 print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+"); 590 qemu_printf("\n"); 591 } 592 qemu_printf("Default CPU feature flags (use '-' to remove): "); 593 print_features(CPU_DEFAULT_FEATURES, NULL); 594 qemu_printf("\n"); 595 qemu_printf("Available CPU feature flags (use '+' to add): "); 596 print_features(~CPU_DEFAULT_FEATURES, NULL); 597 qemu_printf("\n"); 598 qemu_printf("Numerical features (use '=' to set): iu_version " 599 "fpu_version mmu_version nwindows\n"); 600 } 601 602 static void cpu_print_cc(FILE *f, uint32_t cc) 603 { 604 qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', 605 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', 606 cc & PSR_CARRY ? 'C' : '-'); 607 } 608 609 #ifdef TARGET_SPARC64 610 #define REGS_PER_LINE 4 611 #else 612 #define REGS_PER_LINE 8 613 #endif 614 615 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 616 { 617 SPARCCPU *cpu = SPARC_CPU(cs); 618 CPUSPARCState *env = &cpu->env; 619 int i, x; 620 621 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, 622 env->npc); 623 624 for (i = 0; i < 8; i++) { 625 if (i % REGS_PER_LINE == 0) { 626 qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); 627 } 628 qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); 629 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 630 qemu_fprintf(f, "\n"); 631 } 632 } 633 for (x = 0; x < 3; x++) { 634 for (i = 0; i < 8; i++) { 635 if (i % REGS_PER_LINE == 0) { 636 qemu_fprintf(f, "%%%c%d-%d: ", 637 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), 638 i, i + REGS_PER_LINE - 1); 639 } 640 qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); 641 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 642 qemu_fprintf(f, "\n"); 643 } 644 } 645 } 646 647 if (flags & CPU_DUMP_FPU) { 648 for (i = 0; i < TARGET_DPREGS; i++) { 649 if ((i & 3) == 0) { 650 qemu_fprintf(f, "%%f%02d: ", i * 2); 651 } 652 qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); 653 if ((i & 3) == 3) { 654 qemu_fprintf(f, "\n"); 655 } 656 } 657 } 658 659 #ifdef TARGET_SPARC64 660 qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, 661 (unsigned)cpu_get_ccr(env)); 662 cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT); 663 qemu_fprintf(f, " xcc: "); 664 cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); 665 qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl, 666 env->psrpil, env->gl); 667 qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: " 668 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); 669 qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " 670 "cleanwin: %d cwp: %d\n", 671 env->cansave, env->canrestore, env->otherwin, env->wstate, 672 env->cleanwin, env->nwindows - 1 - env->cwp); 673 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n", 674 env->fsr, env->y, env->fprs); 675 676 #else 677 qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); 678 cpu_print_cc(f, cpu_get_psr(env)); 679 qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', 680 env->psrps ? 'P' : '-', env->psret ? 'E' : '-', 681 env->wim); 682 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", 683 env->fsr, env->y); 684 #endif 685 qemu_fprintf(f, "\n"); 686 } 687 688 static void sparc_cpu_set_pc(CPUState *cs, vaddr value) 689 { 690 SPARCCPU *cpu = SPARC_CPU(cs); 691 692 cpu->env.pc = value; 693 cpu->env.npc = value + 4; 694 } 695 696 static vaddr sparc_cpu_get_pc(CPUState *cs) 697 { 698 SPARCCPU *cpu = SPARC_CPU(cs); 699 700 return cpu->env.pc; 701 } 702 703 static void sparc_cpu_synchronize_from_tb(CPUState *cs, 704 const TranslationBlock *tb) 705 { 706 SPARCCPU *cpu = SPARC_CPU(cs); 707 708 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 709 cpu->env.pc = tb->pc; 710 cpu->env.npc = tb->cs_base; 711 } 712 713 static bool sparc_cpu_has_work(CPUState *cs) 714 { 715 SPARCCPU *cpu = SPARC_CPU(cs); 716 CPUSPARCState *env = &cpu->env; 717 718 return (cs->interrupt_request & CPU_INTERRUPT_HARD) && 719 cpu_interrupts_enabled(env); 720 } 721 722 static char *sparc_cpu_type_name(const char *cpu_model) 723 { 724 char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model); 725 char *s = name; 726 727 /* SPARC cpu model names happen to have whitespaces, 728 * as type names shouldn't have spaces replace them with '-' 729 */ 730 while ((s = strchr(s, ' '))) { 731 *s = '-'; 732 } 733 734 return name; 735 } 736 737 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model) 738 { 739 ObjectClass *oc; 740 char *typename; 741 742 typename = sparc_cpu_type_name(cpu_model); 743 oc = object_class_by_name(typename); 744 g_free(typename); 745 return oc; 746 } 747 748 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) 749 { 750 CPUState *cs = CPU(dev); 751 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); 752 Error *local_err = NULL; 753 SPARCCPU *cpu = SPARC_CPU(dev); 754 CPUSPARCState *env = &cpu->env; 755 756 #if defined(CONFIG_USER_ONLY) 757 /* We are emulating the kernel, which will trap and emulate float128. */ 758 env->def.features |= CPU_FEATURE_FLOAT128; 759 #endif 760 761 env->version = env->def.iu_version; 762 env->fsr = env->def.fpu_version; 763 env->nwindows = env->def.nwindows; 764 #if !defined(TARGET_SPARC64) 765 env->mmuregs[0] |= env->def.mmu_version; 766 cpu_sparc_set_id(env, 0); 767 env->mxccregs[7] |= env->def.mxcc_version; 768 #else 769 env->mmu_version = env->def.mmu_version; 770 env->maxtl = env->def.maxtl; 771 env->version |= env->def.maxtl << 8; 772 env->version |= env->def.nwindows - 1; 773 #endif 774 775 cpu_exec_realizefn(cs, &local_err); 776 if (local_err != NULL) { 777 error_propagate(errp, local_err); 778 return; 779 } 780 781 qemu_init_vcpu(cs); 782 783 scc->parent_realize(dev, errp); 784 } 785 786 static void sparc_cpu_initfn(Object *obj) 787 { 788 SPARCCPU *cpu = SPARC_CPU(obj); 789 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); 790 CPUSPARCState *env = &cpu->env; 791 792 if (scc->cpu_def) { 793 env->def = *scc->cpu_def; 794 } 795 } 796 797 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name, 798 void *opaque, Error **errp) 799 { 800 SPARCCPU *cpu = SPARC_CPU(obj); 801 int64_t value = cpu->env.def.nwindows; 802 803 visit_type_int(v, name, &value, errp); 804 } 805 806 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name, 807 void *opaque, Error **errp) 808 { 809 const int64_t min = MIN_NWINDOWS; 810 const int64_t max = MAX_NWINDOWS; 811 SPARCCPU *cpu = SPARC_CPU(obj); 812 int64_t value; 813 814 if (!visit_type_int(v, name, &value, errp)) { 815 return; 816 } 817 818 if (value < min || value > max) { 819 error_setg(errp, "Property %s.%s doesn't take value %" PRId64 820 " (minimum: %" PRId64 ", maximum: %" PRId64 ")", 821 object_get_typename(obj), name ? name : "null", 822 value, min, max); 823 return; 824 } 825 cpu->env.def.nwindows = value; 826 } 827 828 static PropertyInfo qdev_prop_nwindows = { 829 .name = "int", 830 .get = sparc_get_nwindows, 831 .set = sparc_set_nwindows, 832 }; 833 834 /* This must match feature_name[]. */ 835 static Property sparc_cpu_properties[] = { 836 DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 837 CPU_FEATURE_BIT_FLOAT128, false), 838 #ifdef TARGET_SPARC64 839 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 840 CPU_FEATURE_BIT_CMT, false), 841 DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 842 CPU_FEATURE_BIT_GL, false), 843 DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 844 CPU_FEATURE_BIT_HYPV, false), 845 DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 846 CPU_FEATURE_BIT_VIS1, false), 847 DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 848 CPU_FEATURE_BIT_VIS2, false), 849 #else 850 DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 851 CPU_FEATURE_BIT_MUL, false), 852 DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 853 CPU_FEATURE_BIT_DIV, false), 854 DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 855 CPU_FEATURE_BIT_FSMULD, false), 856 #endif 857 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0, 858 qdev_prop_uint64, target_ulong), 859 DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0), 860 DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0), 861 DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows, 862 qdev_prop_nwindows, uint32_t), 863 DEFINE_PROP_END_OF_LIST() 864 }; 865 866 #ifndef CONFIG_USER_ONLY 867 #include "hw/core/sysemu-cpu-ops.h" 868 869 static const struct SysemuCPUOps sparc_sysemu_ops = { 870 .get_phys_page_debug = sparc_cpu_get_phys_page_debug, 871 .legacy_vmsd = &vmstate_sparc_cpu, 872 }; 873 #endif 874 875 #ifdef CONFIG_TCG 876 #include "hw/core/tcg-cpu-ops.h" 877 878 static const struct TCGCPUOps sparc_tcg_ops = { 879 .initialize = sparc_tcg_init, 880 .synchronize_from_tb = sparc_cpu_synchronize_from_tb, 881 .restore_state_to_opc = sparc_restore_state_to_opc, 882 883 #ifndef CONFIG_USER_ONLY 884 .tlb_fill = sparc_cpu_tlb_fill, 885 .cpu_exec_interrupt = sparc_cpu_exec_interrupt, 886 .do_interrupt = sparc_cpu_do_interrupt, 887 .do_transaction_failed = sparc_cpu_do_transaction_failed, 888 .do_unaligned_access = sparc_cpu_do_unaligned_access, 889 #endif /* !CONFIG_USER_ONLY */ 890 }; 891 #endif /* CONFIG_TCG */ 892 893 static void sparc_cpu_class_init(ObjectClass *oc, void *data) 894 { 895 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 896 CPUClass *cc = CPU_CLASS(oc); 897 DeviceClass *dc = DEVICE_CLASS(oc); 898 ResettableClass *rc = RESETTABLE_CLASS(oc); 899 900 device_class_set_parent_realize(dc, sparc_cpu_realizefn, 901 &scc->parent_realize); 902 device_class_set_props(dc, sparc_cpu_properties); 903 904 resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL, 905 &scc->parent_phases); 906 907 cc->class_by_name = sparc_cpu_class_by_name; 908 cc->parse_features = sparc_cpu_parse_features; 909 cc->has_work = sparc_cpu_has_work; 910 cc->dump_state = sparc_cpu_dump_state; 911 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 912 cc->memory_rw_debug = sparc_cpu_memory_rw_debug; 913 #endif 914 cc->set_pc = sparc_cpu_set_pc; 915 cc->get_pc = sparc_cpu_get_pc; 916 cc->gdb_read_register = sparc_cpu_gdb_read_register; 917 cc->gdb_write_register = sparc_cpu_gdb_write_register; 918 #ifndef CONFIG_USER_ONLY 919 cc->sysemu_ops = &sparc_sysemu_ops; 920 #endif 921 cc->disas_set_info = cpu_sparc_disas_set_info; 922 923 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 924 cc->gdb_num_core_regs = 86; 925 #else 926 cc->gdb_num_core_regs = 72; 927 #endif 928 cc->tcg_ops = &sparc_tcg_ops; 929 } 930 931 static const TypeInfo sparc_cpu_type_info = { 932 .name = TYPE_SPARC_CPU, 933 .parent = TYPE_CPU, 934 .instance_size = sizeof(SPARCCPU), 935 .instance_align = __alignof(SPARCCPU), 936 .instance_init = sparc_cpu_initfn, 937 .abstract = true, 938 .class_size = sizeof(SPARCCPUClass), 939 .class_init = sparc_cpu_class_init, 940 }; 941 942 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data) 943 { 944 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 945 scc->cpu_def = data; 946 } 947 948 static void sparc_register_cpudef_type(const struct sparc_def_t *def) 949 { 950 char *typename = sparc_cpu_type_name(def->name); 951 TypeInfo ti = { 952 .name = typename, 953 .parent = TYPE_SPARC_CPU, 954 .class_init = sparc_cpu_cpudef_class_init, 955 .class_data = (void *)def, 956 }; 957 958 type_register(&ti); 959 g_free(typename); 960 } 961 962 static void sparc_cpu_register_types(void) 963 { 964 int i; 965 966 type_register_static(&sparc_cpu_type_info); 967 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 968 sparc_register_cpudef_type(&sparc_defs[i]); 969 } 970 } 971 972 type_init(sparc_cpu_register_types) 973