1 /* 2 * Sparc CPU init helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu/error-report.h" 24 #include "exec/exec-all.h" 25 #include "hw/qdev-properties.h" 26 #include "qapi/visitor.h" 27 28 //#define DEBUG_FEATURES 29 30 /* CPUClass::reset() */ 31 static void sparc_cpu_reset(CPUState *s) 32 { 33 SPARCCPU *cpu = SPARC_CPU(s); 34 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); 35 CPUSPARCState *env = &cpu->env; 36 37 scc->parent_reset(s); 38 39 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); 40 env->cwp = 0; 41 #ifndef TARGET_SPARC64 42 env->wim = 1; 43 #endif 44 env->regwptr = env->regbase + (env->cwp * 16); 45 CC_OP = CC_OP_FLAGS; 46 #if defined(CONFIG_USER_ONLY) 47 #ifdef TARGET_SPARC64 48 env->cleanwin = env->nwindows - 2; 49 env->cansave = env->nwindows - 2; 50 env->pstate = PS_RMO | PS_PEF | PS_IE; 51 env->asi = 0x82; /* Primary no-fault */ 52 #endif 53 #else 54 #if !defined(TARGET_SPARC64) 55 env->psret = 0; 56 env->psrs = 1; 57 env->psrps = 1; 58 #endif 59 #ifdef TARGET_SPARC64 60 env->pstate = PS_PRIV | PS_RED | PS_PEF; 61 if (!cpu_has_hypervisor(env)) { 62 env->pstate |= PS_AG; 63 } 64 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0; 65 env->tl = env->maxtl; 66 env->gl = 2; 67 cpu_tsptr(env)->tt = TT_POWER_ON_RESET; 68 env->lsu = 0; 69 #else 70 env->mmuregs[0] &= ~(MMU_E | MMU_NF); 71 env->mmuregs[0] |= env->def.mmu_bm; 72 #endif 73 env->pc = 0; 74 env->npc = env->pc + 4; 75 #endif 76 env->cache_control = 0; 77 } 78 79 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 80 { 81 if (interrupt_request & CPU_INTERRUPT_HARD) { 82 SPARCCPU *cpu = SPARC_CPU(cs); 83 CPUSPARCState *env = &cpu->env; 84 85 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { 86 int pil = env->interrupt_index & 0xf; 87 int type = env->interrupt_index & 0xf0; 88 89 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) { 90 cs->exception_index = env->interrupt_index; 91 sparc_cpu_do_interrupt(cs); 92 return true; 93 } 94 } 95 } 96 return false; 97 } 98 99 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) 100 { 101 info->print_insn = print_insn_sparc; 102 #ifdef TARGET_SPARC64 103 info->mach = bfd_mach_sparc_v9b; 104 #endif 105 } 106 107 static void sparc_cpu_parse_features(CPUState *cs, char *features, 108 Error **errp); 109 110 static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model) 111 { 112 char *s = g_strdup(cpu_model); 113 char *featurestr = strtok(s, ","); 114 Error *err = NULL; 115 116 featurestr = strtok(NULL, ","); 117 sparc_cpu_parse_features(CPU(cpu), featurestr, &err); 118 g_free(s); 119 if (err) { 120 error_report_err(err); 121 return -1; 122 } 123 124 return 0; 125 } 126 127 SPARCCPU *cpu_sparc_init(const char *cpu_model) 128 { 129 SPARCCPU *cpu; 130 ObjectClass *oc; 131 char *str, *name; 132 133 str = g_strdup(cpu_model); 134 name = strtok(str, ","); 135 oc = cpu_class_by_name(TYPE_SPARC_CPU, name); 136 g_free(str); 137 if (oc == NULL) { 138 return NULL; 139 } 140 141 cpu = SPARC_CPU(object_new(object_class_get_name(oc))); 142 143 if (cpu_sparc_register(cpu, cpu_model) < 0) { 144 object_unref(OBJECT(cpu)); 145 return NULL; 146 } 147 148 object_property_set_bool(OBJECT(cpu), true, "realized", NULL); 149 150 return cpu; 151 } 152 153 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) 154 { 155 #if !defined(TARGET_SPARC64) 156 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; 157 #endif 158 } 159 160 static const sparc_def_t sparc_defs[] = { 161 #ifdef TARGET_SPARC64 162 { 163 .name = "Fujitsu Sparc64", 164 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), 165 .fpu_version = 0x00000000, 166 .mmu_version = mmu_us_12, 167 .nwindows = 4, 168 .maxtl = 4, 169 .features = CPU_DEFAULT_FEATURES, 170 }, 171 { 172 .name = "Fujitsu Sparc64 III", 173 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), 174 .fpu_version = 0x00000000, 175 .mmu_version = mmu_us_12, 176 .nwindows = 5, 177 .maxtl = 4, 178 .features = CPU_DEFAULT_FEATURES, 179 }, 180 { 181 .name = "Fujitsu Sparc64 IV", 182 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), 183 .fpu_version = 0x00000000, 184 .mmu_version = mmu_us_12, 185 .nwindows = 8, 186 .maxtl = 5, 187 .features = CPU_DEFAULT_FEATURES, 188 }, 189 { 190 .name = "Fujitsu Sparc64 V", 191 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), 192 .fpu_version = 0x00000000, 193 .mmu_version = mmu_us_12, 194 .nwindows = 8, 195 .maxtl = 5, 196 .features = CPU_DEFAULT_FEATURES, 197 }, 198 { 199 .name = "TI UltraSparc I", 200 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 201 .fpu_version = 0x00000000, 202 .mmu_version = mmu_us_12, 203 .nwindows = 8, 204 .maxtl = 5, 205 .features = CPU_DEFAULT_FEATURES, 206 }, 207 { 208 .name = "TI UltraSparc II", 209 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), 210 .fpu_version = 0x00000000, 211 .mmu_version = mmu_us_12, 212 .nwindows = 8, 213 .maxtl = 5, 214 .features = CPU_DEFAULT_FEATURES, 215 }, 216 { 217 .name = "TI UltraSparc IIi", 218 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), 219 .fpu_version = 0x00000000, 220 .mmu_version = mmu_us_12, 221 .nwindows = 8, 222 .maxtl = 5, 223 .features = CPU_DEFAULT_FEATURES, 224 }, 225 { 226 .name = "TI UltraSparc IIe", 227 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), 228 .fpu_version = 0x00000000, 229 .mmu_version = mmu_us_12, 230 .nwindows = 8, 231 .maxtl = 5, 232 .features = CPU_DEFAULT_FEATURES, 233 }, 234 { 235 .name = "Sun UltraSparc III", 236 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), 237 .fpu_version = 0x00000000, 238 .mmu_version = mmu_us_12, 239 .nwindows = 8, 240 .maxtl = 5, 241 .features = CPU_DEFAULT_FEATURES, 242 }, 243 { 244 .name = "Sun UltraSparc III Cu", 245 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), 246 .fpu_version = 0x00000000, 247 .mmu_version = mmu_us_3, 248 .nwindows = 8, 249 .maxtl = 5, 250 .features = CPU_DEFAULT_FEATURES, 251 }, 252 { 253 .name = "Sun UltraSparc IIIi", 254 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), 255 .fpu_version = 0x00000000, 256 .mmu_version = mmu_us_12, 257 .nwindows = 8, 258 .maxtl = 5, 259 .features = CPU_DEFAULT_FEATURES, 260 }, 261 { 262 .name = "Sun UltraSparc IV", 263 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), 264 .fpu_version = 0x00000000, 265 .mmu_version = mmu_us_4, 266 .nwindows = 8, 267 .maxtl = 5, 268 .features = CPU_DEFAULT_FEATURES, 269 }, 270 { 271 .name = "Sun UltraSparc IV+", 272 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), 273 .fpu_version = 0x00000000, 274 .mmu_version = mmu_us_12, 275 .nwindows = 8, 276 .maxtl = 5, 277 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, 278 }, 279 { 280 .name = "Sun UltraSparc IIIi+", 281 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), 282 .fpu_version = 0x00000000, 283 .mmu_version = mmu_us_3, 284 .nwindows = 8, 285 .maxtl = 5, 286 .features = CPU_DEFAULT_FEATURES, 287 }, 288 { 289 .name = "Sun UltraSparc T1", 290 /* defined in sparc_ifu_fdp.v and ctu.h */ 291 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), 292 .fpu_version = 0x00000000, 293 .mmu_version = mmu_sun4v, 294 .nwindows = 8, 295 .maxtl = 6, 296 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 297 | CPU_FEATURE_GL, 298 }, 299 { 300 .name = "Sun UltraSparc T2", 301 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ 302 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), 303 .fpu_version = 0x00000000, 304 .mmu_version = mmu_sun4v, 305 .nwindows = 8, 306 .maxtl = 6, 307 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 308 | CPU_FEATURE_GL, 309 }, 310 { 311 .name = "NEC UltraSparc I", 312 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 313 .fpu_version = 0x00000000, 314 .mmu_version = mmu_us_12, 315 .nwindows = 8, 316 .maxtl = 5, 317 .features = CPU_DEFAULT_FEATURES, 318 }, 319 #else 320 { 321 .name = "Fujitsu MB86904", 322 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ 323 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 324 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ 325 .mmu_bm = 0x00004000, 326 .mmu_ctpr_mask = 0x00ffffc0, 327 .mmu_cxr_mask = 0x000000ff, 328 .mmu_sfsr_mask = 0x00016fff, 329 .mmu_trcr_mask = 0x00ffffff, 330 .nwindows = 8, 331 .features = CPU_DEFAULT_FEATURES, 332 }, 333 { 334 .name = "Fujitsu MB86907", 335 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ 336 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 337 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ 338 .mmu_bm = 0x00004000, 339 .mmu_ctpr_mask = 0xffffffc0, 340 .mmu_cxr_mask = 0x000000ff, 341 .mmu_sfsr_mask = 0x00016fff, 342 .mmu_trcr_mask = 0xffffffff, 343 .nwindows = 8, 344 .features = CPU_DEFAULT_FEATURES, 345 }, 346 { 347 .name = "TI MicroSparc I", 348 .iu_version = 0x41000000, 349 .fpu_version = 4 << 17, 350 .mmu_version = 0x41000000, 351 .mmu_bm = 0x00004000, 352 .mmu_ctpr_mask = 0x007ffff0, 353 .mmu_cxr_mask = 0x0000003f, 354 .mmu_sfsr_mask = 0x00016fff, 355 .mmu_trcr_mask = 0x0000003f, 356 .nwindows = 7, 357 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | 358 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | 359 CPU_FEATURE_FMUL, 360 }, 361 { 362 .name = "TI MicroSparc II", 363 .iu_version = 0x42000000, 364 .fpu_version = 4 << 17, 365 .mmu_version = 0x02000000, 366 .mmu_bm = 0x00004000, 367 .mmu_ctpr_mask = 0x00ffffc0, 368 .mmu_cxr_mask = 0x000000ff, 369 .mmu_sfsr_mask = 0x00016fff, 370 .mmu_trcr_mask = 0x00ffffff, 371 .nwindows = 8, 372 .features = CPU_DEFAULT_FEATURES, 373 }, 374 { 375 .name = "TI MicroSparc IIep", 376 .iu_version = 0x42000000, 377 .fpu_version = 4 << 17, 378 .mmu_version = 0x04000000, 379 .mmu_bm = 0x00004000, 380 .mmu_ctpr_mask = 0x00ffffc0, 381 .mmu_cxr_mask = 0x000000ff, 382 .mmu_sfsr_mask = 0x00016bff, 383 .mmu_trcr_mask = 0x00ffffff, 384 .nwindows = 8, 385 .features = CPU_DEFAULT_FEATURES, 386 }, 387 { 388 .name = "TI SuperSparc 40", /* STP1020NPGA */ 389 .iu_version = 0x41000000, /* SuperSPARC 2.x */ 390 .fpu_version = 0 << 17, 391 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ 392 .mmu_bm = 0x00002000, 393 .mmu_ctpr_mask = 0xffffffc0, 394 .mmu_cxr_mask = 0x0000ffff, 395 .mmu_sfsr_mask = 0xffffffff, 396 .mmu_trcr_mask = 0xffffffff, 397 .nwindows = 8, 398 .features = CPU_DEFAULT_FEATURES, 399 }, 400 { 401 .name = "TI SuperSparc 50", /* STP1020PGA */ 402 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 403 .fpu_version = 0 << 17, 404 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 405 .mmu_bm = 0x00002000, 406 .mmu_ctpr_mask = 0xffffffc0, 407 .mmu_cxr_mask = 0x0000ffff, 408 .mmu_sfsr_mask = 0xffffffff, 409 .mmu_trcr_mask = 0xffffffff, 410 .nwindows = 8, 411 .features = CPU_DEFAULT_FEATURES, 412 }, 413 { 414 .name = "TI SuperSparc 51", 415 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 416 .fpu_version = 0 << 17, 417 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 418 .mmu_bm = 0x00002000, 419 .mmu_ctpr_mask = 0xffffffc0, 420 .mmu_cxr_mask = 0x0000ffff, 421 .mmu_sfsr_mask = 0xffffffff, 422 .mmu_trcr_mask = 0xffffffff, 423 .mxcc_version = 0x00000104, 424 .nwindows = 8, 425 .features = CPU_DEFAULT_FEATURES, 426 }, 427 { 428 .name = "TI SuperSparc 60", /* STP1020APGA */ 429 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 430 .fpu_version = 0 << 17, 431 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 432 .mmu_bm = 0x00002000, 433 .mmu_ctpr_mask = 0xffffffc0, 434 .mmu_cxr_mask = 0x0000ffff, 435 .mmu_sfsr_mask = 0xffffffff, 436 .mmu_trcr_mask = 0xffffffff, 437 .nwindows = 8, 438 .features = CPU_DEFAULT_FEATURES, 439 }, 440 { 441 .name = "TI SuperSparc 61", 442 .iu_version = 0x44000000, /* SuperSPARC 3.x */ 443 .fpu_version = 0 << 17, 444 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 445 .mmu_bm = 0x00002000, 446 .mmu_ctpr_mask = 0xffffffc0, 447 .mmu_cxr_mask = 0x0000ffff, 448 .mmu_sfsr_mask = 0xffffffff, 449 .mmu_trcr_mask = 0xffffffff, 450 .mxcc_version = 0x00000104, 451 .nwindows = 8, 452 .features = CPU_DEFAULT_FEATURES, 453 }, 454 { 455 .name = "TI SuperSparc II", 456 .iu_version = 0x40000000, /* SuperSPARC II 1.x */ 457 .fpu_version = 0 << 17, 458 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ 459 .mmu_bm = 0x00002000, 460 .mmu_ctpr_mask = 0xffffffc0, 461 .mmu_cxr_mask = 0x0000ffff, 462 .mmu_sfsr_mask = 0xffffffff, 463 .mmu_trcr_mask = 0xffffffff, 464 .mxcc_version = 0x00000104, 465 .nwindows = 8, 466 .features = CPU_DEFAULT_FEATURES, 467 }, 468 { 469 .name = "LEON2", 470 .iu_version = 0xf2000000, 471 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 472 .mmu_version = 0xf2000000, 473 .mmu_bm = 0x00004000, 474 .mmu_ctpr_mask = 0x007ffff0, 475 .mmu_cxr_mask = 0x0000003f, 476 .mmu_sfsr_mask = 0xffffffff, 477 .mmu_trcr_mask = 0xffffffff, 478 .nwindows = 8, 479 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, 480 }, 481 { 482 .name = "LEON3", 483 .iu_version = 0xf3000000, 484 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 485 .mmu_version = 0xf3000000, 486 .mmu_bm = 0x00000000, 487 .mmu_ctpr_mask = 0xfffffffc, 488 .mmu_cxr_mask = 0x000000ff, 489 .mmu_sfsr_mask = 0xffffffff, 490 .mmu_trcr_mask = 0xffffffff, 491 .nwindows = 8, 492 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | 493 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | 494 CPU_FEATURE_CASA, 495 }, 496 #endif 497 }; 498 499 static const char * const feature_name[] = { 500 "float", 501 "float128", 502 "swap", 503 "mul", 504 "div", 505 "flush", 506 "fsqrt", 507 "fmul", 508 "vis1", 509 "vis2", 510 "fsmuld", 511 "hypv", 512 "cmt", 513 "gl", 514 }; 515 516 static void print_features(FILE *f, fprintf_function cpu_fprintf, 517 uint32_t features, const char *prefix) 518 { 519 unsigned int i; 520 521 for (i = 0; i < ARRAY_SIZE(feature_name); i++) { 522 if (feature_name[i] && (features & (1 << i))) { 523 if (prefix) { 524 (*cpu_fprintf)(f, "%s", prefix); 525 } 526 (*cpu_fprintf)(f, "%s ", feature_name[i]); 527 } 528 } 529 } 530 531 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) 532 { 533 unsigned int i; 534 535 for (i = 0; i < ARRAY_SIZE(feature_name); i++) { 536 if (feature_name[i] && !strcmp(flagname, feature_name[i])) { 537 *features |= 1 << i; 538 return; 539 } 540 } 541 error_report("CPU feature %s not found", flagname); 542 } 543 544 static void sparc_cpu_parse_features(CPUState *cs, char *features, 545 Error **errp) 546 { 547 SPARCCPU *cpu = SPARC_CPU(cs); 548 sparc_def_t *cpu_def = &cpu->env.def; 549 char *featurestr; 550 uint32_t plus_features = 0; 551 uint32_t minus_features = 0; 552 uint64_t iu_version; 553 uint32_t fpu_version, mmu_version, nwindows; 554 555 featurestr = features ? strtok(features, ",") : NULL; 556 while (featurestr) { 557 char *val; 558 559 if (featurestr[0] == '+') { 560 add_flagname_to_bitmaps(featurestr + 1, &plus_features); 561 } else if (featurestr[0] == '-') { 562 add_flagname_to_bitmaps(featurestr + 1, &minus_features); 563 } else if ((val = strchr(featurestr, '='))) { 564 *val = 0; val++; 565 if (!strcmp(featurestr, "iu_version")) { 566 char *err; 567 568 iu_version = strtoll(val, &err, 0); 569 if (!*val || *err) { 570 error_setg(errp, "bad numerical value %s", val); 571 return; 572 } 573 cpu_def->iu_version = iu_version; 574 #ifdef DEBUG_FEATURES 575 fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version); 576 #endif 577 } else if (!strcmp(featurestr, "fpu_version")) { 578 char *err; 579 580 fpu_version = strtol(val, &err, 0); 581 if (!*val || *err) { 582 error_setg(errp, "bad numerical value %s", val); 583 return; 584 } 585 cpu_def->fpu_version = fpu_version; 586 #ifdef DEBUG_FEATURES 587 fprintf(stderr, "fpu_version %x\n", fpu_version); 588 #endif 589 } else if (!strcmp(featurestr, "mmu_version")) { 590 char *err; 591 592 mmu_version = strtol(val, &err, 0); 593 if (!*val || *err) { 594 error_setg(errp, "bad numerical value %s", val); 595 return; 596 } 597 cpu_def->mmu_version = mmu_version; 598 #ifdef DEBUG_FEATURES 599 fprintf(stderr, "mmu_version %x\n", mmu_version); 600 #endif 601 } else if (!strcmp(featurestr, "nwindows")) { 602 char *err; 603 604 nwindows = strtol(val, &err, 0); 605 if (!*val || *err || nwindows > MAX_NWINDOWS || 606 nwindows < MIN_NWINDOWS) { 607 error_setg(errp, "bad numerical value %s", val); 608 return; 609 } 610 cpu_def->nwindows = nwindows; 611 #ifdef DEBUG_FEATURES 612 fprintf(stderr, "nwindows %d\n", nwindows); 613 #endif 614 } else { 615 error_setg(errp, "unrecognized feature %s", featurestr); 616 return; 617 } 618 } else { 619 error_setg(errp, "feature string `%s' not in format " 620 "(+feature|-feature|feature=xyz)", featurestr); 621 return; 622 } 623 featurestr = strtok(NULL, ","); 624 } 625 cpu_def->features |= plus_features; 626 cpu_def->features &= ~minus_features; 627 #ifdef DEBUG_FEATURES 628 print_features(stderr, fprintf, cpu_def->features, NULL); 629 #endif 630 } 631 632 void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf) 633 { 634 unsigned int i; 635 636 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 637 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx 638 " FPU %08x MMU %08x NWINS %d ", 639 sparc_defs[i].name, 640 sparc_defs[i].iu_version, 641 sparc_defs[i].fpu_version, 642 sparc_defs[i].mmu_version, 643 sparc_defs[i].nwindows); 644 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & 645 ~sparc_defs[i].features, "-"); 646 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & 647 sparc_defs[i].features, "+"); 648 (*cpu_fprintf)(f, "\n"); 649 } 650 (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): "); 651 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL); 652 (*cpu_fprintf)(f, "\n"); 653 (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): "); 654 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL); 655 (*cpu_fprintf)(f, "\n"); 656 (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version " 657 "fpu_version mmu_version nwindows\n"); 658 } 659 660 static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf, 661 uint32_t cc) 662 { 663 cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', 664 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', 665 cc & PSR_CARRY ? 'C' : '-'); 666 } 667 668 #ifdef TARGET_SPARC64 669 #define REGS_PER_LINE 4 670 #else 671 #define REGS_PER_LINE 8 672 #endif 673 674 void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 675 int flags) 676 { 677 SPARCCPU *cpu = SPARC_CPU(cs); 678 CPUSPARCState *env = &cpu->env; 679 int i, x; 680 681 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, 682 env->npc); 683 684 for (i = 0; i < 8; i++) { 685 if (i % REGS_PER_LINE == 0) { 686 cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); 687 } 688 cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); 689 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 690 cpu_fprintf(f, "\n"); 691 } 692 } 693 for (x = 0; x < 3; x++) { 694 for (i = 0; i < 8; i++) { 695 if (i % REGS_PER_LINE == 0) { 696 cpu_fprintf(f, "%%%c%d-%d: ", 697 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), 698 i, i + REGS_PER_LINE - 1); 699 } 700 cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); 701 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 702 cpu_fprintf(f, "\n"); 703 } 704 } 705 } 706 707 for (i = 0; i < TARGET_DPREGS; i++) { 708 if ((i & 3) == 0) { 709 cpu_fprintf(f, "%%f%02d: ", i * 2); 710 } 711 cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); 712 if ((i & 3) == 3) { 713 cpu_fprintf(f, "\n"); 714 } 715 } 716 #ifdef TARGET_SPARC64 717 cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, 718 (unsigned)cpu_get_ccr(env)); 719 cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT); 720 cpu_fprintf(f, " xcc: "); 721 cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); 722 cpu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl, 723 env->psrpil, env->gl); 724 cpu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: " 725 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); 726 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " 727 "cleanwin: %d cwp: %d\n", 728 env->cansave, env->canrestore, env->otherwin, env->wstate, 729 env->cleanwin, env->nwindows - 1 - env->cwp); 730 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: " 731 TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs); 732 733 #else 734 cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); 735 cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env)); 736 cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', 737 env->psrps ? 'P' : '-', env->psret ? 'E' : '-', 738 env->wim); 739 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", 740 env->fsr, env->y); 741 #endif 742 cpu_fprintf(f, "\n"); 743 } 744 745 static void sparc_cpu_set_pc(CPUState *cs, vaddr value) 746 { 747 SPARCCPU *cpu = SPARC_CPU(cs); 748 749 cpu->env.pc = value; 750 cpu->env.npc = value + 4; 751 } 752 753 static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 754 { 755 SPARCCPU *cpu = SPARC_CPU(cs); 756 757 cpu->env.pc = tb->pc; 758 cpu->env.npc = tb->cs_base; 759 } 760 761 static bool sparc_cpu_has_work(CPUState *cs) 762 { 763 SPARCCPU *cpu = SPARC_CPU(cs); 764 CPUSPARCState *env = &cpu->env; 765 766 return (cs->interrupt_request & CPU_INTERRUPT_HARD) && 767 cpu_interrupts_enabled(env); 768 } 769 770 static char *sparc_cpu_type_name(const char *cpu_model) 771 { 772 char *name = g_strdup_printf("%s-" TYPE_SPARC_CPU, cpu_model); 773 char *s = name; 774 775 /* SPARC cpu model names happen to have whitespaces, 776 * as type names shouldn't have spaces replace them with '-' 777 */ 778 while ((s = strchr(s, ' '))) { 779 *s = '-'; 780 } 781 782 return name; 783 } 784 785 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model) 786 { 787 ObjectClass *oc; 788 char *typename; 789 790 if (cpu_model == NULL) { 791 return NULL; 792 } 793 794 typename = sparc_cpu_type_name(cpu_model); 795 oc = object_class_by_name(typename); 796 g_free(typename); 797 return oc; 798 } 799 800 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) 801 { 802 CPUState *cs = CPU(dev); 803 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); 804 Error *local_err = NULL; 805 SPARCCPU *cpu = SPARC_CPU(dev); 806 CPUSPARCState *env = &cpu->env; 807 808 #if defined(CONFIG_USER_ONLY) 809 if ((env->def.features & CPU_FEATURE_FLOAT)) { 810 env->def.features |= CPU_FEATURE_FLOAT128; 811 } 812 #endif 813 814 env->version = env->def.iu_version; 815 env->fsr = env->def.fpu_version; 816 env->nwindows = env->def.nwindows; 817 #if !defined(TARGET_SPARC64) 818 env->mmuregs[0] |= env->def.mmu_version; 819 cpu_sparc_set_id(env, 0); 820 env->mxccregs[7] |= env->def.mxcc_version; 821 #else 822 env->mmu_version = env->def.mmu_version; 823 env->maxtl = env->def.maxtl; 824 env->version |= env->def.maxtl << 8; 825 env->version |= env->def.nwindows - 1; 826 #endif 827 828 cpu_exec_realizefn(cs, &local_err); 829 if (local_err != NULL) { 830 error_propagate(errp, local_err); 831 return; 832 } 833 834 qemu_init_vcpu(cs); 835 836 scc->parent_realize(dev, errp); 837 } 838 839 static void sparc_cpu_initfn(Object *obj) 840 { 841 CPUState *cs = CPU(obj); 842 SPARCCPU *cpu = SPARC_CPU(obj); 843 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); 844 CPUSPARCState *env = &cpu->env; 845 846 cs->env_ptr = env; 847 848 if (tcg_enabled()) { 849 gen_intermediate_code_init(env); 850 } 851 852 if (scc->cpu_def) { 853 env->def = *scc->cpu_def; 854 } 855 } 856 857 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name, 858 void *opaque, Error **errp) 859 { 860 SPARCCPU *cpu = SPARC_CPU(obj); 861 int64_t value = cpu->env.def.nwindows; 862 863 visit_type_int(v, name, &value, errp); 864 } 865 866 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name, 867 void *opaque, Error **errp) 868 { 869 const int64_t min = MIN_NWINDOWS; 870 const int64_t max = MAX_NWINDOWS; 871 SPARCCPU *cpu = SPARC_CPU(obj); 872 Error *err = NULL; 873 int64_t value; 874 875 visit_type_int(v, name, &value, &err); 876 if (err) { 877 error_propagate(errp, err); 878 return; 879 } 880 881 if (value < min || value > max) { 882 error_setg(errp, "Property %s.%s doesn't take value %" PRId64 883 " (minimum: %" PRId64 ", maximum: %" PRId64 ")", 884 object_get_typename(obj), name ? name : "null", 885 value, min, max); 886 return; 887 } 888 cpu->env.def.nwindows = value; 889 } 890 891 static PropertyInfo qdev_prop_nwindows = { 892 .name = "int", 893 .get = sparc_get_nwindows, 894 .set = sparc_set_nwindows, 895 }; 896 897 static Property sparc_cpu_properties[] = { 898 DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, 0, false), 899 DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 1, false), 900 DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, 2, false), 901 DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 3, false), 902 DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 4, false), 903 DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, 5, false), 904 DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, 6, false), 905 DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, 7, false), 906 DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 8, false), 907 DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 9, false), 908 DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 10, false), 909 DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 11, false), 910 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 12, false), 911 DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 13, false), 912 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0, 913 qdev_prop_uint64, target_ulong), 914 DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0), 915 DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0), 916 { .name = "nwindows", .info = &qdev_prop_nwindows }, 917 DEFINE_PROP_END_OF_LIST() 918 }; 919 920 static void sparc_cpu_class_init(ObjectClass *oc, void *data) 921 { 922 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 923 CPUClass *cc = CPU_CLASS(oc); 924 DeviceClass *dc = DEVICE_CLASS(oc); 925 926 scc->parent_realize = dc->realize; 927 dc->realize = sparc_cpu_realizefn; 928 dc->props = sparc_cpu_properties; 929 930 scc->parent_reset = cc->reset; 931 cc->reset = sparc_cpu_reset; 932 933 cc->class_by_name = sparc_cpu_class_by_name; 934 cc->has_work = sparc_cpu_has_work; 935 cc->do_interrupt = sparc_cpu_do_interrupt; 936 cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt; 937 cc->dump_state = sparc_cpu_dump_state; 938 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 939 cc->memory_rw_debug = sparc_cpu_memory_rw_debug; 940 #endif 941 cc->set_pc = sparc_cpu_set_pc; 942 cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb; 943 cc->gdb_read_register = sparc_cpu_gdb_read_register; 944 cc->gdb_write_register = sparc_cpu_gdb_write_register; 945 #ifdef CONFIG_USER_ONLY 946 cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault; 947 #else 948 cc->do_unassigned_access = sparc_cpu_unassigned_access; 949 cc->do_unaligned_access = sparc_cpu_do_unaligned_access; 950 cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; 951 cc->vmsd = &vmstate_sparc_cpu; 952 #endif 953 cc->disas_set_info = cpu_sparc_disas_set_info; 954 955 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 956 cc->gdb_num_core_regs = 86; 957 #else 958 cc->gdb_num_core_regs = 72; 959 #endif 960 } 961 962 static const TypeInfo sparc_cpu_type_info = { 963 .name = TYPE_SPARC_CPU, 964 .parent = TYPE_CPU, 965 .instance_size = sizeof(SPARCCPU), 966 .instance_init = sparc_cpu_initfn, 967 .abstract = true, 968 .class_size = sizeof(SPARCCPUClass), 969 .class_init = sparc_cpu_class_init, 970 }; 971 972 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data) 973 { 974 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 975 scc->cpu_def = data; 976 } 977 978 static void sparc_register_cpudef_type(const struct sparc_def_t *def) 979 { 980 char *typename = sparc_cpu_type_name(def->name); 981 TypeInfo ti = { 982 .name = typename, 983 .parent = TYPE_SPARC_CPU, 984 .class_init = sparc_cpu_cpudef_class_init, 985 .class_data = (void *)def, 986 }; 987 988 type_register(&ti); 989 g_free(typename); 990 } 991 992 static void sparc_cpu_register_types(void) 993 { 994 int i; 995 996 type_register_static(&sparc_cpu_type_info); 997 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 998 sparc_register_cpudef_type(&sparc_defs[i]); 999 } 1000 } 1001 1002 type_init(sparc_cpu_register_types) 1003