1 /* 2 * Sparc CPU init helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu/error-report.h" 24 #include "exec/exec-all.h" 25 26 //#define DEBUG_FEATURES 27 28 /* CPUClass::reset() */ 29 static void sparc_cpu_reset(CPUState *s) 30 { 31 SPARCCPU *cpu = SPARC_CPU(s); 32 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); 33 CPUSPARCState *env = &cpu->env; 34 35 scc->parent_reset(s); 36 37 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); 38 env->cwp = 0; 39 #ifndef TARGET_SPARC64 40 env->wim = 1; 41 #endif 42 env->regwptr = env->regbase + (env->cwp * 16); 43 CC_OP = CC_OP_FLAGS; 44 #if defined(CONFIG_USER_ONLY) 45 #ifdef TARGET_SPARC64 46 env->cleanwin = env->nwindows - 2; 47 env->cansave = env->nwindows - 2; 48 env->pstate = PS_RMO | PS_PEF | PS_IE; 49 env->asi = 0x82; /* Primary no-fault */ 50 #endif 51 #else 52 #if !defined(TARGET_SPARC64) 53 env->psret = 0; 54 env->psrs = 1; 55 env->psrps = 1; 56 #endif 57 #ifdef TARGET_SPARC64 58 env->pstate = PS_PRIV | PS_RED | PS_PEF; 59 if (!cpu_has_hypervisor(env)) { 60 env->pstate |= PS_AG; 61 } 62 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0; 63 env->tl = env->maxtl; 64 env->gl = 2; 65 cpu_tsptr(env)->tt = TT_POWER_ON_RESET; 66 env->lsu = 0; 67 #else 68 env->mmuregs[0] &= ~(MMU_E | MMU_NF); 69 env->mmuregs[0] |= env->def->mmu_bm; 70 #endif 71 env->pc = 0; 72 env->npc = env->pc + 4; 73 #endif 74 env->cache_control = 0; 75 } 76 77 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 78 { 79 if (interrupt_request & CPU_INTERRUPT_HARD) { 80 SPARCCPU *cpu = SPARC_CPU(cs); 81 CPUSPARCState *env = &cpu->env; 82 83 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { 84 int pil = env->interrupt_index & 0xf; 85 int type = env->interrupt_index & 0xf0; 86 87 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) { 88 cs->exception_index = env->interrupt_index; 89 sparc_cpu_do_interrupt(cs); 90 return true; 91 } 92 } 93 } 94 return false; 95 } 96 97 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) 98 { 99 info->print_insn = print_insn_sparc; 100 #ifdef TARGET_SPARC64 101 info->mach = bfd_mach_sparc_v9b; 102 #endif 103 } 104 105 static void sparc_cpu_parse_features(CPUState *cs, char *features, 106 Error **errp); 107 108 static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model) 109 { 110 CPUSPARCState *env = &cpu->env; 111 char *s = g_strdup(cpu_model); 112 char *featurestr = strtok(s, ","); 113 Error *err = NULL; 114 115 featurestr = strtok(NULL, ","); 116 sparc_cpu_parse_features(CPU(cpu), featurestr, &err); 117 g_free(s); 118 if (err) { 119 error_report_err(err); 120 return -1; 121 } 122 123 env->version = env->def->iu_version; 124 env->fsr = env->def->fpu_version; 125 env->nwindows = env->def->nwindows; 126 #if !defined(TARGET_SPARC64) 127 env->mmuregs[0] |= env->def->mmu_version; 128 cpu_sparc_set_id(env, 0); 129 env->mxccregs[7] |= env->def->mxcc_version; 130 #else 131 env->mmu_version = env->def->mmu_version; 132 env->maxtl = env->def->maxtl; 133 env->version |= env->def->maxtl << 8; 134 env->version |= env->def->nwindows - 1; 135 #endif 136 return 0; 137 } 138 139 SPARCCPU *cpu_sparc_init(const char *cpu_model) 140 { 141 SPARCCPU *cpu; 142 ObjectClass *oc; 143 char *str, *name; 144 145 str = g_strdup(cpu_model); 146 name = strtok(str, ","); 147 oc = cpu_class_by_name(TYPE_SPARC_CPU, name); 148 g_free(str); 149 if (oc == NULL) { 150 return NULL; 151 } 152 153 cpu = SPARC_CPU(object_new(object_class_get_name(oc))); 154 155 if (cpu_sparc_register(cpu, cpu_model) < 0) { 156 object_unref(OBJECT(cpu)); 157 return NULL; 158 } 159 160 object_property_set_bool(OBJECT(cpu), true, "realized", NULL); 161 162 return cpu; 163 } 164 165 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) 166 { 167 #if !defined(TARGET_SPARC64) 168 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; 169 #endif 170 } 171 172 static const sparc_def_t sparc_defs[] = { 173 #ifdef TARGET_SPARC64 174 { 175 .name = "Fujitsu Sparc64", 176 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), 177 .fpu_version = 0x00000000, 178 .mmu_version = mmu_us_12, 179 .nwindows = 4, 180 .maxtl = 4, 181 .features = CPU_DEFAULT_FEATURES, 182 }, 183 { 184 .name = "Fujitsu Sparc64 III", 185 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), 186 .fpu_version = 0x00000000, 187 .mmu_version = mmu_us_12, 188 .nwindows = 5, 189 .maxtl = 4, 190 .features = CPU_DEFAULT_FEATURES, 191 }, 192 { 193 .name = "Fujitsu Sparc64 IV", 194 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), 195 .fpu_version = 0x00000000, 196 .mmu_version = mmu_us_12, 197 .nwindows = 8, 198 .maxtl = 5, 199 .features = CPU_DEFAULT_FEATURES, 200 }, 201 { 202 .name = "Fujitsu Sparc64 V", 203 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), 204 .fpu_version = 0x00000000, 205 .mmu_version = mmu_us_12, 206 .nwindows = 8, 207 .maxtl = 5, 208 .features = CPU_DEFAULT_FEATURES, 209 }, 210 { 211 .name = "TI UltraSparc I", 212 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 213 .fpu_version = 0x00000000, 214 .mmu_version = mmu_us_12, 215 .nwindows = 8, 216 .maxtl = 5, 217 .features = CPU_DEFAULT_FEATURES, 218 }, 219 { 220 .name = "TI UltraSparc II", 221 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), 222 .fpu_version = 0x00000000, 223 .mmu_version = mmu_us_12, 224 .nwindows = 8, 225 .maxtl = 5, 226 .features = CPU_DEFAULT_FEATURES, 227 }, 228 { 229 .name = "TI UltraSparc IIi", 230 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), 231 .fpu_version = 0x00000000, 232 .mmu_version = mmu_us_12, 233 .nwindows = 8, 234 .maxtl = 5, 235 .features = CPU_DEFAULT_FEATURES, 236 }, 237 { 238 .name = "TI UltraSparc IIe", 239 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), 240 .fpu_version = 0x00000000, 241 .mmu_version = mmu_us_12, 242 .nwindows = 8, 243 .maxtl = 5, 244 .features = CPU_DEFAULT_FEATURES, 245 }, 246 { 247 .name = "Sun UltraSparc III", 248 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), 249 .fpu_version = 0x00000000, 250 .mmu_version = mmu_us_12, 251 .nwindows = 8, 252 .maxtl = 5, 253 .features = CPU_DEFAULT_FEATURES, 254 }, 255 { 256 .name = "Sun UltraSparc III Cu", 257 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), 258 .fpu_version = 0x00000000, 259 .mmu_version = mmu_us_3, 260 .nwindows = 8, 261 .maxtl = 5, 262 .features = CPU_DEFAULT_FEATURES, 263 }, 264 { 265 .name = "Sun UltraSparc IIIi", 266 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), 267 .fpu_version = 0x00000000, 268 .mmu_version = mmu_us_12, 269 .nwindows = 8, 270 .maxtl = 5, 271 .features = CPU_DEFAULT_FEATURES, 272 }, 273 { 274 .name = "Sun UltraSparc IV", 275 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), 276 .fpu_version = 0x00000000, 277 .mmu_version = mmu_us_4, 278 .nwindows = 8, 279 .maxtl = 5, 280 .features = CPU_DEFAULT_FEATURES, 281 }, 282 { 283 .name = "Sun UltraSparc IV+", 284 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), 285 .fpu_version = 0x00000000, 286 .mmu_version = mmu_us_12, 287 .nwindows = 8, 288 .maxtl = 5, 289 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, 290 }, 291 { 292 .name = "Sun UltraSparc IIIi+", 293 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), 294 .fpu_version = 0x00000000, 295 .mmu_version = mmu_us_3, 296 .nwindows = 8, 297 .maxtl = 5, 298 .features = CPU_DEFAULT_FEATURES, 299 }, 300 { 301 .name = "Sun UltraSparc T1", 302 /* defined in sparc_ifu_fdp.v and ctu.h */ 303 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), 304 .fpu_version = 0x00000000, 305 .mmu_version = mmu_sun4v, 306 .nwindows = 8, 307 .maxtl = 6, 308 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 309 | CPU_FEATURE_GL, 310 }, 311 { 312 .name = "Sun UltraSparc T2", 313 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ 314 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), 315 .fpu_version = 0x00000000, 316 .mmu_version = mmu_sun4v, 317 .nwindows = 8, 318 .maxtl = 6, 319 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT 320 | CPU_FEATURE_GL, 321 }, 322 { 323 .name = "NEC UltraSparc I", 324 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), 325 .fpu_version = 0x00000000, 326 .mmu_version = mmu_us_12, 327 .nwindows = 8, 328 .maxtl = 5, 329 .features = CPU_DEFAULT_FEATURES, 330 }, 331 #else 332 { 333 .name = "Fujitsu MB86904", 334 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ 335 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 336 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ 337 .mmu_bm = 0x00004000, 338 .mmu_ctpr_mask = 0x00ffffc0, 339 .mmu_cxr_mask = 0x000000ff, 340 .mmu_sfsr_mask = 0x00016fff, 341 .mmu_trcr_mask = 0x00ffffff, 342 .nwindows = 8, 343 .features = CPU_DEFAULT_FEATURES, 344 }, 345 { 346 .name = "Fujitsu MB86907", 347 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ 348 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 349 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ 350 .mmu_bm = 0x00004000, 351 .mmu_ctpr_mask = 0xffffffc0, 352 .mmu_cxr_mask = 0x000000ff, 353 .mmu_sfsr_mask = 0x00016fff, 354 .mmu_trcr_mask = 0xffffffff, 355 .nwindows = 8, 356 .features = CPU_DEFAULT_FEATURES, 357 }, 358 { 359 .name = "TI MicroSparc I", 360 .iu_version = 0x41000000, 361 .fpu_version = 4 << 17, 362 .mmu_version = 0x41000000, 363 .mmu_bm = 0x00004000, 364 .mmu_ctpr_mask = 0x007ffff0, 365 .mmu_cxr_mask = 0x0000003f, 366 .mmu_sfsr_mask = 0x00016fff, 367 .mmu_trcr_mask = 0x0000003f, 368 .nwindows = 7, 369 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | 370 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | 371 CPU_FEATURE_FMUL, 372 }, 373 { 374 .name = "TI MicroSparc II", 375 .iu_version = 0x42000000, 376 .fpu_version = 4 << 17, 377 .mmu_version = 0x02000000, 378 .mmu_bm = 0x00004000, 379 .mmu_ctpr_mask = 0x00ffffc0, 380 .mmu_cxr_mask = 0x000000ff, 381 .mmu_sfsr_mask = 0x00016fff, 382 .mmu_trcr_mask = 0x00ffffff, 383 .nwindows = 8, 384 .features = CPU_DEFAULT_FEATURES, 385 }, 386 { 387 .name = "TI MicroSparc IIep", 388 .iu_version = 0x42000000, 389 .fpu_version = 4 << 17, 390 .mmu_version = 0x04000000, 391 .mmu_bm = 0x00004000, 392 .mmu_ctpr_mask = 0x00ffffc0, 393 .mmu_cxr_mask = 0x000000ff, 394 .mmu_sfsr_mask = 0x00016bff, 395 .mmu_trcr_mask = 0x00ffffff, 396 .nwindows = 8, 397 .features = CPU_DEFAULT_FEATURES, 398 }, 399 { 400 .name = "TI SuperSparc 40", /* STP1020NPGA */ 401 .iu_version = 0x41000000, /* SuperSPARC 2.x */ 402 .fpu_version = 0 << 17, 403 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ 404 .mmu_bm = 0x00002000, 405 .mmu_ctpr_mask = 0xffffffc0, 406 .mmu_cxr_mask = 0x0000ffff, 407 .mmu_sfsr_mask = 0xffffffff, 408 .mmu_trcr_mask = 0xffffffff, 409 .nwindows = 8, 410 .features = CPU_DEFAULT_FEATURES, 411 }, 412 { 413 .name = "TI SuperSparc 50", /* STP1020PGA */ 414 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 415 .fpu_version = 0 << 17, 416 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 417 .mmu_bm = 0x00002000, 418 .mmu_ctpr_mask = 0xffffffc0, 419 .mmu_cxr_mask = 0x0000ffff, 420 .mmu_sfsr_mask = 0xffffffff, 421 .mmu_trcr_mask = 0xffffffff, 422 .nwindows = 8, 423 .features = CPU_DEFAULT_FEATURES, 424 }, 425 { 426 .name = "TI SuperSparc 51", 427 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 428 .fpu_version = 0 << 17, 429 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 430 .mmu_bm = 0x00002000, 431 .mmu_ctpr_mask = 0xffffffc0, 432 .mmu_cxr_mask = 0x0000ffff, 433 .mmu_sfsr_mask = 0xffffffff, 434 .mmu_trcr_mask = 0xffffffff, 435 .mxcc_version = 0x00000104, 436 .nwindows = 8, 437 .features = CPU_DEFAULT_FEATURES, 438 }, 439 { 440 .name = "TI SuperSparc 60", /* STP1020APGA */ 441 .iu_version = 0x40000000, /* SuperSPARC 3.x */ 442 .fpu_version = 0 << 17, 443 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ 444 .mmu_bm = 0x00002000, 445 .mmu_ctpr_mask = 0xffffffc0, 446 .mmu_cxr_mask = 0x0000ffff, 447 .mmu_sfsr_mask = 0xffffffff, 448 .mmu_trcr_mask = 0xffffffff, 449 .nwindows = 8, 450 .features = CPU_DEFAULT_FEATURES, 451 }, 452 { 453 .name = "TI SuperSparc 61", 454 .iu_version = 0x44000000, /* SuperSPARC 3.x */ 455 .fpu_version = 0 << 17, 456 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ 457 .mmu_bm = 0x00002000, 458 .mmu_ctpr_mask = 0xffffffc0, 459 .mmu_cxr_mask = 0x0000ffff, 460 .mmu_sfsr_mask = 0xffffffff, 461 .mmu_trcr_mask = 0xffffffff, 462 .mxcc_version = 0x00000104, 463 .nwindows = 8, 464 .features = CPU_DEFAULT_FEATURES, 465 }, 466 { 467 .name = "TI SuperSparc II", 468 .iu_version = 0x40000000, /* SuperSPARC II 1.x */ 469 .fpu_version = 0 << 17, 470 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ 471 .mmu_bm = 0x00002000, 472 .mmu_ctpr_mask = 0xffffffc0, 473 .mmu_cxr_mask = 0x0000ffff, 474 .mmu_sfsr_mask = 0xffffffff, 475 .mmu_trcr_mask = 0xffffffff, 476 .mxcc_version = 0x00000104, 477 .nwindows = 8, 478 .features = CPU_DEFAULT_FEATURES, 479 }, 480 { 481 .name = "LEON2", 482 .iu_version = 0xf2000000, 483 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 484 .mmu_version = 0xf2000000, 485 .mmu_bm = 0x00004000, 486 .mmu_ctpr_mask = 0x007ffff0, 487 .mmu_cxr_mask = 0x0000003f, 488 .mmu_sfsr_mask = 0xffffffff, 489 .mmu_trcr_mask = 0xffffffff, 490 .nwindows = 8, 491 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, 492 }, 493 { 494 .name = "LEON3", 495 .iu_version = 0xf3000000, 496 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ 497 .mmu_version = 0xf3000000, 498 .mmu_bm = 0x00000000, 499 .mmu_ctpr_mask = 0xfffffffc, 500 .mmu_cxr_mask = 0x000000ff, 501 .mmu_sfsr_mask = 0xffffffff, 502 .mmu_trcr_mask = 0xffffffff, 503 .nwindows = 8, 504 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | 505 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | 506 CPU_FEATURE_CASA, 507 }, 508 #endif 509 }; 510 511 static const char * const feature_name[] = { 512 "float", 513 "float128", 514 "swap", 515 "mul", 516 "div", 517 "flush", 518 "fsqrt", 519 "fmul", 520 "vis1", 521 "vis2", 522 "fsmuld", 523 "hypv", 524 "cmt", 525 "gl", 526 }; 527 528 static void print_features(FILE *f, fprintf_function cpu_fprintf, 529 uint32_t features, const char *prefix) 530 { 531 unsigned int i; 532 533 for (i = 0; i < ARRAY_SIZE(feature_name); i++) { 534 if (feature_name[i] && (features & (1 << i))) { 535 if (prefix) { 536 (*cpu_fprintf)(f, "%s", prefix); 537 } 538 (*cpu_fprintf)(f, "%s ", feature_name[i]); 539 } 540 } 541 } 542 543 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) 544 { 545 unsigned int i; 546 547 for (i = 0; i < ARRAY_SIZE(feature_name); i++) { 548 if (feature_name[i] && !strcmp(flagname, feature_name[i])) { 549 *features |= 1 << i; 550 return; 551 } 552 } 553 error_report("CPU feature %s not found", flagname); 554 } 555 556 static void sparc_cpu_parse_features(CPUState *cs, char *features, 557 Error **errp) 558 { 559 SPARCCPU *cpu = SPARC_CPU(cs); 560 sparc_def_t *cpu_def = cpu->env.def; 561 char *featurestr; 562 uint32_t plus_features = 0; 563 uint32_t minus_features = 0; 564 uint64_t iu_version; 565 uint32_t fpu_version, mmu_version, nwindows; 566 567 featurestr = features ? strtok(features, ",") : NULL; 568 while (featurestr) { 569 char *val; 570 571 if (featurestr[0] == '+') { 572 add_flagname_to_bitmaps(featurestr + 1, &plus_features); 573 } else if (featurestr[0] == '-') { 574 add_flagname_to_bitmaps(featurestr + 1, &minus_features); 575 } else if ((val = strchr(featurestr, '='))) { 576 *val = 0; val++; 577 if (!strcmp(featurestr, "iu_version")) { 578 char *err; 579 580 iu_version = strtoll(val, &err, 0); 581 if (!*val || *err) { 582 error_setg(errp, "bad numerical value %s", val); 583 return; 584 } 585 cpu_def->iu_version = iu_version; 586 #ifdef DEBUG_FEATURES 587 fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version); 588 #endif 589 } else if (!strcmp(featurestr, "fpu_version")) { 590 char *err; 591 592 fpu_version = strtol(val, &err, 0); 593 if (!*val || *err) { 594 error_setg(errp, "bad numerical value %s", val); 595 return; 596 } 597 cpu_def->fpu_version = fpu_version; 598 #ifdef DEBUG_FEATURES 599 fprintf(stderr, "fpu_version %x\n", fpu_version); 600 #endif 601 } else if (!strcmp(featurestr, "mmu_version")) { 602 char *err; 603 604 mmu_version = strtol(val, &err, 0); 605 if (!*val || *err) { 606 error_setg(errp, "bad numerical value %s", val); 607 return; 608 } 609 cpu_def->mmu_version = mmu_version; 610 #ifdef DEBUG_FEATURES 611 fprintf(stderr, "mmu_version %x\n", mmu_version); 612 #endif 613 } else if (!strcmp(featurestr, "nwindows")) { 614 char *err; 615 616 nwindows = strtol(val, &err, 0); 617 if (!*val || *err || nwindows > MAX_NWINDOWS || 618 nwindows < MIN_NWINDOWS) { 619 error_setg(errp, "bad numerical value %s", val); 620 return; 621 } 622 cpu_def->nwindows = nwindows; 623 #ifdef DEBUG_FEATURES 624 fprintf(stderr, "nwindows %d\n", nwindows); 625 #endif 626 } else { 627 error_setg(errp, "unrecognized feature %s", featurestr); 628 return; 629 } 630 } else { 631 error_setg(errp, "feature string `%s' not in format " 632 "(+feature|-feature|feature=xyz)", featurestr); 633 return; 634 } 635 featurestr = strtok(NULL, ","); 636 } 637 cpu_def->features |= plus_features; 638 cpu_def->features &= ~minus_features; 639 #ifdef DEBUG_FEATURES 640 print_features(stderr, fprintf, cpu_def->features, NULL); 641 #endif 642 } 643 644 void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf) 645 { 646 unsigned int i; 647 648 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 649 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx 650 " FPU %08x MMU %08x NWINS %d ", 651 sparc_defs[i].name, 652 sparc_defs[i].iu_version, 653 sparc_defs[i].fpu_version, 654 sparc_defs[i].mmu_version, 655 sparc_defs[i].nwindows); 656 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & 657 ~sparc_defs[i].features, "-"); 658 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & 659 sparc_defs[i].features, "+"); 660 (*cpu_fprintf)(f, "\n"); 661 } 662 (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): "); 663 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL); 664 (*cpu_fprintf)(f, "\n"); 665 (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): "); 666 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL); 667 (*cpu_fprintf)(f, "\n"); 668 (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version " 669 "fpu_version mmu_version nwindows\n"); 670 } 671 672 static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf, 673 uint32_t cc) 674 { 675 cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', 676 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', 677 cc & PSR_CARRY ? 'C' : '-'); 678 } 679 680 #ifdef TARGET_SPARC64 681 #define REGS_PER_LINE 4 682 #else 683 #define REGS_PER_LINE 8 684 #endif 685 686 void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 687 int flags) 688 { 689 SPARCCPU *cpu = SPARC_CPU(cs); 690 CPUSPARCState *env = &cpu->env; 691 int i, x; 692 693 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, 694 env->npc); 695 696 for (i = 0; i < 8; i++) { 697 if (i % REGS_PER_LINE == 0) { 698 cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); 699 } 700 cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); 701 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 702 cpu_fprintf(f, "\n"); 703 } 704 } 705 for (x = 0; x < 3; x++) { 706 for (i = 0; i < 8; i++) { 707 if (i % REGS_PER_LINE == 0) { 708 cpu_fprintf(f, "%%%c%d-%d: ", 709 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), 710 i, i + REGS_PER_LINE - 1); 711 } 712 cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); 713 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { 714 cpu_fprintf(f, "\n"); 715 } 716 } 717 } 718 719 for (i = 0; i < TARGET_DPREGS; i++) { 720 if ((i & 3) == 0) { 721 cpu_fprintf(f, "%%f%02d: ", i * 2); 722 } 723 cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); 724 if ((i & 3) == 3) { 725 cpu_fprintf(f, "\n"); 726 } 727 } 728 #ifdef TARGET_SPARC64 729 cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, 730 (unsigned)cpu_get_ccr(env)); 731 cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT); 732 cpu_fprintf(f, " xcc: "); 733 cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); 734 cpu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl, 735 env->psrpil, env->gl); 736 cpu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: " 737 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); 738 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " 739 "cleanwin: %d cwp: %d\n", 740 env->cansave, env->canrestore, env->otherwin, env->wstate, 741 env->cleanwin, env->nwindows - 1 - env->cwp); 742 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: " 743 TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs); 744 745 #else 746 cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); 747 cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env)); 748 cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', 749 env->psrps ? 'P' : '-', env->psret ? 'E' : '-', 750 env->wim); 751 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", 752 env->fsr, env->y); 753 #endif 754 cpu_fprintf(f, "\n"); 755 } 756 757 static void sparc_cpu_set_pc(CPUState *cs, vaddr value) 758 { 759 SPARCCPU *cpu = SPARC_CPU(cs); 760 761 cpu->env.pc = value; 762 cpu->env.npc = value + 4; 763 } 764 765 static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 766 { 767 SPARCCPU *cpu = SPARC_CPU(cs); 768 769 cpu->env.pc = tb->pc; 770 cpu->env.npc = tb->cs_base; 771 } 772 773 static bool sparc_cpu_has_work(CPUState *cs) 774 { 775 SPARCCPU *cpu = SPARC_CPU(cs); 776 CPUSPARCState *env = &cpu->env; 777 778 return (cs->interrupt_request & CPU_INTERRUPT_HARD) && 779 cpu_interrupts_enabled(env); 780 } 781 782 static char *sparc_cpu_type_name(const char *cpu_model) 783 { 784 char *name = g_strdup_printf("%s-" TYPE_SPARC_CPU, cpu_model); 785 char *s = name; 786 787 /* SPARC cpu model names happen to have whitespaces, 788 * as type names shouldn't have spaces replace them with '-' 789 */ 790 while ((s = strchr(s, ' '))) { 791 *s = '-'; 792 } 793 794 return name; 795 } 796 797 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model) 798 { 799 ObjectClass *oc; 800 char *typename; 801 802 if (cpu_model == NULL) { 803 return NULL; 804 } 805 806 typename = sparc_cpu_type_name(cpu_model); 807 oc = object_class_by_name(typename); 808 g_free(typename); 809 return oc; 810 } 811 812 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) 813 { 814 CPUState *cs = CPU(dev); 815 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); 816 Error *local_err = NULL; 817 #if defined(CONFIG_USER_ONLY) 818 SPARCCPU *cpu = SPARC_CPU(dev); 819 CPUSPARCState *env = &cpu->env; 820 821 if ((env->def->features & CPU_FEATURE_FLOAT)) { 822 env->def->features |= CPU_FEATURE_FLOAT128; 823 } 824 #endif 825 826 cpu_exec_realizefn(cs, &local_err); 827 if (local_err != NULL) { 828 error_propagate(errp, local_err); 829 return; 830 } 831 832 qemu_init_vcpu(cs); 833 834 scc->parent_realize(dev, errp); 835 } 836 837 static void sparc_cpu_initfn(Object *obj) 838 { 839 CPUState *cs = CPU(obj); 840 SPARCCPU *cpu = SPARC_CPU(obj); 841 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); 842 CPUSPARCState *env = &cpu->env; 843 844 cs->env_ptr = env; 845 846 if (tcg_enabled()) { 847 gen_intermediate_code_init(env); 848 } 849 850 env->def = g_memdup(scc->cpu_def, sizeof(*scc->cpu_def)); 851 } 852 853 static void sparc_cpu_uninitfn(Object *obj) 854 { 855 SPARCCPU *cpu = SPARC_CPU(obj); 856 CPUSPARCState *env = &cpu->env; 857 858 g_free(env->def); 859 } 860 861 static void sparc_cpu_class_init(ObjectClass *oc, void *data) 862 { 863 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 864 CPUClass *cc = CPU_CLASS(oc); 865 DeviceClass *dc = DEVICE_CLASS(oc); 866 867 scc->parent_realize = dc->realize; 868 dc->realize = sparc_cpu_realizefn; 869 870 scc->parent_reset = cc->reset; 871 cc->reset = sparc_cpu_reset; 872 873 cc->class_by_name = sparc_cpu_class_by_name; 874 cc->has_work = sparc_cpu_has_work; 875 cc->do_interrupt = sparc_cpu_do_interrupt; 876 cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt; 877 cc->dump_state = sparc_cpu_dump_state; 878 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 879 cc->memory_rw_debug = sparc_cpu_memory_rw_debug; 880 #endif 881 cc->set_pc = sparc_cpu_set_pc; 882 cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb; 883 cc->gdb_read_register = sparc_cpu_gdb_read_register; 884 cc->gdb_write_register = sparc_cpu_gdb_write_register; 885 #ifdef CONFIG_USER_ONLY 886 cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault; 887 #else 888 cc->do_unassigned_access = sparc_cpu_unassigned_access; 889 cc->do_unaligned_access = sparc_cpu_do_unaligned_access; 890 cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; 891 cc->vmsd = &vmstate_sparc_cpu; 892 #endif 893 cc->disas_set_info = cpu_sparc_disas_set_info; 894 895 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 896 cc->gdb_num_core_regs = 86; 897 #else 898 cc->gdb_num_core_regs = 72; 899 #endif 900 } 901 902 static const TypeInfo sparc_cpu_type_info = { 903 .name = TYPE_SPARC_CPU, 904 .parent = TYPE_CPU, 905 .instance_size = sizeof(SPARCCPU), 906 .instance_init = sparc_cpu_initfn, 907 .instance_finalize = sparc_cpu_uninitfn, 908 .abstract = true, 909 .class_size = sizeof(SPARCCPUClass), 910 .class_init = sparc_cpu_class_init, 911 }; 912 913 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data) 914 { 915 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); 916 scc->cpu_def = data; 917 } 918 919 static void sparc_register_cpudef_type(const struct sparc_def_t *def) 920 { 921 char *typename = sparc_cpu_type_name(def->name); 922 TypeInfo ti = { 923 .name = typename, 924 .parent = TYPE_SPARC_CPU, 925 .class_init = sparc_cpu_cpudef_class_init, 926 .class_data = (void *)def, 927 }; 928 929 type_register(&ti); 930 g_free(typename); 931 } 932 933 static void sparc_cpu_register_types(void) 934 { 935 int i; 936 937 type_register_static(&sparc_cpu_type_info); 938 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { 939 sparc_register_cpudef_type(&sparc_defs[i]); 940 } 941 } 942 943 type_init(sparc_cpu_register_types) 944