1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * QEMU SPARC CPU 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2012 SUSE LINUX Products GmbH 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 9fcf5ef2aSThomas Huth * version 2.1 of the License, or (at your option) any later version. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15fcf5ef2aSThomas Huth * 16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17fcf5ef2aSThomas Huth * License along with this library; if not, see 18fcf5ef2aSThomas Huth * <http://www.gnu.org/licenses/lgpl-2.1.html> 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth #ifndef QEMU_SPARC_CPU_QOM_H 21fcf5ef2aSThomas Huth #define QEMU_SPARC_CPU_QOM_H 22fcf5ef2aSThomas Huth 232e5b09fdSMarkus Armbruster #include "hw/core/cpu.h" 24db1015e9SEduardo Habkost #include "qom/object.h" 25fcf5ef2aSThomas Huth 26fcf5ef2aSThomas Huth #ifdef TARGET_SPARC64 27fcf5ef2aSThomas Huth #define TYPE_SPARC_CPU "sparc64-cpu" 28fcf5ef2aSThomas Huth #else 29fcf5ef2aSThomas Huth #define TYPE_SPARC_CPU "sparc-cpu" 30fcf5ef2aSThomas Huth #endif 31fcf5ef2aSThomas Huth 32*9295b1aaSPhilippe Mathieu-Daudé OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) 33fcf5ef2aSThomas Huth 3412a6c15eSIgor Mammedov typedef struct sparc_def_t sparc_def_t; 35fcf5ef2aSThomas Huth /** 36fcf5ef2aSThomas Huth * SPARCCPUClass: 37fcf5ef2aSThomas Huth * @parent_realize: The parent class' realize handler. 38fcf5ef2aSThomas Huth * @parent_reset: The parent class' reset handler. 39fcf5ef2aSThomas Huth * 40fcf5ef2aSThomas Huth * A SPARC CPU model. 41fcf5ef2aSThomas Huth */ 42db1015e9SEduardo Habkost struct SPARCCPUClass { 43fcf5ef2aSThomas Huth /*< private >*/ 44fcf5ef2aSThomas Huth CPUClass parent_class; 45fcf5ef2aSThomas Huth /*< public >*/ 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth DeviceRealize parent_realize; 48781c67caSPeter Maydell DeviceReset parent_reset; 4912a6c15eSIgor Mammedov sparc_def_t *cpu_def; 50db1015e9SEduardo Habkost }; 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth 53fcf5ef2aSThomas Huth #endif 54