1 #ifndef SPARC_ASI_H 2 #define SPARC_ASI_H 3 4 /* asi.h: Address Space Identifier values for the sparc. 5 * 6 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu) 7 * 8 * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au) 9 * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su> 10 */ 11 12 /* The first batch are for the sun4c. */ 13 14 #define ASI_NULL1 0x00 15 #define ASI_NULL2 0x01 16 17 /* sun4c and sun4 control registers and mmu/vac ops */ 18 #define ASI_CONTROL 0x02 19 #define ASI_SEGMAP 0x03 20 #define ASI_PTE 0x04 21 #define ASI_HWFLUSHSEG 0x05 22 #define ASI_HWFLUSHPAGE 0x06 23 #define ASI_REGMAP 0x06 24 #define ASI_HWFLUSHCONTEXT 0x07 25 26 #define ASI_USERTXT 0x08 27 #define ASI_KERNELTXT 0x09 28 #define ASI_USERDATA 0x0a 29 #define ASI_KERNELDATA 0x0b 30 31 /* VAC Cache flushing on sun4c and sun4 */ 32 #define ASI_FLUSHSEG 0x0c 33 #define ASI_FLUSHPG 0x0d 34 #define ASI_FLUSHCTX 0x0e 35 36 /* SPARCstation-5: only 6 bits are decoded. */ 37 /* wo = Write Only, rw = Read Write; */ 38 /* ss = Single Size, as = All Sizes; */ 39 #define ASI_M_RES00 0x00 /* Don't touch... */ 40 #define ASI_M_UNA01 0x01 /* Same here... */ 41 #define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */ 42 #define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */ 43 #define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */ 44 #define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */ 45 #define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */ 46 #define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */ 47 #define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */ 48 #define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */ 49 #define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */ 50 #define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */ 51 #define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */ 52 #define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */ 53 #define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */ 54 #define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */ 55 56 /* The following cache flushing ASIs work only with the 'sta' 57 * instruction. Results are unpredictable for 'swap' and 'ldstuba', 58 * so don't do it. 59 */ 60 61 /* These ASI flushes affect external caches too. */ 62 #define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */ 63 #define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */ 64 #define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */ 65 #define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */ 66 #define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */ 67 68 /* Block-copy operations are available only on certain V8 cpus. */ 69 #define ASI_M_BCOPY 0x17 /* Block copy */ 70 71 /* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */ 72 #define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */ 73 #define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */ 74 #define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */ 75 #define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */ 76 #define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */ 77 78 /* Block-fill operations are available on certain V8 cpus */ 79 #define ASI_M_BFILL 0x1F 80 81 /* This allows direct access to main memory, actually 0x20 to 0x2f are 82 * the available ASI's for physical ram pass-through, but I don't have 83 * any idea what the other ones do.... 84 */ 85 86 #define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */ 87 #define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */ 88 #define ASI_M_VMEUS 0x2A /* VME user 16-bit access */ 89 #define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */ 90 #define ASI_M_VMEUT 0x2C /* VME user 32-bit access */ 91 #define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */ 92 #define ASI_M_SBUS 0x2E /* Direct SBus access */ 93 #define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */ 94 95 96 /* This is ROSS HyperSparc only. */ 97 #define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */ 98 99 /* Tsunami/Viking/TurboSparc i/d cache flash clear. */ 100 #define ASI_M_IC_FLCLEAR 0x36 101 #define ASI_M_DC_FLCLEAR 0x37 102 103 #define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */ 104 105 #define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */ 106 /* only available on SuperSparc I */ 107 /* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */ 108 109 #define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */ 110 111 /* LEON ASI */ 112 #define ASI_LEON_NOCACHE 0x01 113 114 #define ASI_LEON_DCACHE_MISS 0x01 115 116 #define ASI_LEON_CACHEREGS 0x02 117 #define ASI_LEON_IFLUSH 0x10 118 #define ASI_LEON_DFLUSH 0x11 119 120 #define ASI_LEON_MMUFLUSH 0x18 121 #define ASI_LEON_MMUREGS 0x19 122 #define ASI_LEON_BYPASS 0x1c 123 #define ASI_LEON_FLUSH_PAGE 0x10 124 125 /* V9 Architecture mandary ASIs. */ 126 #define ASI_N 0x04 /* Nucleus */ 127 #define ASI_NL 0x0c /* Nucleus, little endian */ 128 #define ASI_AIUP 0x10 /* Primary, user */ 129 #define ASI_AIUS 0x11 /* Secondary, user */ 130 #define ASI_AIUPL 0x18 /* Primary, user, little endian */ 131 #define ASI_AIUSL 0x19 /* Secondary, user, little endian */ 132 #define ASI_P 0x80 /* Primary, implicit */ 133 #define ASI_S 0x81 /* Secondary, implicit */ 134 #define ASI_PNF 0x82 /* Primary, no fault */ 135 #define ASI_SNF 0x83 /* Secondary, no fault */ 136 #define ASI_PL 0x88 /* Primary, implicit, l-endian */ 137 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */ 138 #define ASI_PNFL 0x8a /* Primary, no fault, l-endian */ 139 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */ 140 141 /* SpitFire and later extended ASIs. The "(III)" marker designates 142 * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates 143 * Chip Multi Threading specific ASIs. "(NG)" designates Niagara specific 144 * ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4 145 * and later ASIs. 146 */ 147 #define ASI_REAL 0x14 /* Real address, cacheable */ 148 #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */ 149 #define ASI_REAL_IO 0x15 /* Real address, non-cachable */ 150 #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ 151 #define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */ 152 #define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */ 153 #define ASI_REAL_L 0x1c /* Real address, cacheable, LE */ 154 #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/ 155 #define ASI_REAL_IO_L 0x1d /* Real address, non-cachable, LE */ 156 #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ 157 #define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/ 158 #define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */ 159 #define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */ 160 #define ASI_MMU 0x21 /* (4V) MMU Context Registers */ 161 #define ASI_TWINX_AIUP 0x22 /* twin load, primary user */ 162 #define ASI_TWINX_AIUS 0x23 /* twin load, secondary user */ 163 #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load, 164 * secondary, user 165 */ 166 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */ 167 #define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */ 168 #define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */ 169 #define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */ 170 #define ASI_TWINX_N 0x27 /* twin load, nucleus */ 171 #define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */ 172 #define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */ 173 #define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */ 174 #define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */ 175 #define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */ 176 #define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */ 177 #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ 178 #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */ 179 #define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */ 180 #define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */ 181 #define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */ 182 #define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */ 183 #define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */ 184 #define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */ 185 #define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */ 186 #define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */ 187 #define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */ 188 #define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */ 189 #define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */ 190 #define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */ 191 #define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */ 192 #define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */ 193 #define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */ 194 #define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */ 195 #define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */ 196 #define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */ 197 #define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */ 198 #define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */ 199 #define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */ 200 #define ASI_LSU_CONTROL 0x45 /* Load-store control unit */ 201 #define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */ 202 #define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */ 203 #define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/ 204 #define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */ 205 #define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */ 206 #define ASI_UPA_CONFIG 0x4a /* UPA config space */ 207 #define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */ 208 #define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */ 209 #define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */ 210 #define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */ 211 #define ASI_AFSR 0x4c /* Async fault status register */ 212 #define ASI_AFAR 0x4d /* Async fault address register */ 213 #define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */ 214 #define ASI_HYP_SCRATCHPAD 0x4f /* (4V) Hypervisor scratchpad */ 215 #define ASI_IMMU 0x50 /* Insn-MMU main register space */ 216 #define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */ 217 #define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */ 218 #define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */ 219 #define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */ 220 #define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */ 221 #define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */ 222 #define ASI_DMMU 0x58 /* Data-MMU main register space */ 223 #define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */ 224 #define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */ 225 #define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */ 226 #define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */ 227 #define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */ 228 #define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */ 229 #define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */ 230 #define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */ 231 #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ 232 #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ 233 #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ 234 #define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ 235 #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ 236 #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ 237 #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ 238 #define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */ 239 #define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/ 240 #define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */ 241 #define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */ 242 #define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */ 243 #define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */ 244 #define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */ 245 #define ASI_EC_W 0x76 /* E-cache diag write access */ 246 #define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */ 247 #define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */ 248 #define ASI_INTR_W 0x77 /* IRQ vector dispatch write */ 249 #define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */ 250 #define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */ 251 #define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/ 252 #define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/ 253 #define ASI_EC_R 0x7e /* E-cache diag read access */ 254 #define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */ 255 #define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */ 256 #define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */ 257 #define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/ 258 #define ASI_INTR_R 0x7f /* IRQ vector dispatch read */ 259 #define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */ 260 #define ASI_PIC 0xb0 /* (NG4) PIC registers */ 261 #define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */ 262 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */ 263 #define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */ 264 #define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */ 265 #define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */ 266 #define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */ 267 #define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */ 268 #define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */ 269 #define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */ 270 #define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */ 271 #define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */ 272 #define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */ 273 #define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */ 274 #define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */ 275 #define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */ 276 #define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */ 277 #define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */ 278 #define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/ 279 #define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */ 280 #define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/ 281 #define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ 282 #define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ 283 #define ASI_TWINX_P 0xe2 /* twin load, primary implicit */ 284 #define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load, 285 * primary, implicit */ 286 #define ASI_TWINX_S 0xe3 /* twin load, secondary implicit */ 287 #define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load, 288 * secondary, implicit */ 289 #define ASI_TWINX_PL 0xea /* twin load, primary implicit, LE */ 290 #define ASI_TWINX_SL 0xeb /* twin load, secondary implicit, LE */ 291 #define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ 292 #define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ 293 #define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load, 294 * Most-Recently-Used, primary, 295 * implicit 296 */ 297 #define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load, 298 * Most-Recently-Used, secondary, 299 * implicit 300 */ 301 #define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */ 302 #define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */ 303 #define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load, 304 * Most-Recently-Used, primary, 305 * implicit, little-endian 306 */ 307 #define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load, 308 * Most-Recently-Used, secondary, 309 * implicit, little-endian 310 */ 311 312 #endif /* SPARC_ASI_H */ 313