1 /* 2 * SH4 emulation 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "exec/helper-proto.h" 22 #include "exec/exec-all.h" 23 #include "exec/cpu_ldst.h" 24 #include "fpu/softfloat.h" 25 26 #ifndef CONFIG_USER_ONLY 27 28 void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 29 MMUAccessType access_type, 30 int mmu_idx, uintptr_t retaddr) 31 { 32 cpu_env(cs)->tea = addr; 33 switch (access_type) { 34 case MMU_INST_FETCH: 35 case MMU_DATA_LOAD: 36 cs->exception_index = 0x0e0; 37 break; 38 case MMU_DATA_STORE: 39 cs->exception_index = 0x100; 40 break; 41 default: 42 g_assert_not_reached(); 43 } 44 cpu_loop_exit_restore(cs, retaddr); 45 } 46 47 #endif 48 49 void helper_ldtlb(CPUSH4State *env) 50 { 51 #ifdef CONFIG_USER_ONLY 52 cpu_abort(env_cpu(env), "Unhandled ldtlb"); 53 #else 54 cpu_load_tlb(env); 55 #endif 56 } 57 58 static inline G_NORETURN 59 void raise_exception(CPUSH4State *env, int index, 60 uintptr_t retaddr) 61 { 62 CPUState *cs = env_cpu(env); 63 64 cs->exception_index = index; 65 cpu_loop_exit_restore(cs, retaddr); 66 } 67 68 void helper_raise_illegal_instruction(CPUSH4State *env) 69 { 70 raise_exception(env, 0x180, 0); 71 } 72 73 void helper_raise_slot_illegal_instruction(CPUSH4State *env) 74 { 75 raise_exception(env, 0x1a0, 0); 76 } 77 78 void helper_raise_fpu_disable(CPUSH4State *env) 79 { 80 raise_exception(env, 0x800, 0); 81 } 82 83 void helper_raise_slot_fpu_disable(CPUSH4State *env) 84 { 85 raise_exception(env, 0x820, 0); 86 } 87 88 void helper_sleep(CPUSH4State *env) 89 { 90 CPUState *cs = env_cpu(env); 91 92 cs->halted = 1; 93 env->in_sleep = 1; 94 raise_exception(env, EXCP_HLT, 0); 95 } 96 97 void helper_trapa(CPUSH4State *env, uint32_t tra) 98 { 99 env->tra = tra << 2; 100 raise_exception(env, 0x160, 0); 101 } 102 103 void helper_exclusive(CPUSH4State *env) 104 { 105 /* We do not want cpu_restore_state to run. */ 106 cpu_loop_exit_atomic(env_cpu(env), 0); 107 } 108 109 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value) 110 { 111 if (cpu_sh4_is_cached (env, address)) 112 { 113 memory_content *r = g_new(memory_content, 1); 114 115 r->address = address; 116 r->value = value; 117 r->next = NULL; 118 119 *(env->movcal_backup_tail) = r; 120 env->movcal_backup_tail = &(r->next); 121 } 122 } 123 124 void helper_discard_movcal_backup(CPUSH4State *env) 125 { 126 memory_content *current = env->movcal_backup; 127 128 while(current) 129 { 130 memory_content *next = current->next; 131 g_free(current); 132 env->movcal_backup = current = next; 133 if (current == NULL) 134 env->movcal_backup_tail = &(env->movcal_backup); 135 } 136 } 137 138 void helper_ocbi(CPUSH4State *env, uint32_t address) 139 { 140 memory_content **current = &(env->movcal_backup); 141 while (*current) 142 { 143 uint32_t a = (*current)->address; 144 if ((a & ~0x1F) == (address & ~0x1F)) 145 { 146 memory_content *next = (*current)->next; 147 cpu_stl_data(env, a, (*current)->value); 148 149 if (next == NULL) 150 { 151 env->movcal_backup_tail = current; 152 } 153 154 g_free(*current); 155 *current = next; 156 break; 157 } 158 } 159 } 160 161 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1) 162 { 163 int64_t res; 164 165 res = ((uint64_t) env->mach << 32) | env->macl; 166 res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1; 167 env->mach = (res >> 32) & 0xffffffff; 168 env->macl = res & 0xffffffff; 169 if (env->sr & (1u << SR_S)) { 170 if (res < 0) 171 env->mach |= 0xffff0000; 172 else 173 env->mach &= 0x00007fff; 174 } 175 } 176 177 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1) 178 { 179 int64_t res; 180 181 res = ((uint64_t) env->mach << 32) | env->macl; 182 res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1; 183 env->mach = (res >> 32) & 0xffffffff; 184 env->macl = res & 0xffffffff; 185 if (env->sr & (1u << SR_S)) { 186 if (res < -0x80000000) { 187 env->mach = 1; 188 env->macl = 0x80000000; 189 } else if (res > 0x000000007fffffff) { 190 env->mach = 1; 191 env->macl = 0x7fffffff; 192 } 193 } 194 } 195 196 void helper_ld_fpscr(CPUSH4State *env, uint32_t val) 197 { 198 env->fpscr = val & FPSCR_MASK; 199 if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) { 200 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 201 } else { 202 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 203 } 204 set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status); 205 } 206 207 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr) 208 { 209 int xcpt, cause, enable; 210 211 xcpt = get_float_exception_flags(&env->fp_status); 212 213 /* Clear the cause entries */ 214 env->fpscr &= ~FPSCR_CAUSE_MASK; 215 216 if (unlikely(xcpt)) { 217 if (xcpt & float_flag_invalid) { 218 env->fpscr |= FPSCR_CAUSE_V; 219 } 220 if (xcpt & float_flag_divbyzero) { 221 env->fpscr |= FPSCR_CAUSE_Z; 222 } 223 if (xcpt & float_flag_overflow) { 224 env->fpscr |= FPSCR_CAUSE_O; 225 } 226 if (xcpt & float_flag_underflow) { 227 env->fpscr |= FPSCR_CAUSE_U; 228 } 229 if (xcpt & float_flag_inexact) { 230 env->fpscr |= FPSCR_CAUSE_I; 231 } 232 233 /* Accumulate in flag entries */ 234 env->fpscr |= (env->fpscr & FPSCR_CAUSE_MASK) 235 >> (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT); 236 237 /* Generate an exception if enabled */ 238 cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; 239 enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT; 240 if (cause & enable) { 241 raise_exception(env, 0x120, retaddr); 242 } 243 } 244 } 245 246 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1) 247 { 248 set_float_exception_flags(0, &env->fp_status); 249 t0 = float32_add(t0, t1, &env->fp_status); 250 update_fpscr(env, GETPC()); 251 return t0; 252 } 253 254 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1) 255 { 256 set_float_exception_flags(0, &env->fp_status); 257 t0 = float64_add(t0, t1, &env->fp_status); 258 update_fpscr(env, GETPC()); 259 return t0; 260 } 261 262 uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1) 263 { 264 int relation; 265 266 set_float_exception_flags(0, &env->fp_status); 267 relation = float32_compare(t0, t1, &env->fp_status); 268 update_fpscr(env, GETPC()); 269 return relation == float_relation_equal; 270 } 271 272 uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) 273 { 274 int relation; 275 276 set_float_exception_flags(0, &env->fp_status); 277 relation = float64_compare(t0, t1, &env->fp_status); 278 update_fpscr(env, GETPC()); 279 return relation == float_relation_equal; 280 } 281 282 uint32_t helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1) 283 { 284 int relation; 285 286 set_float_exception_flags(0, &env->fp_status); 287 relation = float32_compare(t0, t1, &env->fp_status); 288 update_fpscr(env, GETPC()); 289 return relation == float_relation_greater; 290 } 291 292 uint32_t helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1) 293 { 294 int relation; 295 296 set_float_exception_flags(0, &env->fp_status); 297 relation = float64_compare(t0, t1, &env->fp_status); 298 update_fpscr(env, GETPC()); 299 return relation == float_relation_greater; 300 } 301 302 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0) 303 { 304 float64 ret; 305 set_float_exception_flags(0, &env->fp_status); 306 ret = float32_to_float64(t0, &env->fp_status); 307 update_fpscr(env, GETPC()); 308 return ret; 309 } 310 311 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0) 312 { 313 float32 ret; 314 set_float_exception_flags(0, &env->fp_status); 315 ret = float64_to_float32(t0, &env->fp_status); 316 update_fpscr(env, GETPC()); 317 return ret; 318 } 319 320 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1) 321 { 322 set_float_exception_flags(0, &env->fp_status); 323 t0 = float32_div(t0, t1, &env->fp_status); 324 update_fpscr(env, GETPC()); 325 return t0; 326 } 327 328 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1) 329 { 330 set_float_exception_flags(0, &env->fp_status); 331 t0 = float64_div(t0, t1, &env->fp_status); 332 update_fpscr(env, GETPC()); 333 return t0; 334 } 335 336 float32 helper_float_FT(CPUSH4State *env, uint32_t t0) 337 { 338 float32 ret; 339 set_float_exception_flags(0, &env->fp_status); 340 ret = int32_to_float32(t0, &env->fp_status); 341 update_fpscr(env, GETPC()); 342 return ret; 343 } 344 345 float64 helper_float_DT(CPUSH4State *env, uint32_t t0) 346 { 347 float64 ret; 348 set_float_exception_flags(0, &env->fp_status); 349 ret = int32_to_float64(t0, &env->fp_status); 350 update_fpscr(env, GETPC()); 351 return ret; 352 } 353 354 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2) 355 { 356 set_float_exception_flags(0, &env->fp_status); 357 t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status); 358 update_fpscr(env, GETPC()); 359 return t0; 360 } 361 362 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1) 363 { 364 set_float_exception_flags(0, &env->fp_status); 365 t0 = float32_mul(t0, t1, &env->fp_status); 366 update_fpscr(env, GETPC()); 367 return t0; 368 } 369 370 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1) 371 { 372 set_float_exception_flags(0, &env->fp_status); 373 t0 = float64_mul(t0, t1, &env->fp_status); 374 update_fpscr(env, GETPC()); 375 return t0; 376 } 377 378 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0) 379 { 380 set_float_exception_flags(0, &env->fp_status); 381 t0 = float32_sqrt(t0, &env->fp_status); 382 update_fpscr(env, GETPC()); 383 return t0; 384 } 385 386 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0) 387 { 388 set_float_exception_flags(0, &env->fp_status); 389 t0 = float64_sqrt(t0, &env->fp_status); 390 update_fpscr(env, GETPC()); 391 return t0; 392 } 393 394 float32 helper_fsrra_FT(CPUSH4State *env, float32 t0) 395 { 396 set_float_exception_flags(0, &env->fp_status); 397 /* "Approximate" 1/sqrt(x) via actual computation. */ 398 t0 = float32_sqrt(t0, &env->fp_status); 399 t0 = float32_div(float32_one, t0, &env->fp_status); 400 /* 401 * Since this is supposed to be an approximation, an imprecision 402 * exception is required. One supposes this also follows the usual 403 * IEEE rule that other exceptions take precedence. 404 */ 405 if (get_float_exception_flags(&env->fp_status) == 0) { 406 set_float_exception_flags(float_flag_inexact, &env->fp_status); 407 } 408 update_fpscr(env, GETPC()); 409 return t0; 410 } 411 412 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1) 413 { 414 set_float_exception_flags(0, &env->fp_status); 415 t0 = float32_sub(t0, t1, &env->fp_status); 416 update_fpscr(env, GETPC()); 417 return t0; 418 } 419 420 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1) 421 { 422 set_float_exception_flags(0, &env->fp_status); 423 t0 = float64_sub(t0, t1, &env->fp_status); 424 update_fpscr(env, GETPC()); 425 return t0; 426 } 427 428 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0) 429 { 430 uint32_t ret; 431 set_float_exception_flags(0, &env->fp_status); 432 ret = float32_to_int32_round_to_zero(t0, &env->fp_status); 433 update_fpscr(env, GETPC()); 434 return ret; 435 } 436 437 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0) 438 { 439 uint32_t ret; 440 set_float_exception_flags(0, &env->fp_status); 441 ret = float64_to_int32_round_to_zero(t0, &env->fp_status); 442 update_fpscr(env, GETPC()); 443 return ret; 444 } 445 446 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n) 447 { 448 int bank, i; 449 float32 r, p; 450 451 bank = (env->sr & FPSCR_FR) ? 16 : 0; 452 r = float32_zero; 453 set_float_exception_flags(0, &env->fp_status); 454 455 for (i = 0 ; i < 4 ; i++) { 456 p = float32_mul(env->fregs[bank + m + i], 457 env->fregs[bank + n + i], 458 &env->fp_status); 459 r = float32_add(r, p, &env->fp_status); 460 } 461 update_fpscr(env, GETPC()); 462 463 env->fregs[bank + n + 3] = r; 464 } 465 466 void helper_ftrv(CPUSH4State *env, uint32_t n) 467 { 468 int bank_matrix, bank_vector; 469 int i, j; 470 float32 r[4]; 471 float32 p; 472 473 bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16; 474 bank_vector = (env->sr & FPSCR_FR) ? 16 : 0; 475 set_float_exception_flags(0, &env->fp_status); 476 for (i = 0 ; i < 4 ; i++) { 477 r[i] = float32_zero; 478 for (j = 0 ; j < 4 ; j++) { 479 p = float32_mul(env->fregs[bank_matrix + 4 * j + i], 480 env->fregs[bank_vector + j], 481 &env->fp_status); 482 r[i] = float32_add(r[i], p, &env->fp_status); 483 } 484 } 485 update_fpscr(env, GETPC()); 486 487 for (i = 0 ; i < 4 ; i++) { 488 env->fregs[bank_vector + i] = r[i]; 489 } 490 } 491