xref: /openbmc/qemu/target/sh4/helper.c (revision 80adf54e)
1 /*
2  *  SH4 emulation
3  *
4  *  Copyright (c) 2005 Samuel Tardieu
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 #include "qemu/osdep.h"
20 
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "exec/log.h"
24 #include "sysemu/sysemu.h"
25 
26 #if !defined(CONFIG_USER_ONLY)
27 #include "hw/sh4/sh_intc.h"
28 #endif
29 
30 #if defined(CONFIG_USER_ONLY)
31 
32 void superh_cpu_do_interrupt(CPUState *cs)
33 {
34     cs->exception_index = -1;
35 }
36 
37 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
38                                 int mmu_idx)
39 {
40     SuperHCPU *cpu = SUPERH_CPU(cs);
41     CPUSH4State *env = &cpu->env;
42 
43     env->tea = address;
44     cs->exception_index = -1;
45     switch (rw) {
46     case 0:
47         cs->exception_index = 0x0a0;
48         break;
49     case 1:
50         cs->exception_index = 0x0c0;
51         break;
52     case 2:
53         cs->exception_index = 0x0a0;
54         break;
55     }
56     return 1;
57 }
58 
59 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
60 {
61     /* For user mode, only U0 area is cacheable. */
62     return !(addr & 0x80000000);
63 }
64 
65 #else /* !CONFIG_USER_ONLY */
66 
67 #define MMU_OK                   0
68 #define MMU_ITLB_MISS            (-1)
69 #define MMU_ITLB_MULTIPLE        (-2)
70 #define MMU_ITLB_VIOLATION       (-3)
71 #define MMU_DTLB_MISS_READ       (-4)
72 #define MMU_DTLB_MISS_WRITE      (-5)
73 #define MMU_DTLB_INITIAL_WRITE   (-6)
74 #define MMU_DTLB_VIOLATION_READ  (-7)
75 #define MMU_DTLB_VIOLATION_WRITE (-8)
76 #define MMU_DTLB_MULTIPLE        (-9)
77 #define MMU_DTLB_MISS            (-10)
78 #define MMU_IADDR_ERROR          (-11)
79 #define MMU_DADDR_ERROR_READ     (-12)
80 #define MMU_DADDR_ERROR_WRITE    (-13)
81 
82 void superh_cpu_do_interrupt(CPUState *cs)
83 {
84     SuperHCPU *cpu = SUPERH_CPU(cs);
85     CPUSH4State *env = &cpu->env;
86     int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
87     int do_exp, irq_vector = cs->exception_index;
88 
89     /* prioritize exceptions over interrupts */
90 
91     do_exp = cs->exception_index != -1;
92     do_irq = do_irq && (cs->exception_index == -1);
93 
94     if (env->sr & (1u << SR_BL)) {
95         if (do_exp && cs->exception_index != 0x1e0) {
96             /* In theory a masked exception generates a reset exception,
97                which in turn jumps to the reset vector. However this only
98                works when using a bootloader. When using a kernel and an
99                initrd, they need to be reloaded and the program counter
100                should be loaded with the kernel entry point.
101                qemu_system_reset_request takes care of that.  */
102             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
103             return;
104         }
105         if (do_irq && !env->in_sleep) {
106             return; /* masked */
107         }
108     }
109     env->in_sleep = 0;
110 
111     if (do_irq) {
112         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
113 						(env->sr >> 4) & 0xf);
114         if (irq_vector == -1) {
115             return; /* masked */
116 	}
117     }
118 
119     if (qemu_loglevel_mask(CPU_LOG_INT)) {
120 	const char *expname;
121         switch (cs->exception_index) {
122 	case 0x0e0:
123 	    expname = "addr_error";
124 	    break;
125 	case 0x040:
126 	    expname = "tlb_miss";
127 	    break;
128 	case 0x0a0:
129 	    expname = "tlb_violation";
130 	    break;
131 	case 0x180:
132 	    expname = "illegal_instruction";
133 	    break;
134 	case 0x1a0:
135 	    expname = "slot_illegal_instruction";
136 	    break;
137 	case 0x800:
138 	    expname = "fpu_disable";
139 	    break;
140 	case 0x820:
141 	    expname = "slot_fpu";
142 	    break;
143 	case 0x100:
144 	    expname = "data_write";
145 	    break;
146 	case 0x060:
147 	    expname = "dtlb_miss_write";
148 	    break;
149 	case 0x0c0:
150 	    expname = "dtlb_violation_write";
151 	    break;
152 	case 0x120:
153 	    expname = "fpu_exception";
154 	    break;
155 	case 0x080:
156 	    expname = "initial_page_write";
157 	    break;
158 	case 0x160:
159 	    expname = "trapa";
160 	    break;
161 	default:
162             expname = do_irq ? "interrupt" : "???";
163             break;
164 	}
165 	qemu_log("exception 0x%03x [%s] raised\n",
166 		  irq_vector, expname);
167         log_cpu_state(cs, 0);
168     }
169 
170     env->ssr = cpu_read_sr(env);
171     env->spc = env->pc;
172     env->sgr = env->gregs[15];
173     env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
174 
175     if (env->flags & DELAY_SLOT_MASK) {
176         /* Branch instruction should be executed again before delay slot. */
177 	env->spc -= 2;
178 	/* Clear flags for exception/interrupt routine. */
179         env->flags &= ~DELAY_SLOT_MASK;
180     }
181 
182     if (do_exp) {
183         env->expevt = cs->exception_index;
184         switch (cs->exception_index) {
185         case 0x000:
186         case 0x020:
187         case 0x140:
188             env->sr &= ~(1u << SR_FD);
189             env->sr |= 0xf << 4; /* IMASK */
190             env->pc = 0xa0000000;
191             break;
192         case 0x040:
193         case 0x060:
194             env->pc = env->vbr + 0x400;
195             break;
196         case 0x160:
197             env->spc += 2; /* special case for TRAPA */
198             /* fall through */
199         default:
200             env->pc = env->vbr + 0x100;
201             break;
202         }
203         return;
204     }
205 
206     if (do_irq) {
207         env->intevt = irq_vector;
208         env->pc = env->vbr + 0x600;
209         return;
210     }
211 }
212 
213 static void update_itlb_use(CPUSH4State * env, int itlbnb)
214 {
215     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
216 
217     switch (itlbnb) {
218     case 0:
219 	and_mask = 0x1f;
220 	break;
221     case 1:
222 	and_mask = 0xe7;
223 	or_mask = 0x80;
224 	break;
225     case 2:
226 	and_mask = 0xfb;
227 	or_mask = 0x50;
228 	break;
229     case 3:
230 	or_mask = 0x2c;
231 	break;
232     }
233 
234     env->mmucr &= (and_mask << 24) | 0x00ffffff;
235     env->mmucr |= (or_mask << 24);
236 }
237 
238 static int itlb_replacement(CPUSH4State * env)
239 {
240     SuperHCPU *cpu = sh_env_get_cpu(env);
241 
242     if ((env->mmucr & 0xe0000000) == 0xe0000000) {
243 	return 0;
244     }
245     if ((env->mmucr & 0x98000000) == 0x18000000) {
246 	return 1;
247     }
248     if ((env->mmucr & 0x54000000) == 0x04000000) {
249 	return 2;
250     }
251     if ((env->mmucr & 0x2c000000) == 0x00000000) {
252 	return 3;
253     }
254     cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
255 }
256 
257 /* Find the corresponding entry in the right TLB
258    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
259 */
260 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
261 			  tlb_t * entries, uint8_t nbtlb, int use_asid)
262 {
263     int match = MMU_DTLB_MISS;
264     uint32_t start, end;
265     uint8_t asid;
266     int i;
267 
268     asid = env->pteh & 0xff;
269 
270     for (i = 0; i < nbtlb; i++) {
271 	if (!entries[i].v)
272 	    continue;		/* Invalid entry */
273 	if (!entries[i].sh && use_asid && entries[i].asid != asid)
274 	    continue;		/* Bad ASID */
275 	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
276 	end = start + entries[i].size - 1;
277 	if (address >= start && address <= end) {	/* Match */
278 	    if (match != MMU_DTLB_MISS)
279 		return MMU_DTLB_MULTIPLE;	/* Multiple match */
280 	    match = i;
281 	}
282     }
283     return match;
284 }
285 
286 static void increment_urc(CPUSH4State * env)
287 {
288     uint8_t urb, urc;
289 
290     /* Increment URC */
291     urb = ((env->mmucr) >> 18) & 0x3f;
292     urc = ((env->mmucr) >> 10) & 0x3f;
293     urc++;
294     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
295 	urc = 0;
296     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
297 }
298 
299 /* Copy and utlb entry into itlb
300    Return entry
301 */
302 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
303 {
304     int itlb;
305 
306     tlb_t * ientry;
307     itlb = itlb_replacement(env);
308     ientry = &env->itlb[itlb];
309     if (ientry->v) {
310         tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
311     }
312     *ientry = env->utlb[utlb];
313     update_itlb_use(env, itlb);
314     return itlb;
315 }
316 
317 /* Find itlb entry
318    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
319 */
320 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
321                            int use_asid)
322 {
323     int e;
324 
325     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
326     if (e == MMU_DTLB_MULTIPLE) {
327 	e = MMU_ITLB_MULTIPLE;
328     } else if (e == MMU_DTLB_MISS) {
329 	e = MMU_ITLB_MISS;
330     } else if (e >= 0) {
331 	update_itlb_use(env, e);
332     }
333     return e;
334 }
335 
336 /* Find utlb entry
337    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
338 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
339 {
340     /* per utlb access */
341     increment_urc(env);
342 
343     /* Return entry */
344     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
345 }
346 
347 /* Match address against MMU
348    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
349    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
350    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
351    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
352    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
353 */
354 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
355 			   int *prot, target_ulong address,
356 			   int rw, int access_type)
357 {
358     int use_asid, n;
359     tlb_t *matching = NULL;
360 
361     use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
362 
363     if (rw == 2) {
364         n = find_itlb_entry(env, address, use_asid);
365 	if (n >= 0) {
366 	    matching = &env->itlb[n];
367             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
368 		n = MMU_ITLB_VIOLATION;
369             } else {
370 		*prot = PAGE_EXEC;
371             }
372         } else {
373             n = find_utlb_entry(env, address, use_asid);
374             if (n >= 0) {
375                 n = copy_utlb_entry_itlb(env, n);
376                 matching = &env->itlb[n];
377                 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
378                     n = MMU_ITLB_VIOLATION;
379                 } else {
380                     *prot = PAGE_READ | PAGE_EXEC;
381                     if ((matching->pr & 1) && matching->d) {
382                         *prot |= PAGE_WRITE;
383                     }
384                 }
385             } else if (n == MMU_DTLB_MULTIPLE) {
386                 n = MMU_ITLB_MULTIPLE;
387             } else if (n == MMU_DTLB_MISS) {
388                 n = MMU_ITLB_MISS;
389             }
390 	}
391     } else {
392 	n = find_utlb_entry(env, address, use_asid);
393 	if (n >= 0) {
394 	    matching = &env->utlb[n];
395             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
396                 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
397                     MMU_DTLB_VIOLATION_READ;
398             } else if ((rw == 1) && !(matching->pr & 1)) {
399                 n = MMU_DTLB_VIOLATION_WRITE;
400             } else if ((rw == 1) && !matching->d) {
401                 n = MMU_DTLB_INITIAL_WRITE;
402             } else {
403                 *prot = PAGE_READ;
404                 if ((matching->pr & 1) && matching->d) {
405                     *prot |= PAGE_WRITE;
406                 }
407             }
408 	} else if (n == MMU_DTLB_MISS) {
409 	    n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
410 		MMU_DTLB_MISS_READ;
411 	}
412     }
413     if (n >= 0) {
414 	n = MMU_OK;
415 	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
416 	    (address & (matching->size - 1));
417     }
418     return n;
419 }
420 
421 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
422                                 int *prot, target_ulong address,
423                                 int rw, int access_type)
424 {
425     /* P1, P2 and P4 areas do not use translation */
426     if ((address >= 0x80000000 && address < 0xc0000000) ||
427 	address >= 0xe0000000) {
428         if (!(env->sr & (1u << SR_MD))
429 	    && (address < 0xe0000000 || address >= 0xe4000000)) {
430 	    /* Unauthorized access in user mode (only store queues are available) */
431             qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
432 	    if (rw == 0)
433 		return MMU_DADDR_ERROR_READ;
434 	    else if (rw == 1)
435 		return MMU_DADDR_ERROR_WRITE;
436 	    else
437 		return MMU_IADDR_ERROR;
438 	}
439 	if (address >= 0x80000000 && address < 0xc0000000) {
440 	    /* Mask upper 3 bits for P1 and P2 areas */
441 	    *physical = address & 0x1fffffff;
442 	} else {
443 	    *physical = address;
444 	}
445 	*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
446 	return MMU_OK;
447     }
448 
449     /* If MMU is disabled, return the corresponding physical page */
450     if (!(env->mmucr & MMUCR_AT)) {
451 	*physical = address & 0x1FFFFFFF;
452 	*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
453 	return MMU_OK;
454     }
455 
456     /* We need to resort to the MMU */
457     return get_mmu_address(env, physical, prot, address, rw, access_type);
458 }
459 
460 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
461                                 int mmu_idx)
462 {
463     SuperHCPU *cpu = SUPERH_CPU(cs);
464     CPUSH4State *env = &cpu->env;
465     target_ulong physical;
466     int prot, ret, access_type;
467 
468     access_type = ACCESS_INT;
469     ret =
470 	get_physical_address(env, &physical, &prot, address, rw,
471 			     access_type);
472 
473     if (ret != MMU_OK) {
474 	env->tea = address;
475 	if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
476 	    env->pteh = (env->pteh & PTEH_ASID_MASK) |
477 		    (address & PTEH_VPN_MASK);
478 	}
479 	switch (ret) {
480 	case MMU_ITLB_MISS:
481 	case MMU_DTLB_MISS_READ:
482             cs->exception_index = 0x040;
483 	    break;
484 	case MMU_DTLB_MULTIPLE:
485 	case MMU_ITLB_MULTIPLE:
486             cs->exception_index = 0x140;
487 	    break;
488 	case MMU_ITLB_VIOLATION:
489             cs->exception_index = 0x0a0;
490 	    break;
491 	case MMU_DTLB_MISS_WRITE:
492             cs->exception_index = 0x060;
493 	    break;
494 	case MMU_DTLB_INITIAL_WRITE:
495             cs->exception_index = 0x080;
496 	    break;
497 	case MMU_DTLB_VIOLATION_READ:
498             cs->exception_index = 0x0a0;
499 	    break;
500 	case MMU_DTLB_VIOLATION_WRITE:
501             cs->exception_index = 0x0c0;
502 	    break;
503 	case MMU_IADDR_ERROR:
504 	case MMU_DADDR_ERROR_READ:
505             cs->exception_index = 0x0e0;
506 	    break;
507 	case MMU_DADDR_ERROR_WRITE:
508             cs->exception_index = 0x100;
509 	    break;
510 	default:
511             cpu_abort(cs, "Unhandled MMU fault");
512 	}
513 	return 1;
514     }
515 
516     address &= TARGET_PAGE_MASK;
517     physical &= TARGET_PAGE_MASK;
518 
519     tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
520     return 0;
521 }
522 
523 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
524 {
525     SuperHCPU *cpu = SUPERH_CPU(cs);
526     target_ulong physical;
527     int prot;
528 
529     get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
530     return physical;
531 }
532 
533 void cpu_load_tlb(CPUSH4State * env)
534 {
535     SuperHCPU *cpu = sh_env_get_cpu(env);
536     int n = cpu_mmucr_urc(env->mmucr);
537     tlb_t * entry = &env->utlb[n];
538 
539     if (entry->v) {
540         /* Overwriting valid entry in utlb. */
541         target_ulong address = entry->vpn << 10;
542         tlb_flush_page(CPU(cpu), address);
543     }
544 
545     /* Take values into cpu status from registers. */
546     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
547     entry->vpn  = cpu_pteh_vpn(env->pteh);
548     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
549     entry->ppn  = cpu_ptel_ppn(env->ptel);
550     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
551     switch (entry->sz) {
552     case 0: /* 00 */
553         entry->size = 1024; /* 1K */
554         break;
555     case 1: /* 01 */
556         entry->size = 1024 * 4; /* 4K */
557         break;
558     case 2: /* 10 */
559         entry->size = 1024 * 64; /* 64K */
560         break;
561     case 3: /* 11 */
562         entry->size = 1024 * 1024; /* 1M */
563         break;
564     default:
565         cpu_abort(CPU(cpu), "Unhandled load_tlb");
566         break;
567     }
568     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
569     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
570     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
571     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
572     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
573     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
574     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
575 }
576 
577  void cpu_sh4_invalidate_tlb(CPUSH4State *s)
578 {
579     int i;
580 
581     /* UTLB */
582     for (i = 0; i < UTLB_SIZE; i++) {
583         tlb_t * entry = &s->utlb[i];
584         entry->v = 0;
585     }
586     /* ITLB */
587     for (i = 0; i < ITLB_SIZE; i++) {
588         tlb_t * entry = &s->itlb[i];
589         entry->v = 0;
590     }
591 
592     tlb_flush(CPU(sh_env_get_cpu(s)));
593 }
594 
595 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
596                                        hwaddr addr)
597 {
598     int index = (addr & 0x00000300) >> 8;
599     tlb_t * entry = &s->itlb[index];
600 
601     return (entry->vpn  << 10) |
602            (entry->v    <<  8) |
603            (entry->asid);
604 }
605 
606 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
607 				    uint32_t mem_value)
608 {
609     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
610     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
611     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
612 
613     int index = (addr & 0x00000300) >> 8;
614     tlb_t * entry = &s->itlb[index];
615     if (entry->v) {
616         /* Overwriting valid entry in itlb. */
617         target_ulong address = entry->vpn << 10;
618         tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
619     }
620     entry->asid = asid;
621     entry->vpn = vpn;
622     entry->v = v;
623 }
624 
625 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
626                                        hwaddr addr)
627 {
628     int array = (addr & 0x00800000) >> 23;
629     int index = (addr & 0x00000300) >> 8;
630     tlb_t * entry = &s->itlb[index];
631 
632     if (array == 0) {
633         /* ITLB Data Array 1 */
634         return (entry->ppn << 10) |
635                (entry->v   <<  8) |
636                (entry->pr  <<  5) |
637                ((entry->sz & 1) <<  6) |
638                ((entry->sz & 2) <<  4) |
639                (entry->c   <<  3) |
640                (entry->sh  <<  1);
641     } else {
642         /* ITLB Data Array 2 */
643         return (entry->tc << 1) |
644                (entry->sa);
645     }
646 }
647 
648 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
649                                     uint32_t mem_value)
650 {
651     int array = (addr & 0x00800000) >> 23;
652     int index = (addr & 0x00000300) >> 8;
653     tlb_t * entry = &s->itlb[index];
654 
655     if (array == 0) {
656         /* ITLB Data Array 1 */
657         if (entry->v) {
658             /* Overwriting valid entry in utlb. */
659             target_ulong address = entry->vpn << 10;
660             tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
661         }
662         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
663         entry->v   = (mem_value & 0x00000100) >> 8;
664         entry->sz  = (mem_value & 0x00000080) >> 6 |
665                      (mem_value & 0x00000010) >> 4;
666         entry->pr  = (mem_value & 0x00000040) >> 5;
667         entry->c   = (mem_value & 0x00000008) >> 3;
668         entry->sh  = (mem_value & 0x00000002) >> 1;
669     } else {
670         /* ITLB Data Array 2 */
671         entry->tc  = (mem_value & 0x00000008) >> 3;
672         entry->sa  = (mem_value & 0x00000007);
673     }
674 }
675 
676 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
677                                        hwaddr addr)
678 {
679     int index = (addr & 0x00003f00) >> 8;
680     tlb_t * entry = &s->utlb[index];
681 
682     increment_urc(s); /* per utlb access */
683 
684     return (entry->vpn  << 10) |
685            (entry->v    <<  8) |
686            (entry->asid);
687 }
688 
689 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
690 				    uint32_t mem_value)
691 {
692     int associate = addr & 0x0000080;
693     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
694     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
695     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
696     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
697     int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
698 
699     if (associate) {
700         int i;
701 	tlb_t * utlb_match_entry = NULL;
702 	int needs_tlb_flush = 0;
703 
704 	/* search UTLB */
705 	for (i = 0; i < UTLB_SIZE; i++) {
706             tlb_t * entry = &s->utlb[i];
707             if (!entry->v)
708 	        continue;
709 
710             if (entry->vpn == vpn
711                 && (!use_asid || entry->asid == asid || entry->sh)) {
712 	        if (utlb_match_entry) {
713                     CPUState *cs = CPU(sh_env_get_cpu(s));
714 
715 		    /* Multiple TLB Exception */
716                     cs->exception_index = 0x140;
717 		    s->tea = addr;
718 		    break;
719 	        }
720 		if (entry->v && !v)
721 		    needs_tlb_flush = 1;
722 		entry->v = v;
723 		entry->d = d;
724 	        utlb_match_entry = entry;
725 	    }
726 	    increment_urc(s); /* per utlb access */
727 	}
728 
729 	/* search ITLB */
730 	for (i = 0; i < ITLB_SIZE; i++) {
731             tlb_t * entry = &s->itlb[i];
732             if (entry->vpn == vpn
733                 && (!use_asid || entry->asid == asid || entry->sh)) {
734 	        if (entry->v && !v)
735 		    needs_tlb_flush = 1;
736 	        if (utlb_match_entry)
737 		    *entry = *utlb_match_entry;
738 	        else
739 		    entry->v = v;
740 		break;
741 	    }
742 	}
743 
744         if (needs_tlb_flush) {
745             tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
746         }
747 
748     } else {
749         int index = (addr & 0x00003f00) >> 8;
750         tlb_t * entry = &s->utlb[index];
751 	if (entry->v) {
752             CPUState *cs = CPU(sh_env_get_cpu(s));
753 
754 	    /* Overwriting valid entry in utlb. */
755             target_ulong address = entry->vpn << 10;
756             tlb_flush_page(cs, address);
757 	}
758 	entry->asid = asid;
759 	entry->vpn = vpn;
760 	entry->d = d;
761 	entry->v = v;
762 	increment_urc(s);
763     }
764 }
765 
766 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
767                                        hwaddr addr)
768 {
769     int array = (addr & 0x00800000) >> 23;
770     int index = (addr & 0x00003f00) >> 8;
771     tlb_t * entry = &s->utlb[index];
772 
773     increment_urc(s); /* per utlb access */
774 
775     if (array == 0) {
776         /* ITLB Data Array 1 */
777         return (entry->ppn << 10) |
778                (entry->v   <<  8) |
779                (entry->pr  <<  5) |
780                ((entry->sz & 1) <<  6) |
781                ((entry->sz & 2) <<  4) |
782                (entry->c   <<  3) |
783                (entry->d   <<  2) |
784                (entry->sh  <<  1) |
785                (entry->wt);
786     } else {
787         /* ITLB Data Array 2 */
788         return (entry->tc << 1) |
789                (entry->sa);
790     }
791 }
792 
793 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
794                                     uint32_t mem_value)
795 {
796     int array = (addr & 0x00800000) >> 23;
797     int index = (addr & 0x00003f00) >> 8;
798     tlb_t * entry = &s->utlb[index];
799 
800     increment_urc(s); /* per utlb access */
801 
802     if (array == 0) {
803         /* UTLB Data Array 1 */
804         if (entry->v) {
805             /* Overwriting valid entry in utlb. */
806             target_ulong address = entry->vpn << 10;
807             tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
808         }
809         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
810         entry->v   = (mem_value & 0x00000100) >> 8;
811         entry->sz  = (mem_value & 0x00000080) >> 6 |
812                      (mem_value & 0x00000010) >> 4;
813         entry->pr  = (mem_value & 0x00000060) >> 5;
814         entry->c   = (mem_value & 0x00000008) >> 3;
815         entry->d   = (mem_value & 0x00000004) >> 2;
816         entry->sh  = (mem_value & 0x00000002) >> 1;
817         entry->wt  = (mem_value & 0x00000001);
818     } else {
819         /* UTLB Data Array 2 */
820         entry->tc = (mem_value & 0x00000008) >> 3;
821         entry->sa = (mem_value & 0x00000007);
822     }
823 }
824 
825 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
826 {
827     int n;
828     int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
829 
830     /* check area */
831     if (env->sr & (1u << SR_MD)) {
832         /* For privileged mode, P2 and P4 area is not cacheable. */
833         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
834             return 0;
835     } else {
836         /* For user mode, only U0 area is cacheable. */
837         if (0x80000000 <= addr)
838             return 0;
839     }
840 
841     /*
842      * TODO : Evaluate CCR and check if the cache is on or off.
843      *        Now CCR is not in CPUSH4State, but in SH7750State.
844      *        When you move the ccr into CPUSH4State, the code will be
845      *        as follows.
846      */
847 #if 0
848     /* check if operand cache is enabled or not. */
849     if (!(env->ccr & 1))
850         return 0;
851 #endif
852 
853     /* if MMU is off, no check for TLB. */
854     if (env->mmucr & MMUCR_AT)
855         return 1;
856 
857     /* check TLB */
858     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
859     if (n >= 0)
860         return env->itlb[n].c;
861 
862     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
863     if (n >= 0)
864         return env->utlb[n].c;
865 
866     return 0;
867 }
868 
869 #endif
870 
871 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
872 {
873     if (interrupt_request & CPU_INTERRUPT_HARD) {
874         SuperHCPU *cpu = SUPERH_CPU(cs);
875         CPUSH4State *env = &cpu->env;
876 
877         /* Delay slots are indivisible, ignore interrupts */
878         if (env->flags & DELAY_SLOT_MASK) {
879             return false;
880         } else {
881             superh_cpu_do_interrupt(cs);
882             return true;
883         }
884     }
885     return false;
886 }
887