1 /* 2 * SuperH gdb server stub 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "cpu.h" 23 #include "exec/gdbstub.h" 24 25 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ 26 /* FIXME: We should use XML for this. */ 27 28 int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) 29 { 30 SuperHCPU *cpu = SUPERH_CPU(cs); 31 CPUSH4State *env = &cpu->env; 32 33 switch (n) { 34 case 0 ... 7: 35 if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) { 36 return gdb_get_regl(mem_buf, env->gregs[n + 16]); 37 } else { 38 return gdb_get_regl(mem_buf, env->gregs[n]); 39 } 40 case 8 ... 15: 41 return gdb_get_regl(mem_buf, env->gregs[n]); 42 case 16: 43 return gdb_get_regl(mem_buf, env->pc); 44 case 17: 45 return gdb_get_regl(mem_buf, env->pr); 46 case 18: 47 return gdb_get_regl(mem_buf, env->gbr); 48 case 19: 49 return gdb_get_regl(mem_buf, env->vbr); 50 case 20: 51 return gdb_get_regl(mem_buf, env->mach); 52 case 21: 53 return gdb_get_regl(mem_buf, env->macl); 54 case 22: 55 return gdb_get_regl(mem_buf, cpu_read_sr(env)); 56 case 23: 57 return gdb_get_regl(mem_buf, env->fpul); 58 case 24: 59 return gdb_get_regl(mem_buf, env->fpscr); 60 case 25 ... 40: 61 if (env->fpscr & FPSCR_FR) { 62 stfl_p(mem_buf, env->fregs[n - 9]); 63 } else { 64 stfl_p(mem_buf, env->fregs[n - 25]); 65 } 66 return 4; 67 case 41: 68 return gdb_get_regl(mem_buf, env->ssr); 69 case 42: 70 return gdb_get_regl(mem_buf, env->spc); 71 case 43 ... 50: 72 return gdb_get_regl(mem_buf, env->gregs[n - 43]); 73 case 51 ... 58: 74 return gdb_get_regl(mem_buf, env->gregs[n - (51 - 16)]); 75 } 76 77 return 0; 78 } 79 80 int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 81 { 82 SuperHCPU *cpu = SUPERH_CPU(cs); 83 CPUSH4State *env = &cpu->env; 84 85 switch (n) { 86 case 0 ... 7: 87 if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) { 88 env->gregs[n + 16] = ldl_p(mem_buf); 89 } else { 90 env->gregs[n] = ldl_p(mem_buf); 91 } 92 break; 93 case 8 ... 15: 94 env->gregs[n] = ldl_p(mem_buf); 95 break; 96 case 16: 97 env->pc = ldl_p(mem_buf); 98 break; 99 case 17: 100 env->pr = ldl_p(mem_buf); 101 break; 102 case 18: 103 env->gbr = ldl_p(mem_buf); 104 break; 105 case 19: 106 env->vbr = ldl_p(mem_buf); 107 break; 108 case 20: 109 env->mach = ldl_p(mem_buf); 110 break; 111 case 21: 112 env->macl = ldl_p(mem_buf); 113 break; 114 case 22: 115 cpu_write_sr(env, ldl_p(mem_buf)); 116 break; 117 case 23: 118 env->fpul = ldl_p(mem_buf); 119 break; 120 case 24: 121 env->fpscr = ldl_p(mem_buf); 122 break; 123 case 25 ... 40: 124 if (env->fpscr & FPSCR_FR) { 125 env->fregs[n - 9] = ldfl_p(mem_buf); 126 } else { 127 env->fregs[n - 25] = ldfl_p(mem_buf); 128 } 129 break; 130 case 41: 131 env->ssr = ldl_p(mem_buf); 132 break; 133 case 42: 134 env->spc = ldl_p(mem_buf); 135 break; 136 case 43 ... 50: 137 env->gregs[n - 43] = ldl_p(mem_buf); 138 break; 139 case 51 ... 58: 140 env->gregs[n - (51 - 16)] = ldl_p(mem_buf); 141 break; 142 default: 143 return 0; 144 } 145 146 return 4; 147 } 148