1 /* 2 * SuperH gdb server stub 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "gdbstub/helpers.h" 23 24 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ 25 /* FIXME: We should use XML for this. */ 26 27 int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) 28 { 29 CPUSH4State *env = cpu_env(cs); 30 31 switch (n) { 32 case 0 ... 7: 33 if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) { 34 return gdb_get_regl(mem_buf, env->gregs[n + 16]); 35 } else { 36 return gdb_get_regl(mem_buf, env->gregs[n]); 37 } 38 case 8 ... 15: 39 return gdb_get_regl(mem_buf, env->gregs[n]); 40 case 16: 41 return gdb_get_regl(mem_buf, env->pc); 42 case 17: 43 return gdb_get_regl(mem_buf, env->pr); 44 case 18: 45 return gdb_get_regl(mem_buf, env->gbr); 46 case 19: 47 return gdb_get_regl(mem_buf, env->vbr); 48 case 20: 49 return gdb_get_regl(mem_buf, env->mach); 50 case 21: 51 return gdb_get_regl(mem_buf, env->macl); 52 case 22: 53 return gdb_get_regl(mem_buf, cpu_read_sr(env)); 54 case 23: 55 return gdb_get_regl(mem_buf, env->fpul); 56 case 24: 57 return gdb_get_regl(mem_buf, env->fpscr); 58 case 25 ... 40: 59 if (env->fpscr & FPSCR_FR) { 60 return gdb_get_reg32(mem_buf, env->fregs[n - 9]); 61 } 62 return gdb_get_reg32(mem_buf, env->fregs[n - 25]); 63 case 41: 64 return gdb_get_regl(mem_buf, env->ssr); 65 case 42: 66 return gdb_get_regl(mem_buf, env->spc); 67 case 43 ... 50: 68 return gdb_get_regl(mem_buf, env->gregs[n - 43]); 69 case 51 ... 58: 70 return gdb_get_regl(mem_buf, env->gregs[n - (51 - 16)]); 71 } 72 73 return 0; 74 } 75 76 int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 77 { 78 CPUSH4State *env = cpu_env(cs); 79 80 switch (n) { 81 case 0 ... 7: 82 if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) { 83 env->gregs[n + 16] = ldl_p(mem_buf); 84 } else { 85 env->gregs[n] = ldl_p(mem_buf); 86 } 87 break; 88 case 8 ... 15: 89 env->gregs[n] = ldl_p(mem_buf); 90 break; 91 case 16: 92 env->pc = ldl_p(mem_buf); 93 break; 94 case 17: 95 env->pr = ldl_p(mem_buf); 96 break; 97 case 18: 98 env->gbr = ldl_p(mem_buf); 99 break; 100 case 19: 101 env->vbr = ldl_p(mem_buf); 102 break; 103 case 20: 104 env->mach = ldl_p(mem_buf); 105 break; 106 case 21: 107 env->macl = ldl_p(mem_buf); 108 break; 109 case 22: 110 cpu_write_sr(env, ldl_p(mem_buf)); 111 break; 112 case 23: 113 env->fpul = ldl_p(mem_buf); 114 break; 115 case 24: 116 env->fpscr = ldl_p(mem_buf); 117 break; 118 case 25 ... 40: 119 if (env->fpscr & FPSCR_FR) { 120 env->fregs[n - 9] = ldl_p(mem_buf); 121 } else { 122 env->fregs[n - 25] = ldl_p(mem_buf); 123 } 124 break; 125 case 41: 126 env->ssr = ldl_p(mem_buf); 127 break; 128 case 42: 129 env->spc = ldl_p(mem_buf); 130 break; 131 case 43 ... 50: 132 env->gregs[n - 43] = ldl_p(mem_buf); 133 break; 134 case 51 ... 58: 135 env->gregs[n - (51 - 16)] = ldl_p(mem_buf); 136 break; 137 default: 138 return 0; 139 } 140 141 return 4; 142 } 143