1 /* 2 * SH4 emulation 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef SH4_CPU_H 21 #define SH4_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 26 #define TARGET_LONG_BITS 32 27 #define ALIGNED_ONLY 28 29 /* CPU Subtypes */ 30 #define SH_CPU_SH7750 (1 << 0) 31 #define SH_CPU_SH7750S (1 << 1) 32 #define SH_CPU_SH7750R (1 << 2) 33 #define SH_CPU_SH7751 (1 << 3) 34 #define SH_CPU_SH7751R (1 << 4) 35 #define SH_CPU_SH7785 (1 << 5) 36 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) 37 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) 38 39 #define CPUArchState struct CPUSH4State 40 41 #include "exec/cpu-defs.h" 42 43 #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ 44 45 #define TARGET_PHYS_ADDR_SPACE_BITS 32 46 #ifdef CONFIG_USER_ONLY 47 # define TARGET_VIRT_ADDR_SPACE_BITS 31 48 #else 49 # define TARGET_VIRT_ADDR_SPACE_BITS 32 50 #endif 51 52 #define SR_MD 30 53 #define SR_RB 29 54 #define SR_BL 28 55 #define SR_FD 15 56 #define SR_M 9 57 #define SR_Q 8 58 #define SR_I3 7 59 #define SR_I2 6 60 #define SR_I1 5 61 #define SR_I0 4 62 #define SR_S 1 63 #define SR_T 0 64 65 #define FPSCR_MASK (0x003fffff) 66 #define FPSCR_FR (1 << 21) 67 #define FPSCR_SZ (1 << 20) 68 #define FPSCR_PR (1 << 19) 69 #define FPSCR_DN (1 << 18) 70 #define FPSCR_CAUSE_MASK (0x3f << 12) 71 #define FPSCR_CAUSE_SHIFT (12) 72 #define FPSCR_CAUSE_E (1 << 17) 73 #define FPSCR_CAUSE_V (1 << 16) 74 #define FPSCR_CAUSE_Z (1 << 15) 75 #define FPSCR_CAUSE_O (1 << 14) 76 #define FPSCR_CAUSE_U (1 << 13) 77 #define FPSCR_CAUSE_I (1 << 12) 78 #define FPSCR_ENABLE_MASK (0x1f << 7) 79 #define FPSCR_ENABLE_SHIFT (7) 80 #define FPSCR_ENABLE_V (1 << 11) 81 #define FPSCR_ENABLE_Z (1 << 10) 82 #define FPSCR_ENABLE_O (1 << 9) 83 #define FPSCR_ENABLE_U (1 << 8) 84 #define FPSCR_ENABLE_I (1 << 7) 85 #define FPSCR_FLAG_MASK (0x1f << 2) 86 #define FPSCR_FLAG_SHIFT (2) 87 #define FPSCR_FLAG_V (1 << 6) 88 #define FPSCR_FLAG_Z (1 << 5) 89 #define FPSCR_FLAG_O (1 << 4) 90 #define FPSCR_FLAG_U (1 << 3) 91 #define FPSCR_FLAG_I (1 << 2) 92 #define FPSCR_RM_MASK (0x03 << 0) 93 #define FPSCR_RM_NEAREST (0 << 0) 94 #define FPSCR_RM_ZERO (1 << 0) 95 96 #define DELAY_SLOT_MASK 0x7 97 #define DELAY_SLOT (1 << 0) 98 #define DELAY_SLOT_CONDITIONAL (1 << 1) 99 #define DELAY_SLOT_RTE (1 << 2) 100 101 #define TB_FLAG_PENDING_MOVCA (1 << 3) 102 103 #define GUSA_SHIFT 4 104 #ifdef CONFIG_USER_ONLY 105 #define GUSA_EXCLUSIVE (1 << 12) 106 #define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE) 107 #else 108 /* Provide dummy versions of the above to allow tests against tbflags 109 to be elided while avoiding ifdefs. */ 110 #define GUSA_EXCLUSIVE 0 111 #define GUSA_MASK 0 112 #endif 113 114 #define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK) 115 116 typedef struct tlb_t { 117 uint32_t vpn; /* virtual page number */ 118 uint32_t ppn; /* physical page number */ 119 uint32_t size; /* mapped page size in bytes */ 120 uint8_t asid; /* address space identifier */ 121 uint8_t v:1; /* validity */ 122 uint8_t sz:2; /* page size */ 123 uint8_t sh:1; /* share status */ 124 uint8_t c:1; /* cacheability */ 125 uint8_t pr:2; /* protection key */ 126 uint8_t d:1; /* dirty */ 127 uint8_t wt:1; /* write through */ 128 uint8_t sa:3; /* space attribute (PCMCIA) */ 129 uint8_t tc:1; /* timing control */ 130 } tlb_t; 131 132 #define UTLB_SIZE 64 133 #define ITLB_SIZE 4 134 135 #define NB_MMU_MODES 2 136 #define TARGET_INSN_START_EXTRA_WORDS 1 137 138 enum sh_features { 139 SH_FEATURE_SH4A = 1, 140 SH_FEATURE_BCR3_AND_BCR4 = 2, 141 }; 142 143 typedef struct memory_content { 144 uint32_t address; 145 uint32_t value; 146 struct memory_content *next; 147 } memory_content; 148 149 typedef struct CPUSH4State { 150 uint32_t flags; /* general execution flags */ 151 uint32_t gregs[24]; /* general registers */ 152 float32 fregs[32]; /* floating point registers */ 153 uint32_t sr; /* status register (with T split out) */ 154 uint32_t sr_m; /* M bit of status register */ 155 uint32_t sr_q; /* Q bit of status register */ 156 uint32_t sr_t; /* T bit of status register */ 157 uint32_t ssr; /* saved status register */ 158 uint32_t spc; /* saved program counter */ 159 uint32_t gbr; /* global base register */ 160 uint32_t vbr; /* vector base register */ 161 uint32_t sgr; /* saved global register 15 */ 162 uint32_t dbr; /* debug base register */ 163 uint32_t pc; /* program counter */ 164 uint32_t delayed_pc; /* target of delayed branch */ 165 uint32_t delayed_cond; /* condition of delayed branch */ 166 uint32_t mach; /* multiply and accumulate high */ 167 uint32_t macl; /* multiply and accumulate low */ 168 uint32_t pr; /* procedure register */ 169 uint32_t fpscr; /* floating point status/control register */ 170 uint32_t fpul; /* floating point communication register */ 171 172 /* float point status register */ 173 float_status fp_status; 174 175 /* Those belong to the specific unit (SH7750) but are handled here */ 176 uint32_t mmucr; /* MMU control register */ 177 uint32_t pteh; /* page table entry high register */ 178 uint32_t ptel; /* page table entry low register */ 179 uint32_t ptea; /* page table entry assistance register */ 180 uint32_t ttb; /* tranlation table base register */ 181 uint32_t tea; /* TLB exception address register */ 182 uint32_t tra; /* TRAPA exception register */ 183 uint32_t expevt; /* exception event register */ 184 uint32_t intevt; /* interrupt event register */ 185 186 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ 187 tlb_t utlb[UTLB_SIZE]; /* unified translation table */ 188 189 /* LDST = LOCK_ADDR != -1. */ 190 uint32_t lock_addr; 191 uint32_t lock_value; 192 193 /* Fields up to this point are cleared by a CPU reset */ 194 struct {} end_reset_fields; 195 196 CPU_COMMON 197 198 /* Fields from here on are preserved over CPU reset. */ 199 int id; /* CPU model */ 200 201 /* The features that we should emulate. See sh_features above. */ 202 uint32_t features; 203 204 void *intc_handle; 205 int in_sleep; /* SR_BL ignored during sleep */ 206 memory_content *movcal_backup; 207 memory_content **movcal_backup_tail; 208 } CPUSH4State; 209 210 /** 211 * SuperHCPU: 212 * @env: #CPUSH4State 213 * 214 * A SuperH CPU. 215 */ 216 struct SuperHCPU { 217 /*< private >*/ 218 CPUState parent_obj; 219 /*< public >*/ 220 221 CPUSH4State env; 222 }; 223 224 static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) 225 { 226 return container_of(env, SuperHCPU, env); 227 } 228 229 #define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e)) 230 231 #define ENV_OFFSET offsetof(SuperHCPU, env) 232 233 void superh_cpu_do_interrupt(CPUState *cpu); 234 bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); 235 void superh_cpu_dump_state(CPUState *cpu, FILE *f, 236 fprintf_function cpu_fprintf, int flags); 237 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 238 int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 239 int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 240 void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 241 MMUAccessType access_type, 242 int mmu_idx, uintptr_t retaddr); 243 244 void sh4_translate_init(void); 245 int cpu_sh4_signal_handler(int host_signum, void *pinfo, 246 void *puc); 247 int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, 248 int mmu_idx); 249 250 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf); 251 #if !defined(CONFIG_USER_ONLY) 252 void cpu_sh4_invalidate_tlb(CPUSH4State *s); 253 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, 254 hwaddr addr); 255 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, 256 uint32_t mem_value); 257 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, 258 hwaddr addr); 259 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, 260 uint32_t mem_value); 261 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, 262 hwaddr addr); 263 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, 264 uint32_t mem_value); 265 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, 266 hwaddr addr); 267 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, 268 uint32_t mem_value); 269 #endif 270 271 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); 272 273 void cpu_load_tlb(CPUSH4State * env); 274 275 #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU 276 #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX 277 #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU 278 279 #define cpu_signal_handler cpu_sh4_signal_handler 280 #define cpu_list sh4_cpu_list 281 282 /* MMU modes definitions */ 283 #define MMU_MODE0_SUFFIX _kernel 284 #define MMU_MODE1_SUFFIX _user 285 #define MMU_USER_IDX 1 286 static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) 287 { 288 /* The instruction in a RTE delay slot is fetched in privileged 289 mode, but executed in user mode. */ 290 if (ifetch && (env->flags & DELAY_SLOT_RTE)) { 291 return 0; 292 } else { 293 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; 294 } 295 } 296 297 #include "exec/cpu-all.h" 298 299 /* Memory access type */ 300 enum { 301 /* Privilege */ 302 ACCESS_PRIV = 0x01, 303 /* Direction */ 304 ACCESS_WRITE = 0x02, 305 /* Type of instruction */ 306 ACCESS_CODE = 0x10, 307 ACCESS_INT = 0x20 308 }; 309 310 /* MMU control register */ 311 #define MMUCR 0x1F000010 312 #define MMUCR_AT (1<<0) 313 #define MMUCR_TI (1<<2) 314 #define MMUCR_SV (1<<8) 315 #define MMUCR_URC_BITS (6) 316 #define MMUCR_URC_OFFSET (10) 317 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) 318 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) 319 static inline int cpu_mmucr_urc (uint32_t mmucr) 320 { 321 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET); 322 } 323 324 /* PTEH : Page Translation Entry High register */ 325 #define PTEH_ASID_BITS (8) 326 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) 327 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) 328 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK) 329 #define PTEH_VPN_BITS (22) 330 #define PTEH_VPN_OFFSET (10) 331 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) 332 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) 333 static inline int cpu_pteh_vpn (uint32_t pteh) 334 { 335 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET); 336 } 337 338 /* PTEL : Page Translation Entry Low register */ 339 #define PTEL_V (1 << 8) 340 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) 341 #define PTEL_C (1 << 3) 342 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) 343 #define PTEL_D (1 << 2) 344 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) 345 #define PTEL_SH (1 << 1) 346 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) 347 #define PTEL_WT (1 << 0) 348 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT) 349 350 #define PTEL_SZ_HIGH_OFFSET (7) 351 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) 352 #define PTEL_SZ_LOW_OFFSET (4) 353 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) 354 static inline int cpu_ptel_sz (uint32_t ptel) 355 { 356 int sz; 357 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; 358 sz <<= 1; 359 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; 360 return sz; 361 } 362 363 #define PTEL_PPN_BITS (19) 364 #define PTEL_PPN_OFFSET (10) 365 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) 366 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) 367 static inline int cpu_ptel_ppn (uint32_t ptel) 368 { 369 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET); 370 } 371 372 #define PTEL_PR_BITS (2) 373 #define PTEL_PR_OFFSET (5) 374 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) 375 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) 376 static inline int cpu_ptel_pr (uint32_t ptel) 377 { 378 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET); 379 } 380 381 /* PTEA : Page Translation Entry Assistance register */ 382 #define PTEA_SA_BITS (3) 383 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) 384 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) 385 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK) 386 #define PTEA_TC (1 << 3) 387 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) 388 389 static inline target_ulong cpu_read_sr(CPUSH4State *env) 390 { 391 return env->sr | (env->sr_m << SR_M) | 392 (env->sr_q << SR_Q) | 393 (env->sr_t << SR_T); 394 } 395 396 static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) 397 { 398 env->sr_m = (sr >> SR_M) & 1; 399 env->sr_q = (sr >> SR_Q) & 1; 400 env->sr_t = (sr >> SR_T) & 1; 401 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); 402 } 403 404 static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, 405 target_ulong *cs_base, uint32_t *flags) 406 { 407 *pc = env->pc; 408 /* For a gUSA region, notice the end of the region. */ 409 *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0; 410 *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */ 411 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */ 412 | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */ 413 | (env->sr & (1u << SR_FD)) /* Bit 15 */ 414 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ 415 } 416 417 #endif /* SH4_CPU_H */ 418