xref: /openbmc/qemu/target/sh4/cpu.h (revision 9d81b2d2)
1  /*
2   *  SH4 emulation
3   *
4   *  Copyright (c) 2005 Samuel Tardieu
5   *
6   * This library is free software; you can redistribute it and/or
7   * modify it under the terms of the GNU Lesser General Public
8   * License as published by the Free Software Foundation; either
9   * version 2 of the License, or (at your option) any later version.
10   *
11   * This library is distributed in the hope that it will be useful,
12   * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14   * Lesser General Public License for more details.
15   *
16   * You should have received a copy of the GNU Lesser General Public
17   * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18   */
19  
20  #ifndef SH4_CPU_H
21  #define SH4_CPU_H
22  
23  #include "qemu-common.h"
24  #include "cpu-qom.h"
25  
26  #define TARGET_LONG_BITS 32
27  #define ALIGNED_ONLY
28  
29  /* CPU Subtypes */
30  #define SH_CPU_SH7750  (1 << 0)
31  #define SH_CPU_SH7750S (1 << 1)
32  #define SH_CPU_SH7750R (1 << 2)
33  #define SH_CPU_SH7751  (1 << 3)
34  #define SH_CPU_SH7751R (1 << 4)
35  #define SH_CPU_SH7785  (1 << 5)
36  #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
37  #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
38  
39  #define CPUArchState struct CPUSH4State
40  
41  #include "exec/cpu-defs.h"
42  
43  #include "fpu/softfloat.h"
44  
45  #define TARGET_PAGE_BITS 12	/* 4k XXXXX */
46  
47  #define TARGET_PHYS_ADDR_SPACE_BITS 32
48  #define TARGET_VIRT_ADDR_SPACE_BITS 32
49  
50  #define SR_MD 30
51  #define SR_RB 29
52  #define SR_BL 28
53  #define SR_FD 15
54  #define SR_M  9
55  #define SR_Q  8
56  #define SR_I3 7
57  #define SR_I2 6
58  #define SR_I1 5
59  #define SR_I0 4
60  #define SR_S  1
61  #define SR_T  0
62  
63  #define FPSCR_MASK             (0x003fffff)
64  #define FPSCR_FR               (1 << 21)
65  #define FPSCR_SZ               (1 << 20)
66  #define FPSCR_PR               (1 << 19)
67  #define FPSCR_DN               (1 << 18)
68  #define FPSCR_CAUSE_MASK       (0x3f << 12)
69  #define FPSCR_CAUSE_SHIFT      (12)
70  #define FPSCR_CAUSE_E          (1 << 17)
71  #define FPSCR_CAUSE_V          (1 << 16)
72  #define FPSCR_CAUSE_Z          (1 << 15)
73  #define FPSCR_CAUSE_O          (1 << 14)
74  #define FPSCR_CAUSE_U          (1 << 13)
75  #define FPSCR_CAUSE_I          (1 << 12)
76  #define FPSCR_ENABLE_MASK      (0x1f << 7)
77  #define FPSCR_ENABLE_SHIFT     (7)
78  #define FPSCR_ENABLE_V         (1 << 11)
79  #define FPSCR_ENABLE_Z         (1 << 10)
80  #define FPSCR_ENABLE_O         (1 << 9)
81  #define FPSCR_ENABLE_U         (1 << 8)
82  #define FPSCR_ENABLE_I         (1 << 7)
83  #define FPSCR_FLAG_MASK        (0x1f << 2)
84  #define FPSCR_FLAG_SHIFT       (2)
85  #define FPSCR_FLAG_V           (1 << 6)
86  #define FPSCR_FLAG_Z           (1 << 5)
87  #define FPSCR_FLAG_O           (1 << 4)
88  #define FPSCR_FLAG_U           (1 << 3)
89  #define FPSCR_FLAG_I           (1 << 2)
90  #define FPSCR_RM_MASK          (0x03 << 0)
91  #define FPSCR_RM_NEAREST       (0 << 0)
92  #define FPSCR_RM_ZERO          (1 << 0)
93  
94  #define DELAY_SLOT_MASK        0x7
95  #define DELAY_SLOT             (1 << 0)
96  #define DELAY_SLOT_CONDITIONAL (1 << 1)
97  #define DELAY_SLOT_RTE         (1 << 2)
98  
99  #define TB_FLAG_PENDING_MOVCA  (1 << 3)
100  
101  #define GUSA_SHIFT             4
102  #ifdef CONFIG_USER_ONLY
103  #define GUSA_EXCLUSIVE         (1 << 12)
104  #define GUSA_MASK              ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
105  #else
106  /* Provide dummy versions of the above to allow tests against tbflags
107     to be elided while avoiding ifdefs.  */
108  #define GUSA_EXCLUSIVE         0
109  #define GUSA_MASK              0
110  #endif
111  
112  #define TB_FLAG_ENVFLAGS_MASK  (DELAY_SLOT_MASK | GUSA_MASK)
113  
114  typedef struct tlb_t {
115      uint32_t vpn;		/* virtual page number */
116      uint32_t ppn;		/* physical page number */
117      uint32_t size;		/* mapped page size in bytes */
118      uint8_t asid;		/* address space identifier */
119      uint8_t v:1;		/* validity */
120      uint8_t sz:2;		/* page size */
121      uint8_t sh:1;		/* share status */
122      uint8_t c:1;		/* cacheability */
123      uint8_t pr:2;		/* protection key */
124      uint8_t d:1;		/* dirty */
125      uint8_t wt:1;		/* write through */
126      uint8_t sa:3;		/* space attribute (PCMCIA) */
127      uint8_t tc:1;		/* timing control */
128  } tlb_t;
129  
130  #define UTLB_SIZE 64
131  #define ITLB_SIZE 4
132  
133  #define NB_MMU_MODES 2
134  #define TARGET_INSN_START_EXTRA_WORDS 1
135  
136  enum sh_features {
137      SH_FEATURE_SH4A = 1,
138      SH_FEATURE_BCR3_AND_BCR4 = 2,
139  };
140  
141  typedef struct memory_content {
142      uint32_t address;
143      uint32_t value;
144      struct memory_content *next;
145  } memory_content;
146  
147  typedef struct CPUSH4State {
148      uint32_t flags;		/* general execution flags */
149      uint32_t gregs[24];		/* general registers */
150      float32 fregs[32];		/* floating point registers */
151      uint32_t sr;                /* status register (with T split out) */
152      uint32_t sr_m;              /* M bit of status register */
153      uint32_t sr_q;              /* Q bit of status register */
154      uint32_t sr_t;              /* T bit of status register */
155      uint32_t ssr;		/* saved status register */
156      uint32_t spc;		/* saved program counter */
157      uint32_t gbr;		/* global base register */
158      uint32_t vbr;		/* vector base register */
159      uint32_t sgr;		/* saved global register 15 */
160      uint32_t dbr;		/* debug base register */
161      uint32_t pc;		/* program counter */
162      uint32_t delayed_pc;        /* target of delayed branch */
163      uint32_t delayed_cond;      /* condition of delayed branch */
164      uint32_t mach;		/* multiply and accumulate high */
165      uint32_t macl;		/* multiply and accumulate low */
166      uint32_t pr;		/* procedure register */
167      uint32_t fpscr;		/* floating point status/control register */
168      uint32_t fpul;		/* floating point communication register */
169  
170      /* float point status register */
171      float_status fp_status;
172  
173      /* Those belong to the specific unit (SH7750) but are handled here */
174      uint32_t mmucr;		/* MMU control register */
175      uint32_t pteh;		/* page table entry high register */
176      uint32_t ptel;		/* page table entry low register */
177      uint32_t ptea;		/* page table entry assistance register */
178      uint32_t ttb;		/* tranlation table base register */
179      uint32_t tea;		/* TLB exception address register */
180      uint32_t tra;		/* TRAPA exception register */
181      uint32_t expevt;		/* exception event register */
182      uint32_t intevt;		/* interrupt event register */
183  
184      tlb_t itlb[ITLB_SIZE];	/* instruction translation table */
185      tlb_t utlb[UTLB_SIZE];	/* unified translation table */
186  
187      uint32_t ldst;
188  
189      /* Fields up to this point are cleared by a CPU reset */
190      struct {} end_reset_fields;
191  
192      CPU_COMMON
193  
194      /* Fields from here on are preserved over CPU reset. */
195      int id;			/* CPU model */
196  
197      /* The features that we should emulate. See sh_features above.  */
198      uint32_t features;
199  
200      void *intc_handle;
201      int in_sleep;		/* SR_BL ignored during sleep */
202      memory_content *movcal_backup;
203      memory_content **movcal_backup_tail;
204  } CPUSH4State;
205  
206  /**
207   * SuperHCPU:
208   * @env: #CPUSH4State
209   *
210   * A SuperH CPU.
211   */
212  struct SuperHCPU {
213      /*< private >*/
214      CPUState parent_obj;
215      /*< public >*/
216  
217      CPUSH4State env;
218  };
219  
220  static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
221  {
222      return container_of(env, SuperHCPU, env);
223  }
224  
225  #define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e))
226  
227  #define ENV_OFFSET offsetof(SuperHCPU, env)
228  
229  void superh_cpu_do_interrupt(CPUState *cpu);
230  bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
231  void superh_cpu_dump_state(CPUState *cpu, FILE *f,
232                             fprintf_function cpu_fprintf, int flags);
233  hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
234  int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
235  int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
236  void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
237                                      MMUAccessType access_type,
238                                      int mmu_idx, uintptr_t retaddr);
239  
240  void sh4_translate_init(void);
241  int cpu_sh4_signal_handler(int host_signum, void *pinfo,
242                             void *puc);
243  int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
244                                  int mmu_idx);
245  
246  void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
247  #if !defined(CONFIG_USER_ONLY)
248  void cpu_sh4_invalidate_tlb(CPUSH4State *s);
249  uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
250                                         hwaddr addr);
251  void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
252                                      uint32_t mem_value);
253  uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
254                                         hwaddr addr);
255  void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
256                                      uint32_t mem_value);
257  uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
258                                         hwaddr addr);
259  void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
260                                      uint32_t mem_value);
261  uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
262                                         hwaddr addr);
263  void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
264                                      uint32_t mem_value);
265  #endif
266  
267  int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
268  
269  void cpu_load_tlb(CPUSH4State * env);
270  
271  #define cpu_init(cpu_model) cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)
272  
273  #define cpu_signal_handler cpu_sh4_signal_handler
274  #define cpu_list sh4_cpu_list
275  
276  /* MMU modes definitions */
277  #define MMU_MODE0_SUFFIX _kernel
278  #define MMU_MODE1_SUFFIX _user
279  #define MMU_USER_IDX 1
280  static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
281  {
282      /* The instruction in a RTE delay slot is fetched in privileged
283         mode, but executed in user mode.  */
284      if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
285          return 0;
286      } else {
287          return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
288      }
289  }
290  
291  #include "exec/cpu-all.h"
292  
293  /* Memory access type */
294  enum {
295      /* Privilege */
296      ACCESS_PRIV = 0x01,
297      /* Direction */
298      ACCESS_WRITE = 0x02,
299      /* Type of instruction */
300      ACCESS_CODE = 0x10,
301      ACCESS_INT = 0x20
302  };
303  
304  /* MMU control register */
305  #define MMUCR    0x1F000010
306  #define MMUCR_AT (1<<0)
307  #define MMUCR_TI (1<<2)
308  #define MMUCR_SV (1<<8)
309  #define MMUCR_URC_BITS (6)
310  #define MMUCR_URC_OFFSET (10)
311  #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
312  #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
313  static inline int cpu_mmucr_urc (uint32_t mmucr)
314  {
315      return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
316  }
317  
318  /* PTEH : Page Translation Entry High register */
319  #define PTEH_ASID_BITS (8)
320  #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
321  #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
322  #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
323  #define PTEH_VPN_BITS (22)
324  #define PTEH_VPN_OFFSET (10)
325  #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
326  #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
327  static inline int cpu_pteh_vpn (uint32_t pteh)
328  {
329      return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
330  }
331  
332  /* PTEL : Page Translation Entry Low register */
333  #define PTEL_V        (1 << 8)
334  #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
335  #define PTEL_C        (1 << 3)
336  #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
337  #define PTEL_D        (1 << 2)
338  #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
339  #define PTEL_SH       (1 << 1)
340  #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
341  #define PTEL_WT       (1 << 0)
342  #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
343  
344  #define PTEL_SZ_HIGH_OFFSET  (7)
345  #define PTEL_SZ_HIGH  (1 << PTEL_SZ_HIGH_OFFSET)
346  #define PTEL_SZ_LOW_OFFSET   (4)
347  #define PTEL_SZ_LOW   (1 << PTEL_SZ_LOW_OFFSET)
348  static inline int cpu_ptel_sz (uint32_t ptel)
349  {
350      int sz;
351      sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
352      sz <<= 1;
353      sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
354      return sz;
355  }
356  
357  #define PTEL_PPN_BITS (19)
358  #define PTEL_PPN_OFFSET (10)
359  #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
360  #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
361  static inline int cpu_ptel_ppn (uint32_t ptel)
362  {
363      return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
364  }
365  
366  #define PTEL_PR_BITS   (2)
367  #define PTEL_PR_OFFSET (5)
368  #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
369  #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
370  static inline int cpu_ptel_pr (uint32_t ptel)
371  {
372      return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
373  }
374  
375  /* PTEA : Page Translation Entry Assistance register */
376  #define PTEA_SA_BITS (3)
377  #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
378  #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
379  #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
380  #define PTEA_TC        (1 << 3)
381  #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
382  
383  static inline target_ulong cpu_read_sr(CPUSH4State *env)
384  {
385      return env->sr | (env->sr_m << SR_M) |
386                       (env->sr_q << SR_Q) |
387                       (env->sr_t << SR_T);
388  }
389  
390  static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
391  {
392      env->sr_m = (sr >> SR_M) & 1;
393      env->sr_q = (sr >> SR_Q) & 1;
394      env->sr_t = (sr >> SR_T) & 1;
395      env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
396  }
397  
398  static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
399                                          target_ulong *cs_base, uint32_t *flags)
400  {
401      *pc = env->pc;
402      /* For a gUSA region, notice the end of the region.  */
403      *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
404      *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
405              | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */
406              | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))      /* Bits 29-30 */
407              | (env->sr & (1u << SR_FD))                        /* Bit 15 */
408              | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
409  }
410  
411  #endif /* SH4_CPU_H */
412