xref: /openbmc/qemu/target/sh4/cpu.h (revision 6c187695)
1 /*
2  *  SH4 emulation
3  *
4  *  Copyright (c) 2005 Samuel Tardieu
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef SH4_CPU_H
21 #define SH4_CPU_H
22 
23 #include "cpu-qom.h"
24 #include "exec/cpu-defs.h"
25 #include "qemu/cpu-float.h"
26 
27 /* CPU Subtypes */
28 #define SH_CPU_SH7750  (1 << 0)
29 #define SH_CPU_SH7750S (1 << 1)
30 #define SH_CPU_SH7750R (1 << 2)
31 #define SH_CPU_SH7751  (1 << 3)
32 #define SH_CPU_SH7751R (1 << 4)
33 #define SH_CPU_SH7785  (1 << 5)
34 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
35 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
36 
37 #define SR_MD 30
38 #define SR_RB 29
39 #define SR_BL 28
40 #define SR_FD 15
41 #define SR_M  9
42 #define SR_Q  8
43 #define SR_I3 7
44 #define SR_I2 6
45 #define SR_I1 5
46 #define SR_I0 4
47 #define SR_S  1
48 #define SR_T  0
49 
50 #define FPSCR_MASK             (0x003fffff)
51 #define FPSCR_FR               (1 << 21)
52 #define FPSCR_SZ               (1 << 20)
53 #define FPSCR_PR               (1 << 19)
54 #define FPSCR_DN               (1 << 18)
55 #define FPSCR_CAUSE_MASK       (0x3f << 12)
56 #define FPSCR_CAUSE_SHIFT      (12)
57 #define FPSCR_CAUSE_E          (1 << 17)
58 #define FPSCR_CAUSE_V          (1 << 16)
59 #define FPSCR_CAUSE_Z          (1 << 15)
60 #define FPSCR_CAUSE_O          (1 << 14)
61 #define FPSCR_CAUSE_U          (1 << 13)
62 #define FPSCR_CAUSE_I          (1 << 12)
63 #define FPSCR_ENABLE_MASK      (0x1f << 7)
64 #define FPSCR_ENABLE_SHIFT     (7)
65 #define FPSCR_ENABLE_V         (1 << 11)
66 #define FPSCR_ENABLE_Z         (1 << 10)
67 #define FPSCR_ENABLE_O         (1 << 9)
68 #define FPSCR_ENABLE_U         (1 << 8)
69 #define FPSCR_ENABLE_I         (1 << 7)
70 #define FPSCR_FLAG_MASK        (0x1f << 2)
71 #define FPSCR_FLAG_SHIFT       (2)
72 #define FPSCR_FLAG_V           (1 << 6)
73 #define FPSCR_FLAG_Z           (1 << 5)
74 #define FPSCR_FLAG_O           (1 << 4)
75 #define FPSCR_FLAG_U           (1 << 3)
76 #define FPSCR_FLAG_I           (1 << 2)
77 #define FPSCR_RM_MASK          (0x03 << 0)
78 #define FPSCR_RM_NEAREST       (0 << 0)
79 #define FPSCR_RM_ZERO          (1 << 0)
80 
81 #define TB_FLAG_DELAY_SLOT       (1 << 0)
82 #define TB_FLAG_DELAY_SLOT_COND  (1 << 1)
83 #define TB_FLAG_DELAY_SLOT_RTE   (1 << 2)
84 #define TB_FLAG_PENDING_MOVCA    (1 << 3)
85 #define TB_FLAG_GUSA_SHIFT       4                      /* [11:4] */
86 #define TB_FLAG_GUSA_EXCLUSIVE   (1 << 12)
87 #define TB_FLAG_UNALIGN          (1 << 13)
88 #define TB_FLAG_SR_FD            (1 << SR_FD)           /* 15 */
89 #define TB_FLAG_FPSCR_PR         FPSCR_PR               /* 19 */
90 #define TB_FLAG_FPSCR_SZ         FPSCR_SZ               /* 20 */
91 #define TB_FLAG_FPSCR_FR         FPSCR_FR               /* 21 */
92 #define TB_FLAG_SR_RB            (1 << SR_RB)           /* 29 */
93 #define TB_FLAG_SR_MD            (1 << SR_MD)           /* 30 */
94 
95 #define TB_FLAG_DELAY_SLOT_MASK  (TB_FLAG_DELAY_SLOT |       \
96                                   TB_FLAG_DELAY_SLOT_COND |  \
97                                   TB_FLAG_DELAY_SLOT_RTE)
98 #define TB_FLAG_GUSA_MASK        ((0xff << TB_FLAG_GUSA_SHIFT) | \
99                                   TB_FLAG_GUSA_EXCLUSIVE)
100 #define TB_FLAG_FPSCR_MASK       (TB_FLAG_FPSCR_PR | \
101                                   TB_FLAG_FPSCR_SZ | \
102                                   TB_FLAG_FPSCR_FR)
103 #define TB_FLAG_SR_MASK          (TB_FLAG_SR_FD | \
104                                   TB_FLAG_SR_RB | \
105                                   TB_FLAG_SR_MD)
106 #define TB_FLAG_ENVFLAGS_MASK    (TB_FLAG_DELAY_SLOT_MASK | \
107                                   TB_FLAG_GUSA_MASK)
108 
109 typedef struct tlb_t {
110     uint32_t vpn;		/* virtual page number */
111     uint32_t ppn;		/* physical page number */
112     uint32_t size;		/* mapped page size in bytes */
113     uint8_t asid;		/* address space identifier */
114     uint8_t v:1;		/* validity */
115     uint8_t sz:2;		/* page size */
116     uint8_t sh:1;		/* share status */
117     uint8_t c:1;		/* cacheability */
118     uint8_t pr:2;		/* protection key */
119     uint8_t d:1;		/* dirty */
120     uint8_t wt:1;		/* write through */
121     uint8_t sa:3;		/* space attribute (PCMCIA) */
122     uint8_t tc:1;		/* timing control */
123 } tlb_t;
124 
125 #define UTLB_SIZE 64
126 #define ITLB_SIZE 4
127 
128 #define TARGET_INSN_START_EXTRA_WORDS 1
129 
130 enum sh_features {
131     SH_FEATURE_SH4A = 1,
132     SH_FEATURE_BCR3_AND_BCR4 = 2,
133 };
134 
135 typedef struct memory_content {
136     uint32_t address;
137     uint32_t value;
138     struct memory_content *next;
139 } memory_content;
140 
141 typedef struct CPUArchState {
142     uint32_t flags;		/* general execution flags */
143     uint32_t gregs[24];		/* general registers */
144     float32 fregs[32];		/* floating point registers */
145     uint32_t sr;                /* status register (with T split out) */
146     uint32_t sr_m;              /* M bit of status register */
147     uint32_t sr_q;              /* Q bit of status register */
148     uint32_t sr_t;              /* T bit of status register */
149     uint32_t ssr;		/* saved status register */
150     uint32_t spc;		/* saved program counter */
151     uint32_t gbr;		/* global base register */
152     uint32_t vbr;		/* vector base register */
153     uint32_t sgr;		/* saved global register 15 */
154     uint32_t dbr;		/* debug base register */
155     uint32_t pc;		/* program counter */
156     uint32_t delayed_pc;        /* target of delayed branch */
157     uint32_t delayed_cond;      /* condition of delayed branch */
158     uint32_t mach;		/* multiply and accumulate high */
159     uint32_t macl;		/* multiply and accumulate low */
160     uint32_t pr;		/* procedure register */
161     uint32_t fpscr;		/* floating point status/control register */
162     uint32_t fpul;		/* floating point communication register */
163 
164     /* float point status register */
165     float_status fp_status;
166 
167     /* Those belong to the specific unit (SH7750) but are handled here */
168     uint32_t mmucr;		/* MMU control register */
169     uint32_t pteh;		/* page table entry high register */
170     uint32_t ptel;		/* page table entry low register */
171     uint32_t ptea;		/* page table entry assistance register */
172     uint32_t ttb;               /* translation table base register */
173     uint32_t tea;		/* TLB exception address register */
174     uint32_t tra;		/* TRAPA exception register */
175     uint32_t expevt;		/* exception event register */
176     uint32_t intevt;		/* interrupt event register */
177 
178     tlb_t itlb[ITLB_SIZE];	/* instruction translation table */
179     tlb_t utlb[UTLB_SIZE];	/* unified translation table */
180 
181     /* LDST = LOCK_ADDR != -1.  */
182     uint32_t lock_addr;
183     uint32_t lock_value;
184 
185     /* Fields up to this point are cleared by a CPU reset */
186     struct {} end_reset_fields;
187 
188     /* Fields from here on are preserved over CPU reset. */
189     int id;			/* CPU model */
190 
191     /* The features that we should emulate. See sh_features above.  */
192     uint32_t features;
193 
194     void *intc_handle;
195     int in_sleep;		/* SR_BL ignored during sleep */
196     memory_content *movcal_backup;
197     memory_content **movcal_backup_tail;
198 } CPUSH4State;
199 
200 /**
201  * SuperHCPU:
202  * @env: #CPUSH4State
203  *
204  * A SuperH CPU.
205  */
206 struct ArchCPU {
207     /*< private >*/
208     CPUState parent_obj;
209     /*< public >*/
210 
211     CPUNegativeOffsetState neg;
212     CPUSH4State env;
213 };
214 
215 
216 void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
217 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
218 int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
219 int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
220 G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
221                                                MMUAccessType access_type, int mmu_idx,
222                                                uintptr_t retaddr);
223 
224 void sh4_translate_init(void);
225 void sh4_cpu_list(void);
226 
227 #if !defined(CONFIG_USER_ONLY)
228 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
229                          MMUAccessType access_type, int mmu_idx,
230                          bool probe, uintptr_t retaddr);
231 void superh_cpu_do_interrupt(CPUState *cpu);
232 bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
233 void cpu_sh4_invalidate_tlb(CPUSH4State *s);
234 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
235                                        hwaddr addr);
236 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
237                                     uint32_t mem_value);
238 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
239                                        hwaddr addr);
240 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
241                                     uint32_t mem_value);
242 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
243                                        hwaddr addr);
244 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
245                                     uint32_t mem_value);
246 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
247                                        hwaddr addr);
248 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
249                                     uint32_t mem_value);
250 #endif
251 
252 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
253 
254 void cpu_load_tlb(CPUSH4State * env);
255 
256 #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
257 #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
258 #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
259 
260 #define cpu_list sh4_cpu_list
261 
262 /* MMU modes definitions */
263 #define MMU_USER_IDX 1
264 static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
265 {
266     /* The instruction in a RTE delay slot is fetched in privileged
267        mode, but executed in user mode.  */
268     if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
269         return 0;
270     } else {
271         return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
272     }
273 }
274 
275 #include "exec/cpu-all.h"
276 
277 /* MMU control register */
278 #define MMUCR    0x1F000010
279 #define MMUCR_AT (1<<0)
280 #define MMUCR_TI (1<<2)
281 #define MMUCR_SV (1<<8)
282 #define MMUCR_URC_BITS (6)
283 #define MMUCR_URC_OFFSET (10)
284 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
285 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
286 static inline int cpu_mmucr_urc (uint32_t mmucr)
287 {
288     return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
289 }
290 
291 /* PTEH : Page Translation Entry High register */
292 #define PTEH_ASID_BITS (8)
293 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
294 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
295 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
296 #define PTEH_VPN_BITS (22)
297 #define PTEH_VPN_OFFSET (10)
298 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
299 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
300 static inline int cpu_pteh_vpn (uint32_t pteh)
301 {
302     return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
303 }
304 
305 /* PTEL : Page Translation Entry Low register */
306 #define PTEL_V        (1 << 8)
307 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
308 #define PTEL_C        (1 << 3)
309 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
310 #define PTEL_D        (1 << 2)
311 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
312 #define PTEL_SH       (1 << 1)
313 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
314 #define PTEL_WT       (1 << 0)
315 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
316 
317 #define PTEL_SZ_HIGH_OFFSET  (7)
318 #define PTEL_SZ_HIGH  (1 << PTEL_SZ_HIGH_OFFSET)
319 #define PTEL_SZ_LOW_OFFSET   (4)
320 #define PTEL_SZ_LOW   (1 << PTEL_SZ_LOW_OFFSET)
321 static inline int cpu_ptel_sz (uint32_t ptel)
322 {
323     int sz;
324     sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
325     sz <<= 1;
326     sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
327     return sz;
328 }
329 
330 #define PTEL_PPN_BITS (19)
331 #define PTEL_PPN_OFFSET (10)
332 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
333 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
334 static inline int cpu_ptel_ppn (uint32_t ptel)
335 {
336     return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
337 }
338 
339 #define PTEL_PR_BITS   (2)
340 #define PTEL_PR_OFFSET (5)
341 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
342 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
343 static inline int cpu_ptel_pr (uint32_t ptel)
344 {
345     return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
346 }
347 
348 /* PTEA : Page Translation Entry Assistance register */
349 #define PTEA_SA_BITS (3)
350 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
351 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
352 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
353 #define PTEA_TC        (1 << 3)
354 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
355 
356 static inline target_ulong cpu_read_sr(CPUSH4State *env)
357 {
358     return env->sr | (env->sr_m << SR_M) |
359                      (env->sr_q << SR_Q) |
360                      (env->sr_t << SR_T);
361 }
362 
363 static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
364 {
365     env->sr_m = (sr >> SR_M) & 1;
366     env->sr_q = (sr >> SR_Q) & 1;
367     env->sr_t = (sr >> SR_T) & 1;
368     env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
369 }
370 
371 static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
372                                         target_ulong *cs_base, uint32_t *flags)
373 {
374     *pc = env->pc;
375     /* For a gUSA region, notice the end of the region.  */
376     *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
377     *flags = env->flags
378             | (env->fpscr & TB_FLAG_FPSCR_MASK)
379             | (env->sr & TB_FLAG_SR_MASK)
380             | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
381 #ifdef CONFIG_USER_ONLY
382     *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
383 #endif
384 }
385 
386 #endif /* SH4_CPU_H */
387