1 /* 2 * SH4 emulation 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef SH4_CPU_H 21 #define SH4_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 #include "exec/cpu-defs.h" 26 27 #define ALIGNED_ONLY 28 29 /* CPU Subtypes */ 30 #define SH_CPU_SH7750 (1 << 0) 31 #define SH_CPU_SH7750S (1 << 1) 32 #define SH_CPU_SH7750R (1 << 2) 33 #define SH_CPU_SH7751 (1 << 3) 34 #define SH_CPU_SH7751R (1 << 4) 35 #define SH_CPU_SH7785 (1 << 5) 36 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) 37 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) 38 39 #define SR_MD 30 40 #define SR_RB 29 41 #define SR_BL 28 42 #define SR_FD 15 43 #define SR_M 9 44 #define SR_Q 8 45 #define SR_I3 7 46 #define SR_I2 6 47 #define SR_I1 5 48 #define SR_I0 4 49 #define SR_S 1 50 #define SR_T 0 51 52 #define FPSCR_MASK (0x003fffff) 53 #define FPSCR_FR (1 << 21) 54 #define FPSCR_SZ (1 << 20) 55 #define FPSCR_PR (1 << 19) 56 #define FPSCR_DN (1 << 18) 57 #define FPSCR_CAUSE_MASK (0x3f << 12) 58 #define FPSCR_CAUSE_SHIFT (12) 59 #define FPSCR_CAUSE_E (1 << 17) 60 #define FPSCR_CAUSE_V (1 << 16) 61 #define FPSCR_CAUSE_Z (1 << 15) 62 #define FPSCR_CAUSE_O (1 << 14) 63 #define FPSCR_CAUSE_U (1 << 13) 64 #define FPSCR_CAUSE_I (1 << 12) 65 #define FPSCR_ENABLE_MASK (0x1f << 7) 66 #define FPSCR_ENABLE_SHIFT (7) 67 #define FPSCR_ENABLE_V (1 << 11) 68 #define FPSCR_ENABLE_Z (1 << 10) 69 #define FPSCR_ENABLE_O (1 << 9) 70 #define FPSCR_ENABLE_U (1 << 8) 71 #define FPSCR_ENABLE_I (1 << 7) 72 #define FPSCR_FLAG_MASK (0x1f << 2) 73 #define FPSCR_FLAG_SHIFT (2) 74 #define FPSCR_FLAG_V (1 << 6) 75 #define FPSCR_FLAG_Z (1 << 5) 76 #define FPSCR_FLAG_O (1 << 4) 77 #define FPSCR_FLAG_U (1 << 3) 78 #define FPSCR_FLAG_I (1 << 2) 79 #define FPSCR_RM_MASK (0x03 << 0) 80 #define FPSCR_RM_NEAREST (0 << 0) 81 #define FPSCR_RM_ZERO (1 << 0) 82 83 #define DELAY_SLOT_MASK 0x7 84 #define DELAY_SLOT (1 << 0) 85 #define DELAY_SLOT_CONDITIONAL (1 << 1) 86 #define DELAY_SLOT_RTE (1 << 2) 87 88 #define TB_FLAG_PENDING_MOVCA (1 << 3) 89 90 #define GUSA_SHIFT 4 91 #ifdef CONFIG_USER_ONLY 92 #define GUSA_EXCLUSIVE (1 << 12) 93 #define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE) 94 #else 95 /* Provide dummy versions of the above to allow tests against tbflags 96 to be elided while avoiding ifdefs. */ 97 #define GUSA_EXCLUSIVE 0 98 #define GUSA_MASK 0 99 #endif 100 101 #define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK) 102 103 typedef struct tlb_t { 104 uint32_t vpn; /* virtual page number */ 105 uint32_t ppn; /* physical page number */ 106 uint32_t size; /* mapped page size in bytes */ 107 uint8_t asid; /* address space identifier */ 108 uint8_t v:1; /* validity */ 109 uint8_t sz:2; /* page size */ 110 uint8_t sh:1; /* share status */ 111 uint8_t c:1; /* cacheability */ 112 uint8_t pr:2; /* protection key */ 113 uint8_t d:1; /* dirty */ 114 uint8_t wt:1; /* write through */ 115 uint8_t sa:3; /* space attribute (PCMCIA) */ 116 uint8_t tc:1; /* timing control */ 117 } tlb_t; 118 119 #define UTLB_SIZE 64 120 #define ITLB_SIZE 4 121 122 #define TARGET_INSN_START_EXTRA_WORDS 1 123 124 enum sh_features { 125 SH_FEATURE_SH4A = 1, 126 SH_FEATURE_BCR3_AND_BCR4 = 2, 127 }; 128 129 typedef struct memory_content { 130 uint32_t address; 131 uint32_t value; 132 struct memory_content *next; 133 } memory_content; 134 135 typedef struct CPUSH4State { 136 uint32_t flags; /* general execution flags */ 137 uint32_t gregs[24]; /* general registers */ 138 float32 fregs[32]; /* floating point registers */ 139 uint32_t sr; /* status register (with T split out) */ 140 uint32_t sr_m; /* M bit of status register */ 141 uint32_t sr_q; /* Q bit of status register */ 142 uint32_t sr_t; /* T bit of status register */ 143 uint32_t ssr; /* saved status register */ 144 uint32_t spc; /* saved program counter */ 145 uint32_t gbr; /* global base register */ 146 uint32_t vbr; /* vector base register */ 147 uint32_t sgr; /* saved global register 15 */ 148 uint32_t dbr; /* debug base register */ 149 uint32_t pc; /* program counter */ 150 uint32_t delayed_pc; /* target of delayed branch */ 151 uint32_t delayed_cond; /* condition of delayed branch */ 152 uint32_t mach; /* multiply and accumulate high */ 153 uint32_t macl; /* multiply and accumulate low */ 154 uint32_t pr; /* procedure register */ 155 uint32_t fpscr; /* floating point status/control register */ 156 uint32_t fpul; /* floating point communication register */ 157 158 /* float point status register */ 159 float_status fp_status; 160 161 /* Those belong to the specific unit (SH7750) but are handled here */ 162 uint32_t mmucr; /* MMU control register */ 163 uint32_t pteh; /* page table entry high register */ 164 uint32_t ptel; /* page table entry low register */ 165 uint32_t ptea; /* page table entry assistance register */ 166 uint32_t ttb; /* tranlation table base register */ 167 uint32_t tea; /* TLB exception address register */ 168 uint32_t tra; /* TRAPA exception register */ 169 uint32_t expevt; /* exception event register */ 170 uint32_t intevt; /* interrupt event register */ 171 172 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ 173 tlb_t utlb[UTLB_SIZE]; /* unified translation table */ 174 175 /* LDST = LOCK_ADDR != -1. */ 176 uint32_t lock_addr; 177 uint32_t lock_value; 178 179 /* Fields up to this point are cleared by a CPU reset */ 180 struct {} end_reset_fields; 181 182 CPU_COMMON 183 184 /* Fields from here on are preserved over CPU reset. */ 185 int id; /* CPU model */ 186 187 /* The features that we should emulate. See sh_features above. */ 188 uint32_t features; 189 190 void *intc_handle; 191 int in_sleep; /* SR_BL ignored during sleep */ 192 memory_content *movcal_backup; 193 memory_content **movcal_backup_tail; 194 } CPUSH4State; 195 196 /** 197 * SuperHCPU: 198 * @env: #CPUSH4State 199 * 200 * A SuperH CPU. 201 */ 202 struct SuperHCPU { 203 /*< private >*/ 204 CPUState parent_obj; 205 /*< public >*/ 206 207 CPUSH4State env; 208 }; 209 210 static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) 211 { 212 return container_of(env, SuperHCPU, env); 213 } 214 215 #define ENV_OFFSET offsetof(SuperHCPU, env) 216 217 void superh_cpu_do_interrupt(CPUState *cpu); 218 bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); 219 void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 220 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 221 int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 222 int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 223 void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 224 MMUAccessType access_type, 225 int mmu_idx, uintptr_t retaddr); 226 227 void sh4_translate_init(void); 228 int cpu_sh4_signal_handler(int host_signum, void *pinfo, 229 void *puc); 230 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 231 MMUAccessType access_type, int mmu_idx, 232 bool probe, uintptr_t retaddr); 233 234 void sh4_cpu_list(void); 235 #if !defined(CONFIG_USER_ONLY) 236 void cpu_sh4_invalidate_tlb(CPUSH4State *s); 237 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, 238 hwaddr addr); 239 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, 240 uint32_t mem_value); 241 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, 242 hwaddr addr); 243 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, 244 uint32_t mem_value); 245 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, 246 hwaddr addr); 247 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, 248 uint32_t mem_value); 249 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, 250 hwaddr addr); 251 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, 252 uint32_t mem_value); 253 #endif 254 255 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); 256 257 void cpu_load_tlb(CPUSH4State * env); 258 259 #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU 260 #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX 261 #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU 262 263 #define cpu_signal_handler cpu_sh4_signal_handler 264 #define cpu_list sh4_cpu_list 265 266 /* MMU modes definitions */ 267 #define MMU_MODE0_SUFFIX _kernel 268 #define MMU_MODE1_SUFFIX _user 269 #define MMU_USER_IDX 1 270 static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) 271 { 272 /* The instruction in a RTE delay slot is fetched in privileged 273 mode, but executed in user mode. */ 274 if (ifetch && (env->flags & DELAY_SLOT_RTE)) { 275 return 0; 276 } else { 277 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; 278 } 279 } 280 281 typedef CPUSH4State CPUArchState; 282 typedef SuperHCPU ArchCPU; 283 284 #include "exec/cpu-all.h" 285 286 /* Memory access type */ 287 enum { 288 /* Privilege */ 289 ACCESS_PRIV = 0x01, 290 /* Direction */ 291 ACCESS_WRITE = 0x02, 292 /* Type of instruction */ 293 ACCESS_CODE = 0x10, 294 ACCESS_INT = 0x20 295 }; 296 297 /* MMU control register */ 298 #define MMUCR 0x1F000010 299 #define MMUCR_AT (1<<0) 300 #define MMUCR_TI (1<<2) 301 #define MMUCR_SV (1<<8) 302 #define MMUCR_URC_BITS (6) 303 #define MMUCR_URC_OFFSET (10) 304 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) 305 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) 306 static inline int cpu_mmucr_urc (uint32_t mmucr) 307 { 308 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET); 309 } 310 311 /* PTEH : Page Translation Entry High register */ 312 #define PTEH_ASID_BITS (8) 313 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) 314 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) 315 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK) 316 #define PTEH_VPN_BITS (22) 317 #define PTEH_VPN_OFFSET (10) 318 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) 319 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) 320 static inline int cpu_pteh_vpn (uint32_t pteh) 321 { 322 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET); 323 } 324 325 /* PTEL : Page Translation Entry Low register */ 326 #define PTEL_V (1 << 8) 327 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) 328 #define PTEL_C (1 << 3) 329 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) 330 #define PTEL_D (1 << 2) 331 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) 332 #define PTEL_SH (1 << 1) 333 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) 334 #define PTEL_WT (1 << 0) 335 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT) 336 337 #define PTEL_SZ_HIGH_OFFSET (7) 338 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) 339 #define PTEL_SZ_LOW_OFFSET (4) 340 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) 341 static inline int cpu_ptel_sz (uint32_t ptel) 342 { 343 int sz; 344 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; 345 sz <<= 1; 346 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; 347 return sz; 348 } 349 350 #define PTEL_PPN_BITS (19) 351 #define PTEL_PPN_OFFSET (10) 352 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) 353 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) 354 static inline int cpu_ptel_ppn (uint32_t ptel) 355 { 356 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET); 357 } 358 359 #define PTEL_PR_BITS (2) 360 #define PTEL_PR_OFFSET (5) 361 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) 362 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) 363 static inline int cpu_ptel_pr (uint32_t ptel) 364 { 365 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET); 366 } 367 368 /* PTEA : Page Translation Entry Assistance register */ 369 #define PTEA_SA_BITS (3) 370 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) 371 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) 372 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK) 373 #define PTEA_TC (1 << 3) 374 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) 375 376 static inline target_ulong cpu_read_sr(CPUSH4State *env) 377 { 378 return env->sr | (env->sr_m << SR_M) | 379 (env->sr_q << SR_Q) | 380 (env->sr_t << SR_T); 381 } 382 383 static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) 384 { 385 env->sr_m = (sr >> SR_M) & 1; 386 env->sr_q = (sr >> SR_Q) & 1; 387 env->sr_t = (sr >> SR_T) & 1; 388 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); 389 } 390 391 static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, 392 target_ulong *cs_base, uint32_t *flags) 393 { 394 *pc = env->pc; 395 /* For a gUSA region, notice the end of the region. */ 396 *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0; 397 *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */ 398 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */ 399 | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */ 400 | (env->sr & (1u << SR_FD)) /* Bit 15 */ 401 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ 402 } 403 404 #endif /* SH4_CPU_H */ 405