1 /* 2 * SH4 emulation 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef SH4_CPU_H 21 #define SH4_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-common.h" 25 #include "exec/cpu-defs.h" 26 #include "exec/cpu-interrupt.h" 27 #include "qemu/cpu-float.h" 28 29 /* CPU Subtypes */ 30 #define SH_CPU_SH7750 (1 << 0) 31 #define SH_CPU_SH7750S (1 << 1) 32 #define SH_CPU_SH7750R (1 << 2) 33 #define SH_CPU_SH7751 (1 << 3) 34 #define SH_CPU_SH7751R (1 << 4) 35 #define SH_CPU_SH7785 (1 << 5) 36 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) 37 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) 38 39 #define SR_MD 30 40 #define SR_RB 29 41 #define SR_BL 28 42 #define SR_FD 15 43 #define SR_M 9 44 #define SR_Q 8 45 #define SR_I3 7 46 #define SR_I2 6 47 #define SR_I1 5 48 #define SR_I0 4 49 #define SR_S 1 50 #define SR_T 0 51 52 #define FPSCR_MASK (0x003fffff) 53 #define FPSCR_FR (1 << 21) 54 #define FPSCR_SZ (1 << 20) 55 #define FPSCR_PR (1 << 19) 56 #define FPSCR_DN (1 << 18) 57 #define FPSCR_CAUSE_MASK (0x3f << 12) 58 #define FPSCR_CAUSE_SHIFT (12) 59 #define FPSCR_CAUSE_E (1 << 17) 60 #define FPSCR_CAUSE_V (1 << 16) 61 #define FPSCR_CAUSE_Z (1 << 15) 62 #define FPSCR_CAUSE_O (1 << 14) 63 #define FPSCR_CAUSE_U (1 << 13) 64 #define FPSCR_CAUSE_I (1 << 12) 65 #define FPSCR_ENABLE_MASK (0x1f << 7) 66 #define FPSCR_ENABLE_SHIFT (7) 67 #define FPSCR_ENABLE_V (1 << 11) 68 #define FPSCR_ENABLE_Z (1 << 10) 69 #define FPSCR_ENABLE_O (1 << 9) 70 #define FPSCR_ENABLE_U (1 << 8) 71 #define FPSCR_ENABLE_I (1 << 7) 72 #define FPSCR_FLAG_MASK (0x1f << 2) 73 #define FPSCR_FLAG_SHIFT (2) 74 #define FPSCR_FLAG_V (1 << 6) 75 #define FPSCR_FLAG_Z (1 << 5) 76 #define FPSCR_FLAG_O (1 << 4) 77 #define FPSCR_FLAG_U (1 << 3) 78 #define FPSCR_FLAG_I (1 << 2) 79 #define FPSCR_RM_MASK (0x03 << 0) 80 #define FPSCR_RM_NEAREST (0 << 0) 81 #define FPSCR_RM_ZERO (1 << 0) 82 83 #define TB_FLAG_DELAY_SLOT (1 << 0) 84 #define TB_FLAG_DELAY_SLOT_COND (1 << 1) 85 #define TB_FLAG_DELAY_SLOT_RTE (1 << 2) 86 #define TB_FLAG_PENDING_MOVCA (1 << 3) 87 #define TB_FLAG_GUSA_SHIFT 4 /* [11:4] */ 88 #define TB_FLAG_GUSA_EXCLUSIVE (1 << 12) 89 #define TB_FLAG_UNALIGN (1 << 13) 90 #define TB_FLAG_SR_FD (1 << SR_FD) /* 15 */ 91 #define TB_FLAG_FPSCR_PR FPSCR_PR /* 19 */ 92 #define TB_FLAG_FPSCR_SZ FPSCR_SZ /* 20 */ 93 #define TB_FLAG_FPSCR_FR FPSCR_FR /* 21 */ 94 #define TB_FLAG_SR_RB (1 << SR_RB) /* 29 */ 95 #define TB_FLAG_SR_MD (1 << SR_MD) /* 30 */ 96 97 #define TB_FLAG_DELAY_SLOT_MASK (TB_FLAG_DELAY_SLOT | \ 98 TB_FLAG_DELAY_SLOT_COND | \ 99 TB_FLAG_DELAY_SLOT_RTE) 100 #define TB_FLAG_GUSA_MASK ((0xff << TB_FLAG_GUSA_SHIFT) | \ 101 TB_FLAG_GUSA_EXCLUSIVE) 102 #define TB_FLAG_FPSCR_MASK (TB_FLAG_FPSCR_PR | \ 103 TB_FLAG_FPSCR_SZ | \ 104 TB_FLAG_FPSCR_FR) 105 #define TB_FLAG_SR_MASK (TB_FLAG_SR_FD | \ 106 TB_FLAG_SR_RB | \ 107 TB_FLAG_SR_MD) 108 #define TB_FLAG_ENVFLAGS_MASK (TB_FLAG_DELAY_SLOT_MASK | \ 109 TB_FLAG_GUSA_MASK) 110 111 typedef struct tlb_t { 112 uint32_t vpn; /* virtual page number */ 113 uint32_t ppn; /* physical page number */ 114 uint32_t size; /* mapped page size in bytes */ 115 uint8_t asid; /* address space identifier */ 116 uint8_t v:1; /* validity */ 117 uint8_t sz:2; /* page size */ 118 uint8_t sh:1; /* share status */ 119 uint8_t c:1; /* cacheability */ 120 uint8_t pr:2; /* protection key */ 121 uint8_t d:1; /* dirty */ 122 uint8_t wt:1; /* write through */ 123 uint8_t sa:3; /* space attribute (PCMCIA) */ 124 uint8_t tc:1; /* timing control */ 125 } tlb_t; 126 127 #define UTLB_SIZE 64 128 #define ITLB_SIZE 4 129 130 #define TARGET_INSN_START_EXTRA_WORDS 1 131 132 enum sh_features { 133 SH_FEATURE_SH4A = 1, 134 SH_FEATURE_BCR3_AND_BCR4 = 2, 135 }; 136 137 typedef struct memory_content { 138 uint32_t address; 139 uint32_t value; 140 struct memory_content *next; 141 } memory_content; 142 143 typedef struct CPUArchState { 144 uint32_t flags; /* general execution flags */ 145 uint32_t gregs[24]; /* general registers */ 146 float32 fregs[32]; /* floating point registers */ 147 uint32_t sr; /* status register (with T split out) */ 148 uint32_t sr_m; /* M bit of status register */ 149 uint32_t sr_q; /* Q bit of status register */ 150 uint32_t sr_t; /* T bit of status register */ 151 uint32_t ssr; /* saved status register */ 152 uint32_t spc; /* saved program counter */ 153 uint32_t gbr; /* global base register */ 154 uint32_t vbr; /* vector base register */ 155 uint32_t sgr; /* saved global register 15 */ 156 uint32_t dbr; /* debug base register */ 157 uint32_t pc; /* program counter */ 158 uint32_t delayed_pc; /* target of delayed branch */ 159 uint32_t delayed_cond; /* condition of delayed branch */ 160 uint32_t pr; /* procedure register */ 161 uint32_t fpscr; /* floating point status/control register */ 162 uint32_t fpul; /* floating point communication register */ 163 164 /* multiply and accumulate: high, low and combined. */ 165 union { 166 uint64_t mac; 167 struct { 168 #if HOST_BIG_ENDIAN 169 uint32_t mach, macl; 170 #else 171 uint32_t macl, mach; 172 #endif 173 }; 174 }; 175 176 /* float point status register */ 177 float_status fp_status; 178 179 /* Those belong to the specific unit (SH7750) but are handled here */ 180 uint32_t mmucr; /* MMU control register */ 181 uint32_t pteh; /* page table entry high register */ 182 uint32_t ptel; /* page table entry low register */ 183 uint32_t ptea; /* page table entry assistance register */ 184 uint32_t ttb; /* translation table base register */ 185 uint32_t tea; /* TLB exception address register */ 186 uint32_t tra; /* TRAPA exception register */ 187 uint32_t expevt; /* exception event register */ 188 uint32_t intevt; /* interrupt event register */ 189 190 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ 191 tlb_t utlb[UTLB_SIZE]; /* unified translation table */ 192 193 /* LDST = LOCK_ADDR != -1. */ 194 uint32_t lock_addr; 195 uint32_t lock_value; 196 197 /* Fields up to this point are cleared by a CPU reset */ 198 struct {} end_reset_fields; 199 200 /* Fields from here on are preserved over CPU reset. */ 201 int id; /* CPU model */ 202 203 /* The features that we should emulate. See sh_features above. */ 204 uint32_t features; 205 206 void *intc_handle; 207 int in_sleep; /* SR_BL ignored during sleep */ 208 memory_content *movcal_backup; 209 memory_content **movcal_backup_tail; 210 } CPUSH4State; 211 212 /** 213 * SuperHCPU: 214 * @env: #CPUSH4State 215 * 216 * A SuperH CPU. 217 */ 218 struct ArchCPU { 219 CPUState parent_obj; 220 221 CPUSH4State env; 222 }; 223 224 /** 225 * SuperHCPUClass: 226 * @parent_realize: The parent class' realize handler. 227 * @parent_phases: The parent class' reset phase handlers. 228 * @pvr: Processor Version Register 229 * @prr: Processor Revision Register 230 * @cvr: Cache Version Register 231 * 232 * A SuperH CPU model. 233 */ 234 struct SuperHCPUClass { 235 CPUClass parent_class; 236 237 DeviceRealize parent_realize; 238 ResettablePhases parent_phases; 239 240 uint32_t pvr; 241 uint32_t prr; 242 uint32_t cvr; 243 }; 244 245 void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 246 int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 247 int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 248 G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 249 MMUAccessType access_type, int mmu_idx, 250 uintptr_t retaddr); 251 252 void sh4_translate_init(void); 253 void sh4_translate_code(CPUState *cs, TranslationBlock *tb, 254 int *max_insns, vaddr pc, void *host_pc); 255 256 #if !defined(CONFIG_USER_ONLY) 257 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 258 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 259 MMUAccessType access_type, int mmu_idx, 260 bool probe, uintptr_t retaddr); 261 void superh_cpu_do_interrupt(CPUState *cpu); 262 bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); 263 void cpu_sh4_invalidate_tlb(CPUSH4State *s); 264 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, 265 hwaddr addr); 266 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, 267 uint32_t mem_value); 268 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, 269 hwaddr addr); 270 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, 271 uint32_t mem_value); 272 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, 273 hwaddr addr); 274 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, 275 uint32_t mem_value); 276 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, 277 hwaddr addr); 278 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, 279 uint32_t mem_value); 280 #endif 281 282 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); 283 284 void cpu_load_tlb(CPUSH4State * env); 285 286 #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU 287 288 /* MMU modes definitions */ 289 #define MMU_USER_IDX 1 290 291 /* MMU control register */ 292 #define MMUCR 0x1F000010 293 #define MMUCR_AT (1<<0) 294 #define MMUCR_TI (1<<2) 295 #define MMUCR_SV (1<<8) 296 #define MMUCR_URC_BITS (6) 297 #define MMUCR_URC_OFFSET (10) 298 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) 299 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) 300 static inline int cpu_mmucr_urc (uint32_t mmucr) 301 { 302 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET); 303 } 304 305 /* PTEH : Page Translation Entry High register */ 306 #define PTEH_ASID_BITS (8) 307 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) 308 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) 309 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK) 310 #define PTEH_VPN_BITS (22) 311 #define PTEH_VPN_OFFSET (10) 312 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) 313 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) 314 static inline int cpu_pteh_vpn (uint32_t pteh) 315 { 316 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET); 317 } 318 319 /* PTEL : Page Translation Entry Low register */ 320 #define PTEL_V (1 << 8) 321 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) 322 #define PTEL_C (1 << 3) 323 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) 324 #define PTEL_D (1 << 2) 325 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) 326 #define PTEL_SH (1 << 1) 327 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) 328 #define PTEL_WT (1 << 0) 329 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT) 330 331 #define PTEL_SZ_HIGH_OFFSET (7) 332 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) 333 #define PTEL_SZ_LOW_OFFSET (4) 334 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) 335 static inline int cpu_ptel_sz (uint32_t ptel) 336 { 337 int sz; 338 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; 339 sz <<= 1; 340 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; 341 return sz; 342 } 343 344 #define PTEL_PPN_BITS (19) 345 #define PTEL_PPN_OFFSET (10) 346 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) 347 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) 348 static inline int cpu_ptel_ppn (uint32_t ptel) 349 { 350 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET); 351 } 352 353 #define PTEL_PR_BITS (2) 354 #define PTEL_PR_OFFSET (5) 355 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) 356 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) 357 static inline int cpu_ptel_pr (uint32_t ptel) 358 { 359 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET); 360 } 361 362 /* PTEA : Page Translation Entry Assistance register */ 363 #define PTEA_SA_BITS (3) 364 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) 365 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) 366 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK) 367 #define PTEA_TC (1 << 3) 368 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) 369 370 static inline target_ulong cpu_read_sr(CPUSH4State *env) 371 { 372 return env->sr | (env->sr_m << SR_M) | 373 (env->sr_q << SR_Q) | 374 (env->sr_t << SR_T); 375 } 376 377 static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) 378 { 379 env->sr_m = (sr >> SR_M) & 1; 380 env->sr_q = (sr >> SR_Q) & 1; 381 env->sr_t = (sr >> SR_T) & 1; 382 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); 383 } 384 385 static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, 386 uint64_t *cs_base, uint32_t *flags) 387 { 388 *pc = env->pc; 389 /* For a gUSA region, notice the end of the region. */ 390 *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; 391 *flags = env->flags 392 | (env->fpscr & TB_FLAG_FPSCR_MASK) 393 | (env->sr & TB_FLAG_SR_MASK) 394 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ 395 #ifdef CONFIG_USER_ONLY 396 *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; 397 #endif 398 } 399 400 #endif /* SH4_CPU_H */ 401