1 /* 2 * QEMU SuperH CPU 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "qemu-common.h" 26 #include "migration/vmstate.h" 27 #include "exec/exec-all.h" 28 #include "fpu/softfloat.h" 29 30 31 static void superh_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 SuperHCPU *cpu = SUPERH_CPU(cs); 34 35 cpu->env.pc = value; 36 } 37 38 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 39 { 40 SuperHCPU *cpu = SUPERH_CPU(cs); 41 42 cpu->env.pc = tb->pc; 43 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; 44 } 45 46 static bool superh_cpu_has_work(CPUState *cs) 47 { 48 return cs->interrupt_request & CPU_INTERRUPT_HARD; 49 } 50 51 /* CPUClass::reset() */ 52 static void superh_cpu_reset(CPUState *s) 53 { 54 SuperHCPU *cpu = SUPERH_CPU(s); 55 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); 56 CPUSH4State *env = &cpu->env; 57 58 scc->parent_reset(s); 59 60 memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); 61 62 env->pc = 0xA0000000; 63 #if defined(CONFIG_USER_ONLY) 64 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ 65 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ 66 #else 67 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | 68 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); 69 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ 70 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 71 set_flush_to_zero(1, &env->fp_status); 72 #endif 73 set_default_nan_mode(1, &env->fp_status); 74 set_snan_bit_is_one(1, &env->fp_status); 75 } 76 77 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 78 { 79 info->mach = bfd_mach_sh4; 80 info->print_insn = print_insn_sh; 81 } 82 83 typedef struct SuperHCPUListState { 84 fprintf_function cpu_fprintf; 85 FILE *file; 86 } SuperHCPUListState; 87 88 /* Sort alphabetically by type name. */ 89 static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b) 90 { 91 ObjectClass *class_a = (ObjectClass *)a; 92 ObjectClass *class_b = (ObjectClass *)b; 93 const char *name_a, *name_b; 94 95 name_a = object_class_get_name(class_a); 96 name_b = object_class_get_name(class_b); 97 return strcmp(name_a, name_b); 98 } 99 100 static void superh_cpu_list_entry(gpointer data, gpointer user_data) 101 { 102 SuperHCPUListState *s = user_data; 103 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 104 int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX); 105 106 (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename); 107 } 108 109 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf) 110 { 111 SuperHCPUListState s = { 112 .cpu_fprintf = cpu_fprintf, 113 .file = f, 114 }; 115 GSList *list; 116 117 list = object_class_get_list(TYPE_SUPERH_CPU, false); 118 list = g_slist_sort(list, superh_cpu_list_compare); 119 g_slist_foreach(list, superh_cpu_list_entry, &s); 120 g_slist_free(list); 121 } 122 123 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) 124 { 125 ObjectClass *oc; 126 char *s, *typename = NULL; 127 128 s = g_ascii_strdown(cpu_model, -1); 129 if (strcmp(s, "any") == 0) { 130 oc = object_class_by_name(TYPE_SH7750R_CPU); 131 goto out; 132 } 133 134 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); 135 oc = object_class_by_name(typename); 136 if (oc != NULL && object_class_is_abstract(oc)) { 137 oc = NULL; 138 } 139 140 out: 141 g_free(s); 142 g_free(typename); 143 return oc; 144 } 145 146 static void sh7750r_cpu_initfn(Object *obj) 147 { 148 SuperHCPU *cpu = SUPERH_CPU(obj); 149 CPUSH4State *env = &cpu->env; 150 151 env->id = SH_CPU_SH7750R; 152 env->features = SH_FEATURE_BCR3_AND_BCR4; 153 } 154 155 static void sh7750r_class_init(ObjectClass *oc, void *data) 156 { 157 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 158 159 scc->pvr = 0x00050000; 160 scc->prr = 0x00000100; 161 scc->cvr = 0x00110000; 162 } 163 164 static void sh7751r_cpu_initfn(Object *obj) 165 { 166 SuperHCPU *cpu = SUPERH_CPU(obj); 167 CPUSH4State *env = &cpu->env; 168 169 env->id = SH_CPU_SH7751R; 170 env->features = SH_FEATURE_BCR3_AND_BCR4; 171 } 172 173 static void sh7751r_class_init(ObjectClass *oc, void *data) 174 { 175 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 176 177 scc->pvr = 0x04050005; 178 scc->prr = 0x00000113; 179 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ 180 } 181 182 static void sh7785_cpu_initfn(Object *obj) 183 { 184 SuperHCPU *cpu = SUPERH_CPU(obj); 185 CPUSH4State *env = &cpu->env; 186 187 env->id = SH_CPU_SH7785; 188 env->features = SH_FEATURE_SH4A; 189 } 190 191 static void sh7785_class_init(ObjectClass *oc, void *data) 192 { 193 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 194 195 scc->pvr = 0x10300700; 196 scc->prr = 0x00000200; 197 scc->cvr = 0x71440211; 198 } 199 200 static void superh_cpu_realizefn(DeviceState *dev, Error **errp) 201 { 202 CPUState *cs = CPU(dev); 203 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); 204 Error *local_err = NULL; 205 206 cpu_exec_realizefn(cs, &local_err); 207 if (local_err != NULL) { 208 error_propagate(errp, local_err); 209 return; 210 } 211 212 cpu_reset(cs); 213 qemu_init_vcpu(cs); 214 215 scc->parent_realize(dev, errp); 216 } 217 218 static void superh_cpu_initfn(Object *obj) 219 { 220 CPUState *cs = CPU(obj); 221 SuperHCPU *cpu = SUPERH_CPU(obj); 222 CPUSH4State *env = &cpu->env; 223 224 cs->env_ptr = env; 225 226 env->movcal_backup_tail = &(env->movcal_backup); 227 } 228 229 static const VMStateDescription vmstate_sh_cpu = { 230 .name = "cpu", 231 .unmigratable = 1, 232 }; 233 234 static void superh_cpu_class_init(ObjectClass *oc, void *data) 235 { 236 DeviceClass *dc = DEVICE_CLASS(oc); 237 CPUClass *cc = CPU_CLASS(oc); 238 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 239 240 device_class_set_parent_realize(dc, superh_cpu_realizefn, 241 &scc->parent_realize); 242 243 scc->parent_reset = cc->reset; 244 cc->reset = superh_cpu_reset; 245 246 cc->class_by_name = superh_cpu_class_by_name; 247 cc->has_work = superh_cpu_has_work; 248 cc->do_interrupt = superh_cpu_do_interrupt; 249 cc->cpu_exec_interrupt = superh_cpu_exec_interrupt; 250 cc->dump_state = superh_cpu_dump_state; 251 cc->set_pc = superh_cpu_set_pc; 252 cc->synchronize_from_tb = superh_cpu_synchronize_from_tb; 253 cc->gdb_read_register = superh_cpu_gdb_read_register; 254 cc->gdb_write_register = superh_cpu_gdb_write_register; 255 #ifdef CONFIG_USER_ONLY 256 cc->handle_mmu_fault = superh_cpu_handle_mmu_fault; 257 #else 258 cc->do_unaligned_access = superh_cpu_do_unaligned_access; 259 cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; 260 #endif 261 cc->disas_set_info = superh_cpu_disas_set_info; 262 cc->tcg_initialize = sh4_translate_init; 263 264 cc->gdb_num_core_regs = 59; 265 266 dc->vmsd = &vmstate_sh_cpu; 267 } 268 269 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ 270 { \ 271 .name = type_name, \ 272 .parent = TYPE_SUPERH_CPU, \ 273 .class_init = cinit, \ 274 .instance_init = initfn, \ 275 } 276 static const TypeInfo superh_cpu_type_infos[] = { 277 { 278 .name = TYPE_SUPERH_CPU, 279 .parent = TYPE_CPU, 280 .instance_size = sizeof(SuperHCPU), 281 .instance_init = superh_cpu_initfn, 282 .abstract = true, 283 .class_size = sizeof(SuperHCPUClass), 284 .class_init = superh_cpu_class_init, 285 }, 286 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, 287 sh7750r_cpu_initfn), 288 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, 289 sh7751r_cpu_initfn), 290 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, 291 sh7785_cpu_initfn), 292 293 }; 294 295 DEFINE_TYPES(superh_cpu_type_infos) 296