1 /* 2 * QEMU SuperH CPU 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "migration/vmstate.h" 27 #include "exec/exec-all.h" 28 #include "fpu/softfloat-helpers.h" 29 #include "tcg/tcg.h" 30 31 static void superh_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 SuperHCPU *cpu = SUPERH_CPU(cs); 34 35 cpu->env.pc = value; 36 } 37 38 static vaddr superh_cpu_get_pc(CPUState *cs) 39 { 40 SuperHCPU *cpu = SUPERH_CPU(cs); 41 42 return cpu->env.pc; 43 } 44 45 static void superh_cpu_synchronize_from_tb(CPUState *cs, 46 const TranslationBlock *tb) 47 { 48 SuperHCPU *cpu = SUPERH_CPU(cs); 49 50 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 51 cpu->env.pc = tb->pc; 52 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; 53 } 54 55 static void superh_restore_state_to_opc(CPUState *cs, 56 const TranslationBlock *tb, 57 const uint64_t *data) 58 { 59 SuperHCPU *cpu = SUPERH_CPU(cs); 60 61 cpu->env.pc = data[0]; 62 cpu->env.flags = data[1]; 63 /* 64 * Theoretically delayed_pc should also be restored. In practice the 65 * branch instruction is re-executed after exception, so the delayed 66 * branch target will be recomputed. 67 */ 68 } 69 70 #ifndef CONFIG_USER_ONLY 71 static bool superh_io_recompile_replay_branch(CPUState *cs, 72 const TranslationBlock *tb) 73 { 74 SuperHCPU *cpu = SUPERH_CPU(cs); 75 CPUSH4State *env = &cpu->env; 76 77 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) 78 && !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) { 79 env->pc -= 2; 80 env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); 81 return true; 82 } 83 return false; 84 } 85 #endif 86 87 static bool superh_cpu_has_work(CPUState *cs) 88 { 89 return cs->interrupt_request & CPU_INTERRUPT_HARD; 90 } 91 92 static void superh_cpu_reset_hold(Object *obj) 93 { 94 CPUState *s = CPU(obj); 95 SuperHCPU *cpu = SUPERH_CPU(s); 96 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); 97 CPUSH4State *env = &cpu->env; 98 99 if (scc->parent_phases.hold) { 100 scc->parent_phases.hold(obj); 101 } 102 103 memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); 104 105 env->pc = 0xA0000000; 106 #if defined(CONFIG_USER_ONLY) 107 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ 108 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ 109 #else 110 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | 111 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); 112 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ 113 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 114 set_flush_to_zero(1, &env->fp_status); 115 #endif 116 set_default_nan_mode(1, &env->fp_status); 117 } 118 119 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 120 { 121 info->mach = bfd_mach_sh4; 122 info->print_insn = print_insn_sh; 123 } 124 125 static void superh_cpu_list_entry(gpointer data, gpointer user_data) 126 { 127 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 128 int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX); 129 130 qemu_printf("%.*s\n", len, typename); 131 } 132 133 void sh4_cpu_list(void) 134 { 135 GSList *list; 136 137 list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false); 138 g_slist_foreach(list, superh_cpu_list_entry, NULL); 139 g_slist_free(list); 140 } 141 142 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) 143 { 144 ObjectClass *oc; 145 char *s, *typename = NULL; 146 147 s = g_ascii_strdown(cpu_model, -1); 148 if (strcmp(s, "any") == 0) { 149 oc = object_class_by_name(TYPE_SH7750R_CPU); 150 goto out; 151 } 152 153 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); 154 oc = object_class_by_name(typename); 155 if (oc != NULL && object_class_is_abstract(oc)) { 156 oc = NULL; 157 } 158 159 out: 160 g_free(s); 161 g_free(typename); 162 return oc; 163 } 164 165 static void sh7750r_cpu_initfn(Object *obj) 166 { 167 SuperHCPU *cpu = SUPERH_CPU(obj); 168 CPUSH4State *env = &cpu->env; 169 170 env->id = SH_CPU_SH7750R; 171 env->features = SH_FEATURE_BCR3_AND_BCR4; 172 } 173 174 static void sh7750r_class_init(ObjectClass *oc, void *data) 175 { 176 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 177 178 scc->pvr = 0x00050000; 179 scc->prr = 0x00000100; 180 scc->cvr = 0x00110000; 181 } 182 183 static void sh7751r_cpu_initfn(Object *obj) 184 { 185 SuperHCPU *cpu = SUPERH_CPU(obj); 186 CPUSH4State *env = &cpu->env; 187 188 env->id = SH_CPU_SH7751R; 189 env->features = SH_FEATURE_BCR3_AND_BCR4; 190 } 191 192 static void sh7751r_class_init(ObjectClass *oc, void *data) 193 { 194 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 195 196 scc->pvr = 0x04050005; 197 scc->prr = 0x00000113; 198 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ 199 } 200 201 static void sh7785_cpu_initfn(Object *obj) 202 { 203 SuperHCPU *cpu = SUPERH_CPU(obj); 204 CPUSH4State *env = &cpu->env; 205 206 env->id = SH_CPU_SH7785; 207 env->features = SH_FEATURE_SH4A; 208 } 209 210 static void sh7785_class_init(ObjectClass *oc, void *data) 211 { 212 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 213 214 scc->pvr = 0x10300700; 215 scc->prr = 0x00000200; 216 scc->cvr = 0x71440211; 217 } 218 219 static void superh_cpu_realizefn(DeviceState *dev, Error **errp) 220 { 221 CPUState *cs = CPU(dev); 222 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); 223 Error *local_err = NULL; 224 225 cpu_exec_realizefn(cs, &local_err); 226 if (local_err != NULL) { 227 error_propagate(errp, local_err); 228 return; 229 } 230 231 cpu_reset(cs); 232 qemu_init_vcpu(cs); 233 234 scc->parent_realize(dev, errp); 235 } 236 237 static void superh_cpu_initfn(Object *obj) 238 { 239 SuperHCPU *cpu = SUPERH_CPU(obj); 240 CPUSH4State *env = &cpu->env; 241 242 cpu_set_cpustate_pointers(cpu); 243 244 env->movcal_backup_tail = &(env->movcal_backup); 245 } 246 247 #ifndef CONFIG_USER_ONLY 248 static const VMStateDescription vmstate_sh_cpu = { 249 .name = "cpu", 250 .unmigratable = 1, 251 }; 252 253 #include "hw/core/sysemu-cpu-ops.h" 254 255 static const struct SysemuCPUOps sh4_sysemu_ops = { 256 .get_phys_page_debug = superh_cpu_get_phys_page_debug, 257 }; 258 #endif 259 260 #include "hw/core/tcg-cpu-ops.h" 261 262 static const struct TCGCPUOps superh_tcg_ops = { 263 .initialize = sh4_translate_init, 264 .synchronize_from_tb = superh_cpu_synchronize_from_tb, 265 .restore_state_to_opc = superh_restore_state_to_opc, 266 267 #ifndef CONFIG_USER_ONLY 268 .tlb_fill = superh_cpu_tlb_fill, 269 .cpu_exec_interrupt = superh_cpu_exec_interrupt, 270 .do_interrupt = superh_cpu_do_interrupt, 271 .do_unaligned_access = superh_cpu_do_unaligned_access, 272 .io_recompile_replay_branch = superh_io_recompile_replay_branch, 273 #endif /* !CONFIG_USER_ONLY */ 274 }; 275 276 static void superh_cpu_class_init(ObjectClass *oc, void *data) 277 { 278 DeviceClass *dc = DEVICE_CLASS(oc); 279 CPUClass *cc = CPU_CLASS(oc); 280 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 281 ResettableClass *rc = RESETTABLE_CLASS(oc); 282 283 device_class_set_parent_realize(dc, superh_cpu_realizefn, 284 &scc->parent_realize); 285 286 resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL, 287 &scc->parent_phases); 288 289 cc->class_by_name = superh_cpu_class_by_name; 290 cc->has_work = superh_cpu_has_work; 291 cc->dump_state = superh_cpu_dump_state; 292 cc->set_pc = superh_cpu_set_pc; 293 cc->get_pc = superh_cpu_get_pc; 294 cc->gdb_read_register = superh_cpu_gdb_read_register; 295 cc->gdb_write_register = superh_cpu_gdb_write_register; 296 #ifndef CONFIG_USER_ONLY 297 cc->sysemu_ops = &sh4_sysemu_ops; 298 dc->vmsd = &vmstate_sh_cpu; 299 #endif 300 cc->disas_set_info = superh_cpu_disas_set_info; 301 302 cc->gdb_num_core_regs = 59; 303 cc->tcg_ops = &superh_tcg_ops; 304 } 305 306 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ 307 { \ 308 .name = type_name, \ 309 .parent = TYPE_SUPERH_CPU, \ 310 .class_init = cinit, \ 311 .instance_init = initfn, \ 312 } 313 static const TypeInfo superh_cpu_type_infos[] = { 314 { 315 .name = TYPE_SUPERH_CPU, 316 .parent = TYPE_CPU, 317 .instance_size = sizeof(SuperHCPU), 318 .instance_init = superh_cpu_initfn, 319 .abstract = true, 320 .class_size = sizeof(SuperHCPUClass), 321 .class_init = superh_cpu_class_init, 322 }, 323 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, 324 sh7750r_cpu_initfn), 325 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, 326 sh7751r_cpu_initfn), 327 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, 328 sh7785_cpu_initfn), 329 330 }; 331 332 DEFINE_TYPES(superh_cpu_type_infos) 333