1 /* 2 * QEMU SuperH CPU 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "migration/vmstate.h" 27 #include "exec/exec-all.h" 28 #include "fpu/softfloat-helpers.h" 29 30 static void superh_cpu_set_pc(CPUState *cs, vaddr value) 31 { 32 SuperHCPU *cpu = SUPERH_CPU(cs); 33 34 cpu->env.pc = value; 35 } 36 37 static vaddr superh_cpu_get_pc(CPUState *cs) 38 { 39 SuperHCPU *cpu = SUPERH_CPU(cs); 40 41 return cpu->env.pc; 42 } 43 44 static void superh_cpu_synchronize_from_tb(CPUState *cs, 45 const TranslationBlock *tb) 46 { 47 SuperHCPU *cpu = SUPERH_CPU(cs); 48 49 cpu->env.pc = tb_pc(tb); 50 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; 51 } 52 53 static void superh_restore_state_to_opc(CPUState *cs, 54 const TranslationBlock *tb, 55 const uint64_t *data) 56 { 57 SuperHCPU *cpu = SUPERH_CPU(cs); 58 59 cpu->env.pc = data[0]; 60 cpu->env.flags = data[1]; 61 /* 62 * Theoretically delayed_pc should also be restored. In practice the 63 * branch instruction is re-executed after exception, so the delayed 64 * branch target will be recomputed. 65 */ 66 } 67 68 #ifndef CONFIG_USER_ONLY 69 static bool superh_io_recompile_replay_branch(CPUState *cs, 70 const TranslationBlock *tb) 71 { 72 SuperHCPU *cpu = SUPERH_CPU(cs); 73 CPUSH4State *env = &cpu->env; 74 75 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) 76 && env->pc != tb_pc(tb)) { 77 env->pc -= 2; 78 env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); 79 return true; 80 } 81 return false; 82 } 83 #endif 84 85 static bool superh_cpu_has_work(CPUState *cs) 86 { 87 return cs->interrupt_request & CPU_INTERRUPT_HARD; 88 } 89 90 static void superh_cpu_reset_hold(Object *obj) 91 { 92 CPUState *s = CPU(obj); 93 SuperHCPU *cpu = SUPERH_CPU(s); 94 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); 95 CPUSH4State *env = &cpu->env; 96 97 if (scc->parent_phases.hold) { 98 scc->parent_phases.hold(obj); 99 } 100 101 memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); 102 103 env->pc = 0xA0000000; 104 #if defined(CONFIG_USER_ONLY) 105 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ 106 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ 107 #else 108 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | 109 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); 110 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ 111 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 112 set_flush_to_zero(1, &env->fp_status); 113 #endif 114 set_default_nan_mode(1, &env->fp_status); 115 } 116 117 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 118 { 119 info->mach = bfd_mach_sh4; 120 info->print_insn = print_insn_sh; 121 } 122 123 static void superh_cpu_list_entry(gpointer data, gpointer user_data) 124 { 125 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 126 int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX); 127 128 qemu_printf("%.*s\n", len, typename); 129 } 130 131 void sh4_cpu_list(void) 132 { 133 GSList *list; 134 135 list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false); 136 g_slist_foreach(list, superh_cpu_list_entry, NULL); 137 g_slist_free(list); 138 } 139 140 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) 141 { 142 ObjectClass *oc; 143 char *s, *typename = NULL; 144 145 s = g_ascii_strdown(cpu_model, -1); 146 if (strcmp(s, "any") == 0) { 147 oc = object_class_by_name(TYPE_SH7750R_CPU); 148 goto out; 149 } 150 151 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); 152 oc = object_class_by_name(typename); 153 if (oc != NULL && object_class_is_abstract(oc)) { 154 oc = NULL; 155 } 156 157 out: 158 g_free(s); 159 g_free(typename); 160 return oc; 161 } 162 163 static void sh7750r_cpu_initfn(Object *obj) 164 { 165 SuperHCPU *cpu = SUPERH_CPU(obj); 166 CPUSH4State *env = &cpu->env; 167 168 env->id = SH_CPU_SH7750R; 169 env->features = SH_FEATURE_BCR3_AND_BCR4; 170 } 171 172 static void sh7750r_class_init(ObjectClass *oc, void *data) 173 { 174 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 175 176 scc->pvr = 0x00050000; 177 scc->prr = 0x00000100; 178 scc->cvr = 0x00110000; 179 } 180 181 static void sh7751r_cpu_initfn(Object *obj) 182 { 183 SuperHCPU *cpu = SUPERH_CPU(obj); 184 CPUSH4State *env = &cpu->env; 185 186 env->id = SH_CPU_SH7751R; 187 env->features = SH_FEATURE_BCR3_AND_BCR4; 188 } 189 190 static void sh7751r_class_init(ObjectClass *oc, void *data) 191 { 192 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 193 194 scc->pvr = 0x04050005; 195 scc->prr = 0x00000113; 196 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ 197 } 198 199 static void sh7785_cpu_initfn(Object *obj) 200 { 201 SuperHCPU *cpu = SUPERH_CPU(obj); 202 CPUSH4State *env = &cpu->env; 203 204 env->id = SH_CPU_SH7785; 205 env->features = SH_FEATURE_SH4A; 206 } 207 208 static void sh7785_class_init(ObjectClass *oc, void *data) 209 { 210 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 211 212 scc->pvr = 0x10300700; 213 scc->prr = 0x00000200; 214 scc->cvr = 0x71440211; 215 } 216 217 static void superh_cpu_realizefn(DeviceState *dev, Error **errp) 218 { 219 CPUState *cs = CPU(dev); 220 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); 221 Error *local_err = NULL; 222 223 cpu_exec_realizefn(cs, &local_err); 224 if (local_err != NULL) { 225 error_propagate(errp, local_err); 226 return; 227 } 228 229 cpu_reset(cs); 230 qemu_init_vcpu(cs); 231 232 scc->parent_realize(dev, errp); 233 } 234 235 static void superh_cpu_initfn(Object *obj) 236 { 237 SuperHCPU *cpu = SUPERH_CPU(obj); 238 CPUSH4State *env = &cpu->env; 239 240 cpu_set_cpustate_pointers(cpu); 241 242 env->movcal_backup_tail = &(env->movcal_backup); 243 } 244 245 #ifndef CONFIG_USER_ONLY 246 static const VMStateDescription vmstate_sh_cpu = { 247 .name = "cpu", 248 .unmigratable = 1, 249 }; 250 251 #include "hw/core/sysemu-cpu-ops.h" 252 253 static const struct SysemuCPUOps sh4_sysemu_ops = { 254 .get_phys_page_debug = superh_cpu_get_phys_page_debug, 255 }; 256 #endif 257 258 #include "hw/core/tcg-cpu-ops.h" 259 260 static const struct TCGCPUOps superh_tcg_ops = { 261 .initialize = sh4_translate_init, 262 .synchronize_from_tb = superh_cpu_synchronize_from_tb, 263 .restore_state_to_opc = superh_restore_state_to_opc, 264 265 #ifndef CONFIG_USER_ONLY 266 .tlb_fill = superh_cpu_tlb_fill, 267 .cpu_exec_interrupt = superh_cpu_exec_interrupt, 268 .do_interrupt = superh_cpu_do_interrupt, 269 .do_unaligned_access = superh_cpu_do_unaligned_access, 270 .io_recompile_replay_branch = superh_io_recompile_replay_branch, 271 #endif /* !CONFIG_USER_ONLY */ 272 }; 273 274 static void superh_cpu_class_init(ObjectClass *oc, void *data) 275 { 276 DeviceClass *dc = DEVICE_CLASS(oc); 277 CPUClass *cc = CPU_CLASS(oc); 278 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 279 ResettableClass *rc = RESETTABLE_CLASS(oc); 280 281 device_class_set_parent_realize(dc, superh_cpu_realizefn, 282 &scc->parent_realize); 283 284 resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL, 285 &scc->parent_phases); 286 287 cc->class_by_name = superh_cpu_class_by_name; 288 cc->has_work = superh_cpu_has_work; 289 cc->dump_state = superh_cpu_dump_state; 290 cc->set_pc = superh_cpu_set_pc; 291 cc->get_pc = superh_cpu_get_pc; 292 cc->gdb_read_register = superh_cpu_gdb_read_register; 293 cc->gdb_write_register = superh_cpu_gdb_write_register; 294 #ifndef CONFIG_USER_ONLY 295 cc->sysemu_ops = &sh4_sysemu_ops; 296 dc->vmsd = &vmstate_sh_cpu; 297 #endif 298 cc->disas_set_info = superh_cpu_disas_set_info; 299 300 cc->gdb_num_core_regs = 59; 301 cc->tcg_ops = &superh_tcg_ops; 302 } 303 304 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ 305 { \ 306 .name = type_name, \ 307 .parent = TYPE_SUPERH_CPU, \ 308 .class_init = cinit, \ 309 .instance_init = initfn, \ 310 } 311 static const TypeInfo superh_cpu_type_infos[] = { 312 { 313 .name = TYPE_SUPERH_CPU, 314 .parent = TYPE_CPU, 315 .instance_size = sizeof(SuperHCPU), 316 .instance_init = superh_cpu_initfn, 317 .abstract = true, 318 .class_size = sizeof(SuperHCPUClass), 319 .class_init = superh_cpu_class_init, 320 }, 321 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, 322 sh7750r_cpu_initfn), 323 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, 324 sh7751r_cpu_initfn), 325 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, 326 sh7785_cpu_initfn), 327 328 }; 329 330 DEFINE_TYPES(superh_cpu_type_infos) 331