1 /* 2 * QEMU SuperH CPU 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "migration/vmstate.h" 27 #include "exec/translation-block.h" 28 #include "fpu/softfloat-helpers.h" 29 #include "tcg/tcg.h" 30 31 static void superh_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 SuperHCPU *cpu = SUPERH_CPU(cs); 34 35 cpu->env.pc = value; 36 } 37 38 static vaddr superh_cpu_get_pc(CPUState *cs) 39 { 40 SuperHCPU *cpu = SUPERH_CPU(cs); 41 42 return cpu->env.pc; 43 } 44 45 static void superh_cpu_synchronize_from_tb(CPUState *cs, 46 const TranslationBlock *tb) 47 { 48 SuperHCPU *cpu = SUPERH_CPU(cs); 49 50 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 51 cpu->env.pc = tb->pc; 52 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; 53 } 54 55 static void superh_restore_state_to_opc(CPUState *cs, 56 const TranslationBlock *tb, 57 const uint64_t *data) 58 { 59 SuperHCPU *cpu = SUPERH_CPU(cs); 60 61 cpu->env.pc = data[0]; 62 cpu->env.flags = data[1]; 63 /* 64 * Theoretically delayed_pc should also be restored. In practice the 65 * branch instruction is re-executed after exception, so the delayed 66 * branch target will be recomputed. 67 */ 68 } 69 70 #ifndef CONFIG_USER_ONLY 71 static bool superh_io_recompile_replay_branch(CPUState *cs, 72 const TranslationBlock *tb) 73 { 74 CPUSH4State *env = cpu_env(cs); 75 76 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) 77 && !tcg_cflags_has(cs, CF_PCREL) && env->pc != tb->pc) { 78 env->pc -= 2; 79 env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); 80 return true; 81 } 82 return false; 83 } 84 85 static bool superh_cpu_has_work(CPUState *cs) 86 { 87 return cs->interrupt_request & CPU_INTERRUPT_HARD; 88 } 89 #endif /* !CONFIG_USER_ONLY */ 90 91 static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) 92 { 93 CPUSH4State *env = cpu_env(cs); 94 95 /* 96 * The instruction in a RTE delay slot is fetched in privileged mode, 97 * but executed in user mode. 98 */ 99 if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { 100 return 0; 101 } else { 102 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; 103 } 104 } 105 106 static void superh_cpu_reset_hold(Object *obj, ResetType type) 107 { 108 CPUState *cs = CPU(obj); 109 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj); 110 CPUSH4State *env = cpu_env(cs); 111 112 if (scc->parent_phases.hold) { 113 scc->parent_phases.hold(obj, type); 114 } 115 116 memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); 117 118 env->pc = 0xA0000000; 119 #if defined(CONFIG_USER_ONLY) 120 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ 121 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ 122 #else 123 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | 124 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); 125 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ 126 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 127 set_flush_to_zero(1, &env->fp_status); 128 #endif 129 set_default_nan_mode(1, &env->fp_status); 130 set_snan_bit_is_one(true, &env->fp_status); 131 /* sign bit clear, set all frac bits other than msb */ 132 set_float_default_nan_pattern(0b00111111, &env->fp_status); 133 /* 134 * TODO: "SH-4 CPU Core Architecture ADCS 7182230F" doesn't say whether 135 * it detects tininess before or after rounding. Section 6.4 is clear 136 * that flush-to-zero happens when the result underflows, though, so 137 * either this should be "detect ftz after rounding" or else we should 138 * be setting "detect tininess before rounding". 139 */ 140 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); 141 } 142 143 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 144 { 145 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG 146 : BFD_ENDIAN_LITTLE; 147 info->mach = bfd_mach_sh4; 148 info->print_insn = print_insn_sh; 149 } 150 151 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) 152 { 153 ObjectClass *oc; 154 char *s, *typename = NULL; 155 156 s = g_ascii_strdown(cpu_model, -1); 157 if (strcmp(s, "any") == 0) { 158 oc = object_class_by_name(TYPE_SH7750R_CPU); 159 goto out; 160 } 161 162 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); 163 oc = object_class_by_name(typename); 164 165 out: 166 g_free(s); 167 g_free(typename); 168 return oc; 169 } 170 171 static void sh7750r_cpu_initfn(Object *obj) 172 { 173 CPUSH4State *env = cpu_env(CPU(obj)); 174 175 env->id = SH_CPU_SH7750R; 176 env->features = SH_FEATURE_BCR3_AND_BCR4; 177 } 178 179 static void sh7750r_class_init(ObjectClass *oc, const void *data) 180 { 181 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 182 183 scc->pvr = 0x00050000; 184 scc->prr = 0x00000100; 185 scc->cvr = 0x00110000; 186 } 187 188 static void sh7751r_cpu_initfn(Object *obj) 189 { 190 CPUSH4State *env = cpu_env(CPU(obj)); 191 192 env->id = SH_CPU_SH7751R; 193 env->features = SH_FEATURE_BCR3_AND_BCR4; 194 } 195 196 static void sh7751r_class_init(ObjectClass *oc, const void *data) 197 { 198 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 199 200 scc->pvr = 0x04050005; 201 scc->prr = 0x00000113; 202 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ 203 } 204 205 static void sh7785_cpu_initfn(Object *obj) 206 { 207 CPUSH4State *env = cpu_env(CPU(obj)); 208 209 env->id = SH_CPU_SH7785; 210 env->features = SH_FEATURE_SH4A; 211 } 212 213 static void sh7785_class_init(ObjectClass *oc, const void *data) 214 { 215 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 216 217 scc->pvr = 0x10300700; 218 scc->prr = 0x00000200; 219 scc->cvr = 0x71440211; 220 } 221 222 static void superh_cpu_realizefn(DeviceState *dev, Error **errp) 223 { 224 CPUState *cs = CPU(dev); 225 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); 226 Error *local_err = NULL; 227 228 cpu_exec_realizefn(cs, &local_err); 229 if (local_err != NULL) { 230 error_propagate(errp, local_err); 231 return; 232 } 233 234 cpu_reset(cs); 235 qemu_init_vcpu(cs); 236 237 scc->parent_realize(dev, errp); 238 } 239 240 static void superh_cpu_initfn(Object *obj) 241 { 242 CPUSH4State *env = cpu_env(CPU(obj)); 243 244 env->movcal_backup_tail = &(env->movcal_backup); 245 } 246 247 #ifndef CONFIG_USER_ONLY 248 static const VMStateDescription vmstate_sh_cpu = { 249 .name = "cpu", 250 .unmigratable = 1, 251 }; 252 253 #include "hw/core/sysemu-cpu-ops.h" 254 255 static const struct SysemuCPUOps sh4_sysemu_ops = { 256 .has_work = superh_cpu_has_work, 257 .get_phys_page_debug = superh_cpu_get_phys_page_debug, 258 }; 259 #endif 260 261 #include "accel/tcg/cpu-ops.h" 262 263 static const TCGCPUOps superh_tcg_ops = { 264 /* MTTCG not yet supported: require strict ordering */ 265 .guest_default_memory_order = TCG_MO_ALL, 266 .mttcg_supported = false, 267 268 .initialize = sh4_translate_init, 269 .translate_code = sh4_translate_code, 270 .synchronize_from_tb = superh_cpu_synchronize_from_tb, 271 .restore_state_to_opc = superh_restore_state_to_opc, 272 .mmu_index = sh4_cpu_mmu_index, 273 274 #ifndef CONFIG_USER_ONLY 275 .tlb_fill = superh_cpu_tlb_fill, 276 .cpu_exec_interrupt = superh_cpu_exec_interrupt, 277 .cpu_exec_halt = superh_cpu_has_work, 278 .do_interrupt = superh_cpu_do_interrupt, 279 .do_unaligned_access = superh_cpu_do_unaligned_access, 280 .io_recompile_replay_branch = superh_io_recompile_replay_branch, 281 #endif /* !CONFIG_USER_ONLY */ 282 }; 283 284 static void superh_cpu_class_init(ObjectClass *oc, const void *data) 285 { 286 DeviceClass *dc = DEVICE_CLASS(oc); 287 CPUClass *cc = CPU_CLASS(oc); 288 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 289 ResettableClass *rc = RESETTABLE_CLASS(oc); 290 291 device_class_set_parent_realize(dc, superh_cpu_realizefn, 292 &scc->parent_realize); 293 294 resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL, 295 &scc->parent_phases); 296 297 cc->class_by_name = superh_cpu_class_by_name; 298 cc->dump_state = superh_cpu_dump_state; 299 cc->set_pc = superh_cpu_set_pc; 300 cc->get_pc = superh_cpu_get_pc; 301 cc->gdb_read_register = superh_cpu_gdb_read_register; 302 cc->gdb_write_register = superh_cpu_gdb_write_register; 303 #ifndef CONFIG_USER_ONLY 304 cc->sysemu_ops = &sh4_sysemu_ops; 305 dc->vmsd = &vmstate_sh_cpu; 306 #endif 307 cc->disas_set_info = superh_cpu_disas_set_info; 308 309 cc->gdb_num_core_regs = 59; 310 cc->tcg_ops = &superh_tcg_ops; 311 } 312 313 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ 314 { \ 315 .name = type_name, \ 316 .parent = TYPE_SUPERH_CPU, \ 317 .class_init = cinit, \ 318 .instance_init = initfn, \ 319 } 320 static const TypeInfo superh_cpu_type_infos[] = { 321 { 322 .name = TYPE_SUPERH_CPU, 323 .parent = TYPE_CPU, 324 .instance_size = sizeof(SuperHCPU), 325 .instance_align = __alignof(SuperHCPU), 326 .instance_init = superh_cpu_initfn, 327 .abstract = true, 328 .class_size = sizeof(SuperHCPUClass), 329 .class_init = superh_cpu_class_init, 330 }, 331 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, 332 sh7750r_cpu_initfn), 333 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, 334 sh7751r_cpu_initfn), 335 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, 336 sh7785_cpu_initfn), 337 338 }; 339 340 DEFINE_TYPES(superh_cpu_type_infos) 341