xref: /openbmc/qemu/target/sh4/cpu.c (revision 7618fffd)
1 /*
2  * QEMU SuperH CPU
3  *
4  * Copyright (c) 2005 Samuel Tardieu
5  * Copyright (c) 2012 SUSE LINUX Products GmbH
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see
19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
20  */
21 
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/qemu-print.h"
25 #include "cpu.h"
26 #include "migration/vmstate.h"
27 #include "exec/exec-all.h"
28 #include "fpu/softfloat-helpers.h"
29 #include "tcg/tcg.h"
30 
31 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
32 {
33     SuperHCPU *cpu = SUPERH_CPU(cs);
34 
35     cpu->env.pc = value;
36 }
37 
38 static vaddr superh_cpu_get_pc(CPUState *cs)
39 {
40     SuperHCPU *cpu = SUPERH_CPU(cs);
41 
42     return cpu->env.pc;
43 }
44 
45 static void superh_cpu_synchronize_from_tb(CPUState *cs,
46                                            const TranslationBlock *tb)
47 {
48     SuperHCPU *cpu = SUPERH_CPU(cs);
49 
50     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
51     cpu->env.pc = tb->pc;
52     cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
53 }
54 
55 static void superh_restore_state_to_opc(CPUState *cs,
56                                         const TranslationBlock *tb,
57                                         const uint64_t *data)
58 {
59     SuperHCPU *cpu = SUPERH_CPU(cs);
60 
61     cpu->env.pc = data[0];
62     cpu->env.flags = data[1];
63     /*
64      * Theoretically delayed_pc should also be restored. In practice the
65      * branch instruction is re-executed after exception, so the delayed
66      * branch target will be recomputed.
67      */
68 }
69 
70 #ifndef CONFIG_USER_ONLY
71 static bool superh_io_recompile_replay_branch(CPUState *cs,
72                                               const TranslationBlock *tb)
73 {
74     SuperHCPU *cpu = SUPERH_CPU(cs);
75     CPUSH4State *env = &cpu->env;
76 
77     if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
78         && !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) {
79         env->pc -= 2;
80         env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
81         return true;
82     }
83     return false;
84 }
85 #endif
86 
87 static bool superh_cpu_has_work(CPUState *cs)
88 {
89     return cs->interrupt_request & CPU_INTERRUPT_HARD;
90 }
91 
92 static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
93 {
94     CPUSH4State *env = cpu_env(cs);
95 
96     /*
97      * The instruction in a RTE delay slot is fetched in privileged mode,
98      * but executed in user mode.
99      */
100     if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
101         return 0;
102     } else {
103         return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
104     }
105 }
106 
107 static void superh_cpu_reset_hold(Object *obj)
108 {
109     CPUState *s = CPU(obj);
110     SuperHCPU *cpu = SUPERH_CPU(s);
111     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
112     CPUSH4State *env = &cpu->env;
113 
114     if (scc->parent_phases.hold) {
115         scc->parent_phases.hold(obj);
116     }
117 
118     memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
119 
120     env->pc = 0xA0000000;
121 #if defined(CONFIG_USER_ONLY)
122     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
123     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
124 #else
125     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
126               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
127     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
128     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
129     set_flush_to_zero(1, &env->fp_status);
130 #endif
131     set_default_nan_mode(1, &env->fp_status);
132 }
133 
134 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
135 {
136     info->mach = bfd_mach_sh4;
137     info->print_insn = print_insn_sh;
138 }
139 
140 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
141 {
142     ObjectClass *oc;
143     char *s, *typename = NULL;
144 
145     s = g_ascii_strdown(cpu_model, -1);
146     if (strcmp(s, "any") == 0) {
147         oc = object_class_by_name(TYPE_SH7750R_CPU);
148         goto out;
149     }
150 
151     typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
152     oc = object_class_by_name(typename);
153 
154 out:
155     g_free(s);
156     g_free(typename);
157     return oc;
158 }
159 
160 static void sh7750r_cpu_initfn(Object *obj)
161 {
162     SuperHCPU *cpu = SUPERH_CPU(obj);
163     CPUSH4State *env = &cpu->env;
164 
165     env->id = SH_CPU_SH7750R;
166     env->features = SH_FEATURE_BCR3_AND_BCR4;
167 }
168 
169 static void sh7750r_class_init(ObjectClass *oc, void *data)
170 {
171     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
172 
173     scc->pvr = 0x00050000;
174     scc->prr = 0x00000100;
175     scc->cvr = 0x00110000;
176 }
177 
178 static void sh7751r_cpu_initfn(Object *obj)
179 {
180     SuperHCPU *cpu = SUPERH_CPU(obj);
181     CPUSH4State *env = &cpu->env;
182 
183     env->id = SH_CPU_SH7751R;
184     env->features = SH_FEATURE_BCR3_AND_BCR4;
185 }
186 
187 static void sh7751r_class_init(ObjectClass *oc, void *data)
188 {
189     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
190 
191     scc->pvr = 0x04050005;
192     scc->prr = 0x00000113;
193     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
194 }
195 
196 static void sh7785_cpu_initfn(Object *obj)
197 {
198     SuperHCPU *cpu = SUPERH_CPU(obj);
199     CPUSH4State *env = &cpu->env;
200 
201     env->id = SH_CPU_SH7785;
202     env->features = SH_FEATURE_SH4A;
203 }
204 
205 static void sh7785_class_init(ObjectClass *oc, void *data)
206 {
207     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
208 
209     scc->pvr = 0x10300700;
210     scc->prr = 0x00000200;
211     scc->cvr = 0x71440211;
212 }
213 
214 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
215 {
216     CPUState *cs = CPU(dev);
217     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
218     Error *local_err = NULL;
219 
220     cpu_exec_realizefn(cs, &local_err);
221     if (local_err != NULL) {
222         error_propagate(errp, local_err);
223         return;
224     }
225 
226     cpu_reset(cs);
227     qemu_init_vcpu(cs);
228 
229     scc->parent_realize(dev, errp);
230 }
231 
232 static void superh_cpu_initfn(Object *obj)
233 {
234     SuperHCPU *cpu = SUPERH_CPU(obj);
235     CPUSH4State *env = &cpu->env;
236 
237     env->movcal_backup_tail = &(env->movcal_backup);
238 }
239 
240 #ifndef CONFIG_USER_ONLY
241 static const VMStateDescription vmstate_sh_cpu = {
242     .name = "cpu",
243     .unmigratable = 1,
244 };
245 
246 #include "hw/core/sysemu-cpu-ops.h"
247 
248 static const struct SysemuCPUOps sh4_sysemu_ops = {
249     .get_phys_page_debug = superh_cpu_get_phys_page_debug,
250 };
251 #endif
252 
253 #include "hw/core/tcg-cpu-ops.h"
254 
255 static const TCGCPUOps superh_tcg_ops = {
256     .initialize = sh4_translate_init,
257     .synchronize_from_tb = superh_cpu_synchronize_from_tb,
258     .restore_state_to_opc = superh_restore_state_to_opc,
259 
260 #ifndef CONFIG_USER_ONLY
261     .tlb_fill = superh_cpu_tlb_fill,
262     .cpu_exec_interrupt = superh_cpu_exec_interrupt,
263     .do_interrupt = superh_cpu_do_interrupt,
264     .do_unaligned_access = superh_cpu_do_unaligned_access,
265     .io_recompile_replay_branch = superh_io_recompile_replay_branch,
266 #endif /* !CONFIG_USER_ONLY */
267 };
268 
269 static void superh_cpu_class_init(ObjectClass *oc, void *data)
270 {
271     DeviceClass *dc = DEVICE_CLASS(oc);
272     CPUClass *cc = CPU_CLASS(oc);
273     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
274     ResettableClass *rc = RESETTABLE_CLASS(oc);
275 
276     device_class_set_parent_realize(dc, superh_cpu_realizefn,
277                                     &scc->parent_realize);
278 
279     resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL,
280                                        &scc->parent_phases);
281 
282     cc->class_by_name = superh_cpu_class_by_name;
283     cc->has_work = superh_cpu_has_work;
284     cc->mmu_index = sh4_cpu_mmu_index;
285     cc->dump_state = superh_cpu_dump_state;
286     cc->set_pc = superh_cpu_set_pc;
287     cc->get_pc = superh_cpu_get_pc;
288     cc->gdb_read_register = superh_cpu_gdb_read_register;
289     cc->gdb_write_register = superh_cpu_gdb_write_register;
290 #ifndef CONFIG_USER_ONLY
291     cc->sysemu_ops = &sh4_sysemu_ops;
292     dc->vmsd = &vmstate_sh_cpu;
293 #endif
294     cc->disas_set_info = superh_cpu_disas_set_info;
295 
296     cc->gdb_num_core_regs = 59;
297     cc->tcg_ops = &superh_tcg_ops;
298 }
299 
300 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
301     {                                                    \
302         .name = type_name,                               \
303         .parent = TYPE_SUPERH_CPU,                       \
304         .class_init = cinit,                             \
305         .instance_init = initfn,                         \
306     }
307 static const TypeInfo superh_cpu_type_infos[] = {
308     {
309         .name = TYPE_SUPERH_CPU,
310         .parent = TYPE_CPU,
311         .instance_size = sizeof(SuperHCPU),
312         .instance_align = __alignof(SuperHCPU),
313         .instance_init = superh_cpu_initfn,
314         .abstract = true,
315         .class_size = sizeof(SuperHCPUClass),
316         .class_init = superh_cpu_class_init,
317     },
318     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init,
319                            sh7750r_cpu_initfn),
320     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init,
321                            sh7751r_cpu_initfn),
322     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init,
323                            sh7785_cpu_initfn),
324 
325 };
326 
327 DEFINE_TYPES(superh_cpu_type_infos)
328