1 /* 2 * QEMU SuperH CPU 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "migration/vmstate.h" 27 #include "exec/exec-all.h" 28 #include "fpu/softfloat-helpers.h" 29 30 static void superh_cpu_set_pc(CPUState *cs, vaddr value) 31 { 32 SuperHCPU *cpu = SUPERH_CPU(cs); 33 34 cpu->env.pc = value; 35 } 36 37 static vaddr superh_cpu_get_pc(CPUState *cs) 38 { 39 SuperHCPU *cpu = SUPERH_CPU(cs); 40 41 return cpu->env.pc; 42 } 43 44 static void superh_cpu_synchronize_from_tb(CPUState *cs, 45 const TranslationBlock *tb) 46 { 47 SuperHCPU *cpu = SUPERH_CPU(cs); 48 49 cpu->env.pc = tb_pc(tb); 50 cpu->env.flags = tb->flags; 51 } 52 53 #ifndef CONFIG_USER_ONLY 54 static bool superh_io_recompile_replay_branch(CPUState *cs, 55 const TranslationBlock *tb) 56 { 57 SuperHCPU *cpu = SUPERH_CPU(cs); 58 CPUSH4State *env = &cpu->env; 59 60 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) 61 && env->pc != tb_pc(tb)) { 62 env->pc -= 2; 63 env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); 64 return true; 65 } 66 return false; 67 } 68 #endif 69 70 static bool superh_cpu_has_work(CPUState *cs) 71 { 72 return cs->interrupt_request & CPU_INTERRUPT_HARD; 73 } 74 75 static void superh_cpu_reset(DeviceState *dev) 76 { 77 CPUState *s = CPU(dev); 78 SuperHCPU *cpu = SUPERH_CPU(s); 79 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); 80 CPUSH4State *env = &cpu->env; 81 82 scc->parent_reset(dev); 83 84 memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); 85 86 env->pc = 0xA0000000; 87 #if defined(CONFIG_USER_ONLY) 88 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ 89 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ 90 #else 91 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | 92 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); 93 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ 94 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 95 set_flush_to_zero(1, &env->fp_status); 96 #endif 97 set_default_nan_mode(1, &env->fp_status); 98 } 99 100 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 101 { 102 info->mach = bfd_mach_sh4; 103 info->print_insn = print_insn_sh; 104 } 105 106 static void superh_cpu_list_entry(gpointer data, gpointer user_data) 107 { 108 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 109 int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX); 110 111 qemu_printf("%.*s\n", len, typename); 112 } 113 114 void sh4_cpu_list(void) 115 { 116 GSList *list; 117 118 list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false); 119 g_slist_foreach(list, superh_cpu_list_entry, NULL); 120 g_slist_free(list); 121 } 122 123 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) 124 { 125 ObjectClass *oc; 126 char *s, *typename = NULL; 127 128 s = g_ascii_strdown(cpu_model, -1); 129 if (strcmp(s, "any") == 0) { 130 oc = object_class_by_name(TYPE_SH7750R_CPU); 131 goto out; 132 } 133 134 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); 135 oc = object_class_by_name(typename); 136 if (oc != NULL && object_class_is_abstract(oc)) { 137 oc = NULL; 138 } 139 140 out: 141 g_free(s); 142 g_free(typename); 143 return oc; 144 } 145 146 static void sh7750r_cpu_initfn(Object *obj) 147 { 148 SuperHCPU *cpu = SUPERH_CPU(obj); 149 CPUSH4State *env = &cpu->env; 150 151 env->id = SH_CPU_SH7750R; 152 env->features = SH_FEATURE_BCR3_AND_BCR4; 153 } 154 155 static void sh7750r_class_init(ObjectClass *oc, void *data) 156 { 157 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 158 159 scc->pvr = 0x00050000; 160 scc->prr = 0x00000100; 161 scc->cvr = 0x00110000; 162 } 163 164 static void sh7751r_cpu_initfn(Object *obj) 165 { 166 SuperHCPU *cpu = SUPERH_CPU(obj); 167 CPUSH4State *env = &cpu->env; 168 169 env->id = SH_CPU_SH7751R; 170 env->features = SH_FEATURE_BCR3_AND_BCR4; 171 } 172 173 static void sh7751r_class_init(ObjectClass *oc, void *data) 174 { 175 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 176 177 scc->pvr = 0x04050005; 178 scc->prr = 0x00000113; 179 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ 180 } 181 182 static void sh7785_cpu_initfn(Object *obj) 183 { 184 SuperHCPU *cpu = SUPERH_CPU(obj); 185 CPUSH4State *env = &cpu->env; 186 187 env->id = SH_CPU_SH7785; 188 env->features = SH_FEATURE_SH4A; 189 } 190 191 static void sh7785_class_init(ObjectClass *oc, void *data) 192 { 193 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 194 195 scc->pvr = 0x10300700; 196 scc->prr = 0x00000200; 197 scc->cvr = 0x71440211; 198 } 199 200 static void superh_cpu_realizefn(DeviceState *dev, Error **errp) 201 { 202 CPUState *cs = CPU(dev); 203 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); 204 Error *local_err = NULL; 205 206 cpu_exec_realizefn(cs, &local_err); 207 if (local_err != NULL) { 208 error_propagate(errp, local_err); 209 return; 210 } 211 212 cpu_reset(cs); 213 qemu_init_vcpu(cs); 214 215 scc->parent_realize(dev, errp); 216 } 217 218 static void superh_cpu_initfn(Object *obj) 219 { 220 SuperHCPU *cpu = SUPERH_CPU(obj); 221 CPUSH4State *env = &cpu->env; 222 223 cpu_set_cpustate_pointers(cpu); 224 225 env->movcal_backup_tail = &(env->movcal_backup); 226 } 227 228 #ifndef CONFIG_USER_ONLY 229 static const VMStateDescription vmstate_sh_cpu = { 230 .name = "cpu", 231 .unmigratable = 1, 232 }; 233 234 #include "hw/core/sysemu-cpu-ops.h" 235 236 static const struct SysemuCPUOps sh4_sysemu_ops = { 237 .get_phys_page_debug = superh_cpu_get_phys_page_debug, 238 }; 239 #endif 240 241 #include "hw/core/tcg-cpu-ops.h" 242 243 static const struct TCGCPUOps superh_tcg_ops = { 244 .initialize = sh4_translate_init, 245 .synchronize_from_tb = superh_cpu_synchronize_from_tb, 246 247 #ifndef CONFIG_USER_ONLY 248 .tlb_fill = superh_cpu_tlb_fill, 249 .cpu_exec_interrupt = superh_cpu_exec_interrupt, 250 .do_interrupt = superh_cpu_do_interrupt, 251 .do_unaligned_access = superh_cpu_do_unaligned_access, 252 .io_recompile_replay_branch = superh_io_recompile_replay_branch, 253 #endif /* !CONFIG_USER_ONLY */ 254 }; 255 256 static void superh_cpu_class_init(ObjectClass *oc, void *data) 257 { 258 DeviceClass *dc = DEVICE_CLASS(oc); 259 CPUClass *cc = CPU_CLASS(oc); 260 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 261 262 device_class_set_parent_realize(dc, superh_cpu_realizefn, 263 &scc->parent_realize); 264 265 device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset); 266 267 cc->class_by_name = superh_cpu_class_by_name; 268 cc->has_work = superh_cpu_has_work; 269 cc->dump_state = superh_cpu_dump_state; 270 cc->set_pc = superh_cpu_set_pc; 271 cc->get_pc = superh_cpu_get_pc; 272 cc->gdb_read_register = superh_cpu_gdb_read_register; 273 cc->gdb_write_register = superh_cpu_gdb_write_register; 274 #ifndef CONFIG_USER_ONLY 275 cc->sysemu_ops = &sh4_sysemu_ops; 276 dc->vmsd = &vmstate_sh_cpu; 277 #endif 278 cc->disas_set_info = superh_cpu_disas_set_info; 279 280 cc->gdb_num_core_regs = 59; 281 cc->tcg_ops = &superh_tcg_ops; 282 } 283 284 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ 285 { \ 286 .name = type_name, \ 287 .parent = TYPE_SUPERH_CPU, \ 288 .class_init = cinit, \ 289 .instance_init = initfn, \ 290 } 291 static const TypeInfo superh_cpu_type_infos[] = { 292 { 293 .name = TYPE_SUPERH_CPU, 294 .parent = TYPE_CPU, 295 .instance_size = sizeof(SuperHCPU), 296 .instance_init = superh_cpu_initfn, 297 .abstract = true, 298 .class_size = sizeof(SuperHCPUClass), 299 .class_init = superh_cpu_class_init, 300 }, 301 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, 302 sh7750r_cpu_initfn), 303 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, 304 sh7751r_cpu_initfn), 305 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, 306 sh7785_cpu_initfn), 307 308 }; 309 310 DEFINE_TYPES(superh_cpu_type_infos) 311