xref: /openbmc/qemu/target/sh4/cpu-qom.h (revision 6f9ff551)
1 /*
2  * QEMU SuperH CPU
3  *
4  * Copyright (c) 2012 SUSE LINUX Products GmbH
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19  */
20 #ifndef QEMU_SUPERH_CPU_QOM_H
21 #define QEMU_SUPERH_CPU_QOM_H
22 
23 #include "hw/core/cpu.h"
24 #include "qom/object.h"
25 
26 #define TYPE_SUPERH_CPU "superh-cpu"
27 
28 #define TYPE_SH7750R_CPU SUPERH_CPU_TYPE_NAME("sh7750r")
29 #define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r")
30 #define TYPE_SH7785_CPU  SUPERH_CPU_TYPE_NAME("sh7785")
31 
32 OBJECT_DECLARE_TYPE(SuperHCPU, SuperHCPUClass,
33                     superh_cpu, SUPERH_CPU)
34 
35 /**
36  * SuperHCPUClass:
37  * @parent_realize: The parent class' realize handler.
38  * @parent_reset: The parent class' reset handler.
39  * @pvr: Processor Version Register
40  * @prr: Processor Revision Register
41  * @cvr: Cache Version Register
42  *
43  * A SuperH CPU model.
44  */
45 struct SuperHCPUClass {
46     /*< private >*/
47     CPUClass parent_class;
48     /*< public >*/
49 
50     DeviceRealize parent_realize;
51     DeviceReset parent_reset;
52 
53     uint32_t pvr;
54     uint32_t prr;
55     uint32_t cvr;
56 };
57 
58 
59 #endif
60